AM79C982_技术文档

PRELIMINARY

Am79C982

basic Integrated Multiport Repeater (bIMR)

DISTINCTIVE CHARACTERISTICS

■ Fully backward-compatible with existing

■ Expandable to increase number of repeater

IMR/IMR+ device non-managed hub designs

ports

— Pin/socket-compatible with the Am79C980

(IMR) and Am79C981 (IMR+) devices

■ All ports can be separately isolated (partitioned)

in response to excessive collision conditions or

fault conditions

■ Repeater functions comply with IEEE 802.3

■ Network management and optional features are

accessible through a dedicated serial

management port

Repeater Unit speciﬁcations

■ Four and eight 10BASE-T port options available

■ Low-cost, ﬂexible solutions suitable for

■ Twisted-pair Link Test capability conforming to

the 10BASE-T standard. The receive Link Test

function can be optionally disabled through the

management port to facilitate interoperability

with devices that do not implement the LinkTest

function

non-managed repeater designs

■ Integral 10BASE-T transceivers utilize the

required predistortion transmission technique

■ Attachment unit interface (AUI) port allows

connectivity with 10BASE-5 (Ethernet) and

10BASE-2 (Cheapernet) networks, as well as

10BASE-F and/or Fiber Optic Inter-Repeater

Link (FOIRL) segments

■ Programmable option of Automatic Polarity

Detection and Correction permits automatic

recovery due to wiring errors

■ Minimum mode facilitates LED implementation

and provides four LED display options for port

status

■ Full amplitude and timing regeneration for

retransmitted waveforms

■ Preamble loss effects eliminated by deep FIFO

■ Built-in pulse stretching for carrier sense LED

■ CMOS device features high integration and low

display

power with a single +5 V supply

■ On-board PLL, Manchester encoder/decoder,

LED display and FIFO

GENERAL DESCRIPTION

The basic Integrated Multiport Repeater (bIMR™) chip

is a VLSI circuit that provides a system-level solution to

designing a compliant 802.3 repeater incorporating

10BASE-T transceivers. The device integrates the

Repeater functions speciﬁed by Section 9 of the

IEEE 802.3 standard and twisted-pair Transceiver

functions complying to the 10BASE-T standard. The

Am79C982-4 provides four and the Am79C982-8 pro-

vides eight integral twisted-pair medium attachment

units (MAUs), and an attachment unit interface (AUI)

port in an 84-pin plastic leaded chip carrier (PLCC).

of low-cost unshielded twisted-pair (UTP) cable or

existing telephone wiring.

The total number of ports per repeater unit can be in-

creased by connecting multiple bIMR devices through

their expansion ports, hence minimizing the total cost

per repeater port. Furthermore, a general-purpose

attachment unit interface (AUI) provides connection

capability to 10BASE-5 (Ethernet) and 10BASE-2

(Cheapernet) coaxial networks, as well as 10BASE-F

and/or Fiber Optic Inter-Repeater Link (FOIRL) ﬁber

segments. Network management and test functions

are provided through TTL-compatible I/O pins.

A network based on the 10BASE-T standard uses un-

shielded twisted-pair cables, therefore providing an

economical solution to networking by allowing the use

The device is fabricated in CMOS technology and

requires a single +5 V supply.

Publication# 19406 Rev: B Amendment/0

Issue Date: January 1999

This document contains information on a product under development at Advanced Micro Devices. The

information is intended to help you evaluate this product. AMD reserves the right to change or discontinue

work on this proposed product without notice.

1-3

PRELIMINARY

AMD

BLOCK DIAGRAM

DI±

AUI

Port

Manchester

Decoder

RX

MUX

CI±

FIFO

DO±

TX

MUX

Preamble

Phase =

Locked

Loop

Jam Sequence

RXD±

FIFO

Control

TP

Port

0

TXD±

TXP±

Manchester

Encoder

RXD±

REQ

ACK

TP

b IMR Chip

Control

Port n

TXD±

(Note)

Expansion Port

TXP±

COL

Partitioning

Link Test

DAT

JAM

RST

Reset

SI

X

1

Clock

Gen

SO

Test

and

Management

Port

SCLK

TEST

X

2

Timers

CRS

STR

Note: n=3 for Am79C982-4 and n=7 for Am79C982-8.

19406B-1

RELATED AMD PRODUCTS

Part No.

Description

Am79C98

Am79C100

Am7996

Twisted Pair Ethernet Transceiver (TPEX)

Twisted Pair Ethernet Transceiver Plus (TPEX+)

IEEE 802.3/Ethernet/Cheapernet Transceiver

Integrated Multiport Repeater Plus (IMR+)

Am79C981

Am79C987

Am79C940

Am79C90

Am79C900

Am79C960

Am79C961

Am79C965

Am79C970

Am79C974

Hardware Implemented Management Information Base (HIMIB )

Media Access Controller for Ethernet (MACE )

CMOS Local Area Network Controller for Ethernet (C-LANCE)

Integrated Local Area Communications Controller (ILACC )

PCnet-ISA Single-Chip Ethernet Controller (for ISA bus)

PCnet-ISA⁺Single-Chip Ethernet Controller for ISA (with Microsoft Plug n’ Play Support)

PCnet-32 Single-Chip 32-Bit Ethernet Controller

PCnet-PCI Single-Chip Ethernet Controller (for PCI bus)

PCnet-SCSI Combination Ethernet and SCSI Controller for PCI Systems

1–4

Am79C982

P R E L I M I N A R Y

CONNECTION DIAGRAM

PLCC

76

75

11 10 9 8 7

6

5

4

3 2 1 84 83 82 81 80 79 78 77

DO–

12

13

14

74

73

72

71

70

69

68

RXD7–

TXD7+

TXD7–

DV_SS

DO+

TXD0+

15

16

17

18

19

20

TXD0–

DV_SS

TXP7+

TXP7–

DV_DD

TXD6+

TXD6–

TXP0+

TXP0–

DV_DD

67

66

65

TXD1+

TXD1–

TXP1+

TXP1–

21

22

TXP6+

TXP6–

TXD5+

bIMR Chip

Am79C982-8

64

63

62

61

60

59

58

23

24

25

26

27

28

29

30

31

32

TXD2+

TXD2–

TXD5–

TXP5+

TXP2+

TXP2–

DV_DD

TXP5–

DV_DD

TXD4+

TXD3+

57

56

TXD4–

DV_SS

TXD3–

DV_SS

55

54

TXP4+

TXP4–

TXP3+

33 34 35 36 37 38 39 40 41 42 43 44 45 46 4748 49 50 51 52 53

19406B-2

Am79C982

1-5

P R E L I M I N A R Y

CONNECTION DIAGRAM

PLCC

76

75

11 10 9 8 7

6

5

4

3 2 1 84 83 82 81 80 79 78 77

DO–

12

13

14

74

73

72

71

70

69

68

RXD3–

TXD3+

DO+

NC

TXD3–

DV_SS

15

16

17

18

19

20

NC

DV_SS

TXP3+

NC

DV_DD

TXP3–

DV_DD

67

66

65

NC

TXD0+

TXD0–

TXP0+

TXP0–

NC

21

22

NC

bIMR Chip

Am79C982-4

64

63

62

61

60

59

58

NC

23

24

25

26

27

28

29

30

31

32

TXD2+

TXD2–

TXP2+

TXP2–

DVDD

NC

DV_DD

TXD1+

57

56

NC

DV_SS

TXD1–

DV_SS

55

54

NC

TXP1+

33 34 35 36 37 38 39 40 41 42 43 44 45 46 4748 49 50 51 52 53

19406B-3

Note:

Recommended to be tied together.

1-6

Am79C982

PRELIMINARY

AMD

LOGIC SYMBOL

DV_DD

AV_DD

TXD+

TXP+

DO+

DO–

Twisted Pair

Ports

(4 or 8 Ports)

TXD–

TXP–

DI+

DI–

AUI

RXD+

RXD–

CI+

CI–

Am79C982

DAT

JAM

SCLK

SI

SO

Management

Port

Expansion

Port

ACK

COL

REQ

X2

X1

CRS

STR

Port

Activity

Monitor

TEST

RST

DV_SS

AV_SS

19406B-4

LOGIC DIAGRAM

AUI

Repeater

State

Machine

Management

Port

Expansion

Port

Twisted Pair

Port n

Twisted Pair

Port 0

(Note)

19406B-5

Note: n=3 for Am79C982-4 and n=7 for Am79C982-8.

Am79C982

1–7

P R E L I M I N A R Y

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (valid combination) is formed

by a combination of the elements below.

Am79C982

J

C

OPTIONAL PROCESSING

Blank = Standard Processing

TEMPERATURE RANGE

C = Commercial (0°C to +70°C)

PACKAGE TYPE

J = 84-Pin Plastic Leaded Chip Carrier (PL 084)

SPEED OPTION

–8 = bIMR 8 10BASE-T ports

–4 = bIMR 4 10BASE-T ports

DEVICE NUMBER/DESCRIPTION

Am79C982

basic Integrated Multiport Repeater (bIMR)

Valid Combinations

Valid combinations list conﬁgurations planned to be sup-

ported in volume for this device. Consult the local AMD sales

ofﬁce to conﬁrm availability of speciﬁc valid combinations and

to check on newly released combinations.

Am79C982-4

Am79C982-8

JC

1–8

Am79C982

P R E L I M I N A R Y

occurred, the corresponding bit in the CRS output

PIN DESCRIPTION

ACK

stream will remain set for the 2-ms period and will be

reset at the end of this period.

Acknowledge

Input, Active LOW

DAT

Data

When this input is asserted, it signals to the requesting

bIMR device that it may control the DAT and JAM pins.

If the bIMR chip is not requesting control of the DAT line

(REQ pin HIGH), then the assertion of the ACK signal

indicates the presence of valid collision status on the

JAM or valid data on the DAT line.

Input/Output/3-State

In non-collision conditions, the active bIMR device will

drive DAT with NRZ data, including regenerated pre-

amble. During collision, when JAM = HIGH, DAT is

used to signal a multiport (DAT = 0) or single-port

(DAT = 1) condition.

AV_DD

When ACK is not asserted, DAT is in high impedance.

If REQ and ACK are both asserted, then DAT is an out-

put. If ACK is asserted and REQ not asserted, then

DAT is an input.

Analog Power

Power Pin

These pins supply +5 V to the RXD+/– receivers, the

DI+/– and CI+/– receivers, the DO+/– drivers, the inter-

nal PLL, and the internal voltage reference of the bIMR

device. These power pins should be decoupled and

kept separate from other power and ground planes.

This pin needs to be either pulled up or pulled down

through a high-value resistor.

DI+, DI–

AV_SS

Data In

Input

Analog Ground

Ground Pin

AUI port differential receiver. Signals comply with IEEE

802.3, Section 7.

These pins are the 0 V reference for AV_DD

.

DO+, DO–

COL

Data Out

Output

Expansion Collision

Input, Active LOW

AUI port differential driver. Signals comply with IEEE

802.3, Section 7.

When this input is asserted by an external arbiter, it sig-

niﬁes that more than one bIMR device is active and that

each bIMR device should generate the Collision Jam

sequence independently.

DV_DD

Digital Power

Power Pin

CI+, CI–

Control In

Input

These pins supply +5V to the logic portions of the bIMR

chip and the TXP+/–, TXD+/–, and DO+/– line drivers.

AUI port differential receiver. Signals comply with IEEE

802.3, Section 7.

DV_SS

Digital Ground

Ground Pin

CRS

Carrier Sense

Output

These pins are the 0 V reference for DV_DD.

DV_DDPin #

DV_SSPin #

Function

The states of the internal carrier sense signals for the

AUI port and the eight twisted-pair ports are serially

output on this pin continuously. The output serial bit

stream is synchronized to the X₁clock.

19

28

16

31

TP ports 0 & 1 drivers

TP ports 2 & 3 drivers

Core logic and expansion

and control pins

The resolution of the CRS signal is 2 ms. The incoming

data is sampled repeatedly during each 2-ms period. If

any activity occurs (regardless of length) during any

2-ms period, this activity will be latched. At the start of

the next 2-ms period the bIMR device will examine the

latches for each port. For any port for which activity

43, 49

35, 37, 46, 51

59

68

56

71

TP ports 4 & 5 drivers

TP ports 6 & 7 drivers

Am79C982

1–9

P R E L I M I N A R Y

In Minimum mode, the state of SI at the deassertion of

JAM

RST signal determines the programming of automatic

polarity detection/correction for 10BASE-T ports.

Jam

Input/Output/3-State

SO

When JAM is asserted, the state of DAT will indicate

either a multiport (DAT = 0) or single-port (DAT = 1) col-

lision condition.

Serial Out

Output

When ACK is not asserted, JAM is in high impedance.

If REQ and ACK are both asserted, then JAM is an out-

put. If ACK is asserted and REQ not asserted, then

JAM is an input.

In normal operating mode, the SO pin is used for test/

management serial output port. Management results

are clocked out on this pin synchronous to the SCLK

input. In Minimum mode, the SO pin is used to output

the various status information serially based on the

state of the SI and SCLK pins.

This pin needs to be either pulled up or pulled down

through a high-value resistor.

SCLK

SI

0

SO Output

REQ

TP Ports Receive Polarity Status + AUI

SQE Test Error Status

Request

Output, Active LOW

0

This pin is driven LOW when the bIMR chip is active. A

bIMR chip is active when it has one or more ports re-

ceiving or colliding or is in the state where it is still

transmitting data from the internal FIFO. The assertion

of this signal signiﬁes that the bIMR device is request-

ing the use of the DAT and JAM lines for the transfer of

repeated data or collision status to other bIMR devices.

0

1

Bit Rate Error (all ports)

TP Ports Link Status + AUI Loopback

Status

0

1

Port Partitioning Status (all ports)

STR

Store

Output

RST

Reset

Input, Active LOW

The STR pin goes HIGH for two X₁clock cycle times

after the nine carrier sense bits are output on the CRS

pin. Note that the carrier sense signals arriving from

each port are latched internally, so that an active tran-

sition is remembered between samples.

Driving this pin LOW resets the internal logic of the

bIMR device. Reset should be synchronized to the X₁

clock if either expansion or port activity monitor is used.

RXD+_0–7, RXD–_0–7(RXD+_0–3, RXD–_0–3

)

TEST

Receive Data

Input

Test Pin

Input, Active HIGH

10BASE-T port differential receive inputs (4 or 8 ports).

This pin should be tied LOW for normal operation. If

this pin is driven HIGH, then the bIMR device can be

programmed for Loopback Test mode. Also, if this pin is

HIGH when the RST pin is deasserted, the bIMR de-

vice will enter the Minimum mode. An inverted version

of the RST signal can be used to program the device

into the Minimum mode.

SCLK

Serial Clock

Input

In normal operating mode, serial data (input or output)

is clocked (in or out) on the rising edge of the signal on

this pin. SCLK is asynchronous to X₁and can operate

up to 10 MHz. In Minimum mode, this pin, together with

the SI pin, controls which information is output on the

SO pin.

Test

SI

0

Functions

Normal Management Mode

Minimum Mode, Receive

Polarity Correction Disabled

Minimum Mode, Receive

Polarity Correction Enabled

0

1

SI

0

Serial In

Input

In normal operating mode, the SI pin is used for test/

management serial input port. Management com-

mands are clocked in on this pin synchronous to the

SCLK input. In Minimum mode, this pin, together with

the SCLK pin, controls which information is output on

the SO pin.

1

1–10

Am79C982

P R E L I M I N A R Y

TXD+_0–7, TXD–_0–7(TXD+_0–3, TXD–_0–3

)

X₁

Transmit Data

Output

Crystal 1

Crystal Connection

10BASE-T port differential drivers (4 or 8 ports).

The internal clock generator uses a 20 MHz crystal at-

tached to pins X₁and X₂. Alternatively, an external

20MHz CMOS clock signal can be used to drive this

pin.

TXP+_0–7, TXP–_0–7(TXP+_0–3, TXP–_0–3

)

Transmit Predistortion

Output

X₂

10BASE-T transmit waveform predistortion control

differential outputs (4 or 8 ports).

Crystal 2

Crystal Connection

The internal clock generator uses a 20 MHz crystal at-

tached to pins X₁and X₂. If an external clock source is

used, this pin should be left unconnected.

Am79C982

1–11

PRELIMINARY

conditions correctly as specified in Section 9 of the

AMD

FUNCTIONAL DESCRIPTION

802.3 specification.

The Am79C982 Basic Integrated Multiport Repeater

device is a single chip implementation of an IEEE

802.3/Ethernet repeater (or hub). It is offered either with

four or eight integral 10BASE-T ports plus one AUI port

comprising the basic repeater. The bIMR device is also

expandable, enabling the implementation of high port

count repeaters based on several bIMR devices.

Fragment Extension

If the total packet length received by the bIMR device is

less than 96 bits, including preamble, the bIMR chip will

extend the repeated packet length to 96 bits by append-

ing a Jam sequence to the original fragment.

Auto Partitioning/Reconnection

The bIMR chip complies with the full set of repeater ba-

sic functions as defined in section 9 of ISO 8802.3

(ANSI/IEEE 802.3c). These functions are summarized

below.

Any of the integral TP ports and AUI port can be parti-

tioned under excessive duration or frequency of colli-

sion conditions. Once partitioned, the bIMR device will

continue to transmit data packets to a partitioned port,

but will not respond (as a repeater) to activity on the par-

titioned port’s receiver. The bIMR chip will monitor the

port and reconnect it once certain criteria indicating port

‘wellness’ are met. The criteria for reconnection are

specified by the 802.3 standard. In addition to the stan-

dard reconnection algorithm, the bIMR device imple-

ments an alternative reconnection algorithm which

provides a more robust partitioning function for the TP

ports and/or the AUI port. Each TP port and the AUI port

are partitioned and/or reconnected separately and inde-

pendently of other network ports.

Repeater Function

If any single network port senses the start of a valid

packet on its receive lines, then the bIMR device will re-

transmit the received data to all other enabled network

ports. The repeated data will also be presented on the

DAT line to facilitate multiple-bIMR device repeater

applications.

Signal Regeneration

When re-transmitting a packet, the bIMR device en-

sures that the outgoing packet complies with the 802.3

specificationintermsofpreamblestructure, voltageam-

plitude, and timing characteristics. Specifically, data

packets repeated by the bIMR chip will contain a mini-

mum of 56 preamble bits before the Start of Frame De-

limiter. In addition, the voltage amplitude of the repeated

packet waveform will be restored to levels specified in

the 802.3 specification. Finally, signal symmetry is re-

stored to data packets repeated by the bIMR device, re-

moving jitter and distortion caused by the network

cabling.

Either one of the following conditions occuring on any

enabled bIMR device network port will cause the port to

partition:

a. A collision condition exists continuously for a time

between 1024- to 2048-bit times (AUI port—SQE

signal active; TP port—simultaneous transmit and

receive)

b. A collision condition occurs during each of 32 con-

secutive attempts to transmit to that port.

Jabber Lockup Protection

Once a network port is partitioned, the bIMR device will

reconnect that port if the following is met:

The bIMR chip implements a built-in jabber protection

scheme to ensure that the network is not disabled due to

transmission of excessively long data packets. This pro-

tection scheme will automatically interrupt the transmit-

ter circuits of the bIMR device for 96-bit times if the bIMR

device has been transmitting continuously for more than

65,536-bit times. This is referred to as MAU Jabber

Lockup Protection (MJLP). The MJLP status for the

bIMR chip can be read through the Management Port

using the Get MJLP Status command (M bit

returned).

a. Standard reconnection algorithm—A data packet

longer than 512-bit times (nominal) is transmitted or

received by the partitioned port without a collision.

b. Alternate reconnection algorithm—A data packet

longer than 512-bit times (nominal) is transmitted by

the partitioned port without a collision.

The reconnection algorithm option (standard or alter-

nate) is a global function for the TP ports, i.e. all TP ports

use the same reconnection algorithm. The AUI recon-

nection algorithm option is programmed independently

of the TP port reconnection option.

Collision Handling

The bIMR chip will detect and respond to collision condi-

tions as specified in 802.3. A multiple-bIMR device re-

peater implementation also complies with the 802.3

specification due to the inter-bIMR chip status commu-

nication provided by the expansion port. Specifically, a

repeater based on one or more bIMR devices will

handle the transmit collision and one-port-left collision

Link Test

The integral TP ports implement the Link Test function

as specified in the 802.3 10BASE-T standard. The bIMR

device will transmit Link Test pulses to any TP port after

1–12

Am79C982

PRELIMINARY

that port’s transmitter has been inactive for more than 8

AMD

Reset

to 17 ms. Conversely, if a TP port does not receive any

data packets or Link Test pulses for more than 65 to

132 ms and the Link Test function is enabled for that

port then that port will enter link fail state. A port in link

fail state will be disabled by the bIMR chip (repeater

transmit and receive functions disabled) until it receives

either four consecutive Link Test pulses or a data pack-

et. The Link Test receive function itself can be disabled

via the bIMR chip management port on a port-by-port

basis to allow the bIMR device to interoperate with

pre-10BASE-T twisted pair networks that do not imple-

ment the Link Test function. This interoperability is pos-

sible because the bIMR device will not allow the TP port

to enter link fail state, even if no Link Test pulses or data

packetsarebeingreceived. NotehoweverthatthebIMR

chip will always transmit Link Test pulses to all TP ports

regardless of whether or not the port is enabled, parti-

tioned, in link fail state, or has its Link Test receive func-

tion disabled.

The bIMR device enters reset state when theRST pin is

driven LOW. After the initial application of power, the

RST pin must be held LOW for a minimum of 150 µs

(3000 X1 clock cycles). If the RST pin is subsequently

asserted while power is maintained to the bIMR device,

a reset duration of only 4 µs is required. The bIMR chip

continues to be in the reset state for 10 X1 clocks

(0.5 µs) following the rising edge of RST. During reset,

the output signals are placed in their inactive states.

This means that all analog signals are placed in their idle

states, bidirectional signals are not driven, active LOW

signals are driven HIGH, and all active HIGH signals

and the STR pin are driven LOW.

An internal circuit ensures that a minimum reset pulse is

generated for all internal circuits. For a RST input with a

slow rising edge, the input buffer threshold may be

crossed several times due to ripple on the input

waveform.

In a multiple bIMR chip repeater the RST signal should

be applied simultaneously to all bIMR devices and

should be synchronized to the external X1 clock. Reset

synchronization is also required when accessing the

PAM (Port Activity Monitor).

Polarity Reversal

The TP ports have the optional (programmable) ability

to invert (correct) the polarity of the received data if the

TP port senses that the received data packet waveform

polarity is reversed due to a wiring error. This receive

circuitry polarity correction allows subsequent packets

to be repeated with correct polarity. This function is exe-

cuted once following reset or link fail, and has a pro-

grammable enable/disable option on a port-by-port

basis. This function is disabled upon reset and can be

enabled via the bIMR chip Management Port.

The SI signal should be held HIGH for at least 500 ns fol-

lowing the rising edge of RST.

Table 1 summarizes the state of the bIMR chip following

reset.

Table 1. bIMR Chip After Reset

State After Reset

Function

Active LOW outputs

Pull Up/Pull Down

HIGH

LOW

HIGH

No

Active HIGH outputs

SO Output

No

DAT, JAM

HI-IMPEDANCE

LOW

Either

No

STR

Transmitters (TP and AUI)

Receivers (TP and AUI)

AUI Partitioning/Reconnection Algorithm

TP Port Partitioning/Reconnection Algorithm

Link Test Function for TP Ports

Automatic Receiver Polarity Reversal Function

IDLE

No

ENABLED

Terminated

N/A

STANDARD ALGORITHM

ENABLED, TP PORTS IN LINK FAIL

DISABLED

N/A

Am79C982

1–13

PRELIMINARY

than one active bIMR device at a time constitutes a colli-

AMD

Expansion Port

sion condition, and all bIMR devices are notified of this

occurence via the COL line of the Expansion Port.

The bIMR chip Expansion Port is comprised of five pins;

two are bi-directional signals (DAT and JAM), two are in-

put signals (ACK and COL), and one is an output signal

(REQ). These signals are used when a multiple-bIMR

device repeater application is employed. In this configu-

ration, all bIMR chips must be clocked synchronously

with a common clock connected to the X1 inputs of all

bIMR devices. Reset needs to be synchronized to

X1 clock.

Note that a transition from multiple bIMR devices arbi-

trating for the DAT and JAM pins (with COL asserted,

ACK deasserted) to a condition when only one bIMR

chip is arbitrating for the DAT and JAM pins (with ACK

asserted, COLdeasserted) involves one expansion port

bus cycle (100 ns). During this transitional bus cycle,

COL is deasserted, ACK is asserted, and the DAT and

JAM pins are not driven. However, each bIMR device

will remain in the collision state (transmitting jam se-

quence) during this transitional bus cycle. In subse-

quent expansion port bus cycles (REQ and ACK still

asserted), the bIMR devices will return to the ‘master

and slaves’ condition where only one bIMR device is ac-

tive (with collision) and is driving the DAT and JAM pins.

An understanding of this sequence is crucial if non-

bIMR devices (such as an Ethernet controller) are con-

nected to the expansion bus. Specifically, the last

device to back off of the Expansion Port after a multi-

bIMR chip collision must assert the JAM line until it too

drops its request for the Expansion Port.

The bIMR device expansion scheme allows the use of

multiple bIMR chips in a single board repeater or a

modular multiport repeater with a backplane architec-

ture. The DAT pin is a bidirectional I/O pin which can be

used to transfer data between the bIMR devices in a

multiple-bIMR chip design. The data sent over the DAT

line is in NRZ format and is synchronized to the common

clock. The JAM pin is another bidirectional I/O pin that is

used by the active bIMR chip to communicate its internal

status to the remaining (inactive) bIMR devices. When

JAM is asserted HIGH, it indicates that the active bIMR

device has detected a collision condition and is generat-

ing Jam Sequence. During this time when JAM is as-

serted HIGH, the DAT line is used to indicate whether

the active bIMR chip is detecting collision on one port

only or on more than one port. When DAT is driven

HIGH by the bIMR chip (while JAM is asserted by the

bIMR chip), then the active bIMR device is detecting a

collision condition on one port only. This ‘one-port-left’

signaling is necessary for a multiple-bIMR device re-

peatertofunctioncorrectlyasasinglemultiportrepeater

unit. The bIMR chip also signals the ‘one port left’ colli-

sion condition in the event of a runt packet or collision

fragment; this signal will continue for one expansion port

bus cycle (100 ns) before deasserting REQ.

External Arbiter

A simple arbitration scheme is required when multiple

bIMR devices are connected together to increase the to-

tal number of repeater ports. The arbiter should have

one input (REQ1...REQn) for each of the n bIMR de-

vices to be used, and two global outputs (COL and

ACK). This function is easily implemented in a PAL de-

vice, with the following logic equations:

ACK = REQ1 & REQ2 & REQ3 & ....REQn

+

REQ1 & REQ2 & REQ3 & ....REQn

•

The arbitration for access to the bussed bi-directional

signals (DAT and JAM) is provided by one output (REQ)

and two inputs (ACK and COL). The bIMR chip asserts

the REQ pin to indicate that it is active and wishes to

drive the DAT and JAM pins. An external arbiter senses

the REQ lines from all the bIMR devices and asserts the

ACK line when one and only one bIMR chip is asserting

its REQ line. If more than one bIMR chip is asserting its

REQ line, the arbiter must assert the COL signal, indi-

cating that more than one bIMR device is active. More

+

REQ1 & REQ2 & REQ3 & .... REQn

COL = ACK & (REQ1 + REQ2 + REQ3 + ... REQn)

Above equations are in positive logic, i.e., a variable is

true when asserted.

A single PALCE16V8 will perform the arbitration func-

tion for a repeater based on several bIMR devices.

1–14

Am79C982

PRELIMINARY

AMD

Bus transceivers needed

if DAT and JAM buses

exceed 100 pF loading.

REQ2 REQ3 REQ1

COL

ARBITER

ACK

REQ

DIR

DAT

JAM

Note 1

A

B

REQ

ACK

1/2 ’74

ASYNC

RESET

Am79C982

bIMR Chip

1

D

D FF

CK

COL

RST

Q

X1

XTAL

OSC.

REQ

ACK

COL

RST

X1

DAT

JAM

Am79C982

bIMR Chip

2

REQ

ACK

DAT

JAM

COL Am79C982

bIMR Chip

3

RST

Note 1:

X1

Direction

DIR

19406B-6

B → A

A → B

LOW

HIGH

Figure 1. Multiple bIMR Devices

repeater based on modular ‘plug-in’ cards. Each repeat-

er module performs the local arbitration function for the

bIMR devices on that module, and provides signals to

the backplane for use by a global arbiter.

Modular Repeater Design

The expansion port of the bIMR chip also allows for

modular expansion. By sharing the arbitration duties be-

tween a backplane bus architecture and several sepa-

rate repeater modules one can build an expandable

Am79C982

1–15

PRELIMINARY

AMD

necessary due to the low bus loading in this example. In

this case, the arbiter simply assertsACK if one REQ sig-

nal is asserted and COL if both REQ signals are as-

serted. Thearbiterdoesnotasserteithersignalifneither

REQ is asserted. Note that bothACK and COL are logic

low when asserted.

Implementing a 12-Port Unmanaged Hub

Both bIMR4 and bIMR8 chips have an expansion bus

that allows multiple devices to be connected together,

allowing high port count repeaters to be designed. The

operation of the expansion bus is identical for the bIMR4

and bIMR8. Minimum Mode is available in both bIMR4

and bIMR8 devices. This mode facilitates the

implementation of the LED display for unmanaged hub.

The D type flip flop is used to synchronize the reset

signals to both bIMR devices in order to ensure that the

internal 10 MHz clocks of these devices are in phase.

Figure 2 shows a simple example where one four port

bIMR device and one eight port bIMR device are con-

nected together to form one twelve port logical

unmanaged repeater. As both devices are on the same

board the arbiter function can be local, and the bus

transceivers shown at right in Figure 1 are not

More complex repeaters, including stackable hubs, may

be built using the bIMR family. In these cases, the bus

transceivers may be necessary and the arbitration may

be distributed throughout the system.

1–16

Am79C982

PRELIMINARY

AMD

REQ1

ARBITER

REQ2

REQ ACK COL DAT JAM

CRS

X1

CRS

X1

20 MHz CLK

bIMR8

SO

bIMR4

SO

STR

RST

TEST

ASYNC

RESET

SI SCLK

Q

D

Q

CK

CLR

5 V

Q

D

SW 1

5 V

Q

CK

CLR

Q

CK

CLR

SI

CK

SI

SI SHIFT REG

CK

SI SHIFT REG

CK

SHIFT REG

CK

PORT ACTIVITY LEDS

PORT STATUS LEDS

19406B-7

Notes:

1. Both bIMR8 and bIMR4 devices are used in Minimum Mode.

2. The information displayed by Port Status LEDs is selected by SW1. In thisdesign, only Link Status and Port Partition Status can

be selected. Users can implement more display options by changing the state of the SCLK input (see the section on Minimum

Mode for detail).

3. The Polarity correction feature is shown disabled since the SI is high at reset. Users can enable this feature by keeping the SI

input low upon reset.

Figure 2. Implementing a 12-Port Unmanaged Hub using a bIMR8 and a bIMR4

Am79C982

1–17

PRELIMINARY

setup and hold times with respect to the input bit pattern.

AMD

Management Port

If the latter method is used, it is to be noted that 20 SCLK

clock transitions are required for proper execution of

management commands that produce SO data, and

that 14 SCLK clock transitions are needed to execute

management commands that do not produce SO data.

The bIMR device management functions are enabled

when the TEST pin is tied LOW. The management com-

mands are byte oriented data and are input serially on

the SI pin. Any responses generated during execution of

a management command are output serially in a byte-

oriented format by the bIMR device on the SO pin. Both

the input and output data streams are clocked with the

rising edge of the SCLK pin. The serial command data

stream and any associated results data stream are

structured in a manner similar to the RS232 serial data

format, i.e., one Start Bit followed by eight Data Bits.

Management Commands

The following section details the operation of each man-

agement command available in the bIMR chip. In all

cases, the individual bits in each command byte are

shown with the MSB on the left and the LSB on the right.

Data bytes are received and transmitted LSB first and

MSB last. See Table 2 for a summary of the manage-

ment commands.

The externally generated clock at the SCLK pin can be

either a free running clock synchronized to the input bit

patterns or a series of individual transitions meeting the

Command Execution Phase

Results Phase

Next Command

SCLK

SI

STRT D0 D1 D2 D3 D4 D5 D6 D7

SO

STRT D0 D1 D2 D3 D4 D5 D6 D7

19406B-8

Management Command/Response Timing

Command Execution Phase

Next Command Execution Phase

SCLK

SI

STRT D0 D1 D2 D3 D4 D5 D6 D7

19406B-9

SO

Management Command Timing with No Response

1–18

Am79C982

PRELIMINARY

AMD

Table 2. Management Port Command Summary

Commands

SI Data

SO Data

Set (Write) Opcodes

bIMR Chip Programmable Options

Alternate AUI Partitioning Algorithm

Alternate TP Partitioning Algorithm

AUI Port Disable

0000 10SA

0001 1111

0001 0000

0010 1111

AUI Port Enable

0011 1111

TP Port Disable

0010 0### (note 2)

0011 0###

TP Port Enable

Disable Link Test Function (per TP port)

Enable Link Test Function (per TP port)

Disable Automatic Receiver Polarity Reversal (per TP port)

Enable Automatic Receiver Polarity Reversal (per TP port)

Get (Read) Opcodes

0100 0###

0101 0###

0110 0###

0111 0###

AUI Port Status (B, S, L Cleared)

1000 1111

1000 0000

PBSL 0000

TP Port Partitioning Status

C7...C0 (bIMR8),

C3...C0 (bIMR4)

Bit Rate Status of TP ports

1010 0000

1101 0000

1110 0000

E7...E0 (bIMR8),

E3...E0 (bIMR4)

Link Test Status of TP ports

L7...L0 (bIMR8),

L3...L0 (bIMR4)

Receive Polarity Status of all TP ports

P7...P0 (bIMR8),

P3...P0 (bIMR4)

MJLP Status

1111 0000

1111 1111

1000 1011

1000 1101

1000 1001

M000 0000

XXXX 0101

PBSL 0000

Version

AUI Port Status (S, L Cleared)

AUI Port Status (B Cleared)

AUI Port Status (None Cleared)

Notes:

1. Unused opcodes are reserved for future use.

2. Select code for the twisted pair ports (TP0 to TP7).

###

000

001

010

011

100

101

110

111

bIMR8

TP0

TP1

TP2

TP3

TP4

TP5

TP6

TP7

bIMR4

—

TP0

—

TP1

—

TP2

—

TP3

Am79C982

1–19

PRELIMINARY

stream) are masked if the port is either disabled or parti-

AMD

SET (Write) Opcodes

bIMR Chip Programmable Options

tioned. This does not allow the Repeater Management

software to sense activity on all segments at all times.

Theabilitytomonitorpartitionedordisabledportsallows

faulttolerancetobebuiltintotheRepeaterManagement

software.

SI data:

0000 10SA

SO data: None

bIMR Chip Programmable Options can be enabled (dis-

abled) by setting (resetting) the appropriate bit in the

command string. The two programmable bits are:

S—AUI SQE Test Mask, and A—Alternative Port Activ-

ity Monitor (PAM) Function. These options can be en-

abled (disabled) by setting (resetting) the appropriate bit

in the command string.

Alternate AUI Port Partitioning Algorithm

SI data:

00011111

SO data: None

The AUI port Partitioning/Reconnection scheme can be

programmed for the alternate (transmit only) reconnec-

tion algorithm by invoking this command. To return the

AUI back to the standard (transmit or receive) reconnec-

tion algorithm, it is necessary to reset the bIMR device.

Standard partitioning algorithm is selected upon reset.

S—AUI SQE Test Mask

Setting this bit allows the bIMR chip to ignore activity on

the CI signal pair, in the SQE Test Window, following a

transmission on the AUI port. This event occurs when

the attached MAU has the SQE Test option enabled,

thereforegeneratingaburstofCIactivityfollowingevery

transmission. This is interpreted by the bIMR device as

a collision, causing the bIMR device to generate a full

Jam pattern. Although the MAU attached to a repeater is

required not to have its SQE test function active, this is a

common installation error, causing difficulty in diagnos-

ing network throughput problems.

Alternate TP Ports Partitioning Algorithm

SI data:

00010000

SO data: None

The TP ports Partitioning/Reconnection scheme can be

programmed for the alternate (transmit only) reconnec-

tion algorithm by invoking this command. All TP ports

are affected as a group by this command. To return the

TP ports back to the standard (transmit or receive) re-

connection algorithm, it is necessary to reset the bIMR

device. The standard partitioning algorithm is selected

upon reset.

The SQE Test Window, as defined by the IEEE 802.3

(Section 7.2.2.2.4), is from 6-bit times to 34-bit times

(0.6 µs to 3.4 µs). This includes delay introduced by a

50 m AUI. CI activity that occurs outside this window is

not ignored and is treated as true collision.

AUI Port Disable

SI data:

00101111

SO data: None

Note that enabling this function does not prevent the re-

porting of this condition by the bIMR device and the two

functions operate independently.

The AUI port will be disabled upon receiving this com-

mand. Subsequently, the bIMR chip will ignore all inputs

(Carrier Sense and SQE) appearing at the AUI port and

will not transmit any data or Jam Sequence on the AUI

port. Issuing this command will also cause the AUI port

to have its internal partitioning state machine forced to

its idle state. Therefore, a Partitioned Port may be re-

connected by first disabling and then re-enabling

the port.

A—Alternative Port Activity Monitor (PAM)

Function

Setting the Alternative Port Activity Monitor Function al-

lows the PAM function to be altered such that the Carrier

Sense data is presented unmodified. In default opera-

tion the PAM output (Carrier Sense bits in the CRS bit

1–20

Am79C982

PRELIMINARY

Enable Link Test Function of a TP Port

SI data: 01010###

AMD

AUI Port Enable

SI data:

SO data: None

00111111

SO data: None

This command enables a previously disabled AUI port.

Note that a partitioned AUI port may be reconnected by

first disabling (AUI Port Disable Command) and then re-

enabling the port with this command.

(### selects TP port number,

see note 2 on page 17)

This command re-enables the Link Test Function in the

TP port designated in the command byte. This com-

mand executes only if the designated TP port has had

the Link Test Function disabled by the Disable Link Test

Function command. Otherwise, the command is ig-

nored. Link Test is enabled upon reset.

All ports are enabled upon reset.

TP Port Disable

SI data:

00100###

SO data: None

Disable Automatic Receiver Polarity Reversal

(### selects TP port number,

see note 2 on page 17)

SI data:

01100###

SO data: None

The TP port designated in the command byte will be dis-

abled upon receiving this command. Subsequently, the

bIMR device will ignore all inputs appearing at the dis-

abledport’sreceivepinsandwillnottransmitanydataor

JAM Sequence on that port’s transmit pins. Issuing this

command will also cause a TP port to have its partition-

ing state machine returned to its Idle State (Port Recon-

(### selects TP port number,

see note 2 on page 17)

ThiscommanddisablestheAutomaticReceiverPolarity

Reversal Function for the TP port designated in the

command byte. If this function is disabled on a TP port

with reverse polarity (due to a wiring error), then the TP

port will fail Link Test due to the reversed polarity of the

Link Pulses. If the Link Test Function is also disabled on

the TP port, then the received reversed polarity packets

would be repeated to all other network ports in the bIMR

chip as inverted data. Automatic Polarity reversal is dis-

abled upon reset.

nected). Therefore,

a partitioned port may be

reconnected by first disabling and then re-enabling the

port. The disabled port will continue to report correct

Link Test Status.

TP Port Enable

SI data:

SO data: None

00110###

Enable Automatic Receiver Polarity Reversal

SI data:

SO data: None

01110###

(### selects TP port number,

see note 2 on page 17)

(### selects TP port number,

see note 2 on page 17)

This command enables a previously disabled TP port.

Re-enablingadisabledportcausestheporttobeplaced

into Link Test Fail state. This ensures that packet frag-

mentsreceivedontheportarenotrepeatedtotherestof

the network. Note that to force a TP port into the Link Fail

state and/or to reconnect a partitioned TP port, the port

should first be disabled (TP Port Disable Command)

and then re-enabled with this command. All ports are

enabled upon reset.

This command enables the Automatic Receiver Polarity

Reversal Function for the TP port designated in the

command byte. If enabled in a TP port, the bIMR chip

will automatically invert the polarity of that TP port’s re-

ceiver circuitry if the TP port is detected as having re-

versed polarity (due to a wiring error). After reversing

the receiver polarity, the TP port could then receive sub-

sequent (reverse polarity) packets correctly.

Disable Link Test Function of a TP Port

GET (Read) Opcodes

SI data:

01000###

SO data: None

AUI Port Status

(### selects TP port number,

see note 2 on page 17)

SI data:

SO data: PBSL0000

10001111

The combined AUI status allows a single instruction to

be used for monitoring AUI port. The four status bits re-

ported are:

This command disables the Link Test Function at the TP

port designated in the command byte, i.e., the TP port

will no longer be disconnected due to Link Fail. A TP port

which has its Link Test Function disabled will continue to

transmit Link Test Pulses. If a twisted pair port has Link

Test disabled, then reading the Link Test Status indi-

cates it being in Link Test Pass.

P Partitioning Status. This bit is 0 if the AUI port is

partitioned and 1 if connected.

Am79C982

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PRELIMINARY

AMD

B Bit Rate Error. This bit is set to 1 if there has been an

instance of FIFO Overflow or Underflow, caused by

datareceivedattheAUIport. Thisbitisclearedwhen

the status is read.

Ln = 0

Ln = 1

TP Port n in Link Test Fail

TP Port n in Link Test Pass

The Link Test Status of all eight (four) TP ports are ac-

cessed by this command. A disabled port continues to

report correct Link Test Status. Re-enabling a disabled

port causes the port to be placed into Link Test Fail

state. This ensures that packet fragments received on

the port are not repeated to the rest of the network.

S SQE Test Status. This bit is set to 1 if SQE Test is

detected by the bIMR chip. This bit is cleared when

the status is read. A MAU attached to a repeater

must have SQE Test disabled. This bit is set even if

the AUI port is disabled or partitioned.

L

Loop Back Error. The MAU attached to the AUI is

required to loopback data transmitted to DO onto the

DI circuit. If loopback carrier is not detected by the

bIMR device, then this bit is set to 1 to report this

condition. This bit is cleared when the status is read.

For a repeater this is the only indication of a broken

or missing MAU.

Receive Polarity Status of TP Ports

SI data:

11100000

SO data: P7....................P0 (bIMR8)

SO data: P3 X P2 X P1 X P0 (bIMR4)

X = don’t care

Pn = 0

Pn = 1

TP Port n Polarity Correct

TP Port n Polarity Reversed

TP Port Partitioning Status

SI data:

10000000

The statuses of all eight (four) TP port polarities are ac-

cessed with this command. The bIMR chip has the abil-

ity to detect and correct reversed polarity on the TP

ports’ RXD+/– pins. If the polarity is detected as re-

versed for a TP port, then the bIMR chip will set the ap-

propriate bit in this command’s result byte only if the

Polarity Reversal Function is enabled for that port.

SO data: P7....................P0 (bIMR8)

SO data: P3 X P2 X P1 X P0 (bIMR4)

X = don’t care

Pn = 0

Pn = 1

TP port n partitioned

TP port n connected

The partitioning Status of all four or eight TP ports are

accessed by this command. If a port is disabled, reading

it partitioning status will indicate that it is connected.

MJLP Status

SI data:

SO data: M00000000

11110000

Bit Rate Error Status of TP Ports

Each bIMR chip contains an independent MAU Jabber

Lock Up Protection Timer. The timer is designed to in-

hibit the bIMR device transmit function, if it has been

transmitting continuously for more than 65536 Bit

Times. The MJLP Status bit (M) is set to 1 if this hap-

pens. This bit remains set and is only cleared when the

MJLP status is read by using this command.

SI data:

10100000

SO data: E7....................E0 (bIMR8)

SO data: E3 X E2 X E1 X E0 (bIMR4)

X = don’t care

This allows a single command to be used to report Bit

Rate Error condition (FIFO Overflow or Underflow) of all

Twisted Pair ports. The 8 bits (4 bits) of the output pat-

tern correspond to each of the 8 TP (4 TP) ports, with

least significant bit corresponding to port 0.

Version

SI data:

11111111

SO data: XXXX0001

The status bit for a port is set to 1 if there has been an

instance when data received from that port has caused

a FIFO error.

This command (1111 1111) can be used to determine

the device version.

The bIMR chip responds by the bit pattern: XXXX 0101

All status bits stay set until the status is read.

Link Test Status of TP Ports

SI data:

11010000

SO data: L7....................L0 (bIMR8)

SO data: L3 X L2 X L1 X L0 (bIMR4)

X = don’t care

1–22

Am79C982

PRELIMINARY

AMD

In Minimum Mode, the SO pin is used to serially output

the various status information based on the state of the

SI and SCLK pins. A summary of the status information

is provided in the following table.

Minimum Mode

The Minimum Mode reconfigures the bIMR device Man-

agement Port and is intended to provide support for the

low end, non-managed repeaters, requiring minimal ex-

ternal logic to provide LED indication of:

SCLK

SI

SO Output

■ Twisted Pair Ports Link Status indication and AUI

0

TP Ports Receive Polarity Status +

AUI SQE Test Error Status.

Loopback Status

■ Port Partitioning Status

0

1

0

Bit Rate Error (all ports).

■ Twisted Pair Ports Receiver Polarity Status and

TP Ports Link Status + AUI

LoopBack Status

AUI SQE Test Error Status

■ Port Bit Rate Error Status

1

Port Partitioning Status (all ports)

The Minimum Mode is selected by controlling the state

of the TEST pin while RST is asserted. If TEST is High

(asserted), while reset is active (RST LOW), then Mini-

mum Mode is selected. The state of SI pin, at the de-

assertion of the RST signal, determines whether the

bIMR chip is to be programmed for Automatic Polarity

Detection/Correction.

When SI = 0 then SO will output the related AUI status

bits (LoopBack or SQE), followed by the 8 (4) TP status

bits (Link or Polarity), starting with the TP port 0.

When SI = 1, the Port Partitioning Status or Port Bit Rate

Error Status are scanned out with the AUI first and TP

ports following. TP Port 0 is scanned out first.

When entering the Minimum Mode, the TEST input has

to be deasserted on the rising edge of reset. A maximum

delay of 100 ns is allowed to account for slow devices.

The following table summarizes the different modes

available.

Note that the Bit Rate Error, AUI Loopback, and AUI

SQE Test Error status bits stay set until they are

scanned out.

The state of SI and SCLK inputs is checked at the end of

every STR cycle. The rising edge of the X1 clock, occur-

ring before falling edge of STR, is used to strobe in the

state of the SI and SCLK pins.

Test

SI

0

Functions

0

1

Normal Management Mode

1

In this Minimum Mode, the Management Port mode is

not active. To exit the Minimum mode, the bIMR device

must reset into the normal Management Port mode.

0

Minimum Mode, Receive

Polarity Correction disabled

1

Minimum Mode, Receive

Polarity Correction enabled

1/2 ’74

TCK

D

Q

TCK

CK

Q

CLR

XTAL

OSC

X1

X2

CK

SI

SIPO

SO

Am79C982

bIMR8 Chip

1/2 ’74

RST

CK

D

Q

CK

Register

STR

ASYNC

RESET

TEST

T T T

P P P

7 6 5

T A

P U

SCLK SI

19406B-10

0

I

Figure 3. bIMR8 LED Display Design using Minimum Mode

Am79C982

1–23

PRELIMINARY

AMD

X1

TCK

(Note 1)

CRS

AUI

CRS

TP0

CRS

TP1

CRS

TP2

CRS

TP3

CRS

TP4

CRS

TP5

CRS

TP6

CRS

TP7

CRS

AUI

CRS

SO

AUI

SO

TP0

SO

TP1

SO

TP2

SO

TP3

SO

TP4

SO

TP5

SO

TP6

SO

TP7

SO

AUI

SO

(Note 2)

STR

Notes:

19406B-11

1. Externally generated signal illustrates internal bIMR chip clock phase relationship.

2. For Minimum Mode

Figure 4. bIMR8 Management Port Minimum Mode and

Port Activity Monitor Signal Relationship

Q

D

CK

Q

CK

Q

CLR

SHCK

CK

XTAL

OSC

X1

CRS or

SO (Note)

Shift Register

Register

SI

bIMR4 Chip

RST

CK

Q

CK

STR

ASYNC

RESET

Q

D

T

P

3

T

P

2

T

P

1

T

P

0

A

U

I

Note: When used in minimum mode.

19406B-12

Figure 5. bIMR4 LED Display Design using Minimum Mode

‘

1–24

Am79C982

PRELIMINARY

AMD

1

2

10 12

16

20

24

28

32

X1

RST

SHCK

CRS

AUI

TP0

TP1

TP2

TP3

SO

(Note)

STR

19406B-13

Note: When used in minimum mode.

Figure 6. bIMR4 Management Port Minimum Mode and Port Activity Monitor Signal Relationship

1000 ns of the 2 ms period, the CRS signal is reset to

Port Activity Monitor

LOW. Figure 7 illustrates this by showing the output of

Two pins, CRS and STR, are used to serially output the

the register in the recommended LED drive circuitry of

state of the internal Carrier Sense signals from the AUI

Figure 8.

and the eight (four) TP ports. This function together with

external hardware and/or software can be used to moni-

tor repeater receive and/or collision activity.

The CRS pin is used to indicate carrier sense for all nine

ports of the device (five for the Am79C982-4). This pin

outputsatenbitstreamthatrepeatseverymicrosecond.

During this period there are ten bit times (100 ns). Each

port has a “time slot” in this repeating bit stream (see

Figure 4). For example, activity on the AUI port is repre-

sented by the state of the CRS pin during the second

100 ns period of the one microsecond cycle.

The resolution of the CRS signal is 2 ms. The incoming

data is sampled repeatedly during each 2 ms period. If

any activity occurs (regardless of length) during any

2 ms period, this activity will be latched. At the start of

the next 2 ms period, the bIMR device will examine the

latches for each port. For any port in which activity

occurred, the corresponding bit in the CRS output

stream will remain set for the 2 ms period. This means

that during any 2 ms time interval the CRS output bit

stream represents carrier activity that occurred in the

preceding 2 ms period (see Figure 7). During the last

Because the one microsecond sequence is repeated

unchanged for most of the longer 2 ms cycle, any LED

driven by the latch and shift register shown in Figure 3

and 5 will remain on for at least 2 ms. This minimizes the

need for external pulse stretching logic.

2 ms

1000 ns

TPX

or AUI

CRS

19406B-14

Figure 7. Carrier Sense Signal Output Corresponding to the

States of AUI or Twisted-Pair Port Activity

Am79C982

1–25

PRELIMINARY

AMD

1/2 ’74

TCK

D

Q

CK

Q

CLR

Shift Register

SIPO

XTAL

OSC

X1

CK

SI

CRS

Am79C982

bIMR8 Chip

X2

1/2 ’74

RST

CK

D

Q

CK

Register

STR

ASYNC

RESET

T T T

P P P

7 6 5

T A

P U

0

I

Carrier Sense Outputs

19406B-15

Figure 8a. bIMR8 Port Activity Monitor Implementation

1–26

Am79C982

APPENDIX

1 0 BAS E-T INTERFACE

A

The table below lists the recommended resistor values and ﬁlter and transformer modules for the IMR+ device.

b IMR+ De vic e Co m p a t ib le 1 0 BAS E-T Me d ia In t e rfa c e Mo d u le s

¶ Manufacturer

Part #

Package

Description

Bel Fuse

S556-5999-32

0556-2006-14

A556-2006-DE

A556-2006-00

16-pin SMD

Transmit and receive ﬁlters, transformers and common mode chokes.

Transmit and receive ﬁlters and transformers.

10-pin SIL

16-pin 0.3" DIL

16-pin DIL

Transmit ﬁlter, transformers and common mode choke. Receive ﬁlter and

transformer.

Halo Electronics

FS02-101Y4

FS12-101Y4

"Slim SIP"

Transmit and receive ﬁlters and transformers.

Transmit and receive ﬁlters and transformers, transmit common mode reduction

choke.

Halo Electronics

FS22-101Y4

FD02-101G

FD12-101G

FD22-101G

FD22-101R2

"Slim SIP"

Transmit and receive ﬁlters, transformers and common mode chokes.

Transmit and receive ﬁlters and transformers.

16-pin 0.3" DIL

Transmit and receive ﬁlters and transformers, transmit common mode choke.

Transmit and receive ﬁlters, transformers and common mode chokes.

Termination and equalization resistors, transmit and receive ﬁlters, transformers

and common mode chokes.

Nano Pulse

5408-37

5408-40

6612-21

16-pin SMD

9-pin SIP

7 pole transmit and receive ﬁlters with 1CT:1CT Xfmrs (transmit & receive) and a

separate common mode choke for each channel.

7 pole transmit and receive ﬁlters with 1CT:1CT Xfmrs (transmit & receive) and a

separate common mode choke for each channel.

12-pin DIL

7 pole transmit and receive ﬁlters with 1CT:1CT Xfmrs (transmit & receive) and a

separate common mode choke for each channel.

PCA Electronics

Pulse Engineering

TDK

EPA1990A

16-pin 0.3" DIL

SMT device

16-pin 0.3" DIL

SMT device

16-pin DIL

Transmit and receive ﬁlters and transformers.

EPA1990AG

EPA2013D

Transmit and receive ﬁlters and transformers.

Transmit and receive ﬁlters and transformers, transmit common mode choke.

Transmit and receive ﬁlters and transformers, transmit common mode chokes.

Transmit and receive ﬁlters and transformers.

EPA2013DG

78Z034C

78Z1120B-01

78Z1122B-01

PE-68017S

PE-68026

16-pin DIL

Transmit and receive ﬁlters, transformers and common mode chokes.

Transmit and receive ﬁlters and transformers, transmit common mode chokes.

10-pin SIL

16-pin SMT

13-pin PCMCIA-SMT

10-pin SIP

PE-68056

PE-68032

TLA-3M601-RS

TLA-3M102(-T)

TDK

16-pin SMD

Integrated resistors, transmit and receive ﬁlters and transformers, transmit common

mode chokes.

TDK

TLA-3M103(-T)

PT3877

16-pin SMD

Transmit and receive ﬁlters and transformers, transmit common mode chokes.

Transmit and receive ﬁlters and transformers.

Valor Electronics

16-pin 0.3" DIL

8-pin 0.3" DIL

16-pin 0.3" DIL

PT3983

Transmit and receive common mode chokes.

FL1012

Transmit and receive ﬁlters and transformers, transmit common mode chokes.

Am79C982

1-27

APPENDIX B

Glossary

Active Status

Partitioning

In a non-collision state, a bIMR chip is considered active

if it is receiving data on any one of its network ports, or is

in the process of broadcasting (repeating) FIFO data

from a recently completed data reception. In a collision

state(thebIMRdeviceisgeneratingJamSequence), an

bIMR device is considered active if any one or more net-

work ports is receiving data. The bIMR device asserts

the REQ line to indicate that it is active.

A network port on a repeater has been partitioned if the

repeater has internally ‘disconnected’ it from the repeat-

er due to localized faults that would otherwise bring the

entire network down. These faults are generally cable

shorts and opens that tend to cause excessive collisions

at the network ports. The partitioned network port will be

internally re-connected if the network port starts behav-

ing correctly again, usually when successful ‘collision-

less’ transmissions and/or receptions resume.

Collision

Receive Collision

In a carrier sense multiple access/collision detection

(CSMA/CD) network such as Ethernet, only one node

can successfully transfer data at any one time. When

two or more separate nodes (DTEs or repeaters) are si-

multaneously transmitting data onto the network, a Col-

lision state exists. In a repeater using one or more bIMR

devices, a Collision state exists when more than one

network port is receiving data at any instant, or when

any one or more network ports receives data while the

bIMR device is transmitting (repeating) data, or when

the CI+/- pins become active (nominal 10 MHz signal)

on the AUI port.

A network port is in a Receive Collision state when it de-

tects collision and is not one of the colliding network

’nodes’. This applies mainly to a non-transmitting AUI

port because a remote collision is clearly identified by

the presence of a nominal 10 MHz signal on the CI+/-

pins. However, any repeater port would be considered

to be in a receive collision state if the repeater unit is re-

ceiving data from that port as the ‘one-port-left’ in the

collision sequence.

Transmit Collision

A network port is in a Transmit Collision state when colli-

sion occurs while that port is transmitting. On the AUI

port, Transmit Collision is indicated by the presence of a

nominal 10 MHz signal on the CI+/- pins while the AUI

port is transmitting on the DO+/- pins. On a 10BASE-T

port, Transmit Collision occurs when incoming data ap-

pears on the RXD+/- pins while the 10BASE-T port is

transmitting on the TXD+/- and TXP+/- pins.

Jam Sequence

A signal consisting of alternating 1s and 0s that is gener-

ated by the bIMR device when a Collision state is de-

tected. This signal is transmitted by the bIMR device to

indicate to the network that one or more network ports in

the repeater is involved in a collision.

Network Port

Any of the eight (four) 10BASE-T ports or the AUI port

present in the bIMR device (i.e. not the Expansion Port

or the Management Port).

1–28

Am79C982


型号：	AM79C982
厂家：	AMD
描述：	basic Integrated Multiport Repeater (bIMR) Basic集成多端口中继（ bIMR ）
文件：	总26页 (文件大小：194K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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