AS3658E-BCTP [AMSCO]
Power and Audio Management Unit for Portable Devices; 电源及音频管理单元，用于便携式设备
| 型号： | AS3658E-BCTP |
| 厂家： | 
AMS(艾迈斯) |
| 描述： | Power and Audio Management Unit for Portable Devices |
| 文件： | 总158页 (文件大小：6923K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
austriamicrosystems AG
is now
ams AG
The technical content of this austriamicrosystems datasheet is still valid.
Contact information:
Headquarters:
ams AG
Tobelbaderstrasse 30
8141 Unterpremstaetten, Austria
Tel: +43 (0) 3136 500 0
e-Mail: ams_sales@ams.com
Please visit our website at www.ams.com
Data Sheet Confidential
AS3658
Power and Audio Management Unit for Portable Devices
- High Current (1.0A) Linear Charger with external
1 General Description
pass transistor (no step down charger)
- 0.1 Ω Battery switch for start-up and trickle charge
- Integrated USB charger up to 880mA (can be used
as wall adapter charger); current accuracy 440-
500mA for USB specification, in-circuit trimmable
(±1.2% trimsteps)
- Autonomous Battery Temperature Supervision
(0ºC-45ºC or 0ºC- 50ºC) for 10k and 100k NTC
- Charging Timeout (1h-8h in 30min steps)
- Charging in Stanby mode
The AS3658 is highly integrated power and audio
management unit. The AS3658 is designed to include
sophisticated audio features like high performance
audio DAC and ADC. It has several analog and digital
audio interface which are explained in detail in the
following sections. The AS3658 is an integrated solution
for power supply generation and monitoring, battery
management including charging.
- Completely Autonomous (no SW)
ꢀ Power Management Features
2 Key Features
ꢀ System Control
- Wide Battery Supply Range 3.…5.5V
- On-hip Bandgap Tuning fr High Accuracy (±1%)
- Theral and Current Protection (int. sensor)
- tandby Mode exit by interupt e.g. Onkey/RTC
Audio
- Serial Control Interface
- On/Off Control Module with Boot-ROM / GPIO
- Reset Generation for system controller
- Programmable Interrupt Controller and Watchdog
- Low power off mode (9µA; 2.5V LDO on)
- 88 bit unique ID or Boot fuse array
- 94dB Audio DAC16-48kHz sampling rate
- Two Digitl Auio Inputs (2 x I2S interface)
- 2.9V low Nise LDO for Audio DAC
- Tweadphone Amplifier Output with GND
eparation
- TwI2S Inputs and one I2S Output
- 2S master mode with programmable sample rate
(controlled by internal PLL)
- GND Buffer for Headphone Amplifier
- Line/ Headphone outputs with GND separation
- Audio ADC, 82dB SNR with 16ksps
- Microphone Bias Supply and Amplifier (mono)
- 5 Band Adjustable Audio Equalizer (± 12dB in 3dB
gain steps)
- Reset with long ON-Keypress (SW-Interuptable)
- Touchscreen Interface (10 bit, interrupt)
ꢀ Supply Voltage Generation
- 2 RF Programmable Low Noise LOs 250mA) (1
LDO can be a current controlled ch for hotplug
(200mA ± 40%))
- 1 RF Programmable Low Noise LDO (400mA)
- 4 Programmable Dig. Low Power LDOs(200A)
- 2 General Purpose PWM DC/DC step up converter
with three programmable current sinks e.g. for-
white led); for current mode feedbacis atomati-
cally slected (DCDC_CURR1,2,3)
- SPDIF Output
- 3 General Purpose high efficency DC/DC step
down converter (DCDC 1 suport DVM)
- 1 Low noise charge pump with 5V output voltage
- 1 Ultra Low Power 25V LDO (always on)
ꢀ Current sinks
- Audio Mixer and Gain Stages
- PCM Interface
ꢀ Real Time Clock (RTC)
- Alarm and Time function
- Repeated Wakeup (every second or minute)
- 32kHz output
- 4 programmle(8it) from 0.15mA to 38.25mA
(±5% ) optionauseable as GPIOs
- 3 programmable high voltage (15V) (8-bit) from
0.15mA t38.25mA (±5% )
- intal PWM generator (extended time range)
(can control DCDC_CURR1,2,3)
- Backup Battery Charger and Switchover
ꢀ Programmable System clock
- 1.6 MHz to 2.3 MHz with 100 kHz steps
ꢀ Package
ꢀ 0-bit 40µs Successive Approximation ADC
- BGA124 8x8mm, 0.5mm pitch (can be assembled
without micro via boards)
- Two external Inputs (ADC_IN1, ADC_IN2)
ꢀ Battery Management
- Full featured chemistry independent step down
charger with Gas Gauge and Current limitation
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Revision 1v13
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Data Sheet Confidential - Applications
3 Applications
The AS3658 is ideal for PDA, PMP, GPS-Navigation Systems and 1 Cell Li+ or 3 Cell NiMH powered devices.
Figure 1. Blockdiagram AS3658
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Revision 1v13
2 - 157
AS3658
Data Sheet Confidential - Applications
Figure 2. Application Diagram
AS3658
www.austriamicrosystems.com
Revision 1v13
3 - 157
AS3658
Data Sheet Confidential - Applications
Table of Contents
1 General Description ..............................................................................................................................1
2 Key Features .........................................................................................................................................1
3 Applications ...........................................................................................................................................2
4 Pin Assignments ...................................................................................................................................6
4.1 Pin Description ...............................................................................................................................................7
5 Absolute Maximum ratings ..................................................................................................................12
6 Electrical Characteristics .....................................................................................................................13
7 Typical Operating Characteristics ......................................................................................................1
8 Detailed Description-Power Management Functions ........................................................................
8.1 Step Up DC/DC Converters .......................................................................................................................15
8.2 Current Sinks .............................................................................................................................................25
8.3 General Purpose Input / Output (CURR1_GPIO1 … CURR4_GPIO4) ...................................................30
8.4 Backup Battery Charger ..........................................................................................................................38
8.5 Smooth switchover Power Management Overview ...............................................................................41
8.6 Battery switch SINT (Vsupply, Battery) ..................................................................................................42
8.7 External Step Down/Linear Charger ........................................................................................................44
8.8 USB Charger ....................................................................................................................................48
8.9 Battery Charge Controller .......................................................................................................................51
8.10 Charger supervision functions .................................................................................................................63
8.11 Step Down DC/DC Converters ..........................................................................................................67
8.12 Low Dropout Regulators (LDO) .......................................................................................................78
8.13 5V Charge Pump .................................................................................................................................85
9 Detailed Description- Audio Funions .............................................................................................87
9.1 Audio Paths ..................................................................................................................................87
9.2 Common mode voltage generation of HP_CM, _CM ...........................................................................89
9.3 Audio Setup Registers .............................................................................................................................90
9.4 ADC, DAC and Digital Audio Inpu...............................................................................................................91
9.5 I2S master mode and PCM Mode .............................................................................................................95
9.6 Line Input ..............................................................................................................................................98
9.7 Five Band Equalizer ................................................................................................................................99
9.8 Microphone Input ..................................................................................................................................105
9.9 Audio Output Mixer ..................................................................................................................................108
9.10 Line Output .........................................................................................................................................109
9.11 Headphone Outpt ...................................................................................................................................112
9.12 SPDIF oput ...........................................................................................................................................115
10 Detailed Description - System Functions ........................................................................................116
10.1 2C Srial Interface ...................................................................................................................................116
10.Reet generator and XON-Key ................................................................................................................118
10.3 Interrupt Controller ...................................................................................................................................124
104 Startup ......................................................................................................................................................129
10.5 Protection Functions ................................................................................................................................134
10.6 Watchdog ................................................................................................................................................135
10.7 General Purpose 10 Bit ADC ...................................................................................................................136
10.8 Internal References (V, I, fclk) ..................................................................................................................139
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Revision 1v13
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AS3658
Data Sheet Confidential - Applications
10.9 Real-Time Clock (RTC) Module ...............................................................................................................140
10.10 Touchpen Interface ................................................................................................................................143
11 Register map ...................................................................................................................................148
12 Package Drawings and Marking .....................................................................................................154
12.1 Pinout Drawing (Top view) CTBGA 8x8mm .............................................................................................155
13 Ordering Information .......................................................................................................................156
Document Revision History
Table 1. Revision History
Chapter
Rev
Description of Changes
Date
Author
-
1v00
23.3.2009
pk
- updated package drawings
- updated audio path drawings
9.1; 12
1v10
15.4.2009
pkm
- updated packagemarkings and ordering information
- updated packagemarkings and rdering information
- typo corrections
12,13
12,13
1v11
1v12
1v13
23.9.009
23.0.2009
2.9.2010
pkm
pkm
pkm
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Revision 1v13
5 - 157
AS3658
Data Sheet Confidential - Pin Assignments
4 Pin Assignments
1
2
3
4
5
6
7
8
9
10
11
12
13
14
NC/
VSS
_CP
VCP
_OU
T
VDI
G34
_IN
VDI
G1_I
N
NC/
BV
SS
LRC
LK1
SCL
K3
SDO VCP
VCP
_P
LOU LINE
HPL
1
VI2S
A
B
C
D
E
F
1
_N
T_R
_CM
VSS_C
P
VCP_I
N
VDIG_
2
VDIG2
_IN
VDIG_ LOUT_
HP_C
M
HPR
2
SDI2
SCLK1
SDI1
SDA
1
L
Q32k
SCLK2
HPR1
HPL2
DCDC
_SENS
E_P1
HP
CM_
WR
MCLK
2
VDIG_
4
VDIG_
3
MCLK
1
LRCLK
2
ALVD
D
SDO3
SCL
DCDC
VSUP
LRCLK
3
_SENS
BVSS
MICS
MICN
MICP
VREF
AGND
AVDD
VDAC
LINR
LINL
PLY_4
E_N1
DCDC
VSUP
XRES
ET
_GATE
SPDIF
XNT
PLY_3
1
DCDC
DCDC
_SENS
E_N2
DCDC
_SENS
E_P2
VSU
P_S
VSUP
G
H
J
LX3
_GATE
2
VSSA
VSSA
PLY_6
W12
VSU
PGND
3
PGND
2
DCDC
_FB1
VBAT_
SW12
FB3
P_S
W12
VBAT
VSS_C
H
DCDC
_FB2
BAT_S
W
LX2
FB2
VSSA
_SW
12
VSUP
VSUP
ISENS
N
ISEN
SP
K
L
FB1
PLY_1
PLY_2
RR
4_GPI
O4
DCDC
_CUR
R1
D
R3
GND_
SENS
E
VOFF_
B
GND_
SW
RPRO
GRAM
RBIA
S
LX1
CREF
PGND
1
VGAT
E
VBA
CK
M
N
P
V_BAT
XIN32
CR
_G
O
URR
3_GPI
DCDC
_CUR
R2
PGAT
E1
VSUP
ADC_I
N1
ADC_I
N2
VCHA
RGER
XOU
T32
XON
VRF_2
VRF_1
V2_5
PLY_5
O3
CURR
CH_S
CH_S
VCR
NC/
VSS
A
NC/
SS_C
URR
VSUP_
USB
VRF1_
IN
VRF23
_IN
ENSE_ ENSE_ _GP
2_GPI
O2
V_USB
VRF_3
VSSA
P
N
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Revision 1v13
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AS3658
Data Sheet Confidential - Pin Assignments
4.1
Pin Description
Table 2. Pin list CTBGA124, 8x8MM (AS3658)
Pin
Number
Pin
Type
Pin Name
Charger
Supply
Description
USB voltage supply input
V_USB
P8
P7
P
P
Supply output of USB charger (connect to Vsupply)
VSUP_USB
High voltage input coming from the charger; if the charger is
used connect a ceramic capacitor of 1µF
VCHARGER
VGATE
N11
M2
L2
P
A
A
Switch ON control pin for the external PMOS Fet transistor o
the charger step down converter
Switch OFF control pin for the external PMOS Fet transisr of
the charger step down Buck converter
VOFF_B
Ground pad of Step down Charger
Battery switch input1 (battery side)
Battery sitch nut2 (battery side)
VSS_CH
VBAT_SW12
VBAT_SW12
VSUP_SW12
VSUP_SW12
BAT_SW
J2
P
P
P
P
P
A
H13
J14
G14
H14
J13
VBAT
VBAT
VSUPPLY Battery swch input1 (supply sid)
VSUPPLY Baitch input2 (supy side)
Battey switch output foexteal PMOS
Charger step down cnverter, external shunt resistor negative
onnection
VSUPL
CH_SENSE_N
CH_SENSE_P
ISENSP
P3
P2
A
A
A
Charger stp don converter, external shunt resistor positive
connection
VSUPLY
Positivseing input voltage for the external charging current
shunt reistor
K14
K13
V2_5
ve sensing input voltage for the external charging
cunt shunt resistor
ISENSN
V2_5
Serial Interface
SCL input in I2C mode
VSUPPLY
SCL
D6
B5
DI
SDA input / output in I2C mode
VSUPPLY
SDA
DO
Control Interfaces
Bidirectional Reset Pin – add an external pull-up resistor to the
digital supply
VSUPPLY
XRESET
XINT
F7
F8
N4
OD
OD
IPU
Interrupt Pin - add an external pull-up resistor to the digital
VSUPPLY
supply
Input pin to startup the system (power on), internal pull-up,
apply zenerzap-programming voltage here
XON
V2_5
RTC
VSUPPLY 32kHz oscillator digital output
32K
C1
OD
A
32kHz crystal oscillator input
32kHz crystal oscillator output
XIN32
XOUT32
P13
N14
V2_5
V2_5
A
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Revision 1v13
7 - 157
AS3658
Data Sheet Confidential - Pin Assignments
Table 2. Pin list CTBGA124, 8x8MM (AS3658)
Pin
Number
Pin
Type
Pin Name
Supply
Description
Internal Refs
Supply for voltage Measurement, always connect to
VSUPPLY
VSUPPLY_5
N3
P
Battery supply for Reference blocks.
V_BAT
RPROGRAM
V2_5
M13
L9
P
A
P
A
A
VBAT
Select register setup at startup.
V2_5
Internal regulator analogue output
N12
L10
L14
Reference voltage bypass capacitor connection
Internal Bias Reference Resistor (connect 220kΩ resistr)
CREF
V2_5
V2_5
RBIAS
GND reference for analog blocks (connect to GND plane
separate)
GND_SENSE
L13
P
VSSA
Analog input1 for ADC10
Analog input2 for ADC10
Backup attercnnection
ADC_IN1
ADC_IN2
N8
N9
A
A
A
V2_5
V2_5
VBACK
M14
Current Sinks
VCURR_
Cursink 1, or GPIO1
N5
P6
N6
L5
L6
N7
A
A
A
A
A
CURR1_GPIO1
CURR2_GPIO2
CURR3_GPIO3
CURR4_GPIO4
DCDC_CURR1
DCDC_CURR2
GPIO
VCURR_
GPIO
Current sink 2, or GPO2
VURR_
GO
Current sink 3, GPO3
VURR_
GPIO
Current sk 4, r GPIO4
VCURR_
GPIO
Steup C/DC converter2 current source 1
Step up DC/DC converter2 current source 2
VCURR
GP
VCURR_
Step up DC/DC converter2 current source 3
Supply voltage of GPIOs and current sinks
Ground pad of Current sink / GPIO pads
L7
P4
P5
A
A
A
DCDC_CURR3
VCURR_GPIO
GPIO
VCURR_
GPIO
VSS_CURR_GPIO
General Purpose DC/DC Steup Converter 1 and 2
Supply for DCDC step up and control interface, always
connect to VSUPPLY
VSUPPLY_4
E1
P
VSUPPLY Step up DC/DC converter1 feedback input
DCDC_FB
H4
F2
A
A
Step up DC/DC converter1 control for external mosfet
VSUPPLY
DCDC_GATE1
Step up DC/DC converter1 external shunt resistor positive
connection
VSUPPLY
DCDC_ENSE_P1
CDC_SENSE_P2
DCDC_SENSE_N1
DCDC_SENSE_N2
D1
G6
E2
G4
A
A
A
A
Step up DC/DC converter2 external shunt resistor positive
connection
VSUPPLY
VSUPPLY
VSUPPLY
Step up DC/DC converter1 external shunt resistor negative
connection
Step up DC/DC converter2 external shunt resistor negative
connection
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AS3658
Data Sheet Confidential - Pin Assignments
Table 2. Pin list CTBGA124, 8x8MM (AS3658)
Pin
Number
Pin
Type
Pin Name
Supply
Description
VSUPPLY Step up DC/DC converter2 control for external mosfet
VSUPPLY Step up DC/DC converter2 feedback input
DCDC_GATE2
DCDC_FB2
G2
J4
A
A
Linear Regulators (LDOs)
Supply Pad for RF1 LDO (VRF_1), always connect to
Supply>3.0V
VSUPPLY
VRF1_IN
VRF_1
P9
P
A
P
A
Output voltage of one of the RF LDO’s; can be used as High-
VRF1_IN Side Switch, if used as LDO connect a ceramic capacitor o
1µF (±20%) or 2.2µF (+100%/-50%)
P10
P11
N10
Supply Pad for RF2 and RF3 LDO (VRF_2, VRF_3), always
connect to Supply>3.0V
VSUPPLY
VRF23_IN
VRF_2
Output voltage of one of the RF LDO’s; cabe sed as High-
VRF23_IN Side Switch, if used as LDO connect a ceramic caacitor of
1µF (±20%) or 2.2µF (+100%/-50%)
Output vtage one of the RF LDO’s; an be used as High-
VRF23_IN Side Swih, if usd as LDO connect a ceramic capacitor of
1µF (±20%or 2.2µF (+100%/-50%)
VRF_3
P12
A
VSUPPLY Suafor DIG1 LDO VDIG_1)
VDIG1_IN
VDIG_1
A10
B10
B9
P
A
P
A
Outpt voltage of one ohe DG LDO’s. Connect a ceramic
VDIG1_IN
capacitor of 1µF (±2%) or 2.2µF (+100%/-50%)
VSUPPLY upply Pad for LDO (VDIG_2)
VDIG2_IN
VDIG_2
Output vole oone of the DIG LDO’s. Connect a ceramic
DIG2_IN
B8
capacitor of 1F (±20%) or 2.2µF (+100%/-50%)
VSUPPLY SupplPad or DIG3 and DIG4 LDO (VDIG_3, VDIG_4)
VDIG34_IN
VDIG_3
A9
Ot voltage of one of the DIG LDO’s. Connect a ceramic
VDIG3_IN
D8
or of 1µF (±20%) or 2.2µF (+100%/-50%)
Output voltage of one of the DIG LDO’s. Connect a ceramic
VDIGIN
VDIG_4
Charge Pump
VCP_IN
D7
A
apacitor of 1µF (±20%) or 2.2µF (+100%/-50%)
Supply Pad for Charge Pump, always connect to
VSUPPLY
B7
P
Supply>3.0V
VSUPPLY HVS charge pump flying capacitor positive side
HVS charge pump flying capacitor negative side
VCP_N
VCP_P
A6
A7
A
A
Charge pump output, connect a ceramic capacitor of 2.2µF
(+100%/-50%)
VCP_OUT
A8
A
A
VSUPPLY Ground pad of charge pump
VSS_CP
B6
DCDC Step own Converters
VSUPPLY Gate output for external PMOS.(DCDC step down controller 1)
PGATE
N1
K1
A
P
Supply Pad for DCDC_Step down converter1, always connect
to VSUPPLY
VSUPPLY_1
VSUPPLY DC/DC step down converter1 output
VSUPPLY DC/DC step down converter1 feedback
LX1
FB1
L1
K4
M1
A
A
A
Power Ground of DCDC step down converter1
VSUPPLY
PGND1
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AS3658
Data Sheet Confidential - Pin Assignments
Table 2. Pin list CTBGA124, 8x8MM (AS3658)
Pin
Number
Pin
Type
Pin Name
Supply
Description
Supply Pad for DCDC_Step down converter2, always connect
to VSUPPLY
VSUPPLY_2
K2
P
VSUPPLY DC/DC step down converter2 output
VSUPPLY DC/DC step down converter2 feedback
LX2
FB2
J1
J7
A
A
A
Power Ground of DCDC step down converter2
VSUPPLY
PGND2
H2
Supply Pad for DCDC_Step down converter3, always connect
to VSUPPLY
VSUPPLY_3
F1
P
VSUPPLY DC/DC step down converter3 output
VSUPPLY DC/DC step down converter3 feedback
VSUPPLY Power Ground of DCDC step down conveter3
LX3
FB3
G1
H6
H1
A
A
A
PGND3
Audio
Supply for VI2S Regulator
VSUPPLY_6
VI2S
G13
A4
B4
A5
B3
A2
P
P
Supply Pd for I2Interface, Connect to VDAC Supply
I21 Data input to DAC
SDI1
I
VI2S
VI2S
VI2S
VIS
I2Sata output from A
I2S_1 Shift clock inpuor utput
2S_1 Left/Right clock put or output
SDO1
O
SCLK1
LRCLK1
I/O
I/O
Master clock inor output for I2S1: DAC (128*Fsdac or 256
*Fsdac)
MCLK1
D9
I/O
VIS
I2S_2 Datinput to DAC
SDI2
B1
C2
I
I
I
VI2S
VI2S
VI2S
VI2
I2S_2 Sift clock
SCLK2
LRCLK2
MCLK2
Left/Right clock
D10
D2
Master clock input for I2S2: DAC (128*Fsdac or 256 *Fsdac)
I2S_3 Data output (if touchpen interface disabled)
SDO3(X-)
SCLK3(X+)
LRCLK3(Y-)
SPDIF(Y+)
D5
A3
E4
F4
I/O
I/O
I/O
I/O
VI2S Touchpen Interface X- Input/Output (if touchpen interface
enabled)
I2S_3 Shift clock output (if touchpen interface disabled)
VI2S Touchpen Interface X+ Input/Output (if touchpen interface
enabled)
I2S_3 Left/Right clock output (if touchpen interface disabled)
VI2S Touchpen Interface Y- Input/Output (if touchpen interface
enabled)
SPDIF digital output (if touchpen interface disabled)
VI2S Touchpen Interface Y+ Input/Output (if touchpen interface
enabled)
CM voltage bypass capacitor connection (1.45V)
VDAC voltage bypass capacitor connection (2.9V)
Line input left channel.
ND
VREF
K11
J11
F14
E14
L8
A
A
A
A
O
VDAC
VDAC
VDAC
VDAC
LINL
Line input right channel
LINR
VSUPPLY Digital output for controlling the external NMOS
GND_SW
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AS3658
Data Sheet Confidential - Pin Assignments
Table 2. Pin list CTBGA124, 8x8MM (AS3658)
Pin
Number
Pin
Type
Pin Name
Supply
Description
2.9V Output voltage of one of DAC LDO; Connect a ceramic
capacitor of 1µF (±20%) or 2.2µF (+100%/-50%)
VDAC
F13
A
VDAC
Bypass capacitor connection of common mode voltage of
Audio headphone amplifier (AVDD/2)
HP_CM
HP_CM_PWR
LINE_CM
B12
D14
A12
A
A
A
AVDD
AVDD
Buffered voltage of HP_CM
Bypass capacitor connection of common mode voltage of
Audio line out amplifier (ALVDD/2)
ALVDD
Line out output Left channel
Line out output Right channel
Supply pad of Line out amplifier
Supply pad of headphone amplifier
Headphone output1 left channel
Headphoe outut1 right channel
Headphoe outpt2 left channel
Heone output2 right channel
Micrhone Input N
LOUT_L
LOUT_R
ALVDD
AVDD
HPL1
B11
A11
D13
E13
A13
C13
C14
B14
G11
H11
F11
A
A
P
P
A
A
A
A
A
A
A
ALVDD
ALVDD
AVDD
AVDD
AVDD
AVDD
VDAC
VDAC
HPR1
HPL2
HPR2
MICN
Microphone Input P
MICP
VSUPPLY Microphone Sup(2.95V) / Remote Input
MICS
VSS
Power grund f headphone amplifier
Analog Ground Pad
BVSS
VSSA
E11
G9
H9
P
AVDD
V
VS
VSS
VSS
VSS
VSS
VSS
Ground Pad
VSSA
Analog Ground Pad
VSSA
J8
nalog Ground Pad
NC/VSS_CP
NC/VSSA
NC/VSSA
NC/BVSS
A1
Analog Ground Pad
P1
Analog Ground Pad
P14
A14
Power ground of headphone amplifier
Note: The following are the PTypes
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
I: Digital Input Pin
IPD: Digital Input in wih internal pull-down resistor
IPU: Digital Inpt Pin with internal pull-up resistor
IODPU: Dgital Input / Open Drain Output Pin with internal pull-up resistor
O: Digital Otput Pin
OD: gitl Open Drain Output Pin; requires external pull-up resistor
O: Digital Input / Output Pin
A: Analog Pin
P: Power Pin
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AS3658
Data Sheet Confidential - Absolute Maximum ratings
5 Absolute Maximum ratings
Stresses beyond those listed in Table 3 may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in Section 6 Electrical
Characteristics on page 13 is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
Table 3. Absolute Maximum Ratings
Parameter
Min
Max
Unit
Note
Applicable for high voltage pins1
Applicable for pins 5V-pins2
High voltage pins (VIN_HV)
-0.3
17.0
V
5V pins (VIN_MV)
-0.3
7.0
V
Applicable for 3.3V-Pins3
At 25 ºC, Norm: Jeec 78
3.3V pins (VIN_LV)
-0.3
-25
5.0
V
Input pin current (IIN)
+25
mA
Storage Temperature Range
-55
5
125
85
ºC
%
(Tstrg)
Humidity
Noncodens
Norm: MIL 883 E Method 3015; Setup4
Applicable for pins: all
Electrostatic discharge 1kV (VESD)
-1000
1000
V
TA = 70ºC
TA = 84ºC
1
W
W
Total Power Dissipation
0.72
C/JDEC J-STD-020C, reflects moisture
sensitivity level only
Package Body Temperature
260
°C
Te lead finish for Pb-free leaded packages is
matte tin (100% Sn).
TPEAK
235
0
245
45
°C
s
Solder Profile5
DWell, above 217 °C
Moisture Sensitive Level
1. HV pins
3
1
Represents a max. floor live time of 168h
VCHARGER, VGATE, VOFF_B, DDC_CURR1, DCDC_CURR2, DCDC_CURR3
2. 5V pins are
V_USB, CH_SENSE_N, CH_SENE_P, VSUP_SW1, VSUP_SW2, VBAT_SW1, VBAT_SW2, V_BAT, SCL,
SDA, XRESET, XINT, VSUPPLYCURR1_GPIO1…CURR4_GPIO4, DCDC_GATE1, DCDC_GATE2,
DCDC_SENSE_P1, DCDSENSE_P2, DCDC_SENSE_N1, DCDC_SENSE_N2, DCDC_FB1, DCDC_FB2,
VCL, VCP_OUT, VCP_N, VCP_P, VCP_IN, VCP_IN, VRF1, VREF1_IN, VRF2, VRF23_IN, VRF3, VDIG1,
VDIG1_IN, VDIG2, VDIG_IN, VDIG34_IN, VDIG_3, VDIG_4, PGATE1 VSUPPLY_1, VSUPPLY_2, LX1, LX2,
GND_SW, VSUPLY_, LINE_CM, HP_CM_PWR, HP_CM, HPLx, HPRx, ALVDD, AVDD, LSP_R, BVSS,
LSP_L, AVDD, VSUPPLY_5, VSUPPLY_6
3. 3.3V pins are
ISENSEP, ISENSEN, ADC_INx, RPROGRAM, V2_5, CREF, ON, VI2S, SDIx, SCLKx, MCLKx, LRCLKx,
SDOxSPDIF, AGND, VREF, LINL,LINR, VDAC, Q32K, XIN32, XOUT32, VBACK, MICS, MICN, MICP
4. The followinpis are connected to ESD setup:
UPPLY_1...VSUPPLY_6, VCP_IN, VRF1_IN, VRF2_IN, VCURR connected together
VDIG1_IN, VDIG2_IN, VDIG34_IN connected together
AVDD, ALVDD connected together
VBAT_SW1 and VBAT_SW2 connected together
VSUP_SW1 and VSUP_SW2 connected together
All VSS connected together
5. austriamicrosystems strongly recommends to use underfill.
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AS3658
Data Sheet Confidential - Electrical Characteristics
6 Electrical Characteristics
Table 4. Electrical Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Units
Operating Conditions
VCHARGER, VGATE,
DCDC_CURR1,DCDC_CURR2,
DCDC_CURR3
VHV
High Voltage
0.0
15.0
V
For pins V_BAT, VSUPPLY1-6
(always connect all VSUPPLY1-6
pins together), VSUP_SW1-2,
VBAT_SW1-2, VRF1_IN, VRF2_IN,
VCP_IN, AVDD, ALVDD
VBAT,
Battery, Supply Voltage
Voltage on Pin V2_5
3.0
3.6
5.5
V
VSUPPLY,
VCURR_GPIO
V2_5
Internally generated
2.4
4.9
-40
2.5
5.2
25
2.6
5.6
85
V
V
VCP_OUT Output Voltage charge pump Voltage generated by charge pump
TAMB
Ambient Temperature
ºC
Current consumption in low power
mode with step dwn chager on1
7
mA
µA
µA
Low power mode current
consumption
ILOWPOWER
With stedown charger off2
280
10
Current conption in power off
ode3
Power Off mode current
consumption
IPOWEROFF
1. With register bit low_power_on = 1, only Rf1=33VVut2=1.2V, Batter3.6VVcharger=6.0V, no additional
external loads
2. With register bit low_power_on = 0, All reulatos switched off, additional external loads
3. After setting register bit xon_enable=1 nd pwer_off=1; only V2_5 s active in Power Off mode
4. During startup from the AC/DC adapter, te battery voltage an e below 3.0V
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AS3658
Data Sheet Confidential - Typical Operating Characteristics
7 Typical Operating Characteristics
see individual block description
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AS3658
Data Sheet Confidential - Detailed Description-Power Management Functions
8 Detailed Description-Power Management Functions
The power management function consist of the DCDC Step up converters, Current Sink, GPIOs, general purpose 10
bit ADC, backup battery charger, main battery charger and power path management (consisting of the battery switch,
external step down/linear charger, USB charger and battery charge controller), step down dc/dc converters, low
dropout regulators (LDOs) and 5V charge pump.
8.1
Step Up DC/DC Converters
Figure 3. DC/DC step-up Converter 1
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AS3658
Data Sheet Confidential - Detailed Description-Power Management Functions
Figure 4. DC/DC step-up Converter 2
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Table 5. DC/DC Converter parameters
Symbol
Parameter
Min
Typ
140
Max
Unit
Note
IVDD
Quiescent Current
µA
Pulse skipping mode
Feedback voltage r exernal
resistor vider:
VFB1
VFB2
1.20
1.25
0.5
1.30
V
V
for constant voltage control
Feedback voltge for current
sinregulation
DCDC_CURR1, DCDC_CURR2
or DCDC_CURR3
ditioal tuning current at
DCDC_FB
adjustable by software in 1µA
steps
0
31
5
µA
%
IDCDC_FB
Accuracy of feedback current
-5
@ full scale
E.g.: 0.65A for 0.15Ω sense
Vsenseax
Current limit voltage at Rsense
100
mV
resistor
ON-resistance of external
switching transistor
RSW
Iload
fIN
switch resistance
Load current
1
Ω
0
50
mA
at 15V output voltage
fclk_int
/
internal CLK frequency/2
Programmable: 0.8 to 1.15 MHz
Switching frequency
MHz
2
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AS3658
Data Sheet Confidential - Detailed Description-Power Management Functions
Table 5. DC/DC Converter parameters
Symbol
Parameter
Min
Typ
Max
Unit
Note
Cout
Output capacitor
2.2
µF
ceramic, ±20%
Use inductors with small Cparasitic
(<100pF) to get high efficiency
L
Inductor
10
µH
tMIN_ON
MDC
Minimum on time
130
91
ns
%
Maximum duty cycle
The DC/DC Step Up converter is a high efficiency current mode PWM regulator, which provides an output voltage
dependent on the maximum VDS voltage of the external transistor, and maximum load current selectable by the
external shunt resistor.
For Example:
5V,500mA @ 1.1Mhz
25V,50mA @ 1.1MHz
40V,20mA @ 550kHz
A constant switching frequency results in a low noise on supply nd ouut voltage.
8.1.1 Feedback selection
For step up DCDC 1, the feedback is always DCDC_FB1.
For step up DCDC 2 following feedback selections are possle:
Stpup2_fb selects the type of feedback for the DCDC_step_up2 converter:
DCDC_CURR1, DCDC_CURR2, DCDC_CURR3 or DCDC_FB2 feedb(see Figure 5)
Setting stpup2_fb to 00b enables the feedbak on DCDC_FB2, stpp2_fb to 01b enables feedback at pin
DCDC_CURR1, setting step_up_fb to 10enables feedback at pn DCDC_CURR2 and setting step_up_fb to 11b
enables feedback at pin DCDC_CURR. ThStep-up converr is rgulated such that the required current at the
feedback path can be supported.
Always choose the path with the higher voltage drop as ack to guarantee adequate supply for the other,
unregulated path.
To protect the DCDC output voltage against overvoltage, if a LED string is broken, set stpup2_prot=1. In this mode the
output voltage will be limited by limiting the DCDC_FB voltage to 1.25V (select the external resistor network to adjust
this limitation voltage).
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Figure 5. DC/DC step up 2 converter with regulation of LED string on pin DCDC_CURR1,2 or 3
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Figure 6. DC/DC step up 1 converter with regulated output voltage of 5V. Feedback is at pin DCDC_FB1
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For Step UP DCDC 1 voltage feedback is always selectin DCDC_FB1. For Step-up UP DCDC 2 set step2_fb to
00 to enable voltage feedback at pin DCDC_FB2.
Bit stepX_res (X = 1 or 2) should be set to 1 in voltge edback mode using two resistors.
The output voltage is regulated to a constanvalue, given by:
R1 + R
Vstepuout
=
2 1.25 + II
• R1
DCDC _ FB
R2
If R2 is not used, the output oltage is:
Vstepup _ out = 1.25 + II
• R1
DCDC _ FB
Vstepup_out: Stp up regulator output voltage
R1 Feedback resistor R1
RFeedck esistor R2
I
Vturng: Tuning current on DCDC_FB pin: stpupX_v (0µA to 15µA (1µA steps)) (X= 1 or 2)
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Example:
Table 6. Step Up Output Voltage (Voltage mode or protection voltage)
Ivtuning
Vstepup_out
Vstepup_out
µA
0
R1=1M Ω,R2 not used
R1=500k Ω,R2=64k Ω
-
11
11.5
12
1
-
2
-
3
-
12.5
13
4
-
5
6.25
7.25
8.25
9.25
10.25
11.25
1
13.
14.25
15.25
16.25
13.5
14
6
7
1.5
15
8
9
15.5
16
10
11
12
13
14
15
16.5
17
17.5
18
18.5
Note: The voltage on pin DCDC_CURR1DCDC_CURR2 and DDC_CURR3 must never exceed 15V
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Figure 7. DC/DC step up converter 1 with regulated output voltage (15V), and switch off function of output
voltage, to reduce shutdown current
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As the output voltage is always on, an additinal otput transistor n be added to reduce shutdown current through
R1, R2 and the connected output circuit.
Note: A similar circuit can be used foep up converter 2.
8.1.2 StepUp1 Load Detection and Overcurrent tection Circuit
This circuit protects the DCDC step up1 converter durinshort circuit and startup, by regulation of the output current.
An additional feature is the detection of a minimum output load of the Step-up converter. It is also possible to use this
circuit without the DCDC step up converter, y using the sense resistor only:
ꢀ
Detection circuit: If the voltage on Rseexceeds VDETECT for more than 1msecond, or the DCDC Step up
converter is not in Pulseskip for more n 1 millisecond, the stepup1_det bit will be set.
ꢀ
Overcurrent protection: If the vercurrent voltage VOVCURRENT has been exceeded by more than 5 msec the Bit
stpup1_oc will be set and cn only reset, by switching off and on the Protection circuit by writing Stpup1_shortprot
0 – 1. If stepup1_oc is st the oad will be disconnected, if Stpup1_oc_timeout=1
Table 7. StepUp1 protectn/detection circuit parameters
Symbol
Parameter
Min
Typ
Max
Unit
Note
For Rsense=0.150Ω =>
VDETEC
Detection Threshold
2
12.5
25
mV
83mA typ.
Overcurrent Threshold
rising
For Rsense=0.150Ω =>
VOVCRENT
VVhysteresis
150
180
50
215
mV
mV
1.2A typ.
Overcurrent Hysteresis
Interrupt and/or external PMOS
switching off after timeout
tOV_timeout
tdetect
Overcurrent timeout
5
1
ms
ms
f
clk_int = 2.2MHz
Detection denounce
time
f
clk_int = 2.2MHz
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Figure 8. StepUp 1 Load Detection and Overcurrent Protection Application Circuit
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8.1.3 Step Up DCDC Converter Registers
Table 8. Step Up DC/DC Bit definitions
Step Up DC/DC control
This register controls the different modes of the step up DCDC converter
Addr: 30
Bit Name
Bit
5
Default
ROM
Access
R/W
Description
stpup1_on
stpup2_on
On/Off control of the step up dc/dc converter1
On/Off control of the step up dc/dc converter2
6
ROM
R/W
Table 9. Step Up DC/DC Bit definitions
Step Up DC/DC control
Addr: 32
This register controls the different modes of the step up DCDC convrter
Bit
Bit Name
Default Access
Description
Invert input clock of step up2 cnveer
Use positive edge of inernal clk
Use negative edge ointernal clk
0
stpup2_clkinv
00h
R/W
0
1
Dines the clock frequecothe step up1 dc/dc
converter;
1
2
stpup1_freq
-
00h
00h
R/W
n/a
0fclk_i(0.8 to 1.15 MHz)
1fclk_nt/4 .4 to 0.575 MHz)
Always set to 0
selection for DCDC step_up1:
elect 0 if DCDC is used with current feedback
(DDC_CURR1,DCDC_CURR2,DCDC_CURR3)
r if DCDC_FB is used with current feedback only
(Only R1,C1 connected; (see Figure 6))
0
3
4
stpup1_res
0h
00h
R/W
Select 1 if DCDC_FB1 or DCDC_FB2 is used with
external resistor divider (2 resistors)
0
step_up_fb select the feedback of the DCDC
converter
The feedback is automatically chosen within the
current sinks DCDC_CURR1,DCDC_ CURR2 and
DCDC_CURR3 (never DCDC_FB). Only those are
used for this selection, which are enabled and
connected to the step up converter
stpup2_fb_auto
RW
1
(currX_ctrl must be 10)
Defines the clock frequency of the step up2 dc/dc
converter
5
6
stpup2_req
-
00h
00h
R/W
n/a
f
clk_int/2 (0.8 to 1.15 MHz)
0
1
fclk_int/4 (0.4 to 0.575 MHz)
Always set to 0
Gain selection for DCDC step_up2:
Select 0 if DCDC is used with current feedback
(DCDC_CURR1,DCDC_CURR2,DCDC_CURR3)
or if DCDC_FB is used with current feedback only
(Only R1,C1 connected; (see Figure 6))
0
1
stpup2_res
00h
R/W
Select 1 if DCDC_FB1 or DCDC_FB2 is used with
external resistor divider (2 resistors)
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Table 10. Step Up DC/DC Bit definitions
Step Up1 DC/DC control
Addr: 33
This register controls the different modes of the step up1 DCDC
converter
Bit
Bit Name
Default Access
Description
Defines the tuning current at DCDC_fb1 pin;
00000
0 µA
1 µA
4:0
stpup1_v
00h
R/W
00001
.....
11111
31 µA
Invert input clock of step up1 converter;
Use positive edge of inernal clk
Use negative edge of nteral clk
5
6
stpup1_clkinv
00h
00h
R/W
RW
0
1
Enables Protection and Detection cirit foDCDC step
up1
stpup1_shortprot
0
1
No protection and load detection
Short protection and load detection enabled
trols GPIO1 switch ff, after overcurrent timeout (5ms)
fr DCC step up1
7
stpup1_oc_timeout
00h
RW
0
1
disabled
enabled
Table 11. Step Up DC/DC Bit definitions
Stp Up2 DC/DC control
Addr: 34
This registetrols the different modes of the step up2 DCDC
converter
Bit
Bit Name
Default Acess
Description
Defines the tuning current at DCDC_fb2 pin;
00000
0 µA
1 µA
4:0
stpup2_v
0
R/W
00001
.....
11111
31 µA
Controls the feedback source
00
01
DCDC_FB enabled (external resistor divider)
DCDC_CURR1 feedback enabled (feedback
through white LEDs)
6:5
stpup2_fb
00h
R/W
DCDC_CURR2 feedback enabled (feedback
through white LEDs)
10
11
DCDC_CURR3 feedback enabled (feedback
through white LEDs)
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Table 11. Step Up DC/DC Bit definitions
Step Up2 DC/DC control
Addr: 34
This register controls the different modes of the step up2 DCDC
converter
Bit
Bit Name
Default Access
Description
DCDC converter 2 overvoltage protection to prevent
damage of external NFET, if DCDC_CURR1 or
DCDC_CURR2 or DCDC_CURR3 feedback selected, and
no LED string connected:
7
stpup2_prot
00h
RW
0
1
Overvoltage protection disabled
Switch off DCDC step up 2 if the voltage n
DCDC_FB2 exceeds 1.25V
Table 12. stpup1_det and stpup1_oc Bit definitions
Low voltage status bit definitions
Addr: 53
This register shows the status of the overcurrent poteion of the
stepup1dcdc
Bit
Bit Name
Default Access
Description
Step up overcurrent tatus bit
VRnse < VOVCURRENT
1
6
stpup1_oc
NA
NA
R
R
VRsense > VOCURENT for more than 5 msec (latched
state)
p up detection status register
sense < VDETECT for more than 1msecond, and
DCDC Step up converter is in Pulseskip for more than
1 millisecond
0
7
stpup1_det
VRsense > VDETECT for more than 1msecond, or the
DCDC Step up converter is not in Pulseskip for more
than 1 millisecond
8.2
Current Sinks
These are general-purpose current sinks inteded to control the backlight(s), buzzer and vibrator. The low voltage
current sink has an integrated protection aainsover voltage and can therefore also drive inductive loads (VPROTECT).
DCDC_CURR1 and DCDC_CURR2, DCCURR3 are high voltage (15V) current sinks, e.g. for series of white
LEDs
CURR1_GPIO, CURR2_GPIOCURR3_GPIO, CURR4_GPIO are four 5V, 38.25mA current sinks, e.g. for buzzer,
vibrator, LEDs
CURR1_GPIO, CURR2_PIO, CURR3_GPIO, CURR4_GPIO can be used as general propose Input/Output (GPIO)
functions optiona(descibed in section General Purpose Input / Output (CURR1_GPIO1 … CURR4_GPIO4)).
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8.2.1 High voltage Current Sinks (DCDC_CURR1, DCDC_CURR2 and DCDC_CURR3)
Current sinks DCDC_CURR3, DCDC_CURR1 and DCDC_CURR2 can be controlled individually. The step-up DCDC
converter may supply them with voltages up to 15V. If any of these current sinks is used, connected VCURR_GPIO to
a supply with at least 3.0V.
Table 13. Current Sinks Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
Note
DCDC_CURR1,2 and
DCDC_CURR3
For V(DCDC_CURRx) > 0.45V
resolution = 0.15mA
IDCDC_Curr1,2,3
0
38.25
mA
current, 00h-3Fh
Current sink protection
Current
Protection Current if stpup2_on=1
and dcdc_currx_current=00
IDCDC_protect
2
µA
%
Δ
absolute Accuracy
-5
+5
15
All Current sinks
VDCDC_CURR1
VDCDC_CURR2,
VDCDC_CURR3
,
Voltage compliance
0.45
V
during normal operation
Table 14. DCDC_CURR1 Current sink current bit definition
DCD_CURR1 Value
This register controls the current value of the dcdc_curr1 current sink
Addr: 39
Bit
Bit Name
Default Access
escription
Defines the currnt nto DCDC_CURR1 if enabled by
dcc_curr1_ctrl
power down (default state)
00h
7:0
dcdc_curr1_current
00h
R/W
01h
....
0.15mA (LSB)
38.25mA
h
Table 15. DCDC_CURR2 Current sink current bit definition
DCDC_CURR2 Value
This egister controls the current value of the dcdc_curr2 current sink
Addr: 40
Bit
Bit Name
Delt Access
Description
Defines the current into DCDC_CURR2 if enabled by
dcdc_curr2_ctrl
power down (default state)
00h
7:0
dcdc_curr_currnt
00h
R/W
01h
....
0.15mA (LSB)
38.25mA
FFh
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Table 16. DCDC_CURR3 Current sink current bit definition
DCDC_CURR3 Value
This register controls the current value of the dcdc_curr3 current sink
Addr: 45
Bit Name
Bit
Default Access
Description
Defines the current into DCDC_CURR3 if enabled by
dcdc_curr3_ctrl
power down (default state)
00h
7:0
dcdc_curr3_current
00h
R/W
01h
....
0.15mA (LSB)
38.25mA
FFh
Table 17. Current sink control bit definition
CURR control
This register controls the mode of the DCDC curent sinks
Addr: 58
Bit
Bit Name
Default Access
Description
On/ff control of the ad DCDC_CURR1
Curent sink is turned off
0
Currnsink is active
1:0
dcdc_curr1_ctrl
00b
00b
00b
R/W
R/W
R/W
Current sinis active and LED string connected to
stpup2. Requed for automatic feedback selection
10
11
Controd y PWM generator (do not set pwm_div)
OOff control of the pad DCDC_CURR2
Current sink is turned off
00
Current sink is active
3:2
5:4
dcdc_curr2_ctrl
dcdc_curr3_ctrl
Current sink is active and LED string connected to
stpup2. Required for automatic feedback selection
10
11
Controlled by PWM generator (do not set pwm_div)
On/Off control of the pad DCDC_CURR3
Current sink is turned off
00
01
Current sink is active
Current sink is active and LED string connected to
stpup2. Required for automatic feedback selection
10
11
Controlled by PWM generator (do not set pwm_div)
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8.2.2 Low voltage Current Sink (CURR1_GPIO1 … CURR4_GPIO4)
CURR1_GPIO1 … CURR4_GPIO4 can be controlled individually. Each one can sink up to 38.25mA. The voltage on
the current sinks must not exceed the supply VCURR_GPIO (can be connected e.g. to VSUPPLY).
The low voltage current sinks and the gpio pins share the same pins (see General Purpose Input / Output
(CURR1_GPIO1 … CURR4_GPIO4) on page 30) for enabling/disabling of the current sinks / gpio functions.
Table 18. Current Sinks Characteristics
Symbol
Parameter
Min
Typ
Max
38.25
+5
Unit
Note
For V(CURRx_GPIOx) > 0.2V
resolution = 0.15mA,
each current sink
CURR1_GPIO1....
CURR4_GPIO4
current, 00h-1Fh
ICURR1,2,3,4
0
mA
Δ
absolute Accuracy
Voltage compliance
-5
%
V
All Current sinks
V(VCU
RR)
VCurr1,2,3,4
0.2
during normal operation
Table 19. CURR1 Current sink current Bit definition
CURR1 control
This register cotrolte mode of the curr1 crrent sinks
Addr: 41
Bit
Bit Name
Default Access
Description
ethe current intCURR1_GPIO1 if GPIO1_Mode =
011b and outpuenabled (e.g. GPIO1=1)
00h
01h
....
powr down (default state)
0.15mA (LSB)
7:0
curr1_current
(00)h
R/W
FFh
38.25mA
Table 20. CURR2 Current sink currendefinition
CURR2 control
Ths register controls the mode of the curr2 current sinks
Addr: 42
Bit
Bit Name
Deault Access
Description
Defines the current into CURR2_GPIO2 if GPIO2_Mode =
011b and output enabled (e.g. GPIO2=1)
00h
01h
....
power down (default state)
0.15mA (LSB)
7:0
curr2_current
(00)h
R/W
FFh
38.25mA
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Table 21. CURR3 Current sink current Bit definition
CURR3 control
This register controls the mode of the curr3 current sinks
Addr: 43
Bit Name
Bit
Default Access
Description
Defines the current into CURR3_GPIO3 if GPIO3_Mode =
011b and output enabled (e.g. GPIO3=1)
00h
01h
....
power down (default state)
0.15mA (LSB)
7:0
curr3_current
(00)h
R/W
FFh
38.25mA
Table 22. CURR4 Current sink current Bit definition
CURR4 control
This register controls the mode of the curr4 curret sinks
Addr: 44
Bit
Bit Name
Default Access
Descriptio
Defins the crent into CURR4_GPIO3 if GPIO4_Mode =
011and output enald (.g. GPIO4=1)
0h
....
poer down (default state)
015mA (LSB)
7:0
curr4_current
(00)h
R/W
FFh
38.25mA
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8.3
General Purpose Input / Output (CURR1_GPIO1 … CURR4_GPIO4)
Figure 9. CURR1_GPIO1 … CURR4_GPIO4 block diagram
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The device contains 4 high current GPO pins, which share the same pins as the low voltage current sinks and are
capable of sinking 100mA from VCURR_GPIO voltage. Each of the pins can be configured as open drain NMOS or
push-pull output with VCRR_GPIO high levels, as high impedance output or as digital input. When configured as
output the output source can be a register bit, or the PWM generator, furthermore the output signal can be inverted.
Integrated active mp rcuits can be enabled for the open drain NMOS output mode by setting GPIOxPulls=11b,
thus allowing to use te high current GPIO pins for driving inductive loads. A pull-up resistor to VCURR_GPIO can be
enabled for the open drain NMOS output mode by setting GPIOxPulls=10b. When configured as digital input the logic
level (GPxInvert=’0’) or the inverted logic level (GPIOxInvert=’1’) of the pin is reflected by bit GPIOxBit in the GPIO
Bit regis.
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Moreover, a special function can be selected for each digital input pin and a pull-up resistor to VCURR_GPIO or a pull-
down resistor can be enabled.
Table 23. High Current GPIO Pin Characteristics (VCURR1_GPIO1 … VCURR4_GPIO4)
V
=3.0 to 5.5V; T = –20 to +70°C; unless otherwise specified
amb
VSUPPLY
Symbol
Parameter
Min
Typ
Max
Unit
Note
Maximum voltage
on
CURR1...4_GPIO
1…4 pins
VCURR_GPIO
0.3
+
Pin VCURR_GPIO is used as supply for
the GPIO pins
VGPIOMAX
V
IOL=+100mA; digital output
(GPIOxMode=100b and
currX_current=3Fh)
Low level output
voltage switch
mode
VOLH
–0.3
–0.3
+0.35
+0.4
V
IOL=+1mA; digital output
(GPIOxMode=000b ... 010b)
Low level output
voltage
VOL
VOH
VIL
V
V
V
High level output
voltage
0.8·VCURR_G
VCURR_GPIO
0.4
VCURR_GP
IOH=–1mA; digital psh-ull output
dal inut
PIO.
Low level input
voltage
–0.3
1.3
High level input
voltage
VIH
V
digtal input
ILEAKAGE
Rpull-up
Leakage current
Pull-up resistance
µA
kΩ
high impedance
GIOxMode=x0b; GPIOxPulls=10b;
78
VCURR_GPIO=3.6V
digital input; GPIOxPulls=01b;
Pull-down
resistance
Rpull-down
161
VCURR_GPIO=3.6V
Table 24. CURR1_GPIO1 Bit definition
GPIO1
This regontrols the mode of the CURR1_GPIO1 Pin
Addr: 18
Bit
Bit Name
Default Acess
Description
digital open drain NMOS output
(only NMOS enabled)
000b
001b
digital push-pull output
(NMOS & PMOS enabled, no PWM out possible)
digital input
(NMOS & PMOS disabled, digital input logic
enabled)
010b
2…0
GPIO1Mod
ROM
R/W
digital open drain current sink operation Current
defined by curr1_current
011b
100b
digital open drain switch operation On resistance
defined by curr1_current
high impedance (or SD1 in DCDC step
down external controller mode
(sd1_1A_mode = 1100b)).NMOS & PMOS disabled,
digital input logic disabled)
101b
to
111b
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Table 24. CURR1_GPIO1 Bit definition
GPIO1
This register controls the mode of the CURR1_GPIO1 Pin
Addr: 18
Bit Name
Bit
Default Access
Description
input / output signal is written to or set by GPIO1Bit
in the GPIO Bit register
00b
PWM (O) / WDOG (I)
if used for PWM, pwm_h_time and pwm_l_time
define the high and low time of this output and only
allowed for GPIO1Mode=011b,100b
01b
10b
11b
4…3
GPIO1IOSF
ROM
R/W
Protection of DCDC stepUp1 GPIO 1 (O)
Battery charging EOC indication output GPIO (O)
If EOC=1 then GPIO1=1. DCDC_CURR3 is usas
output, if CURR_GPIO1 is used foexternal DCDC
controller
0
1
normal polarity of input / outpt signal
5
GPIO1Invert
GPIO1Pulls
ROM
ROM
R/W
R/W
inverted polarity of int / oput signal
(not possible for PWM out)
no pull-up or pull-down esstor is enabled in all
modes
00b
0b
pull-down resistois enabled in digital input mode
(clmp disabled)
pll-up resistor is enabled for
GP1Moe=000b,010b,011b,100b (clamp
disabled)
7…6
10b
11b
enable active clamp circuit for
GPIO1Mode=000b,010b,011b,100b (pull-up/down
disabled)
Table 25. CURR2_GPIO2 Bit definitio
GPIO2
Addr: 19
Thiregister controls the mode of the CURR1_GPIO2 Pin
Bit
Bit Name
Defaut Access
Description
000b
001b
010b
digital open drain NMOS output
digital push-pull output (no PWM out possible)
digital input
digital open drain current sink operation Current
defined by curr2_current
011b
100b
2…0
GPIO2Mode
ROM
R/W
digital open drain switch operation On resistance
defined by curr2_current
101b
to
111b
high impedance
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Table 25. CURR2_GPIO2 Bit definition
GPIO2
This register controls the mode of the CURR1_GPIO2 Pin
Addr: 19
Bit Name
Bit
Default Access
Description
input / output signal is written to or set by GPIO2Bit in
the GPIO Bit register
00b
01b
10b
PWM (O) / WDOG (I)
if used for PWM, pwm_h_time and pwm_l_time
define the high and low time of this output and only
allowed for GPIO2Mode=011b,100b
4…3
GPIO2IOSF
GPIO2Invert
GPIO2Pulls
ROM
ROM
ROM
R/W
R/W
R/W
Battery charging active indication output GPIO2 (O
If Battery charging = 1 then GPIO2=1
11b
0
NA
normal polarity of input / outpt signal
5
inverted polarity of input / ouput sgnal
(not possible for PWM o)
1
no ull-up or pull-down resitor is enabled in all
modes
00b
1b
pull-down resistor is enabled in digital input mode
(clamp disabled)
7…6
pull-up sistor is enabled for
GPIO2Mode=00b,010b,011b,100b (clamp disabled)
enble active clamp circuit for
GPIOode=000b,010b,011b,100b (pull-up/down
disabled)
11b
Table 26. CURR3_GPIO3 Bit definition
GPIO3
Addr: 20
This regontrols the mode of the CURR3_GPIO3 Pin
Bit
Bit Name
Default Acess
Description
000b
001b
010b
digital open drain NMOS output
digital push-pull output (no PWM out possible)
digital input
digital open drain current sink operation Current
defined by curr3_current
011b
100b
2…0
GPIO3Mode
ROM
R/W
digital open drain switch operation On resistance
defined by curr3_current
101b
to
111b
high impedance
input / output signal is written to or set by GPIO3Bit
in the GPIO Bit register
00b
01b
PWM (O) / WDOG (I)
if used for PWM, pwm_h_time and pwm_l_time
define the high and low time of this output and only
allowed for GPIO2Mode=011b,100b
43
GPIO3IOSF
ROM
R/W
GPIO3 control of regulators if regX_gpio = 1 and
regX_on = 1
10b
11b
Touchpen ADC wait input
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Table 26. CURR3_GPIO3 Bit definition
GPIO3
This register controls the mode of the CURR3_GPIO3 Pin
Addr: 20
Bit Name
Bit
Default Access
Description
0
1
normal polarity of input / output signal
5
GPIO3Invert
GPIO3Pulls
ROM
R/W
inverted polarity of input / output signal
(not possible for PWM out)
no pull-up or pull-down resistor is enabled in all
modes
00b
01b
pull-down resistor is enabled in digital input moe
(clamp disabled)
pull-up resistor is enabled for
GPIO3Mode=000b,010b,011b,100b (clamp
disabled)
7…6
ROM
R/W
10b
11b
enable active clamp circit fo
GPIO3Mode=000b,010b,011b,00b pull-up/down
disabl)
Table 27. CURR4_GPIO4 Bit definition
GPIO4
Addr: 21
This registecontrols the mode of he CURR4_GPIO4 Pin
Bit
Bit Name
Default Access
Description
000b
001b
010b
digital open drain NMOS output
igitpush-pull output (no PWM out possible)
digital input
digital open drain current sink operation Current
defined by curr4_current
011b
0b
2…0
GPIO4Mode
OM
R/W
digital open drain switch operation On resistance
defined by curr4_current
101b
to
111b
high impedance
input / output signal is written to or set by GPIO4Bit
in the GPIO Bit register
00b
01b
10b
PWM (O) / WDOG (I)
if used for PWM, pwm_h_time and pwm_l_time
define the high and low time of this output and only
allowed for GPIO4Mode=011b,100b
4…3
GPIO4IOSF
GPIO4Invert
ROM
ROM
R/W
R/W
GPIO4 control of regulators if regX_gpio = 1 and
regX_on = 0
11b
0
Touchpen dedicated interrupt output
normal polarity of input / output signal
5
inverted polarity of input / output signal
(not possible for PWM out)
1
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Table 27. CURR4_GPIO4 Bit definition
GPIO4
This register controls the mode of the CURR4_GPIO4 Pin
Addr: 21
Bit Name
Bit
Default Access
Description
no pull-up or pull-down resistor is enabled in all
modes
00b
01b
pull-down resistor is enabled in digital input mode
(clamp disabled)
pull-up resistor is enabled for
GPIO4Mode=000b,010b,011b,100b (clamp
disabled)
7…6
GPIO4Pulls
ROM
R/W
10b
11b
enable active clamp circuit for
GPIO4Mode=000b,010b,011b,100b (pull-up/dwn
disabled)
Table 28. GPIO Signal Bit definition
GPIO Signal
Addr: 55
This regiter conols the GPIO state / stus
Bit
Bit Name
Default Access
Description
Tit determines the tput signal of the GPIO1 pin when
selected s output source
0
GPIO1
0
0
R/W
R/W
R/W
R/W
R
This bit determinehe otput signal of the GPIO2 pin when
selcted as output source
1
2
3
4
5
6
7
GPIO2
GPIO3
This bit deternes the output signal of the GPIO3 pin when
selected as output source
0
This bit etermines the output signal of the GPIO4 pin when
selected as output source
GPIO4
This bit reflects the logic level of the GPIO1 pin when
configured as digital input pin
GPIO1_in
GPIO2_in
GPIO3_in
GPIO4_in
NA
NA
NA
This bit reflects the logic level of the GPIO2 pin when
configured as digital input pin
R
This bit reflects the logic level of the GPIO3 pin when
configured as digital input pin
R
This bit reflects the logic level of the GPIO4 pin when
configured as digital input pin
R
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The gpio block includes an internal programmable PWM generator (can be connected to any of the GPIO1_CURR1 …
GPIO4_CURR4 outputs). Its timing is defined by the following tables:
Table 29. PWM Frequency Control High Time Registers
PWM Frequency Control High Time Registers
Addr: 56
This register controls the PWM high time
Bit
Bit Name
Default Access
Description
This bit defines the high time of the pwm generator in
2/fclk_int units
0
1
pwm_div * 2/ fclk_int
pwm_div * 4/ fclk_int
pwm_div * 6/ fclk_int
7:0
pwm_h_time
00h
R/W
2
....
FFh
pwm_div * 512/ fcl_int
Table 30. PWM Frequency Control Low Time Registers
PWM Freuency ontrol Low Time Regers
This registr controls the PWM Low time
Addr: 57
Bit
Bit Name
Default Access
escription
his bit defines the igh time of the pwm generator in
2/clk_int units
0
pwm_div * 2/ fclk_int
pwm_div * 4/ fclk_int
pwm_div * 6/ fclk_int
1
2
7:0
pwm_l_time
00h
R/W
....
pwm_div * 512/ fclk_int
Table 31. PWM Divider Registers bits
CURR control
Addr: 58
This register controls the PWM divider
Dlt Access Description
Bit
Bit Name
This bit defines the divider ratio of the prescaler for the
PWM generator
00
01
10
11
Divide by 1
Divide by 2
Divide by 4
Divide by 16
7:6
pwmdiv
00h
R/W
All Step n DCDC converters and several LDOs can be directly on/off controlled by CURR3_GPIO3 or
CRR4_PIO4. The CURR3_GPIO3 and/or CURR4_GPIO4 pin should be set to digital input mode (GPIO3Mode =
010, GPIO4Mode = 010b) and the following register should be set accordingly:
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Note: The original digital interface on/off signal is used to switch between CURR3_GPIO3 and CURR4_GPIO4; e.g.
if ldo_rf1_gpio is set, ldo_rf1_on is (re-)used to selected either CURR3_GPIO3 (ldo_rf1_on=1) or
CURR4_GPIO4 (ldo_rf1_on=0) as input.
Table 32. Regulator GPIO Control Registers
Reg GPIO Ctrl
Addr: 31
This register enables/disables GPIO control of the regulators
Bit
Bit Name
Default Access
Description
ldo_rf1 on/off control
0
1
Controlled by software (ldo_rf1_on)
Controlled by CURR3_GPIO3, if ldo_rf1_on=1 and
GPIO3IOSF=10b
Controlled by CURR4_GPIO4, if ldo_rf1_on=0 and
GPIO4IOSF=10b
0
ldo_rf1_gpio
0
0
R/W
R/W
ldo_rf2 on/off control
0
1
Controlled by softwre (lo_rf2_on)
1
2
ldo_rf2_gpio
Conroed by CURR3_GPIO3, f ldo_rf2_on=1 and
GPIOIOSF=10b
Controlled by CURR4_GPIO4, if ldo_rf2_on=0 and
GPIO4IOSF=10b
ldo_digon/off control
0
1
Corolled by software (ldo_dig1_on)
Controby CURR3_GPIO3, if ldo_dig1_on=1 and
GPIO3IOSF=10b
Ctrolled by CURR4_GPIO4, if ldo_dig1_on=0 and
GPIO4IOSF=10b;
ldo_dig1_gpio
0
R/W
dnot set ldo_dig1_gpio if DCDC SD1 is in external
controller mode (sd1_1A_mode = 1100b)
ldo_dig2 on/off control
0
1
Controlled by software (ldo_dig2_on)
Controlled by CURR3_GPIO3, if ldo_dig2_on=1 and
GPIO3IOSF=10b
3
ldo_dig2_gpio
R/W
Controlled by CURR4_GPIO4, if ldo_dig2_on=0 and
GPIO4IOSF=10b
do not set ldo_dig2_gpio if DCDC SD1 is in external
controller mode (sd1_1A_mode = 1100b)
sd1 on/off control
0
1
Controlled by software (sd1_on)
4
5
sd1_pio
sd2_gpio
0
0
R/W
R/W
Controlled by CURR3_GPIO3, if sd1_on=1 and
GPIO3IOSF=10b
Controlled by CURR4_GPIO4, if sd1_on=0 and
GPIO4IOSF=10b
sd2 on/off control (or sd2 on/off control in 1A mode)
Controlled by software (sd2_on)
0
1
Controlled by CURR3_GPIO3, if sd2_on=1 and
GPIO3IOSF=10b
Controlled by CURR4_GPIO4, if sd2_on=0 and
GPIO4IOSF=10b
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Table 32. Regulator GPIO Control Registers
Reg GPIO Ctrl
This register enables/disables GPIO control of the regulators
Addr: 31
Bit Name
Bit
Default Access
Description
Sd3 on/off control
0
1
Controlled by software (sd3_on)
6
sd3_gpio
0
0
R/W
R/W
Controlled by CURR3_GPIO3, if sd3_on=1 and
GPIO3IOSF=10b
Controlled by CURR4_GPIO4, if sd3_on=0 and
GPIO4IOSF=10b
ldo_dig3 on/off control
0
1
Controlled by software (ldo_dig3_on)
7
ldo_dig3_gpio
Controlled by CURR3_GPIO3, if ldodig3_on=1 and
GPIO3IOSF=10
Controlled by CURR4_GPIO4if ldodig_on=0 and
GPIO4IOSF=1b
8.4
Backup Battery Charger
The backup battery charger operates as a programmable voltage liited current source with selectable output
resistor. It is enabled by setting BBCMode in the Backup Bharger register o a value other than ‘00’b and offers
the following features:
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Backup battery presence detection
Selectable output resistor (RBBCOUT) to reducte urrent at higher oltags
Programmable charge current IBBC
programmable maximum charging volage VBBC
Reverse current protection turns ofbacup battery chargautomatically if VSUPPLY<VVBACK; as soon as VSUPPLY
exceeds VVBACK charging is starteain automatically
ꢀ
ꢀ
Charging is stopped automatically as soon as the bbattery is fully charged; if the voltage on pin VBACK
drops charging is started again automatically
In case the main supply voltage VSUPPLY is larer tan VVBACK charging of the backup battery is possible in state
“Off” as well; the device will check VVBAK every minute to determine if charging is required.
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Figure 10. Backup Battery Charger Block Diagram
Voltage limited
Current source
VBACK
Rb
VSUPPLY
Digital
Control
Table 33. Backup Battery Charger Characteristics
symbol
Parameter
Min
3.0
3.3
2.4
2.9
Typ
Max
5.5
5.5
.6
3.1
Unit
Nte
BBVolt=0’
BCVolt=’1’
BCVolt=’0’
BBCVolt=’1’
VSUPPLY
Supply voltage range
V
2.5
3
Maximum charging
voltage
VBBC
V
Value is set by BBCCur in the
Backup Battery Charger register
IBBC
Charge current
-30% BBCCr +30%
A
Delta voltage for
resistive mode
VDELTA
16
220
300
V
BBCResOff=’0’
0
BBCResOff=’0’
BBCResOff=’1’
IVSUPPLY
Supply current
µA
BBCPwrSave=’1’; backup battery
full.
0.5
Table 34. Backup Battery Charger Register
Backup Battery Charger
This register controls the Backup battery charger mode
Addr: 38
Bit
Bit Name
Delt Access
Description
00b
01b
Backup battery charger is disabled
Backup battery charger is enabled in states “Power
Off mode”, “standby mode” and “Active mode”.
(32kHz OSC has to be enabled in that mode
rtcmode=01b or 10b)
1:0
BBCMode
00b
R/W
Backup battery charger is enabled in state “Active
1Xb mode” and “standby mode”. (32kHz OSC has to be
enabled in that mode rtcmode=01b or 10b)
0
1
Enable output resistor
Bypass output resistor
2
BBCResOff
BBCCur
0
R/W
R/W
This value determines the charge current IBBC
.
IBBC=50µA
BBC=200µA
00b
10b
01b
11b
I
4:3
00b
IBBC=100µA
BBC=400µA
I
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Table 34. Backup Battery Charger Register
Backup Battery Charger
This register controls the Backup battery charger mode
Addr: 38
Bit Name
Bit
5
Default Access
Description
This value determines the maximum charging voltage
VBBC
.
BBCVolt
0
1
R/W
R/W
VBBC=2.5V
VBBC=3.0V
0
1
0
Normal operation of the backup battery charger
6
BBCPwrSave
The backup battery charger checks if it is actually
charging the battery (bit BUChAct=’1’) and is
disabled if it is not. Every 10s (every 64s in ste
“Off”) the voltage of the backup batery is checked
again to determine if charging is reuired. This
practically reduces the current cosumption to 0 if
the backup battery is fl.
1
reserv
7
-
-
Figure 11. Backup Battery Charger Characteristics
IBACK
400µA
Rb=0FF
Rb=0N
200µA
100µA
50µA
VBACK
Vback_lim-VDelta
Vback_lim
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8.5
Smooth switchover Power Management Overview
Figure 12. Power Source Management Architecture
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The power source management architecture handles the smooth transitions etwen the two chargers (USB Charger
on VBUS, DCDC Step Down charger or Linear Charer on VCHARGER) and te battery. It takes care about the
system power supply VSUPPLY and its power rquirements.
There are following operating conditions possble
1. No Charger connected
The internal switch SINT and the (opnal) external switch MATSW are closed and VSUPPLY is directly supplied by
VBAT. Because of the very low impnce of the swithe energy losses are minimized.
2. The active charger can deliver more current than the m requires
The system is directly supplied by the charger nd the remaining energy can be used to charge the battery (CC/CV
charger). In case of deeply discharged batteriesthe system is always immediately started and the internal current
source between VSUPPLY and VBAT deliers the trickle current to the battery.
3. The current limited (e.g. for USB with 500m) charger cannot deliver the current, the system requires
In this case, the ideal diode starts cnding and delivers the remaining current to the system
The transitions between the different power states are done autonomously by the AS3658 allowing an uninterrupted
operation of the system.
The blocks are described in mordetail in the following sections.
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8.6
Battery switch SINT (Vsupply, Battery)
Figure 13. Battery Switch Diagram
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The internal Battery switch enables normal operation of the System dutrickle charging of a deeply discharged
battery.
The Switch provides the following functios:
ꢀ
Trickle charging, if VBAT is smaller an ResVolt. The currnt is defined in TrickleCurrent[1:0]
PMOS is switched on if VBAT is grr then ResVolt.
ꢀ
Constant current charging, if the external charger is ar operation, or the USB charger is used. the current is
defined by constant_current[2:0].
ꢀ
ꢀ
ꢀ
Current limitation during tricklecharge, to avoid nruh current: Itrickle_Ilimit
Current limitation during Constant currencharging to avoid inrush current: ICC_Ilimit
Undervoltage protection of Vsupply dug trickle charge or constant current charge with linear charger. The
charging current is regulated down, if upply drops below Vsupply_min
ꢀ
Ideal diode operation in IsolatBatery mode and disable charging mode, during charger is unplugged. This
operation is for the internal attery switch only. External battery switch is open in that mode. Regulation will start, if
the VSUPPLY voltage dops bmore then VDiode below the VBAT voltage. After three milliseconds debounce time,
if no charger is recogized, he internal and external battery switch (if enabled) is closed to have a low Ω ic
connection between VBT and VSUPPLY.
Table 35. Battery sitch parameters
Symbo
Vy
Parameter
Input voltage
Min
Typ
Max
Unit
V
Note
3.0
5.5
PIN VSUP_SW1,VSUP_SW2
Itricklelimit
Trickle current limit
400
mA
Current Limit in constant current
mode (Linear charger mode or USB
charger only)
Note: applies only for the battery
switch alone
Constant current
current limit
ICC_limit
800
mA
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Table 35. Battery switch parameters
Symbol
Parameter
Min
Typ
Max
Unit
Note
Ideal Diode start
voltage
VDiode
50
mV
3.9
3.6
4.2
4.5
Vsupply level for
charging current
regulation (reduction),
to avoid voltage drop
on vsupply
Trickle current (or constant current in
linear mode) will be regulated down,
if vsupply drops below this level
Vsupply_min
-6%
3%
V
SINT P-Switch ON
resistance
RSW
0.10
Ω
VSUP_SW=3.6V
Table 36. USB-Charger Bit definitions
USB Charger Control
Addr: 10
This register controls the mode of the USB charger, and te chrger state
machine
Bit
Bit Name
Default Access
Description
Ovetemperature potection of battery switch
enbled. (If battery switch is icurrent source mode,
charging is stopped if chip temperature exceeds
110º)
0
5
dis_batsw_tmp_prot
ROM
ROM
R/W
R/W
Over tempeture protection of battery switch
disabled
1
0
Extebattery switch disabled (Pin BAT_SW =
max(VSUPPLY,VBAT))
7
ext_batsw_en
Extenal battery switch enabled (Pin BAT_SW=0V, if
atus bits batsw_on=1 and batsw_mode=1. These
bs are controlled by the charger state machine)
1
Table 37. Battery switch status Bit definitions
Charger status_usb
Addr: 100
These bits show the status of the battery switch
Bit
Bit Name
DefauAccess
Description
Trickle charging (or constant current charging in
linear mode), if batsw_on=1. External PMOS switch
disabled
0
1
2
batsw_mode
NA
NA
R
R
Switch on Battery switch, if batsw_on=1. External
PMOS switch enabled
0
1
Battery switch off
3
basw_o
Battery switch on (Mode defined by batsw_mode)
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8.7
External Step Down/Linear Charger
The inductive dcdc step down charger (or the external linear charger) converts the input voltage from VCHARGER to
VSUPPLY. The system (DCDC converters, LDOs…) are connected directly to VSUPPLY; the ideal diode and the internal
battery switch SINT (together with the external battery switch MBATSW) connect VSUPPLY to VBAT to allow charging of
the battery.
Figure 14. Step Down Charger Application Diagram with optional reverse polarity and short protection
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If the input voltage can be up t50V additional three transistors and a simple voltage regulator with a zener diode are
required. These circuit ‘isolaes’ the AS3658 from the high input voltage and keep the pins VCHARGER, VOFF_B and
VGATE within its operatig limits (<15V). The actual circuit is shown in the following figure:
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Figure 15. Charger Block Diagram for voltages >15V (Protection up to 50V; minimum Vcharger voltage 8V)
ꢀ
Instead of using an inductive DCDC stdown charger, the AS3658 supports external linear charging mode with an
PMOS transistor. The operating mode selected by cong the pin VOFF_B to GND (for 5.5V limited chargers,
the USB charger can be used alternatively):
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Figure 16. External Linear Charger Application Diagram (VOFF_B connected to GND)
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Table 38. Charger External Components
Symbol
Componen
alue
Note
MCHARGER,
MBATSW,
MREVPOL
P-channel MOSFET
Si103, FDC642P or FDC5614P similar
MCHRGPU
RCHRGPU1
P-channel MOSFET
Pull-up resistor1
BSS84 or FDG312P or similar
2kΩ ± 5%
100Ω ± 5%
for MCHRGPU =BSS84
for MCHRGPU=FDG312P
5V or 6V Vcharger input
12V Vcharger input
RCHRGPU2
LCHARGER
Pull-up resistor2
50Ω ± 5%
10µH
Inductr for charging
22µH
DCHARGER
Diode
MBRS130 or PMEG2010
5.6V Zener Diode
DCHRGPROT
Zener Diode
Current sense resistor
charger
e.g. Vishay Dale WSL0805
series
RCHSHUN
RSNSE
70mΩ ± 5%, 125mW
e.g. Vishay Dale WSL0805
series
50mΩ ± 1%, 125mW for IVBAT,DC<1.5A
Current sense resistor
RILTER1,2
CFILTER
Filter resistor
4.7kΩ ± 1%
Can be omitted if fuel gauge
and charger functionality is
not used
Filter capacitor
1µF ± 20%, X5R or X7R dielectric
Bypass capacitor on
charger pin
1µF ± 20%, X5R or X7R dielectric +
22µF ± 20%, Tantal dielectric
CCHARGER
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Table 38. Charger External Components
Symbol
Component
Value
Note
Minimum total
capacitance parallel to
Vsupply
22µF± 20%, X5R or X7R dielectric
47µF± 20%, X5R or X7R dielectric
10 µH inductor
22 µH inductor
CVSUPPLY
Figure 17. Step down charger Efficiency (Measured) VSupply=4.4V
Step down charger
100
90
80
70
60
50
40
30
20
10
Vcharger=5V, =550Hz
Vcharger=6f=50kHz
Vcharger12V, f=550kHz
Vcharger=5V, f=275kHz
Vcharger=6V, f=275kHz
Vcharger=12V, f=275kHz
0
0,0000 0,2000 0,4000 0,600 0,8000 1,0000 1,2000
Otput current (A)
8.7.1 External Step Down/Linear Charger Characteristics
The battery charge controller controls the external tep Down/ Linear charger.
During Trickle charge of the deeply dischargd battery the step down/Linear converter regulates the Vsupply to Vchlimit
.
In step down charger mode, If the VBAT voge exceeds ResVoltRise, the internal battery switch is switched on, the
Vsupply voltage drops down to VBAT immately, and the step down converter operates as controlled current source
to Vsupply. The battery current is egulated to the value defined in ConstantCurrent register.
In linear charger mode, the Vsuply is still regulated to Vchlimit, if the VBAT voltage exceeds ResVoltRise. The current is
regulated by the battery switch to the value defined in the constant current register.
In EOC operation (see Batery Charge Controller on page 51), the operation of the charger depends on the bit
isolate_battery:
If isolate_battery = 1 nd EOC the output is regulated to Vchlimit.
If isolate_battey = 0 and EOC the output is not allowed to drop below VEOC (3.6V).
Tale 3Step down Charger parameters
Symbol
Parameter
Min
Typ
Max
Unit
Note
Current limit voltage at
Rsense
e.g.: 1.4A for 0.07O sense
resistor typ.
Vrsense_max
70
100
130
mV
Output capacitor with 10µH
inductor
Cout_10
20
60
µF
X7R ceramic
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Table 39. Step down Charger parameters
Symbol
Parameter
Min
Typ
Max
Unit
Note
Output capacitor with 22µH
inductor
Cout_22
40
60
µF
X7R ceramic
Output capacitor in linear
mode
Cout_Linear
20
60
µF
X7R ceramic
L
Inductor
10/22
400
µH
(see Table 38)
Itrickle_limit
Trickle current limit
mA
Table 40. Step down Charger Bit definitions
Step Down charger control
These bits configures the step down charger
Addr: 37
Bit
Bit Name
Default Access
Description
0
1
0
fclk_int/4 (use as defaultif Vhargr>6V)
fclk_int/8 (use as defalt, if charger<6V)
Disable 00% PMOS on mode r step down charger
0
sdc_frequ
0
1
R/W
R/W
1
2
sdc_pon
Eable 100% PMOS on ode to reduce voltage drop
in low dropout regulation
1
Normal mode of step down charger mode
step down harer in pass through mode. Use this
mode with max. 5.5V charger only.
VsupVcharger in that mode, if no_charging=1.
sdc_pass_mode
0
R/W
1
8.8
USB Charger
Figure 18. USB Charger Block Diagra
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The AS3658 serves an integrated USB charger for Li+ batteries. The USB Charger is a current and voltage limited
charger, which can be used to charge Li+ batteries directly from the USB supply. The VBAT voltage limit is set by the
register ChVoltEOC (3.9V – 4.25V in 50mV steps; identical for USB charger and step down charger) and the current
limit is set by the register usb_current (94mA to 881mA). The Vsupply voltage limit is set to Vchlimit during trickle and
constant current charging.
For USB charging, it is recommended to start with a current limit of 94mA and after negotiates via the USB bus (this
has to be done by e.g. the uProcessor directly) a different current setting can be set to speed up charging (e.g.
470mA).
If Bit usb_chgEn=1 in the Boot ROM is set, VSUPPLY can start up with USB supply allowing startup from the USB
supply.
If ChEn=1 and chdet=1 (external charger enabled and connected) the usb_charger will be deactivated automaticlly
(The Battery charger overrides the USB charger). It's not possible to use the internal and the external charger
parallel.
End of charge of the USB charger is reached, if the current through the battery falls below the value et in the
Tricklecurrent [1:0] register.
Table 41. USB-Charger Bit definitions
USB Charger control
Addr: 10
This register controls the modof the USB chrger, and the charger state
machine
Bit
Bit Name
Default Access
Dscription
Sets the SB input current limit.
94mA (USB low current)
141mA
(0000)b
(0001)b
(0010)b
(011)b
0100)b
0101)b
(0110)b
(0111)b
(1000)b
(1001)b
(1010)b
(1011)b
(1100)b
(1101)b
(1110)b
(1111)b
189mA
237mA
285mA
332mA
380mA
3:0
usb_Current
RO
R/W
428mA
470mA (USB high current)
517mA
598mA
668mA
759mA
881mA
881mA (do not use)
881mA (do not use)
ON/OFF control of USB charger
USB charger disabled.
USB charger enabled.
4
usb_chgEn
ROM
R/W
0
1
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Table 41. USB-Charger Bit definitions
USB Charger control
Addr: 10
This register controls the mode of the USB charger, and the charger state
machine
Bit
Bit Name
Default Access
Description
Overtemperature protection of battery switch
enabled. (If battery switch is in current
source mode, charging is stopped if chip
temperature exceeds 110ºC)
0
5
dis_batsw_tmp_prot
no_charging
ROM
ROM
ROM
R/W
R/W
R/W
Overtemperature protection of battery switch
disabled
1
0
Normal battery charger operation (sb
charger and/or step down charger
USB and Step down charger is supplying
VSUPPLY, but battery swich is open.
USB charger or external cargeregulate to
Vchlimit
6
7
1
0
1
External battery witch isabled (Pin
BAT_SW= VSPPLY,VBAT)
External baey witch enabled (Pin
BAT_SW=0V, if status bits batsw_on=1 and
batsw_me=1. These bits are controlled by
thcharger state machine)
ext_batsw_en
Table 42. Charger status Bit definitions
Cher status_usb
Addr:100
These bits shw the status of the USB charger
Bit
0
Bit Name
USB_ChDet
USB_Chact
Defult Access
Description
set to 1 if charger is detected
NA
NA
NA
R
R
R
1
Set to 1 if charger is active
4
Ch_overvoltage
Set to 1 if overvoltage on pin VCHARGER is applied
Charger Detection:
The Charger will be detected by compaisof the V_USB voltage with the Vsupply voltage.
If V_USB is 50mV higher than VSupply vge or V_USB > 4.3V or the USB_ChDet is set to 1.
Table 43. USB Charger CharactesticVUSB=4.3…5.5V; Tamb=–20…+85°C; unless otherwise specified.
Symbol
Pramter
Min
Typ
Min
Unit
Note
USBurrent for 500mA
election
Resistor on pin RBias to ground of
Iusbcurrent500mA
440
470
500
mA
220kΩ
USBcurrent for 100mA
selection
Resistor on pin RBias to ground of
Iusbcurrent10
84
95
104
mA
220kΩ
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Table 44. USB-Charger additional trimming
USB Current control
This register adds or subtracts current limit
Addr:130
Bit Name
Bit
Default Access
Description
Increase or decrease The USB current limit for additional in
system trimming:
100
101
110
111
000
001
010
011
usbcurrent-5.1%
usbcurrent-3.8%
usbcurrent-2.5%
usbcurrent-1.2%
usbcurrent+0%
usbcurrent+1.2%
usbcurrent+2.5
usbcurrent+3.%
2:0
usb_add_trim_current
00h
R/W
8.9
Battery Charge Controller
The AS3658 device serves as a standalone battery chargcontroller supporting rechargeable lithium ion (Li+) and
nickel metal hybrid (NiMH) batteries. Requiring only a few nacomponents, ull-featured battery charger with a
high degree of flexibility can easily be realized. The main feures of the controller a:
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Charge adapter detection
Charging of deeply discharged batteries
Low current (trickle) charging
Real constant current charging by regulatin of the battery curreninstead of the charge current
2 different top-off charging modes: ulse charging and costant voltage charging
Fuel gauge enables highly accuraemaining capastimation of the battery
Overvoltage protection for charge adapter input and battery
Battery presence indication
Operation without battery
Reverse polarity and short protection
Charging timout timer
Battery NTC supervision
8.9.1 Charge Controller Oerating Modes and Building Blocks
Linear Step down Chrger detection
The charging ciruit auomaically detects, if a step down charger or a linear charger is connected externally, by
measuring the volte on the pin VOFF_B. If this pin is tied to GND, the circuit detects a linear charger. Otherwise the
step down charger is etected
Charge apter detection
Te chae cntroller uses an integrated detection circuit to determine if an external charge adapter has been applied
to te VCHARGER or V_USB pin. If the adapter voltage exceeds the supply voltage at pin V_SUPPLY5 by VCHDET the
ChDet or USB_CHDet bit in the Charger Status register will be set. The detection circuit will reset the charge controller
(ChDet or USB_CHDet is cleared) as soon as the voltage at the VCHARGER or USB_CHDet pin drops to only VCHMIN
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above the battery voltage. In case the AS3658 device is reset the charge controller will also be reset, even if a charge
adapter is applied to the VCHARGER or V_USB pin.
Charging deeply discharged batteries
To be able to charge even completely discharged batteries the AS3658 device contains an internal voltage regulator
that uses the voltage of the external charge adapter at pin VCHARGER or V_USB to generate a bootstrap voltage
V2_5V to supply the internal circuitry necessary for charging. As soon as the battery voltage exceeds 2.5V, the
bootstrap regulator is disabled and the battery voltage will be used to generate the internal supply voltage to supply the
charger circuitry.
Low current (trickle) charging
Trickle charge mode is started when an external charge adapter has been detected and ChEn or usb_chgEn is st,
and the battery voltage at pin V_BAT is below the ResVoltRise threshold VRESRISE. The Battery switch is open n th
case (batsw_on=1 batsw_mode=0). Bits ChAct and/or USBChAct and Trickle will be set in the Charger Status
registers. In this mode the charge current into the battery will be limited to TrickleCurrent (set in the Charger Current
register) by the battery switch to prevent undue stress on either the battery or any of the charger ompnents in case
of deeply discharged batteries. if Vsupply drops below Vsupply_min threshold the trickle current is regated down, to
keep the Vsupply voltage up, even with an current limited charger (e.g.:USB charger). Once VRESSE has been
exceeded, the battery switch will be closed and the charge contrller wproceed to constant crrent charge mode.
The Vsupply voltage of the step down charger will be set to Vcu_preseto prevent undrvoltage on vsupply during
the transition between Trickle and constant current chargi.
Constant current charging
Constant current charging is initiated by setting bit ChEn andor USBChEn in the harger Control register, and
resetting the No_charging bit. Note that ChEn andor USBChEn should be seby default to enable operation of the
device without a battery connected to the system. The ChAct and/or UShAct bit is set when the charger has started,
and the charge current into the battery will blimied to ConstantCrent set in the Charger Current register) by the
battery charge controller. When the batteraproaches full charge, itinstantaneous voltage will exceed the charge
termination threshold VCHOFF. VCHOFdepnds on the ChVoltEOCThe top-off charge mode will be started (bit CVM
will be set).
Constant voltage charging
Constant voltage charge mode is initiated and the CVM bit will be set when the VCHOFF threshold has been exceeded
for the first time and bit Pulse is not set. In the following the charge controller will act to regulate the battery voltage to
a value set by ChVoltEOC in the Charger Cofig register.
The charge current is monitored during cotant voltage charging. It will be decreasing from its initial value during
constant current charging and eventually p below the value set by TrickleCurrent in the Charger Current register. If
the measured charge current is les than or equal to TrickleCurrent and the battery voltage is larger than VCHRES, the
charging cycle is terminated anEOC is set. Then the charge controller starts the EOC operation.
EOC operation
There are two possibilies:
1. If isolate_bat=1 he battery switch will be switch off and the battery charger regulates to its highest voltage Vchlimit.
.
The advanage of this mode is a longer lifetime of the Li+ battery, because there is no discharging after the EOC
condition. Iautresume=1 and the battery voltage drops below VCHRES the battery charger continues charging, by
checin trickle charge mode, if there is a battery connected, and then starting with constant voltage.
2If isolae_bat=0 the battery switch remains closed for step down charger or will be closed for linear and usb charger,
ad the power to the system is supplied by the battery. The battery charger and the USB charger regulates to VEOC
in cse the battery is removed. If autoresume=1 and the battery voltage drops below VCHRES the battery charger
continues charging, by checking in trickle charge mode, if there is a battery connected, and then starting with
battery charging.
,
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Battery Detection and Restart of Charging:
In EOC state, If the battery voltage drops below VCHRES and the bit AutoResume is set, the battery detection is
started. The battery switch will be switched into current source mode and VSUPPLY will be regulated to Vchlimit (all
charger). The AS3658 measured the battery current with the fuel gauge in this mode. If there is no current, the AS3658
is kept in this state and the bit NoBat is set. Otherwise the bit NoBat is cleared and the charger and the AS3658
continues in battery charging mode. In addition, if the ntc_on<1:0>=01b (NTC temperature supervision is active) the
NoBat bit is cleared and charging is restarted, if a NTC resistor with normal or high temperature is detected.
Overvoltage protection for external linear charger:
During charging with the external linear charger the battery charge controller constantly monitors the voltage of the
charge adapter at pin VCHARGER. In case the charge adapter voltage exceeds VVCHIN,MAX rise for longer than
3mesec and bit ChOVDetEn in the Charger Control register is set to 1, charging is disabled immediately. If the voltag
on the pin VCHARGER drops below VVCHIN,MAX fall, the charger is re-enabled.
Figure 19. Typical charging cycle (step down charger)
VCHARGER = 6V
VSUPPLY = 4.V (isote_bat=1)
VSPLY = .2V (isolate_bat=0)
VBA= 4.2V
VSUPPLY = 4.4V
VBAres_rise (e.g: 3.4V)
VBAT = 2V
I
BAT = ConsntCuent (e.g 700mA)
Constantvoltage
EOC
IBAT = TricleCurrent (e.g 200
IBAT = 0mA
CH_ET = 1
CH_DET = 0
I2C Write
NO_CHARGING = 1
NO_CHARGING = 0
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Figure 20. Typical charging cycle (External linear charger or USB charger)
VCHARGER = 6V
VSUPPLY = 4.4V...5.0V (isolate_bat=1)
VSUPPLY = 4.4V..5.0V
V
= 4.2V (isolate_bat=0)
SUPPLY
VBAT = 4.2V
VBAT = Vres_rise (e.g: 3.4V)
VBAT = 2V
I
BAT = ConstantCurrent (e.g 700mA)
Constantvoltage
EOC
IBAT = TrickleCurrent (e.g 200mA)
I
BAT = 0mA
CH_DET = 1
CH_DET = 0
I2C Write
NO_CHARGING = 1
NO_HARGING = 0
Table 45. Charger Characteristics VB=3.0…5.5V; Tamb=–0…+85°C; unless otherwise specified
Symbol
Parameter
Min
Typ
Unit
Note
Voltage limit of charger
(if not in current
ch_volt
ae
Vchlimit
-3%
3%
V
Max. Vsupply voltage
limitation mode)
For input voltage higher than 15V see
above protection circuit; for chargers with
input voltages down to 4.5V see:
‘Application Note for DC/DC Step down
Charger for
VCHARGER operating
range
VCHARGER
15.0
V
Chargers Supplying 4.5V to 5.5V’
VCHDET
VCHMIN
50
0
75
20
105
35
mV
mV
Charge adater
detection hreshold
Hysteresis is > 40mV; for USB and step
down charger
Vchdet falling threshold, if
VSUPPLY>4.35V for V_USB and
VCHARGER, and for V_USB, if
usb_hold_chdet=1. Warning:
Backcharging is possible if
usb_hold_chdet=1
Charge adapter
VCHMIN_hold
-5
-20
-40
7.0
mV
detction hold voltage
Charger adapter
overvoltage threshold
rising
ChOVDetEn=’1’ for external linear
charger only
Vc,max
6.0
6.5
6.0
V
V
rise
Charger adapter
overvoltage threshold
falling
ChOVDetEn=’1’ for external linear
charger only
Vchin,max fall
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Table 45. Charger Characteristics VVBAT=3.0…5.5V; Tamb=–20…+85°C; unless otherwise specified
Symbol
Parameter
Min
Typ
Min
Unit
Note
Maximum load current
during startup on
Vsupply
ISTARTmax
5
mA
Undervoltage lockout
threshold
2.7…
3.4
Value is set by ResVoltRise in the Battery
Voltage Monitor register
VUVLO
–3%
+3%
V
V
Charge termination
threshold
3.90…
4.25
Li+ battery; value is set by ChVoltEOC in
the Charger Config register
VCHOFF
–0.06
+0.06
Value is set by ChVoltResume in the
Charger Config register. Do not et
Charger resume
voltage
3.85…
4.20
VCHRES
V
VCHRES higher than VCHOF!
VRESRI
SE
Charger constant
Vcurr_preset
V
V
+
current pre-set voltage
100mV
If isolate_bat=0; to pevent a system reset
if the battery is removed in EOC operation
VEOC
Charger EOC voltage
3.60
Table 46. Charger status Bit definitions
Charger statu
These bits show thstatus of the charger
Addr:99
Bit
Bit Name
Default Acces
Description
Biset when external charge adapter has been
detected on pin VCHARGER
0
ChDet
NA
NA
R
R
Biis set when step down charger is operating
(independent of Reg. bit no_charging)
1
ChAct
is set when battery voltage has dropped below resume
level
2
3
4
Resume
Trickle
CVM
NA
NA
NA
R
R
R
Bit is set when charger is in trickle charge mode
Bit is set when charger is in top-off charge mode
(constant voltage mode)
Bit is set when charging has been terminated. Bit is
cleared automatically when ChEn is cleared, no_charging
is set or charging is resumed.
5
6
7
EOC
Noat
A
NA
NA
R
R
R
Bit is set when battery detection circuit indicates that no
battery is connected to the system. Detection is started
after EOC and if bit autoresume=1 only. Bit is cleared
automatically when a battery is connected, when DisBDet
is set and/or when ChEn is cleared.
Bit is set, if Linear charger is detected, and chDet=1. This
state is latched on the rising edge of chDet. Detected if
VOFF_B is connected to ground
ChLinear
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Table 47. Charger control Bit definitions
Charger Control1
Addr:11
Bit Name
These bits controls the charger
Description
Bit
Default Access
Disable step down charger (Independent of bit
0
no_charging)
0
ChEn
ROM
R/W
Enable step down charger (default) (Independent
of bit no_charging)
1
0
Startup of AS3658 if charger is connected in
power_off mode
Don't exit power off mode, if charger is already
connected before entering power off modno
autonomous charging upon static charger dect.
Startup with rising edge of VCHARGER or V_USB,
RTC wakeup and XON ponly
1
Ch_pwroff_en
ROM
R/W
1
Overvoltage detection with linear xternal charger
enabled
0
1
2
3
4
CHOVDetEn
AutoResume
ROM
ROM
ROM
R/W
R/W
R/W
Ovvoltage detection with near external charger
enbled. Battery charging disabled, if voltage
xeeed
Charging dos not restart automatically in EOC
whn bit Resume is set.
Charging will rstart automatically in EOC when bit
1
0
Resume is set
Normal charge_detect operation
harger detect of USB charger will not be reset, if
USB=VBAT. (Allow Battery charging, with
_USB<4.4V down to 3.3V); for this case, software
should detect the removal of the charger
usb_hold_chdet
1
Read: no timeout
reached
1
Write: reset charger timeout counter
5
6
charging_tmax
Ch_det_500ms
ROM
ROM
/W
R/W
tCHARGING,MAX timeout reached and charging
stopped
Controls the charge detect debounce timer on pin
VCHARGER, if external charger is connected. (If the
charger is removed the debounce time is always 3msec)
VCHARGER debounce timer is 3msec
CHARGER debounce timer is 500msec
0
1
V
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Table 48. Battery, supply voltage Bit definitions
Battery voltage monitor
These bits controls the battery/Supply voltage monitor (Reset levels)
Addr:12
Bit Name
Bit
Default Access
Description
This value determines the reset level VRESRISE for rising
VBAT. It is recommended to set this value at least 200mV
higher than VRESFALL
.
VRESRISE=2.7V
VRESRISE=2.8V
VRESRISE=2.9V
VRESRISE=3.0V
VRESRISE=3.1V
000b
001b
010b
011b
100b
101b
110b
111b
ROM
(101b)
2:0
ResVoltRise
R/W
V
RESRISE=3.2
VRESRIS=3.3V
RESRISE=4V
V
This vaue determines the reslevel VRESFALL for falling
T. It is recommended to set this value at least 200mV
lowehan VRESRISE
.
VRESFALL=2.7V
00b
001b
010b
011b
10b
1b
110b
111b
V
V
V
=2.8V
=2.9V
=3.0V
RESFALL
RESFALL
RESFALL
ROM
(01b
5:3
ResVoltFall
/W
VRESFALL=3.1V
V
V
V
=3.2V
=3.3V
=3.4V
RESFALL
RESFALL
RESFALL
A reset is generated if Vsupply falls below 2.7V.
(If VVBAT falls below VRESFALL only an interrupt is
generated (if enabled) and the Processor can shut
down the system)
0
1
RM
(0b)
6
7
SupResEn
FaResn
R/W
R/W
A reset is generated if Vsupply falls below
VRESFALL
0
1
Vresetfall debounce time = 3msec
Vresetfall debounce time = 4µsec
ROM
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Table 49. Charger Config Register
Charger Config
Addr:13
Bit Name
These bits configure the charger
Description
Bit
Default Access
Sets the end-of-charge voltage level VCHOFF
.
000b
001b
010b
011b
100b
101b
110b
111b
3.90V
3.95V
4.00V
4.05V
4.10V
4.15V
4.20V
4.25V
2:0
ChVoltEOC
Vsupply_min
ChVoltResume
ROM
Reguate down battery charging rrent on that level of
Vsuply durig trickle charging and/linear charging, to
pevent voltage dop on vsupply:
b
b
10b
11b
3.90V
4:3
ROM
3.60V
4.20V
4.50V
Sethe resume voltage level VCHRES
000b
00b
0b
11b
100b
101b
110b
111b
3.85V
3.90V
3.95V
4.00V
4.05V
4.10V
4.15V
4.20V
7:5
ROM
8.9.2 Fuel Gauge
The fuel gauge circuit enableremaining capacity estimation of the battery by tracking the net current flow into and out
of the battery using a voltge-to-frequency converter.
Voltage-to-Freqency Converter
The voltage-to-frequency (VFC) converter constantly monitors the voltage drop across an external current sense
resistor Rsense conected in series between the negative battery terminal and ground. The use of an additional
externalowpass filter is highly recommended. Using two 4.7kΩ resistors (Rfilt1,2) and a 1µF ceramic capacitor
(ilt), the ilter cut-off is approximately 16.9 Hz. This filter will capture the effect of most spikes, and will thus allow the
currnt accumulators to accurately reflect the total charge that has gone into or out of the battery.
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The key building block of the VFC is an integrator. It will integrate the voltage VSNS across input pins ISENSP and
ISENSN. If VSNS is positive (battery is charged), the output voltage of the integrator increases; a negative input voltage
(battery is discharged) will cause the integrator output voltage to decrease.
Table 50. Fuel Gauge parameters
Symbol
fCLK
Parameter
Min
Typ
Max
Unit
MHz
Hz
Note
fclk_int
2
/
Internal reference
clock
internal CLK frequency/2
Programmable: 0.8 to 1.15 MHz
fVFC
f
CLK/59
Sample frequency
Input voltage
VISENSP
VISENSN
-0.1
0.1
V
ZISENSP
ZISENSN
Input impedance
4.67
MΩ
Discharge and Charge
gain
AVFC
FRVFC
VOFF
91.0
3.05
Hz / V
µVh
fCLK = 1.1MHz
Fundamental rate
Uncompensated offset
voltage
-500
-50
500
50
µV
Compensated offset
voltage
VOFF,COMP
±
Charge Current Accumulator
The output signals of the charge count dividers arused as inputs for the chage current accumulator that is realized
as a 15-bit up-down counter with separate inputs for incementing and ementing the counter. An additional sign bit
indicates the polarity of the counter value thais aintained in twocomlement format. The current accumulator is
updated at a rate equivalent to one count per 05µVh, which is equivlent to one count per 61.03µAh when using a
50mΩ current sense resistor. It will roll over beyond (7FFF)h when ncremented and (0000)h when decremented, and
the value given by the counter will be aiguous in that case. Iis the responsibility of the host to read the counter
before rollover occurs.
The content of the charge current accumulator will be transferred into the DeltaCharge register when the UpdReq bit in
the FuelGauge register has been set. The update f the register has to be synchronized to the sample clock fVFC and
can take up to 1.5 clock cycles (max. 2.5µ. After the registers have been updated successfully, the UpdReq bit is
cleared automatically and the charge current ccumulator together with the sign bit will be reset.
Elapsed Time Counter
The sample clock fVFC of the fuel auge circuit is fed to a 14-bit clock count divider. Its output signal is used as a
clocking signal for the 16-bit elpsed time counter, resulting in an equivalent rate of 1.1379 counts per second
(4096.60 counts = 1 hour). The elpsed time counter will rollover beyond (FFFF)h, and the value given by the counter
will be ambiguous in that ase. t is the responsibility of the host to read the counter before rollover occurs.
The content of theaped time counter will be transferred into the ElapsedTime register when the UpdReq bit in the
FuelGauge register as been set. The update of the register has to be synchronized to the sample clock fVFC and can
take up to 1.5 clock cycles (max. 2.5µs). After the registers have been updated successfully, the UpdReq bit is cleared
automatically nd he elapsed time counter will be reset.
Ofset libration Mode
Althugh the VFC compensates for the offset of the integrator the fuel gauge features an additional offset calibration
mode to enhance the measurement accuracy even further. By setting the CalReq bit in the FuelGauge register the
integrator is reset and the offset calibration mode is activated. The charge count dividers are bypassed during offset
calibration to allow a faster calibration procedure with adequate resolution. The offset is accumulated during 16 clocks
of the elapsed time counter, the resulting offset calibration value FGOffCal has a resolution of 3.05µV and is
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transferred to the DeltaCharge register. The CalReq bit is cleared automatically after the calibration has completed
successfully and FGOffCal has been written to the register.
Please note that offset calibration is not possible while the charger is active. If the CalReq bit is set while the charger is
active the calibration will start automatically after the charger has been disabled by clearing the ChEn bit or if the
external charge adapter has been removed. If during an offset calibration procedure the charger is enabled the offset
calibration mode is terminated, the CalReq bit is cleared, the current value of the elapsed time counter is transferred to
the ElapsedTime register and the DeltaCharge register is loaded with (FFFF)h.
Calculation of Battery Status
The host system can calculate all the parameters necessary for estimating the remaining battery capacity by
evaluating ElapsedTime, DeltaCharge and FGOffCal.
Calculating Elapsed Time
The host system can evaluate the change in time Δt by setting the UpdReq bit in the FuelGauge register and reding
ElapsedTime after UpdReq has been automatically cleared. The change in time in seconds is given by:
Δt = ElapsedTime x 3600 / 4096.60 [s]
(EQ 1)
Note that the absolute accuracy of Δt is directly related to the absolue accuracy of the internrefeence oscillator. To
cancel the error associated with the accuracy of the oscillator, a orretin factor CV can be intrduced. CV can be
evaluated by comparing the change in time calculated by (1) with some eference value tRF obtained from a RTC or
measured during system calibration. CV is given by:
CV = ΔtREF Δt
(EQ 2)
By multiplying Δt and CV the correct value for the change in time can be calclated:
ΔtCRR = CV x Δt [s
(EQ 3)
Calculating Average Current
The host system can calculate the avege current during the ast time period by setting the UpdReq bit in the
FuelGauge register and reading Deltaarge and Elapseme fter UpdReq has been automatically cleared.
Together with FGOffCal determined during offset calibraode the average current is given by:
I
AVG = DeltaCharge / (Δt x AVFC Rsse) – FGOffCal x 3.05µV / Rsense [A]
(EQ 4)
Δt is the change in time in seconds calculateby (1), AVFC is the gain of the VFC in Hz/V, Rsense is the value of the
sense resistor in Ω and FGOffCal is the ofset clibration value. As DeltaCharge and Δt both are proportional to the
oscillator frequency, no correction factor ns to be introduced in the formula.
Calculating Accumulated Current
Accumulated current is used to alculate the absolute remaining capacity of the battery. It is given by:
IACC = IAVG x ΔtCORR [A]
(EQ 5)
Calculating the Rainig Capacity
Remaining capacity ithe entire goal of fuel gauging. It is given by:
RC = RC + IACC [As]
(EQ 6)
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Calculating the Time to Empty
The time to empty is calculated from the average current IAVG given by (4). The longer the time period for which IAVG is
calculated, the more accurate the value for IAVG and therefore the estimated time to empty will be. It is given by:
TTE = RC / IAVG [s]
(EQ 7)
Table 51. Fuel Gauge Bit definitions
Fuel Gauge
Addr:15
These bits configures the fuel gauge
Default Access Description
Bit
Bit Name
0
1
Disable Fuel Gauge
Enable Fuel Gauge
0
FGEn
ROM
R/W
This bit controls the update of the DeltaCharge and
ElapsedTime registers. When set, the bis cleared
automatically after the registers have een updated
successfully. Bit should not be set to “0by the host
1
2
UpdReq
CalReq
ROM
R/W
0
Update of regisrs complete
Request update of registers
1
his bit controls the offset calibration. When set, the bit is
d automatically fer the calibration has completed
scessfully.
ROM
OM
R/W
R/W
Calibatiocomplete OR terminate offset
0
calibration
1
Request offset calibration
Sets the mode for offset calibration
Connect inputs to ground internally
Use ISENSP and ISENSN (do not use)
do not use
00
01
11
4:3
CalMod
do not use
Table 52. Delta Charger MSB bit definition
DeltaChargeMSB
Addr:101
hese bits represent the MSB value of the fuel gauge Delta charge
register
Bit
6:0
7
Bit Name
DeltaChrgeMSB
sign
Default Access
Description
The register is maintained in two’s complement format
with a resolution of 3.05µVh and a full-scale value of
±99.98mVh. When using a 50mΩ current sense resistor
this is equivalent to a resolution of 61.03µAh and a full-
scale value of 1.999Ah. Sign is set for negative values.
Register will be updated after setting bit UpdReq to “1”.
(00)h
0
R
R
Sign bit of the delta charge register
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Table 53. DeltaChargerLSB bit definitions
DeltaChargeLSB
Addr:102
These bits represent the LSB value of the fuel gauge Delta charge
register
Bit
Bit Name
Default Access
Description
The register is maintained in two’s complement format
with a resolution of 3.05µVh and a full-scale value of
±99.98mVh. When using a 50mΩ current sense resistor
this is equivalent to a resolution of 61.03µAh and a full-
scale value of 1.999Ah. Sign is set for negative values.
Register will be updated after setting bit UpdReq to “1”.
7:0
DeltaChargeLSB
(00)h
R
Table 54. ElapsedTimeMSB bit definitions
ElapsedTimeMSB
Addr:103
These bits represent the MSB value of the fuel gauge Epsed Time
register
Bit
6:0
7
Bit Name
ElapsedTimeMSB
sign
Default Access
Description
The elapsd time count is stored the register with a
resoluon of 0788s and a full-scale value of 15.997 hours.
Regier wibe updated aftr setng bit UpdReq to “1”.
(00)h
0
R
R
Sign bit of he elapsed time register
Table 55. ElapsedTimeLSB bit definitions
ElapsedmeLSB
Addr:104
Thesbits represent the Lvaue of the fuel gauge Elapsed Time
register
Bit
Bit Name
Deault Access
Description
Thelapsed time count is stored in the register with a
lution of 0.8788s and a full-scale value of 15.997 hours.
egister will be updated after setting bit UpdReq to “1”.
7:0
ElapsedTimeLSB
00)h
R
8.9.3 Charger Operation
The charger controls the battery current thrugh the internal transistor between VSUP_SW1,2 and VBAT_SW1,2, the
step down charger and the battery switch betwen VSUPPLY and VBAT.
Charge Current Regulator
The regulator is programmed by stting TrickleCurrent and ConstantCurrent in the ChargerCurrent register and yields
a resolution of 0.625mV or 12.mA when using a sense resistor of 50mΩ.
Table 56. Charge CurrenReulator parameters
Symbol
tMEAS
Prameter
Min
Typ
Max
Unit
ms
Note
Measurement period
68.65
0.625
fclk_int = 2.2MHz
IMEAS,LS
mV
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Table 57. Charger Current Bit definitions
Charger current
These bits define the battery charging current and voltage
Addr:16
Bit Name
Bit
Default Access
Description
-1
Sets the trickle current. Default is (01)b = 2.5mV x Rsense
.
-1
00b
01b
10b
11b
1.25mV x Rsense
2.50mV x Rsense
5.00mV x Rsense
10.0mV x Rsense
-1
-1
-1
TrickleCurrent
ROM
R/W
1:0
Sets the charging current in constat current mode
from (0mV…35mV) x Rsene-1 istes of 5mV x
-1
Rsene
.
-1
-1
000
0mV x Rsens
5mV x Rsense
ConstantCurrent
ROM
R/W
4:2
001
.
-1
111
35mV x Rsense
Charger age after EOC and isolate_battery=1
000b
4.3V
4.4V
4.5V
4.6V
4.7V
4.8V
4.9V
5.0V
001b
010
b
100b
101b
110b
111b
ch_voltage
ROM
R/W
7:5
8.10 Charger supervison unctions
The charger supervision functios allow charging without processor control by continuously checking the NTC
temperature resistor withithbattery pack using ADC_IN1 pin. The charging cycle is automatically paused, if the
NTC indicates a temperatre range out of 0º to 45º (or 0º to 50º). If the temperature gets into this range again the
charging cycle is eumd.
In addition there is a charge timer that stops charging after a defined time, as additional security feature.
The timer will be reet at charger insertion (charger detect) or at EOC state. The timer is counting during active
charging ly (Trickle charging, Constant current charging, Constant voltage charging).
In case tbttery voltage does not reach EOC voltage within tCHARGINGMAX after charging has been started,
chaging_tmax interrupt will be generated and charging will be stopped. Charging can be started again by writing
charging_tmax=0 in the charger_control1 register.
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Figure 21. Charger Supervision functions – internal circuit
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Table 58. NTC Chargersupervision Chracteristics, VVBAT=0…5.5V; Tamb=–20…+85°C; unless otherwise
specified.
Symbol
Parameter
Min
Max
Unit
Note
Alternating measurement of the NTC
sensor for high temperature and low
temperature with two different
currents
Sample time for NTC
measurement high o
low temperature
tsample
33
ms
Comparator thresol
for high and low
temperaure
Vcomp
1.8
V
On pin ADC_IN1, if ntc_on<1:0>=1
measureent
High temprature
curret fo45 deg limit,
10k NTC
-7%
-7%
388
4.64
457
+7%
+7%
µA
kΩ
µA
kΩ
µA
kΩ
µA
kΩ
µA
kΩ
ntc_type=0, ntc_high_temp=0,
@ 1.8V threshold
IHightemp45deg_1
0k
Hgh temperature
urrent for 50 deg limit,
10k NTC
ntc_type=0, ntc_high_temp=1,
@ 1.8V threshold
IHightemp50deg_1
0k
3.94
60.5
29.7
39.2
4.59
46.8
38.5
High temperature
IHighteeg_10k current for 0 deg limit,
10k NTC
ntc_type=0
@ 1.8V threshold
High temperature
ntc_type=1, ntc_high_temp=0,
@ 1.8V threshold
IHighemp45deg_1
current for 45 deg limit,
00k
100k NTC
Low temperature
ntc_type=1, ntc_high_temp=1,
@ 1.8V threshold
ILowtemp50deg_10
current for 50 deg limit,
0k
100k NTC
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Table 58. NTC Chargersupervision Characteristics, VVBAT=3.0…5.5V; Tamb=–20…+85°C; unless otherwise
specified.
Symbol
Parameter
Min
Typ
6.32
284
Max
Unit
µA
Note
Low temperature
current for 0 deg limit,
100k NTC
ntc_type=1
@ 1.8V threshold
ILowtemp0deg_100
k
kΩ
±4%
±8%
(approx. 1º .), ntc_hyst=0
(approx. 2º.), ntc_hyst=1
NTC Current
hystereses
Hystereses
Current for ADC
measurement High
temp range, 10k NTC
ntc_on<1:0>=2, ntc_type=0,
ntc_high_temp=0
IHightempADC_10k
-7%
234
23.6
36
+7%
µA
µA
µA
µA
Current for ADC
measurement High
temp range, 100k NTC
ntc_on<1:0>=2, ntc_type1,
ntc_high_temp=0
IHightempADC_100
k
Current for ADC
measurement Low
temp range, 10k NTC
ntc_on<1:0>3, n_type=0,
ntc_high_emp=0
ILowtempADC_10k
Current for ADC
measurement Low
temp range, 100k NTC
ntc_on<10>=3, ntc_type=1,
ntc_high_temp=0
ILowtempADC_100
k
3.7
Table 59. Charger supervision bit definitions
Charger suervison
These bits define charging timer anbattery temp. supervision settings
Addr:14
Bit
3:0
4
Bit Name
Default Access
Description
Charging timeout timer
0000b
0001
0b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
1010b
1011b
1100b
1101b
1110b
1111b
Charging timeout disabled
1 hour
1.5 hour
2 hour
2.5 hour
3 hour
3.5 hour
ch_timeout
ROM
R/W
4 hour
4.5 hour
5 hour
5.5 hour
6 hour
6.5 hour
7 hour
7.5 hour
8 hour
auto_shutdown
ROM
0
(see Reset generator and XON-Key on page 118)
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Table 59. Charger supervision bit definitions
Charger supervision
These bits define charging timer and battery temp. supervision settings
Addr:14
Bit Name
Bit
Default Access
Description
Selects the high temp level:
45 º maximum temp
0
1
5
ntc_high_temp
ROM
R/W
50º maximum temp
Low temp is always 0º
Selects the NTC temperature hysteresis
2º hysteresis
6
7
ntc_hyst
ntc_type
ROM
ROM
R/W
R/W
0
1
1º hysteresis
Select the NTC resistor type
10kΩ NTC resisto
0
1
100kΩ NTesisor
Table 60. FuelGauge
FuelGauge
Addr:15
This bit ntrols first startup ot of power on reset
Bit
Bit Name
Default Access
Description
00
01
10
11
Disable NTC supervision
Enable NTC supervision
7:6
ntc_on
ROM
R/W
Enable NTC for ADC measurement high temp
Enable NTC for ADC measurement low temp
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8.11 Step Down DC/DC Converters
8.11.1 Step Down DC/DC Converters Operating Modes
The step down dcdc converters have four operating modes to deliver different output currents for the applications. The
operating mode is selected by setting the register sdx_1A_mode (the default is set by the Boot ROM).
Figure 22. DC/DC step-down SD1, SD2, SD3 Normal Operating Mode; sdx_1A_mode = 0000b
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Figure 23. DC/DC step-down SD1, SD2, SD3 1A Operode; sdx_1A_mode = 1010b
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If one of the DCDC step down converters is not used for an application, connect it as follows:
Figure 24. DC/DC step-down SD3 (as example) not used
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Figure 25. DC/DC step-down SD1, SD2, SD3 External Controller Operating Mode; sdx_1A_mode = 100b
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Note: URR_GPIO has to be connected to VSUPPLY if the external controler mode is used.
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Figure 26. DC/DC step-down SD1, SD2, SD3 External Controller Operating Mode and SD2 in 1A mode;
sd1_1A_mode = 1101b
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Note: The LDO VDIG2 and the Low voltage currnt surce / GPIO pin CURR1_GPIO1 cannot be used in the
‘External Controller’ operating mode configuration.
VCURR_GPIO has to be connected tVSUPPLY if the external controler mode is used.
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8.11.2 Step Down DC/DC Converter Characteristics
Figure 27. Step Down DC/DC Converter Block diagram
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Functional Description
The step-down converter is a high efficieny fixd frequency current mode regulator. By using low resistance internal
PMOS and NMOS switches efficiency up 5% can be achieved. The fast switching frequency allows using small
inductors, without increasing the current ripple. The unique feedback and regulation circuit guarantees optimum load
and line regulation over the whole utpt voltage range, up to an output current of 500mA, with an output capacitor of
only 10µF. The implemented curent limitation protects the DCDC and the coil during overload condition.
To allow optimized perfoancin different applications, there are bit settings possible, to get the best compromise
between high efficiencand low input, output ripple:
Low ripple, low nise operation:
Bit settings:
sdX_dis_min=1
Ihis me here is no minimum coil current necessary before switching off the PMOS. As result, the ON time of the
PMS will be reduced down to tmin_on at no or light load conditions, even if the coil current is very small or the coil
current is inverted. This results in a very low ripple and noise, but decreased efficiency, at light loads, especially at low
input to output voltage differences. Because of the inverted coil current in that case the regulator will not operate in
pulse skip mode.
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Figure 28. sdX_dis_curmin=1 operation
1: LX voltage, 2:coil current (1mV=1mA) 3: Vout
High efficiency operation (default setting):
Bit settings:
sdX_dis_curmin=0
In this mode there is a minimum coil current necessary before switching off te PMOS. As result there are less pulses
at low output load necessary, and therefore the effcieny at low output is icreased. This results in higher ripple,
and noisy pulse skip operation up to a higher ouput current.
Figure 29. sdX_dis_curmin=0 operation
1: LX voltage, 2:coil current (1mV=1m: Vout
Italso pssble to switch between these two modes during operation:
For Example:
sdX_dis_curmin=0: System is in idle state. No audio, RF signal. Decreased supply current preferred. Increased ripple
doesn’t affect system performance.
sdX_dis_curmin=1: System is operating. Audio signal on and/or RF signal used. Decreased ripple and noise preferred.
Increased power supply current can be tolerated.
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100% PMOS ON mode for low dropout regulation: For low input to output voltage difference the sdX_dis_pon bit
can be set, to allow 100% duty cycle of the PMOS transistor.
Low power mode: The sdX_lpo mode bit can be set all the time. This mode allows internal power down, of not used
blocks during pulseskip mode, which results in a better efficiency at light output loads.
Inductor setting: The step down regulator is optimized for 2.2µH at 2.2MHz and 4.7µH at 1.1MHz
Table 61. Step Down DC/DC Converter parameters
Symbol
Parameter
Min
Typ
Max
Unit
Note
PIN VSUPPLY_1,VSUPPLY_2,
VSUPPLY_3
V
Input voltage
3.0
5.5
V
IN
Regulated output
voltage
V
0.6
3.3
V
OUT
-50
+50
mV
mV
mA
output voltae <2.0V
output volge 2.0V
Output voltage
tolerance
VOUT_tol
-100
+100
ILIMIT
RPSW
RNSW
Iload
Current limit
800
P-Switch ON
resistance
0.5
Ω
Ω
V_SUPLYx=3.0V
V_SUPPLYx=3.0V
N-Switch ON
resistance
0.5
Load current
Switching frequency
Efficiency
0
500
mA
MH
MHz
%
sdX_frequ=0, fclk_int =2.2MHz
sdX_frequ=1, fclk_int =2.2MHz
Iout=100mA, Vout=2.3V, Vsup.=3V
2.2
1.1
90
fSW
ηeff
250
Operating current without load
IVDD
Current consumn
µA
0.1
80
Low power mode current
Shutdown current
tMIN_ON
Minimum on time
Minimum off time
ns
ns
tMIN_OFF
40
External Components
CVSD1-3, CVSD1A
Output caacito
Iput apacitor
8.0
10
µF
µF
Ceramic X5R or X7R
Ceramic X5R or X7R
2.2
Ceramic X5R or X7R; CVSUPPLY1
in external controller mode or 1A
operating mode
CVSUPPLY1-3
LSD1-SD
4.7
µF
2.2
4.7
sdX_frequ=0, ± 10% tolerance
sdX_frequ=1, ± 10% tolerance
Inductor
µH
SD1 external controller mode; use
sd1_freq=1 (1.1Mhz)
2.2
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Table 62. Step Down DC/DC Bit definitions
Step Down Control1
These bits configures the step down converters
Addr:35
Bit Name
Bit
0
Default Access
Description
sd1_psw_on
0
0
0
0
0
0
0
0
R/W
n/a
Only if sd1_on = 0, switch on PSW (0.5Ω PMOS)
1
-
2
-
n/a
3
sd1_nsw_on
R/W
R/W
n/a
Only if sd1_on = 0, switch on NSW (0.5Ω NMOS)
Only if sd2_on = 0, switch on PSW (0.5Ω PMOS)
4
sd2_psw_on
5
-
6
-
n/a
7
sd2_nsw_on
R/W
Only if sd2_on = 0, switch on NSW (0.5Ω NMOS)
Table 63. Step Down DC/DC Bit definitions
SteDown Control2
Addr:36
These bits cnfigures the step down cnverters
Bit
0
Bit Name
Default Access
Description
sd3_psw_on
0
0
0
0
R/W
n/a
Only if sd3_on = 0, sitch on PSW (0.5Ω PMOS)
1
-
2
-
n/a
3
sd3_nsw_on
R/W
Onf sd_on = 0, switch on NSW (0.5Ω NMOS)
Step down low power mode:
0
Increased current consumption in pulseskip mode
4
5
sdX_lpo
0
R/W
R/W
Decreased current consumption in pulseskip
mode
Step down pon feature control
PON feature enabled: 100% duty cycle (pmos
always on) if output voltage drops more than 4%.
Increased output ripple in that operation.
0
1
sd1_dis_pon
0
PON feature disabled: Maximum dutycycle=1-
(tmin_off*fsw)
Step down pon feature control
PON feature enabled: 100% duty cycle (pmos
always on) if output voltage drops more than 4%.
Increased output ripple in that operation.
0
1
6
7
sd2_dispon
sd3_dis_pon
0
0
R/W
R/W
PON feature disabled: Maximum dutycycle=1-
(tmin_off*fsw)
Step down pon feature control
PON feature enabled: 100% duty cycle (pmos
always on) if output voltage drops more than 4%.
Increased output ripple in that operation.
0
1
PON feature disabled: Maximum dutycycle=1-
(tmin_off*fsw)
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Table 64. Step Down DC/DC Bit definitions
Step Down charger control
These bits configures the step down converters
Addr:37
Bit Name
Bit
Default Access
Description
3
-
0
n/a
Step down curmin feature control
curmin feature enabled: Inductor current regulated
to min 170mA. Higher efficiency in low dropout
and low output current operation. Higher output
ripple and noise.
0
1
4
5
6
sd1_dis_curmin
0
R/W
curmin feature disabled: Decreased efficiency i
low dropout mode and at low output current. mall
output ripple and noise.
Step down curmin feature contol
curmin feature enabled: Inductor urret regulated
to min 170mA. Higher efficiecy ilow dropout
and low output current oratio. Higher output
ripple and nise.
0
1
sd2_dis_curmin
0
R/W
curin feature disabed: ecreased efficiency in
low dropout mode and at low output current. Small
uput ripple and noise.
Step down cumin feature control
curmin feure enabled: Inductor current regulated
to min 170mA. Higher efficiency in low dropout
anw output current operation. Higher output
ripple and noise.
0
1
sd3_dis_curmin
0
R/W
cumin feature disabled: Decreased efficiency in
ow dropout mode and at low output current. Small
output ripple and noise.
Table 65. Step Down DC/DC Reg Power1 ctrl Bit defini
Reg Power1 Ctrl
Addr:23
These bits control the on/off function of the step down regulator
Bit
Bit Name
Default Access
Description
Switch on/off the step down1 dc/dc converter; it is possible
to on/off control DCDC SD1 by CURR3_GPIO3 or
CURR4_GPIO4 (see General Purpose Input / Output
(CURR1_GPIO1 … CURR4_GPIO4) on page 30)
4
sd1_on
ROM
ROM
R/W
R/W
0
1
Step Down DC/DC 1 off
Step Down DC/DC 1 on
Switch on/off the step down2 dc/dc converter; it is possible
to on/off control DCDC SD2 by CURR3_GPIO3 or
CURR4_GPIO4 (see General Purpose Input / Output
(CURR1_GPIO1 … CURR4_GPIO4) on page 30)
5
sd2_on
0
1
Step Down DC/DC 2 off
Step Down DC/DC 2 on
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Table 65. Step Down DC/DC Reg Power1 ctrl Bit definitions
Reg Power1 Ctrl
These bits control the on/off function of the step down regulator
Addr:23
Bit Name
Bit
Default Access
Description
Switch on/off the step down3 dc/dc converter; it is possible
to on/off control DCDC SD3 by CURR3_GPIO3 or
CURR4_GPIO4 (see General Purpose Input / Output
(CURR1_GPIO1 … CURR4_GPIO4) on page 30)
6
sd3_on
ROM
R/W
0
1
Step Down DC/DC 3 off
Step Down DC/DC 3 on
Table 66. Step Down Voltage1 Bit definitions
Step Down Voltage1
These bits control the step down regulator voltage, freueny, clk phase
Addr:00
Bit
Bit Name
Default Access
Description
Contrl the voltage selection for tstep down1 DC/DC
converter
000000 0.6 V
5:0
step_down1_v
ROM
R/W
…
(LSB=50mV)
111111 3.4 V
Select tstedown1 frequency
lk_int (1.6MHz to 2.3 MHz)
fclk_int/2 (0.8MHz to 1.15 MHz)
0
1
6
7
sd1_frequ
ROM
ROM
R/W
R/W
sd1_clkinvert
Invertthe input clock of the step down1 converter
Table 67. Step Down Voltage2 Bit defitions
Step Down Voltage2
Addr:01
These bits control the step down regulator voltage, frequency, clk phase
Bit
Bit Name
Default Aces
Description
Control the voltage selection for the step down2 DC/DC
converter
000000 0.6 V
5:0
step_down2_v
R
R/W
…
(LSB=50mV)
111000 – 11111 3.4 V
Select the step down2 frequency
fclk_int (1.6MHz to 2.3 MHz)
fclk_int/2 (0.8MHz to 1.15 MHz)
0
1
6
7
sd2_frequ
ROM
ROM
R/W
R/W
sd_clkinvert
Inverts the input clock of the step down1 converter
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Table 68. Step Down Voltage3 Bit definitions
Step Down Voltage3
These bits control the step down regulator voltage, frequency, clk phase
Addr:02
Bit Name
Bit
Default Access
Description
Control the voltage selection for the step down3 DC/DC
converter
000000 0.6 V
5:0
step_down3_v
ROM
R/W
…
(LSB=50mV)
111000 – 11111 3.4 V
Select the step down3 frequency
fclk_int (1.6MHz to 2.3 MHz)
fclk_int/2 (0.8MHz to 1.15 MHz)
0
1
6
7
sd3_frequ
ROM
ROM
R/W
R/W
sd3_clkinvert
Inverts the input clock of the step dow1 converter
Table 69. Step down1 high current and DVM definitions
Charge Pump Control
Addr:17
These bits control the tep don high currenmode and DVM step size
Bit
Bit Name
Default Access
Description
Time step of DVM vltage change of step down1
If vltage of step dow1 (st_down1_v) is changed during
operation, voltagis dcreased or increased by 25 mV
steps with the follwing time separation between steps:
00
01
10
11
0 µsec, immediate change (no DVM)
3:2
sd1_dvm_time
ROM
R/W
4 µsec
8 µsec
16 µsec
ct 1A mode of step down2 (combined operation of SD2
and SD3 with a single coil and up to 1A output current) and/
or controller mode of SD1
1A mode selected Controlled by SD2 The
following pins have to be connected:
1010 VSUPPLY2<->VSUPPLY3, LX2<->LX3, PGND2<-
>PGND3
Stepdown3 is not usable in that mode
External controller mode. LDO DIG1 and current
sink / GPIO CURR1_GPIO1 cannot be used. Set
7:4
sdx_1A_mode
ROM
R/W
1100
ldo_dig1_on=0, GPIO1Mode=111b (tristate),
GPIO1Pulls=00b (no pull-up or pull-down)
External controller mode SD1, and 1A mode
controlled by SD2
The following pins have to be connected:
1101
VSUPPLY2<->VSUPPLY3, LX2<->LX3, PGND2<-
>PGND3
Stepdown3 is not usable in that mode
all other codes (0000...1001,1011,1110...1111) normal
mode
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Table 70. Step Down DC/DC Bit definitions
Step Down Control3
Addr:133
Configurate the SD converters to reduce voltage drops on fast transient
high current load steps. Double the output capacitor size has to be used!
Bit
Bit Name
Default Access
Description
0
1
0
1
0
1
Normal operation
0
sd1_uvlimit
sd2_uvlimit
sd3_uvlimit
0
0
0
R/W
R/W
R/W
Enable SD1 undervoltage limit.
Normal operation
1
2
Enable SD3 undervoltage limit.
Normal operation
Enable SD3 undervoltage limit.
8.11.3 Typical Performance Characteristics
Figure 30. DC/DC step-down Efficiency (sdX_dis_curmin=0, sdX_lpo=0)
Figure 31. PCB Layout recommedation
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8.12 Low Dropout Regulators (LDO)
The low dropout regulators are linear high performance regulators with programmable output voltage.
They are controlled by the following registers:
Table 71. LDO_RF1 voltage bit definitions
LDO_RF1 voltage
Addr:03
These bits control the LDO_RF1 voltage and mode
Bit
Bit Name
Default Access
Description
Control the voltage selection for LDO VRF_1
00000 1.85V
… (LSB=50mV)
11111 3.40V
4:0
ldo_rf1_v
ROM
R/W
0
1
current limitation = Ilimit
5
6
rf1_lcurr_en
ROM
ROM
R/W
R/W
current limitation Ilimt=Iliit/2
If ‘1’ current limitation is enabled, if RF1-LDO is operating
as High side sitch
rf1_swprot_en
Table 72. LDO_RF2 voltage bit definitions
LDO_RF2 voltage
Addr:04
These bcontrol the LDO_R2 voltage and mode
Bit
Bit Name
Default Access
escription
Control the voage selection for LDO VRF_2
00000 1.85V
… (LS50m)
11111 3.40V
4:0
ldo_rf2_v
ROM
OM
R/W
R/W
current limitation = Ilimit
5
rf2_lcurr_en
current limitation Ilimit=Ilimit/2
Table 73. LDO_RF3 voltage bit definitions
LDO_RF3 voltage
These bits control the LDO_RF3voltage and mode
Addr:05
Bit
Bit Name
Delt Access
Description
Control the voltage selection for LDO VRF_3
00000 1.85V
… (LSB=50mV)
11111 3.40V
4:0
ldo_rf3_v
ROM
R/W
0
1
0
current limitation = Ilimit
current limitation Ilimit=Ilimit/2
normal mode
5
6
rf3_lurr_en
ROM
ROM
R/W
R/W
rf_hotplug_en
200mA current limited switch, if bit rf3_sw=1
(rf3_lcurr_en=0)
1
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Table 74. LDO_DIG1 voltage bit definitions
LDO_DIG1 voltage
Addr:06
Bit Name
ldo_dig1_v
These bits control the LDO_DIG1 voltage
Description
Bit
Default Access
ROM R/W
Control the voltage selection for LDO DIG_1
(see Table 82)
5:0
Table 75. LDO_DIG2 voltage bit definitions
LDO_DIG2 voltage
Addr:07
These bits control the LDO_DIG2 voltage
Description
Bit
Bit Name
Default Access
ROM R/W
5:0
ldo_dig2_v
Control the voltage selection for LDO DIG_2(see Tabl82)
Table 76. LDO_DIG3 voltage bit definitions
LDO_DIG3 voltage
Addr:08
These bts conol the LDO_DIG3 volage
Descriton
Bit
Bit Name
Default Access
ROM R/W
5:0
ldo_dig3_v
the voltage selction for LDO DIG_3(see Table 82)
Table 77. LDO_DIG4 voltage bit definitions
LDO_DIGvoltage
Addr:09
These bits cool he LDO_DIG4 voltage
Description
Bit
Bit Name
DeaulAccess
ROR/W
5:0
ldo_dig4_v
Corol thvoltage selection for LDO DIG_4(see Table 82)
Table 78. LDOs Reg Power1 ctrl Bit definitions
Reg Power1 Ctrl
Addr:23
These bits control the on/off function of the ldo regulator
Bit
Bit Name
DefauAccess
Description
Switch on control of RF1 LDO; Important: Set rf1_sw=0
before setting ldo_rf1_on=1; it is possible to on/off control
LDO RF_1 by CURR3_GPIO3 or CURR4_GPIO4 (see
General Purpose Input / Output (CURR1_GPIO1 …
CURR4_GPIO4) on page 30)
0
ldo_rf1_on
ROM
ROM
ROM
R/W
R/W
R/W
Switch on control of RF2 LDO; Important: Set rf2_sw=0
before setting ldo_rf2_on=1; it is possible to on/off control
LDO RF_2 by CURR3_GPIO3 or CURR4_GPIO4 (see
General Purpose Input / Output (CURR1_GPIO1 …
CURR4_GPIO4) on page 30)
1
2
ldorf2_n
Switch on control of DIG1 LDO;
it is possible to on/off control LDO DIG_1 by
CURR3_GPIO3 or CURR4_GPIO4 (see General Purpose
Input / Output (CURR1_GPIO1 … CURR4_GPIO4) on
page 30)
ldo_dig1_on
Switch on control of DIG2 LDO. do not set if DCDC SD1 is
in external controller mode (if sd1_1A_mode = 1100b).
it is possible to on/off control LDO DIG_2 by
CURR3_GPIO3 or CURR4_GPIO4(see General Purpose
Input / Output (CURR1_GPIO1 … CURR4_GPIO4) on
page 30)
3
ldo_dig2_on
ROM
R/W
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Table 79. LDOs Reg Power2ctrl Bit definitions
Reg Power2 Ctrl
These bits control the on/off function of the ldo regulator
Addr:30
Bit Name
Bit
Default Access
Description
Switch on control of RF3 LDO; Important: Set rf3_sw=0
before setting ldo_rf3_on=1
0
ldo_rf3_on
ROM
R/W
Switch on control of DIG3 LDO; it is possible to on/off
control LDO DIG_3 by CURR3_GPIO3 or CURR4_GPIO4
(see General Purpose Input / Output (CURR1_GPIO1 …
CURR4_GPIO4) on page 30)’
1
ldo_dig3_on
ROM
R/W
2
3
ldo_dig4_on
rf1_sw
ROM
ROM
R/W
R/W
Switch on control of DIG4 LDO
If ‘1’ RF1-LDO is operating as High side switch (Ron1Ω),
valid if ldo_rf1_on=0
If ‘1’ RF2-LDO is operating as High side swtch (Ron=1Ω),
4
7
rf2_sw
rf3_sw
ROM
ROM
R/W
R/W
valid if ldo_rf2_on=0
If ‘1’ RF3-LDO is operating as High sidswich (Ron=1Ω),
valid if ldo_rf3_=0
8.12.1 RF LDO’s (VRF_1, VRF_2, VRF_3)
These LDO’s are designed to supply sensitive analogue cts like LNA’s, Transceivers, VCO’s and other critical RF
components of cellular radios. Another application is the suy of audio devices oas a reference for AD and DA
converters. The design is optimized to deliver the best compomise between quscent current and regulator
performance for battery powered devices.
Stability is guaranteed with ceramic output capacitors of 1µF ±20% (X52.2µF +100/-50% (Z5U) for RF2, RF3 and
2.2µF ±20% (X5R) or 4.7µF +100/-50% (Z5U) foRF1. The low ER of ese caps ensures low output impedance at
high frequencies. Regulation performance is ecellent even under lodropout conditions, when the power transistor
has to operate in linear mode. Power supplrejection is high enouh to suppress the PA-ripple on the battery in TDMA
systems at the output. The low noisprmance allows direct onnection of noise sensitive circuits without additional
filtering networks. The low impedance the power deviables the device to deliver up to IOUT current even at
nearly discharged batteries without any decrease of perfnce.
With vrf2_lcurr_en=0 and vrf3_lcurr_en=0 the regator VRF_2, VRF_3 can deliver up to 250mA
With vrf1_lcurr_en=0 the regulator VRF_1 can deliver up to 400mA
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Figure 32. Analog LDO Block diagram
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Table 80. Analog LDO (VRF_1, VRF_2, VRF_3) CharacteristicsVx_IN=4V; ILOAD=150mA; amb=25ºC;
CLOAD =2.2µF (Ceramic); unless otherwise specified
Symbol
Parameter
Min
T
Max
Unit
Note
Vx_IN
Supply voltage rage
3
5.5
V
VRF_2, rf2_lcurr_en=1
VRF_3, rf3_lcurr_en=1
0
0
0
0
150
200
250
VRF_1, rf1_lcurr_en=1
Output current1
IOUT
m
VRF_2, rf2_lcurr_en=0
VRF_3, rf3_lcurr_en=0
40
0.5
1
VRF_1, rf1_lcurr_en=0
VRF_1
Ω
Ω
RON
On resistance
VRF_2, VRF_3
f=1kHz
70
40
Power supply rejection
ratio
PSRR
dB
f=100kHz
IOFF
IVDD
Shut down current
Supply current
Output nise
100
50
nA
µA
without load
µVrms
Noise
50
10Hz < f < 100kHz
VRF_1,2,3 are set to low current
during startup time
tstart
Statup tme
200
µs
V
VRFX_IN>3.0V, VRF_1 @
Iout=300mA, VRF_2 and VRF_3 @
Iout=150mA (X=1,2)
1.85
2.85
Vout
Output voltage
VRFX_IN>3.55V, VRF_1 @
Iout=300mA, VRF_2 and VRF_3@
Iout=150mA (X=1,2)
1.85
-50
3.4
50
V
Output voltage
tolerance
Vout_tol
mV
mV
-1
1
Static
VLineReg
Line regulation
Transient; Slope: tr=10µs
-10
10
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Table 80. Analog LDO (VRF_1, VRF_2, VRF_3) Characteristics, Vx_IN=4V; ILOAD=150mA; Tamb=25ºC;
CLOAD =2.2µF (Ceramic); unless otherwise specified
Symbol
Parameter
Min
-1
Typ
Max
1
Unit
Note
Static
VLoadReg
Load regulation
mV
Transient; Slope: tr=10µs
-10
10
ILIMIT_VRF1_HCUR
Current limitation
Current limitation
800
400
mA
mA
VRF_1, rf1_lcurr_en=0
R
VRF_1, rf1_lcurr_en=1 and during
startup
ILIMIT_VRF1_LCURR
Current limitation
VRF_2,3 low current
limit
ILIMIT_VRF2,3_L
300
500
mA
mA
rf2_lcurr_en=1, rf3_lcurr_en=1
Current limitation
VRF_2,3 high current
limit
ILIMIT_VRF2,3_H
rf2_lcurr_en=0, f3_lcurr_en=0
ceramic only (VRF_1)
CLOAD_RF1
Load capacitor
Load capacitor
2
1
5
5
µF
µF
ceramonly VRF_2,3) for
rf1_lcurr_en=and rf2_lcurr_en=1
CLOAD_RF2,3_L
ceamic only (VRF_2,3) for
rf1_lcurr_en=0 and rf2_lcurr_en=0
CLOAD_RF2,3_H
Load capacitor
2
5
µF
1. Guaranteed by design and verified by laboratory evaluatiand characterization; ot production tested.
8.12.2 Digital LDO’s (VDIG_1, VDIG_2, VDG_3, VDIG_4)
The Digital LDO’s can be used in any medium power system or subsyswhere quiescent power consumption of the
regulator itself has to be minimized without scrificng its performae. For its stability a cheap 1µF ceramic capacitor
is required. The 5V charge pump will be witchd on automaticaly, if oe of the digital LDO’s are switched on.
Figure 33. Digital LDO Block diagram
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Table 81. Digital LDO (DIG1, VDIG2, VDIG3, VDIG4) Characteristics,VSUPPLY=4V; ILOAD=200mA; Tamb=25ºC;
CLOAD =1µF (Cermic); unless otherwise specified
Symbo
Parameter
Min
Typ
Max
Unit
Note
VDIIN
Supply voltage range
1
5.5
V
Vout<2.2V;
0
0
200
mA
VDIGX_IN>Vout+RON*IOUT
Output current1
On resistance
IOUT
RON
Vout<2.5V;
VDIGX_IN>Vout+RON*IOUT
100
4
mA
Ω
Vout<2.2V
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Table 81. Digital LDO (VDIG1, VDIG2, VDIG3, VDIG4) Characteristics,VSUPPLY=4V; ILOAD=200mA; Tamb=25ºC;
CLOAD =1µF (Ceramic); unless otherwise specified
Symbol
Parameter
Min
60
Typ
Max
Unit
Note
f=1kHz
Power supply rejection
ratio
PSRR
dB
30
f=100kHz
IOFF
IVDD
tstart
Shut down current
Supply current
Startup time
100
20
nA
µA
µs
without load
200
Vsupply>3.0V, VCP=5.2V,
Iout<200mA
2.20
2.5
50
V
V
Vout
Output voltage
0.75
Vsupply>3.0V, VCP=5.2
Iout<100mA
Output voltage
tolerance
Vout_tol_lv
Vout_tol_hv
-50
-60
mV
Vou1.8V
Vout1.85V
Output voltage
tolerance
60
mV
mV
-10
-50
-20
-50
10
50
20
50
Static
VLineReg
Line regulation
Transient; Slope: tr=10µs
Static
mV
VLoadReg
ILIMIT
Load regulation
Current limitation
Transient; Slope: tr=10µs
400
mA
1. Guaranteed by design and verified by labratoevaluation and haraterization; not production tested
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Table 82. Digital LDO (VDIG_1.4) Programming voltage table
Code (d)
Code (b)
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
VOUT(V)
0.75
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
1.0
155
1.60
1.65
1.70
1.75
1.8
Code (d)
22
Code (b)
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
VOUT(V)
0
1
1.80
23
1.80
2
24
1.80
3
25
1.80
4
26
1.80
5
27
1.80
6
28
1.80
7
29
1.80
8
30
1.80
9
31
1.80
.50 (do not use)
1.60 (do not use)
1.70 (do n0t use)
1.80 (do not use)
1.90
10
11
12
13
14
15
16
17
18
19
20
21
32
33
34
35
36
37
2.00
38
2.10
3
2.20
0
2.30
41
2.40
42
2.50
Note: Full performance for Vout ≤ 2.20V; ma. 100mA output current for Vout ≤ 2.50V; do not use values Vout>2.50V
8.12.3 Low power LDO (V2_5)
The Low power LDO V2_5 is neeed to supply the chip core (analog and digital) of the device. It is designed to get the
lowest possible power consumtionand still offering reasonable regulation characteristics. The regulator has three
supply inputs selecting autoaticlly the higher one. This gives the possibility to supply the chip core either with the
battery or with the chargdepnding on the conditions. Bulk switch comparators are used to avoid any parasitic
current flow. To ensurhigh PSRR and stability, a low-ESR ceramic capacitor of min. 1µF must be connected to the
output.
Table 83. Lopower LDO (V2_5) Characteristics,VBAT=4V; ILOAD_ext=0; Tamb=25ºC; CLOAD =2.2 µF (Ceramic);
unless otherwe secified
Sbo
VBAT
Parameter
Supply voltage rage
On resistance
Min
2.8
4
Typ
Max
5.5
15
Unit
V
Note
VCHARGER
RON
50
Ω
Guaranteed per design
f=1kHz
60
40
Power supply rejection
ratio
PSRR
dB
f=100kHz
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Table 83. Low power LDO (V2_5) Characteristics,VBAT=4V; ILOAD_ext=0; Tamb=25ºC; CLOAD =2.2 µF (Ceramic);
unless otherwise specified
Symbol
Parameter
Min
Typ
Max
Unit
Note
IOFF
Shut down current
100
nA
Guaranteed per design, consider
chip internal load for measurements.
IVDD
Supply current
3
µA
tstart
Vout
Startup time
200
2.6
µs
V
Output voltage
2.4
-50
2.5
Output voltage
tolerance
Vout_tol
50
mV
mV
-10
-50
-10
-50
10
50
10
50
Static
VLineReg
Line regulation
Load regulation
Transient; Slope: tr=10s
Static
VLoadReg
mV
Transient; Slpe: tr=10s
8.13 5V Charge Pump
Figure 34. 5V Charge Pump Block diagram
ꢑꢕꢗꢙꢗꢉꢑꢕꢁꢊꢚꢛ
ꢅꢌ5ꢃꢄꢅ
ꢅꢌ5ꢃ5
ꢜ
ꢃꢊ
ꢃꢄꢅꢆꢇꢈꢍ
ꢎꢏꢐꢑꢎꢏꢎꢑ
ꢓꢐꢌꢔ
ꢅꢌ5ꢃꢅ
ꢅꢌ5ꢃꢀꢁ
ꢎꢑ
ꢓꢐꢐꢌꢔ
ꢃꢕꢂꢀ#$
ꢘꢏꢘ%ꢜ
The charge pump uses the pad VCP_IN as inut, regulates and doubles its voltage with the help of the flying capacitor
between CAPP and CAPN to its output VC_OUT (the output is automatically limited not to exceed VCPOUT). If the bit
cp_pulseskip is set, the charge pump opes in pulse skip mode, and only starts cycles if its output voltage is below
this level. In this mode the supply urrent is reduced, but the output ripple is increased.
The charge pump requires the llowing external components:
Table 84. Charge Pump xteral Components
Symbol
Parameter
Min
Typ
Min
Unit
Note
External flying
capacitor
Ceramic X5R or X7R low-ESR
capacitor between CAPP and CAPN
CFLY
370
470
850
nF
Ceramic X5R or X7R low-ESR
capacitor between VCP_OUT and
VSS
External storage
capacitor
CRE
1.76
1
2.2
2.64
µF
A
Schottky Diode for
startup between
VCP_IN and
Dout
Peak current of schottky Diode
VCP_OUT
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Make the connections of the external capacitors as short as possible.
Table 85. Charge Pump Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
Note
Charge Pump input
voltage
VCPIN
3.0
5.5
V
cp_freq=0, fclk_int=2.2MHz
cp_freq=1, fclk_int=2.2MHz
1.1
MHz
MHz
fIN
Switching frequency
0.55
VCP_IN = 3.2V, Clock = fclk_int/2;
cp_pulseskip=0; fin=1.1MHz
ICPOUT
VCPOUT
VCPSKIP
Output Current
Output Voltage
0.0
4.9
100
5.6
mA
V
5.2
Output Voltage during
pulseskip
4.92
V
Use with cp_frequ=1 onl
Supply current without
load
ICP_noload
2
mA
µA
1.1MHz swithing requency
Charge pump supply
current without load in
pulseskip mode
ICP_pulseskip
20
cp_pulsep=1 nd cp_frequ=1
Table 86. CP Power1 ctrl Bit definitions
Reg Power1 Ctrl
These bits cntrol the on/offuction of the ldo regulator
Addr:23
Bit
Bit Name
Default Aces
Description
Swtch oof te charge pump block, charge pump is
automtically activated if any of the following blocks are
acve: VDIG_1, VDIG_2, VDIG_3, VDIG_4
7
cp_on
ROR/W
Table 87. Charge Pump Bit definitions
Charge Pump Control
These bits control the Charge Pump
Description
Addr:17
Bit
Bit Name
Deault Access
Switches on the pulseskip mode of the charge pump
0
1
Normal fixed frequency mode
0
cp_pulseskip
R
ROM
R/W
R/W
Pulse skip, low power mode (Set cp_frequ=1 in
this mode)
Defines the clock frequency of the step up dc/dc converter
f
clk_int/2 (0.8 to 1.15 MHz)
0
1
1
cp_fq
fclk_int/4 (0.4 to 0.575 MHz)
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Data Sheet Confidential - Detailed Description- Audio Functions
9 Detailed Description- Audio Functions
The audio functions consist of all the audio features of AS3658 as shown in the following block diagram:
Figure 35. AS3658 Audio Functions
9.1
Audio Paths
Following Audio paths are possible (only one configuration is possible at the amtime):
Figure 36. AS3658 I2S I/O 1 or I2S I/O2 Playback
Note: As the toucscreen interface is merged with I2S Output 3 and SPDIF Output 4 either the touch screen
interfae or I2Output 3 and SPDIF Output 4 can be used at the same time.
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Figure 37. AS3658 Line In Recording
Figure 38. AS3658 Microphone Recording
It is also possible to use the Audio ADC ahe Audio DAC at the same time. In this case, the sampling frequency of
the Audio DAC is either two or four times e sampling rate of the Audio ADC (ADC: max. 16ks / seconds). The
equalizer should not be used in ths cae:
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Figure 39. AS3658 Microphone Recording and I2S I/O Playback (either I2S 1 or I2S 2/PCM)
Figure 40. AS3658 Recording of the Mixed output signal and parallel playback (either I2S 1 I2S /PCM)
9.2
Common mode voltage generation of HP_CM, LINE_CM
The common mode voltage of the Headpe and Lineout is stored in the C_hpcm and C_linecm capacitor
(connected between HP_CM to VS and LINE_CM to VSS). These capacitor are also responsible for the popless
startup, PSRR of the amplifiers and sense path of the GND cancellation circuit.
Startup and PSRR is defined by the value of the external capacitors. The RC limits the maximum achievable PSRR:
R=6MΩ typ, C=0.1...1µF
Table 88. commn modvoltage, Audio start-up and PSRR
Maximum achievable PSRR
Capacitor value for C_hpcm and
Startup time (typ)
Clinecm
@ 1kHz (typ)
@ 100Hz (typ)
µF
0.1
1
msec
150
dB
76
90
dB
56
76
1500
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9.3
Audio Setup Registers
Audio LDO has to be switched on first (aud_ldo_on=1), and enables all other functions.
Table 89. AudioSet1 Register
Audio Set1
Addr:74
These bits control the Audio functions
Bit
Bit Name
Default Access
Description
Line input disabled
0
1
0
lin_on
0
R/W
Line input enabled
Switch on control of AUDIO DAC
DAC disabled
1
dac_on
0
R/W
0
1
0
1
0
1
DAC enabled (Switch on, if I2S signal valid only)
Mixer switched off
2
3
mix_on
0
0
R/W
R/W
Mixer switched on
GND switch off 0V t pin ND_SW
ND switch on Vsupply at pin GND_SW
Audio LDO ON control
gnd_sw_on
4
5
aud_ldo_on
mclk_invert
0
0
R/W
R/W
1
Audio LDO off
Audio LDO on
MLK invert selection
0
1
0
1
ane of LRCLK at falling edge of MCLK
Change of LRCLK at rising edge of MCLK
MCLK = LRCLK* 128
6
7
mclk256
equ_on
0
0
R/W
/W
MCLK = LRCLK* 256
Equalizer switched off (bypassed)
Equalizer switched on
Table 90. AudioSet2Register
Audio Set2
Addr:75
These bits control the Audio functions
Default Access Description
Bit
Bit Name
Bias current reduction settings for DAC:
00
01
10
11
1
default
Don't use
1,0
i_dac<1:0>
00b
R/W
Don't use
Don't use
add dither to the audio stream
no dither added
2
3
dith_on
0
0
R/W
R/W
0
0
Switch off I2S_3 output
Switch on I2S_3 output
I2S_3_on
1
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Table 90. AudioSet2Register
Audio Set2
Addr:75
These bits control the Audio functions
Default Access Description
Bit
Bit Name
Bias current reduction settings for headphone output
00
01
10
11
0
0%
5,4
ibr_hph<1:0>
0
R/W
17%
34%
50%
Select I2S_1 input
6
7
I2S_select
0
0
R/W
R/W
1
Select I2S_2 input
0
Generation of the master clock by te internal PLL
Use Pin MCLK_1, MCLK_2 as msterclock input
I2S_mclk_en
1
9.4
ADC, DAC and Digital Audio Input
9.4.1 General
Digital audio data can be fed into the AS3658 via the I2S ince This input datused by the 18-bit DAC to
generate the analog audio signal.
The stage is set to mute by default; If the DAC input is not enabled.
9.4.2 Signal Description
The digital audio interface uses the standrd S format:
ꢀ
ꢀ
ꢀ
Left justified
MSB first
One additional leading bit
MCLK has to have a fixed ratio of 128 or 256 to LRCLK. With a LRCLK equal to 16, 32, 44.1 or 48kHz, the MCLK can
be generated by the on-chip PLL (do not use the inrnal PLL if there is jitter on the LRCLK1 or 2). For lower sample
rates the bit pll_mode has to be set (for samle rates between 8kHz and 12kHz).
The high going edge of MCLK has to have iming separation from LRCLK edges. If the clock generation is so that
LRCLK edges are at the same time as Mhigh going edges, the MCLK can be inverted to guarantee a proper DAC
function.
This audio input interfaces usean I2S synchronizer to be able to handle audio sample length of 24bits or less.
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Figure 41. I2S Control Diagram
i2s_select
mclk_invert
i2s_mclk_en
0
1
i2s_master_on
i2s_lrck_sclk_out_en
i2s_select
SDI
18 Bit DAC
SDO1
SCLK
LRCLK
MCLK
0
1
sclk_invert
Audio left
mono to stereo
conversion for
pcm_mode=1
Equalizer
SDO
Audio right
SDI1
SCLK1
LRCLK1
MCLK1
SDI2
0
1
i2s_select
pll_mode
i2s_master_on
I2S_mclk_en
0
1
LRCLK_out
* 256
0
1
PLL
SDO
SCLK
LRCLK
MCLK
0
1
rising edge only
for PCM
Audio left
com patibility
* 64
14 Bit ADC
i2s_select
Audio right
mclk256
0
1
0
1
mclk_invert
*2
Fadc2 pcm_mode samlete
Sample rate
0
0
0
1
LRC2
RCL4
1
0
sclk_invert
i2s_master_on
SCLK2
LRCLK2
MCLK2
i2s_lrck_sclk_out_en
sdo3_select
i2s_master_on
MCLK divider
i2s_lrck_sclk_out_en
i2sn
0
1
mclk_out_en
sdo_on_mclk1_en
SDO3
mclk_vert
i2s_clk_divider<11:0>
0
1
SCLK3
i2s_3_on
LRCLK3
SPDIF
S
spdif_ctrl<1:0>
Figure 42. I2S Timing Diagram
64 cycles
64 cycles
MCLK
LRCK
Left Channel
Right Channel
SCLK
SDATA
16 bit
15
17
2
1
0
2
15
17
2
1
0
SDATA
18 bit
1
0
2
1
0
Table 91. PLL,MLK Sttings
I2S_mclk_en I2Sselect
mclk_invert
Description
I2S_1 selected (PLL used)
0
0
0
0
0
0
1
1
0
Internal MCLK synchronized to external LRCLK
I2S_1 selected (PLL used)
Internal LRCLK used, synchronized to external SDI
1
0
1
I2S_2 selected (PLL used)
Internal MCLK synchronized to external LRCLK
I2S_2 selected (PLL used)
Internal LRCLK used, synchronized to external SDI
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Table 91. PLL,MCLK Settings
I2S_mclk_en I2S_select
mclk_invert
Description
1
1
1
1
0
0
1
1
0
1
0
1
I2S_1 selected, external MCLK on MCLK_1
I2S_1 selected, external MCLK on MCLK_1 (inverted)
I2S_2 selected, external MCLK on MCLK_2
I2S_2 selected, external MCLK on MCLK_2 (inverted)
9.4.3 Parameter
Table 92. Audio DAC/ADC Parameter
Parameter
Min
Typ
Max
Unit
Analog Performance
Programmable gain DAC input
-43.43
-34.5
1.7
2
dB
dB
dB
dB
dB
dB
dB
Programmable gain ADC input
Gain step size
1.5
-85
9
DAC THD+Noise at FS
-75
DAC SN/R (20Hz-20kHz, -60dBFS) A-weighted
DAC Inter channel Mismatch
ADC SN/R
90
0.25
82
Table 93. I2S Parameter
I2S Inputs and Outputs I2S=2.9V
SCLK, LCLKx, SDIx
Min
-
Typ
-
Max
0.42V
3.3V
VIL
VIH
SCKx, RCLKx, SDIx
1.02V
-
VOL
VOH
SDOX,SCLK3,LR3,SPDIF,SCLKCLK1,MCLK1
SDOX,SCLK3,LRCLK3,SPDIF,SCLKCLK1,MCLK1
0V
VI2S
Table 94. DAC_L Register
DAC_L
These bits control the Audio DAC volume and functions
Deault Access Description
Addr:77
Bit
Bit Name
volume settings for left DAC input, adjustable in 32 steps @
1.5dB
00000
00001
.....
-40.5 dB gain
-39 dB gain
4:0
dalvol
00000b
R/W
11110
11111
4.5 dB gain
6 dB gain
5
6
-
-
-
0
1
DAC input is set to mute
normal operation
dac_mute_off
0
R/W
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Table 95. DAC_R Register
DAC_R
These bits control the Audio DAC volume and functions
Addr:78
Bit
Bit Name
Default Access
Description
volume settings for right DAC input, adjustable in 32 steps
@ 1.5dB
00000
00001
.....
-40.5 dB gain
-39 dB gain
4:0
dar_vol
00000b
R/W
11110
11111
4.5 dB gain
6 dB gain
Table 96. ADC_L Register
ADC_L
These bits control the Audio ADC volume nd fnctions
Addr:79
Bit
Bit Name
Default Access
Description
olume settings for left ADC input, adjustable in 32 steps @
1.5dB
0000
00001
.....
-34.5 dB gain
-33 dB gain
4:0
adl_vol
00000b
R/W
11110
11111
0
10.5 dB gain
12 dB gain
ADC disabled
5
6
adc_on
0
0
R/W
R/W
ADC enabled
0
ADC input is set to mute
normal operation
adc_mute_off
1
Divider selection for ADC clock
ADC sample clock is I2S LRCLK / 2; every ADC
sample is sent twice to the I2S output (up-
sampling by 2)
0
1
7
ad_fs2
0
R/W
ADC sample clock is I2S LRCLK / 4; every ADC
sample is sent four times to the I2S output (up-
sampling by 4)
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Table 97. ADC_R Register
ADC_R
These bits control the Audio ADC volume and functions
Addr:80
Bit
Bit Name
Default Access
Description
volume settings for right ADC input, adjustable in 32 steps
@ 1.5dB
00000
00001
.....
-34.5 dB gain
-33 dB gain
4:0
adr_vol
00000b
R/W
11110
11111
0
10.5 dB gain
12 dB gain
normal mode
5
adc2dac
adcmux
0b
R/W
R/W
use ADC output as DAC inpt (fotesting
purposes, equalizer is bypssed)
1
00
01
10
Micropne
Line In
7:6
00b
reserved –do not use
AudiSum (Output of Mixer)
9.5
I2S master mode and PCM Mode
The digital audio interface can also operate in master mode by using I2interface.
The pin MCLK2 is used as clock input in that ase. Any input clock tween sampling rate and 24MHz may be used as
input clock.
In Master Mode operation SCLK1 aoput has 32 clock cyclfor each sample word.
SCLK = [MCLK / 4] = [LRC56 / 4] = LRCK * 64
(EQ 8)
Sample Rates
In Master Mode the i2smaster control allos programming various sample rates. The master clock is generated from
the MCLK2 input. Sampling frequencies from kHz to 48kHz can be selected. For certain division ratios between
master clock and sample ratio a certain deation is system inherent.
1
1
LRCLK = fMCLK 2 * *
2
RD + 2
Table 98. PLL,i2s_clk_dider ettings
Actual sample
rate
Sample rate
MCLK2 input
Error
i2s_clk_divider
<10:0>
Divider
kHz
kHz
kHz
%
48,000
400
32,000
29,400
24,000
22,050
12,000
12288
12288
12288
12288
12288
12288
12288
126,00
137,32
190,00
206,98
254,00
276,64
510,00
126
137
190
207
254
277
510
48,00
44,20
32,00
29,40
24,00
22,02
12,00
0,00
0,23
0,00
-0,01
0,00
-0,13
0,00
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Table 98. PLL,i2s_clk_divider settings
Actual sample
rate
Sample rate
MCLK2 input
Error
i2s_clk_divider
<10:0>
Divider
kHz
kHz
kHz
%
11,025
8,000
12288
12288
12000
12000
12000
12000
12000
12000
12000
12000
12000
555,28
766,00
123,00
134,05
185,50
202,08
248,00
270,11
498,00
542,22
748,00
555
766
123
134
186
202
248
270
498
542
748
11,03
8,00
0,05
0,00
0,00
0,04
-0,27
0,04
0,00
0,04
0,00
0,04
0,00
48,000
44,100
32,000
29,400
24,000
22,050
12,000
11,025
8,000
48,00
44,12
31,91
29,41
24,00
22,06
12,00
11,03
8,00
Table 99. i2s master control1 Register
I2s master cntrol1
Addr:131
This register conrols the external ock divider for i2s master mode
Description
Bit
Bit Name
Default Acess
7:0
i2s_clk_divider<7:0>
0h
R/W
Bit 7:0 of divider for MCLK2 input pin
Table 100. i2s master control2 Registe
I2s master control2
Addr:132
This register conts the external clock divider and modes for i2s master
mode
Description
Bit
Bit Name
Defult Access
2:0
i2s_clk_divider<10:8>
0b
0b
R/W
R/W
Bit 10:8 of divider for MCLK2 input pin
i2s master mode disabled
0
1
3
4
i2s_master_on
i2s master mode enabled
LRCLK1 and SCLK1 are used as input (slave
mode)
0
i2s_lrclk_sclkout_en
0b
R/W
LRCLK1 and SCLK1 are used as output (master
mode).
1
0
Clock input for PLL is MCLK2
MCLK1 used as input (slave mode)
MCLK1 used as output for master clock of an
external I2S. Clock input for PLL is MCLK2
(MCLK1=256*LRCLK, if bit mclk256=1;
MCLK=128*LRCLK, if bit mclk256=0)
5
6
i2s_mclk_out_en
sdo_on_ mclk1
0b
0b
R/W
R/W
1
Normal operation of MCLK1 (input or output
according to bit is2_mclk_out_en bit)
0
1
MCLK1 used as SDO output (e.g. for audio ADC).
May be used as data output (SDO) for I2S_2 port
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Table 100. i2s master control2 Register
I2s master control2
Addr:132
This register controls the external clock divider and modes for i2s master
mode
Description
Bit
Bit Name
Default Access
0
1
Normal I2S mode
PCM mode selected. The following additional
settings are necessary to enable PCM mono
mode:
sclk_invert=1
i2s_mclk_en=0 and mclk_invert=1 (internal PLL
used for generation of internal LRCLK
7
pcm_mode
0b
R/W
9.5.1 PCM mode settings
Compatible with BlueCore3-ROM:
Figure 43. Short Frame Sync (shown with 16-bit Sample)
In short Frame Sync the falling edge of PCM_SYNC indicate the start ohe Pword. PCM_Sync is alwas one clock cycle long.
LRCLK
SCLK
PCM_SYNC
PCM_CLK
PCM_OUT
PCM_IN
SDI
1
2
4
5
6
7
8
9
10 11 12
10 11 12
13 14 15 16
13 14 15 16
SDO
3
4
5
6
7
8
9
Undefined
Undefined
The following setup on PCM-Master side is needed
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
AS3658 is slave only
PCM_SYNC is in short frame mode
PCM_SYNC rate is 8ksamples/s
PCM_CLK= 512kHz only (64 PC_SYNC)
16 Bit Linear coding of PCM_OUT and PCM_IN (MSB first, LSB last)
Mono (single channelopration only. Only the right channel of the AS3658 is used. The left channel is same as
right channel (in the inut direction of AS3658) and has to be ignored by PCM master (in output direction of
AS3658)
Note: Internaly the right channel is copied to the right and left channel.
The following etup of AS3658 is needed:
ꢀ
ꢀ
Sclkert=1
i2s_mlk_en=0 and mclk_invert=1 (internal PLL used for generation of internal LRCLK)
pm_mode=1 and ad_fs2=0 (Necessary to allow unsymmetrical LRCLK and sample rate of 8kHz of ADC)
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9.6
Line Input
9.6.1 General
AS3658 includes one stereo single ended inputs.
Figure 44. LineIn Block Diagram
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Table 101. Line Inputs Parameter
Parameter
Analog Performance
Rin
in
Typ
Max
Unit
50
kΩ
Table 102. LINE_IN_R Register
IN_IN_R
Addr:85
These bits controthe LINE_IN volume and functions
Default Access Description
Bit
Bit Name
olume settings for right line input, adjustable in 32 steps
1.5dB; gain from line input pin (LIN1R) to mixer input
00000
00001
.....
-34.5 dB gain
-33 dB gain
4:0
lir_vol
0000b
R/W
11110
11111
10.5 dB gain
12 dB gain
Control of MUTE switch
right line input is set to mute
normal operation
0
1
5
mute_of_ir
0
-
R/W
-
do not change
7:6
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Table 103. LINE_IN_L Register
Addr:86
LINE_IN_L
These bits control the LINE_IN volume and functions
Bit
Bit Name
Default
Access
Description
volume settings for right line input, adjustable in 32 steps @
1.5dB; gain from line input pin (LIN1L) to mixer input
00000
00001
.....
-34.5 dB gain
-33 dB gain
4:0
lil_vol
00000
R/W
11110
11111
10.5 dB gain
12 dB gain
Control of MUTE switch
left line input is set tmu
normal operaon
5
mute_off_inl
0
R/W
n/a
0
1
7:6
00
do not change
9.7
Five Band Equalizer
The 5 Band equalizer is build of one low pass, one high pand 3 band pass filtand is optimized for 44.1kHz
sample frequency:
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Low pass filter: 200Hz ( when programming negaitve gain values, this filtr changes to a HP filter)
Band pass filter1: 340Hz / Q=1.0 (when programmig negative gailues, this filter changes to a notch filter)
Band pass filter2: 1100Hz / Q=0.7 (when progamming negatigain values, this filter changes to a notch filter)
Band pass filter3: 3375Hz / Q=1.0 (wen programming negatve gain values, this filter changes to a notch filter)
High pass filter: 5940Hz (when prramming negative gan values, this filter changes to a LP filter)
The Q factors and the cut off frequencf the High and ss filter are measured at 50% gain and are valid for
+6dB amplification of each band.
The attenuation or amplification of each band can e dyamically adjusted by the serial interface. Additional a pre-gain
stage can adjust the input level. This gain tage is after the 16 to 24 bit extension and therefore additional gain, which
is compensated with the equalizer filter itself (q_lp_gain, eq_band1,2,3_gain, eq_hp_gain) will not cause clipping:
Figure 45. Equalizer Block Diagram
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Figure 46. EQ Filter frequency response sum curve
Figure 47. EQ Filter frequency response +12dB/+6dB/3dB
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Figure 48. EQ Filter frequency response -3dB
Each band has a range from -12 to +B with each innt equal to ±3dB.
For sample frequencies of the I2S stream different from 4kHz, the filter frequencies are shifted (ratiometric).
Table 104. EQ_LP Register
EQ_LP
Addr: 90
These bits control the gain of the low pass filter in dB
Bit
Bit Name
efault Access
Description
EQ_LP filter gain (-12dB... +12dB)
0h
1h
2h
3h
4h
bh
ch
dh
eh
0dB
3dB
6dB
9dB
3:0
eq_lp_gain
0000b
R/W
12dB
-3dB
-6dB
-9dB
-12dB
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Table 105. EQ_Band1 Register
EQ_Band1
These bits control the gain of the Band pass filter1 in dB
Addr: 91
Bit
Bit Name
Default Access
Description
EQ_Band1 filter gain (-12dB... +12dB)
0h
1h
2h
3h
4h
bh
ch
dh
eh
0dB
3dB
6dB
9dB
3:0
eq_band1_gain
0000b
R/W
12dB
-3dB
-6dB
-9dB
-1B
Table 106. EQ_Band2 Register
EQ_Bnd2
Addr: 92
These bits control the gain of thBand pass filter2 in dB
Bit
Bit Name
Default Access
Description
Band2 filter gain (-12dB... +12dB)
0h
1
2h
3h
4h
bh
ch
dh
eh
0dB
3dB
6dB
9dB
3:0
eq_band2_gain
0000b
R
12dB
-3dB
-6dB
-9dB
-12dB
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Table 107. EQ_Band3 Register
EQ_Band3
These bits control the gain of the Band pass filter3 in dB
Addr:93
Bit
Bit Name
Default Access
Description
EQ_Band3 filter gain (-12dB... +12dB)
0h
1h
2h
3h
4h
bh
ch
dh
eh
0dB
3dB
6dB
9dB
3:0
eq_band3_gain
0000b
R/W
12dB
-3dB
-6dB
-9dB
-1B
Table 108. EQ_HP Register
EQ_HP
Addr:94
These bicontrol the gain of thHigh pass filter in dB
Bit
Bit Name
Default Access
Description
_HP filter gain (-12dB... +12dB)
0h
1
2h
3h
4h
bh
ch
dh
eh
0dB
3dB
6dB
9dB
3:0
eq_hp_gain
0000b
R
12dB
-3dB
-6dB
-9dB
-12dB
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Table 109. EQ_preamp Register
EQ_preamp
These bits control the preamplifier of the EQ in dB
Addr:95
Bit
Bit Name
Default Access
Description
EQ_vol gain (-12dB ... +12dB with 1.5dB steps)
0dB
0h
01h
02h
03h
04h
05h
06h
07h
08
0h
bh
-1.5dB
-3.0dB
-4.5dB
-6.0dB
-7.5dB
-9.0dB
-10.5dB
-1B
1.5dB
3.0B
6.0dB
7.5dB
9.0dB
10.5dB
12dB
4:0
eq_pre_gain
00000b
R/W
ch
dh
eh
fh
10h
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9.8
Microphone Input
General
The audio front-end offers one microphone inputs and a low noise microphone voltage supply (microphone bias), voice
activation, microphone connect detection and push button remote control.
Figure 49. Microphone Input Block diagram and External Circuit
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Gain Stage & Limiter
The integrated pre-amplifier allows 3 peset gain settings. The is lso a limiter which attenuates high input signals
from e.g. electret microphones signal tp. The AGC has 15 seps with a dynamic range of about 29dB. The AGC is
ON by default but can be disabled by a microphone regt.
Apart from the microphone pre-amplifier the microhone input signal can further be amplified with 32 @1.5dB
programmable logarithmic gain steps and MUTE. Al gans and MUTE are independently programmable. The gain can
be set from –40.5dB to +6dB.
The stage is set to mute by default. If the icrohone input is not enabled, the volume settings are set to their default
values. Changing the volume and mute col can only be done after enabling the input.
Supply & Detection
The microphone input generatea supply voltage of 1.5V above AGND. The supply is designed for ≤ 2mA and has a
10mA current limit. In OFF mde the MICS terminal is pulled to AVDD with 30kΩ. A current of typically 50µA generates
an interrupt to inform the PU, that a circuit is connected. When using the MICS terminal as ADC-10 input to monitor
external voltage e 30Ω pull-up can be disabled.
Remote Control
Fast changes f thsupply current of typically 500µA are detected as a remote button press, and an interrupt is
generat
Voce Activation
Furthea built-in voice activation comparator can actuate an interrupt if microphone input voltage of about 5mVRMS is
detected.
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Microphone Input Parameter
Table 110. Microphone Inputs Parameter, TA= 25oC unless otherwise mentioned
Symbol
Parameter
Min
Typ
40
Max
Unit
mVPEAK
mVPEAK
mVPEAK
kΩ
Note
VMICIN
VMICIN
VMICIN
0
1
2
AMICPRE = 28dB; AMIC = 0dB
AMICPRE = 34dB; AMIC = 0dB
AMICPRE = 40dB; AMIC = 0dB
MICP, MICN to AGND
Input Signal Level
20
10
RMICIN
MICIN
CMICIN
Input Impedance
15
Input Impedance
Tolerance
±15
%
Input Capacitance
5
pF
28
34
40
Microphone
Preamplifier Gain
dB
Preamplifier has 3 electable (fixed)
gain settigs
AMICPRE
Programmable Gain
Gain Steps
-40.5
+6
dB
dB
AMIC
1.5
±0.25
1
discrete logthmic gain steps
Gain Step Precision
Limiter Activation Level
Limiter Gain Overdrive
Limiter Attack Time
Limiter Decay Time
Mute Attenuation
dB
VMICLIMIT
AMICLIMIT
tATTACK
VPEAK
dB
15*2
50
µs/6d
s/6dB
dB
tDECAY
120
100
AMICMUTE
Microphone Suply
Voltage
VMICSUP
IMICMAX
VNOISE
2.9
5
V
Max. Microphone
Supply Current
microphones nominally need a bias
current of 0.5mA-1mA
mA
µV
µA
µA
Microphone Supply
Voltage Noise
Microphone Detection
Current
IMICDET
IREMDET
50
500
Max. Remote
Detection urrent
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Register Description
Table 111. MIC_R Register
MIC_R
Addr:87
Right Microphone Input Register
Configures the gain from microphone amplifier output
Bit
Bit Name
Default Access
Description
volume settings for right microphone input, adjustable
in 32 steps @ 1.5dB; gain from microphone amplifier
00000
00001
.....
-40.5 dB gain
-39 dB gain
4:0
mr_vol
00000b
R/W
11110
11111
4.5 dB gain
6 dB gai
Sets the gain of the microphne pamplifier
gain set o 28 dB
00
1
10
11
6:5
pre_gain
00
R/W
R/W
gan seto 34 dB
gain set to 40 dB
eserved, do not use
Control of limer AC (automatic gain control). Limits
high dynamirange of electret/MEMS microphone
(e.ser shouts or blows into microphone)
7
mic_agc_off
0
1
automatic gain control enabled
automatic gain control disabled
Table 112. MIC_L Register
MIC_L
Left Microphone Input Register
Configures the gain from microphone amplifier output
Addr:88
Bit
Bit Name
Deault Access
Description
volume settings for left microphone input, adjustable in 32
steps @ 1.5dB; gain from microphone amplifier
00000
00001
.....
-40.5 dB gain
-39 dB gain
4:0
ml_vl
00000
R/W
11110
11111
4.5 dB gain
6 dB gain
Disables the microphone detect function (30kΩ pull-up
from MICS to VDAC) to use the terminal as ADC-10
input
5
6
rdet_off
0
0
R/W
R/W
0
1
microphone detection enabled
microphone detection disabled
Control of MUTE
mute_off
0
1
microphone input set to mute
gain set to 34 dB
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Table 112. MIC_L Register
MIC_L
Addr:88
Left Microphone Input Register
Configures the gain from microphone amplifier output
Bit
Bit Name
Default Access
Description
0
1
microphone supply on if mic_on=1
microphone supply off
7
msup_off
0
R/W
9.9
Audio Output Mixer
9.9.1 General
The mixer stage sums up the audio signals of the following stages
ꢀ
ꢀ
ꢀ
Microphone Input
Line Input
Digital Audio Input (DAC)
The mixing ratios have to be with the volume registers of the corrsponing input stages. Pleabe sure that the input
signals of the mixer stage are not higher than 1Vp. If summing useverasignals, each individual signal has of course
to be accordingly lower. This shall insure that the output signal is alo not higher than 1Vp to gt a proper signal for the
output amplifier.
This stage features an automatic gain control (AGC), which utomatically avoids cliping.
9.9.2 Register Description
Table 113. AudioSet_3 Register
udio_set3 register
Addr:76
onfigres the mixer inputs and AGC
Bit
Bit Name
Default Ac
Description
Preset of PLL bias for the following sampling
frequencies
0
pll_mode
0
0
R/W
R/W
0
1
16-48kS
8-12kS
Controls the pulldown of the HP1 if HP2is enabled and
HP2, if HP1 is enabled
1
hp_pulld_en
0
1
Pulldown disabled if hp_on=1
Pulldown of the not used HP1/2 output
enabled, if hp_on=1
Switches on the voice recognition
2
3
voxm_on
mic_on
0
0
R/W
R/W
0
1
OFF
ON
Switches on the microphone amplifier
0
1
OFF
ON
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Table 113. AudioSet_3 Register
Audio_set3 register
Addr:76
Configures the mixer inputs and AGC
Default Access Description
Bit
Bit Name
Switches the signal limiter OFF
automatic gain control for summing stage
0
4
agc_off
0
R/W
enabled
automatic gain control for summing stage
1
disabled
Input from DAC to R and L
5
6
7
dacmix_off
micmix_off
linmix_off
0
0
0
R/W
R/W
R/
0
1
ON
OFF
Input from microphone tR ad L
0
1
ON
F
Input from line input to R and L
0
1
ON
OFF
9.10 Line Output
9.10.1 General
The line output is designed to provide the audsignal on 600 Ω min
This output stage has an independent ain egulation for left nd riht channel with 32 steps @ 1.5dB each. The gain
can be set from –40.5dB to +6dB.
9.10.2 No-Pop Function
To avoiding click and pop noise during power-up ad shdown, the output is automatically set to mute when the output
stage is disabled. Also the volume settings are set to their default values, and can’t be changed, as long the output
stage is not enabled.
LINE_CM pin, which needs a 0.1µF... 1µF pacitor outside gets charged on power-up with 1µA to ALVDD/2. After
start-up the DC level of the following pins e the same: LOUT_L=LOUT_R=LINE_CM= ALVDD/2. The Start-up time
before releasing mute is about 15ms ith 0.1µF. To avoid pop-noise 150ms discharging time of LINE_CM after a
shutdown, have to be waited bore starting up again.
9.10.3 Ground Noise Cancellation
The purpose of te grond cancellation circuit is to compensate noise (ground noise) between different grounds (e.g.
the ground where tAS3658 is soldered versus e.g. the ground of a car amplifier (see Figure 50)). This noise
between thesdifferent grounds can be caused e.g. by a high current devices like a motor-fan. The ground
cancellation cicuit can be used for line and headphone amplifiers.
Thcircwoks as follows:
Thground noise gets added inside the AS3658 to the audio signal (input LINE_CM for the Line Out amplifier or
HP_Cfor headphone amplifier) in a way that it cancels inside the car amplifier. The sense point is connected with
RGND_SEP (20Ω) to the battery ground.
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The ground cancellation can be disabled by shorting the 20Ω resistor setting bit gnd_sw to ‘1’. This bit should be set if
e.g. a headphone instead of the car amplifier is connected to the output jack.
Note: A similar cicuit can be used for the headphone amplifier.
Figure 50. Ground Noise Cancellation Application Schematic
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9.10.4 Power Save Options
To save power, a reduction of the bias urret can be selecte
Table 114. Line Power-Save Options
IBR_LINE
IDD_LINE (typ.)
0
1
2.2mA
1.5mA
9.10.5 Parameter
Table 115. Line out Block Characeristis
Parameter
Analog Performance
Min
Typ
Max
Unit
R_Loaat LUT_L and LOUT_R single ended
Gain Step Precision (RLmin-max,20Hz-20kHz)
SINAD no load, LineIn-> Line out, A-weighted
THD @ 1kHz, no load
600
Ω
±0.5
-97
-88
-80
90
dB
dB
dB
dB
dB
µA
ms
THD @ 1kHz, 600Ω
PSRR (200Hz-20kHz)
60
IOUT_powerdown
-20
20
Tpower_up (C_LINECM=100nF)
150
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Table 115. Line out Block Characteristics
Parameter
Min
Typ
50
Max
Unit
100Hz
1kHz
GND cancellation GND - AUDIO_GND to
LOUT_R, LOUT_L no load
50
dB
10kHz
40
9.10.6 Register Description
To get an interrupt on an over-current event, the corresponding bit in the Interrupt enable register has to be set. All
other Line/headphone driver settings are controlled by the following two registers.
Right Line Register
Table 116. LINE_OUT_R Register
LINE_OUT_R
Addr:83
These bits control the Line in volume and mod
Bit
Bit Name
Default Access
olumettings for right Line oput, adjustable in 32
steps @ 1.5dB
00000
00001
......
-40.5 dB gain
-39 dB gain
4:0
liner_vol
00000b
R/W
11110
11111
4.5 dB gain
6 dB gain
Line_out amplifier input connected to mixer
output
0
1
5
dac2line_on
ibr_line<1:0>
0
R/W
R/W
Line_out amplifier input connected to Audio
DAC output gain stage (Mixer is bypassed in
this mode)
Bias current reduction settings for line output:
00
0%
7:6
0b
01
10
11
17%
34%
50%
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Left Line Register
Table 117. LINE_OUT_L Register
LINE_OUT_L
These bits control the Line in volume and mode
Addr:84
Bit
Bit Name
Default Access
volume settings for left Line output, adjustable in 32
steps @ 1.5dB
00000
00001
......
-40.5 dB gain
-39 dB gain
4:0
liner_vol
00000b
R/W
11110
11111
4.5 dB gain
6 dB gain
5
6
-
0
0
reserved
0
1
Line stagnot owered
power up Le stage
nomal peration
line_on
R/W
R/
7
line_mute
0
Line ouut set to mute (mute is on during
power-up)
1
9.11 Headphone Output
The headphone output is designed to provide te audio signal with 2x4W @ 16Ω or 2x20mW @32Ω, which are
typical values for headphones.
This output stage has an independent gairegulation for left and ght channel with 32 steps @ 1.5dB each. The gain
can be set from –40.5dB to +6dB.
9.11.1 Phantom Ground
HP_CM_PWR pin is the buffered HP_CM output. can be used to drive the common mode level with a load of 2kΩ.
The phantom ground can be switched off to save pweif not needed.
9.11.2 No-Pop Function
To avoiding click and pop noise during powup and shutdown, the output is automatically set to mute when the output
stage is disabled. Also the volume settingare set to their default values, and can’t be changed, as long the output
stage is not enabled.
HP_CM pin, which needs a 100nto 1µF capacitor outside, gets charged on power-up with 1µA to AVDD/2. After start-
up the DC level of the follwinpins are the same: HPR=HPL=HP_CM=HP_CM_PWR=AVDD/2. The Start-up time
before releasing mute is about 150ms. To avoid pop-noise 150ms discharging time of HP_CM after a shutdown, have
to be waited beforstartg up again.
9.11.3 Ovecurrent Protection
This outpstage has an over-current protection, which disables the output for 256ms or 512ms. This value can be set
in he hephne registers. The over-current protection limit of HPR and HPL pin is about 260mA while HP_CM_PWR
pin has a 370mA limit.
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9.11.4 Power Save Options
To save power, especially when driving 32 Ω loads, a reduction of the bias current can be selected.
Bias current reduction settings for headphone output:
ꢀ
ꢀ
ꢀ
ꢀ
00: 0%
01: 17%
10: 34%
11: 50%
9.11.5 Parameters
Table 118. Power Amplifier Parameter
Parameter
Min
Typ
Max
Unit
Analog Performance
R_Load at AOUTR and AOUTL single ended
16
Ω
Vout
.13
Vp
dB
dB
dB
dB
dB
dB
dB
dB
mA
mA
µA
ms
Gain Step Precision (RLmin-max,20Hz-20kHz)
SINAD no load, LineIn-> HPH, A-weighted
THD @ 1kHz, no load
±0
-97
-88
-80
-74
-68
60
THD @ 1kHz, 32Ω, 10mW
THD @ 1kHz, 32Ω, 20mW
-66
-60
THD @ 1kHz, 16Ω, 40mW
Channel Separation (32Ω, dcoupled)
PSRR (200Hz-20kz)
60
90
Shorted ProtectioLevel
260
370
Shorted Protection Levecommon mode er
IOUT_powerdown
-20
20
Tpower_up (HP_CM=0.1µF)
150
50
100Hz
1kHz
GND cancellation GND - AUDIO_GND to
HP_R, HP_L no oa
50
dB
10kHz
40
9.11.6 Register Description
To get an interrupt on an ovr-curent event, the corresponding bit in the Interrupt enable register has to be set.
Changing the bias currenor the output driver strength is done via AudioSet2 register. All other headphone driver
settings are controlled by thfollowing two registers.
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Right Headphone Register
Table 119. HPH_OUT_R Register
HPH_OUT_R
These bits control the Right headphone ouput volume and mode
Addr:81
Bit
Bit Name
Default Access
Description
volume settings for right headphone output, adjustable
in 32 steps @ 1.5dB
00000
00001
......
-40.5 dB gain
-39 dB gain
4:0
hpr_vol
00000b
11110
11111
4.5 dB gain
6 dB gain
headphone phantom groundisble
normaopertion
5
hpcm_off
0
1
disable commomode buffer
headphone ovr curent time out:
speaker over current time out:
00
01
10
256 ms
128 ms
512 ms
0 ms
7:6
hp_ovc_to
00h
Left Headphone Register
Table 120. HPH_OUT_L Register
HPH_OUT_L
Addr:82
Thee bitcontrol the Left headphone ouput volume and mode
Bit
Bit Name
efault Access
volume settings for left headphone output, adjustable
in 32 steps @ 1.5dB
00000
-40.5 dB gain
-39 dB gain
00001
4:0
hpl_vol
00000b
......
11110
4.5 dB gain
6 dB gain
11111
0
1
0
1
0
use HPL1, HPR1 as headphone output
use HPL2, HPR2 as headphone output
headphone stage not powered
power up headphone stage
normal operation
5
6
hp_mux
hp_on
0
0
R/W
R/W
7
hp_mute
0
R/W
headphone output set to mute (mute is on
during power-up)
1
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9.12 SPDIF output
Enables and controls the SPDIF output pin. SPDIF functionality is enabled, if internal masterclock is used (internal
PLL), or the external masterclock = 256* LRCLK. (No SPDIF function if external masterclock= 128 *LRCLK)
Table 121. SPDIF Register
SPDIF
Addr:89
These bits control the SPDIF output
Bit
Bit Name
Default Access
Description
ISPDIF output ON/OFF control and sample rate status
bits
00
01
10
11
SPDIF output OFF
SPDIF output ON
1:0
spdif_cntr
00b
R/W
reserved (do not use)
reserved (do nt us
SPDIF sample tatubit
samplvalid
2
3
4
5
6
spdif_invalid
spdif_mclk_inv
spdif_copy_ok
sdo3_select
sclk_invert
0
0
0
0
0
R/W
R/W
R/W
R
R/W
0
1
samplinvalid
SPDIF master clock control bit
master clock
0
1
master clock inverted
SPDIF copy control bit
copy not permitted
1
copy permitted
Select source of SDO3 output
Select adc_output
0
1
Select Equalizer output
Invert serial data clock of I2S1 and I2S2
Normal mode
0
1
Invert SCLK1 or SCLK2 input
switch off audio functionality for low power
touchpannel detection
7
audio_of
0
R/W
0
1
Normal mode
audio bias switched off to reduce power
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10 Detailed Description - System Functions
The system functions consist of the I2C interface, the reset controller, the interrupt controller, startup sequences and
programming, the watchdog, internal references, the ON-key detect and the real time clock module.
2
10.1 I C Serial Interface
Table 122. I2C SDA,SCL Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
Note
SCL,SDA Low Level
input voltage
VIL
-0.3
0.4
V
SCL,SDA High Level
input voltage
VSUPP
LY
VIH
1.3
V
10.1.1 Feature List
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Fast-mode capability (max. SCL-frequency is 400 kHzkHz)
7+1-bit addressing mode
60h x 8-bit data registers (word address 0x00 - 0x60)
Write formats: Single-Byte-Write, Page-Write
Read formats: Current-Address-Read, Random-Read, ential-Read
SDA input delay and SCL spike filtering by integrated Rcomponents
10.1.2 Transfer Formats
Figure 51. I2C Byte-Write
S
Sr
DW
DR
WA
A
N
START condition after STOP
repeated START
device address for write
device address for read
word address
S
DW
A
WA
A
reg_data P
write register,
WA++
acknowledge
no acknowledge
P
stop condition
white field
grey field
WA++
slave as receiver
slave as transmitter
increment word address internally
AS3658 device address write (DW):80h = 10000000b
AS3658 device address rad (DR): 81h = 10000001b
Figure 52. I2C Pa-Wrie:
…
reg_data n A P
S
DW
A
WA
A
reg_data 1
A
reg_data 2
A
write register
WA++
write register
WA++
write register
WA++
Byte-Write and Page-Write are used to write data to the slave.
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The transmission begins with the START condition, which is generated by the master when the bus is in IDLE state
(the bus is free). The device-write address is followed by the word address. After the word address any number of data
bytes can be send to the slave. The word address is incriminated internally, in order to write subsequent data bytes on
subsequent address locations.
For reading data from the slave device, the master has to change the transfer direction. This can be done either with a
repeated START condition followed by the device-read address, or simply with a new transmission START followed by
the device-read address, when the bus is in IDLE state. The device-read address is always followed by the 1st register
byte transmitted from the slave. In Read-Mode any number of subsequent register bytes can be read from the slave.
The word address is incriminated internally.
The diagrams below show various read formats available:
Figure 53. I2C Random-Read:
S
DW
A
WA
A Sr
DR
A
data
P
N
read register
WA++
W+
Random-Read and Sequential-Read are combined formaThe repeated START condition is used to change the
direction after the data transfer from the master.
The word address transfer is initiated with a START conditioissued by the maer while the bus is idle. The START
condition is followed by the device-write address and the word address.
In order to change the data direction a repeated START condition is isson the 1st SCL pulse after the acknowledge
bit of the word address transfer. After the recptioof the device-rd address, the slave becomes the transmitter. In
this state the slave transmits register data ocatd by the previoureceed word address vector. The master responds
to the data byte with a not-acknowledg, anissues a STOP onditn on the bus.
Figure 54. I2C Sequential-Read:
data 2
data n
S
DW
A
WA
A Sr
DR
A
data 1
…
A
A
P
N
read register
WA++
WA++
Sequential-Rad is the extended form of Random-Read, as more than one register-data bytes are transferred
subsequetly. In difference to the Random-Read, for a sequential read the transferred register-data bytes are
respondby an acknowledge from the master. The number of data bytes transferred in one sequence is unlimited
cnsider the behavior of the word-address counter). To terminate the transmission the master has to send a not-
acknwledge following the last data byte and generate the STOP condition subsequently.
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Figure 55. I2C Current-Address-Read:
A
data 2
data n
S
DR
A
data 1
…
A
N P
read register
WA++
read register
WA++
read register
WA++
WA++
To keep the access time as small as possible, this format allows a read access without the word address transfer in
advance to the data transfer. The bus is idle and the master issues a START condition followed by the Device-Read
address. Analogous to Random-Read, a single byte transfer is terminated with a not-acknowledge after the 1st regis
byte. Analogous to Sequential-Read an unlimited number of data bytes can be transferred, where the data bytes as to
be responded with an acknowledge from the master. For termination of the transmission the master sends a not-
acknowledge following the last data byte and a subsequent STOP condition.
10.2 Reset generator and XON-Key
XRESET is a low active bi-directional pin. An external pull-up to he perhery supply has to be dded.
During each reset cycle the following states are controlled by the S368:
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Pin XRESET is forced to GND
Programmable Power-off function
Programmable Power-on sequence and regulator voltages
Programmable reset timer
All registers are set to their default valueafr power-on, excpt threst control- and status-registers.
Note: Programming is controlled by the nternl Mask-PROM ad thxternal resistor RPROGRAM
Table 123. XRESET,XON Characteiss
Symbol
Parameter
Min
Max
Unit
Note
XRESET Low Level
input voltage
VXRESET_IL
-0.
0.4
V
XRESET High Level
input voltage
VSUPP
LY
VXRESET_IH
VXON_IL
1.3
V
XON Low Level inpu
voltage
0.3*V2
_5
-0.3
0.7*V2
_5
VXON_IH
XON High Leel iput
XON Pl up current
V2_5
IXON_PUP
12
µA
10.2.1 Reset Conditons
Reset can be activatd from 7 different sources:
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Power on battry or charger insertion)
Low tery
Softwre forced reset
Pwer off mode
External triggered through the pin RESET
Overtemperature
Watchdog
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Voltage detection:
There are two types of voltage dependent resets: VPOR and VXRESET. VPOR monitors the voltage on V2_5 and
VXRESET monitors the voltage on VSUPPLY. The linear regulator for V2_5 is always on and uses the voltage
VCHARGER, VBAT or V_USB as its source.
The pin RESET is only released if V2_5 is above VPOR and VSUPPLY is above VXRESETRISE
.
Table 124. Reset Levels
Symbol
Parameter
Min
Typ
Max
Unit
Note
Monitor voltage on V2_5; power on
reset for all internal functions
VPOR
Overall power on reset
1.5
2.0
2.3
V
Reset level for Vsupply
rising
ResVol
trise
Monitor voltage on Vsupply; risng
level
VXRESETRISE
V
V
V
Monitor voltage on VSupply; flling
level
2.7
Reset level for Vsupply
falling
VXRESETFALLING
ResVol
tfall
if SupResn=1 only
Duration foBATVXRESETFALLING
until a resecycle is started1
Mask time for
VXRESETFALLING
VRESETMASK
2.0
2.5
3.0
ms
1. VRESET signal is debounced with the specified mask me for rising- and falling slope of VBAT.
VRESETFALLING is only accepted if the reset condition is loner than VRESETSK. s guard time is used to avoid a
complete reset of the system in case of short drops of VBAT.
Power off:
To put the chip into ultra low power mode, wte ‘1’ nto xon_enablnd ‘1’ into power_off. The chip stays in power off
mode until the external pin XON is pulled ow, te charger is inseted othe level VPOR is touched to start a complete
reset cycle. The bit power_off is automicallcleared by this rset ccle. During power_off state all circuits are shut-off
except the Low Power LDO (V2_5). Ththe current consptioof AS3658 is reduced to less than 15 µA. The digital
part is supplied by V2_5, all other circuits are turned off mode, including references and oscillator. Except the
reset control registers all other registers are set to heir default value after power-on.
Software forced reset
Writing ‘1’ into the register bit force_reset immediately starts a reset cycle. The bit force_reset is automatically cleared
by this reset.
External triggered reset:
If the pin XRESET is pulled from hih to low by an external source (e.g. microprocessor or button) a reset cycle is
started as well.
Overtemperature rese:
The reset cycle cabe sarted by overtemperature conditions. (see Protection Functions on page 134)
Watchdog reset:
If the watchdog s armed (register bit wtdg_on = 1 and wtdg_res_on = 1) and the timer expires it causes a reset. (see
Watchdon page 135).
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10.2.2 Reset Control Bits
Table 125. Reset Timer Register
Reset Timer
These bits control the reset timer and XON enable register
Addr:22
Bit
Bit Name
Default Access
Description
Set RESTIME
RESTIME=10ms
RESTIME=20ms
RESTIME=35ms
RESTIME=50ms
RESTIME=65ms
RESTIME=8ms
RESTME=5ms
RESTIME110ms
000
001
010
011
100
101
110
111
2:0
res_timer
ROM
R/W
Ts flag enables the XON pad and sets the power on
state of the ASIC
XON pd disabled. Startup of chip; if
0
3
xon_enable
ROM
R/W
VT>VRESETRISING
ON pad enabled. Startup of chip; if
VAT>VRESETRISING and XON=0
1
Table 126. Reset Control Register
Reset Control
Addr:105
These bits cntrol the power off mode and reset timer
Bit
Bit Name
Default Ac
Description
0
force_reset
0b
R/W
Setting to ‘1’ starts a complete reset cycle
Setting to ‘1’ starts a reset cycle, but waits after the
Reg_off state for a falling edge on the pin XON or until
the charger is detected
1
2
power_off
xon_input
0b
R/W
Read:This flag represents the state of the XON pad
directly
NA
R/W
Write: Setting to '1' resets the 5 sec. Onkey reset timer
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Table 126. Reset Control Register
Reset Control
These bits control the power off mode and reset timer
Addr:105
Bit
Bit Name
Default Access
Description
Flags to indicate to the software the reason for the last
reset
VPOR has been reached (battery or charger
0000
insertion from scratch)
VRESETFALLING was reached (battery voltage
0001
drop below 2.75V)
0010
0011
software forced by force_reset
software forced by power_off and XON was
pulled low
software forced by power_f ancharger was
detected
0100
6:3
reset_reason
NA
R
0101
110
0111
1000
1001
1010
1011
external triggered ougthe pin RESET
reset caused by overmperature T140
reset caused by watchdog
reseaused by 5 seconds on press
est caused by rtc_alarm register
reet caused by rtc repeated wakeup
rest caused by interrupt in standby mode
reset caused by XON pulled low in standby
mode
1100
0
1
Reset after 5 seconds ON pressed disabled
Reset after 5 seconds ON pressed enabled
7
Onkey_reset_5s
1
R
Table 127. Internal references Bit definitions
Internal references Bit definitions
Addr:59
These bits control the internal reference mode and internal clk
frequency
Bit
Bit Name
Default Access
Description
Setting to ‘1’ sets the AS3658 into standby mode. All
regulators defined in reg.17h “Reg Power1Ctrl” and
reg.1Eh “Reg Power2 Ctrl are disabled except those
regulators enabled by reg.81h “Reg standby mode”.
XRESET will be pulled to low. A normal startup of all
regulators will be done with any interrupt (has to be
enabled before entering standby mode). During this
startup, regulators defined by Reg standby mode
register are continuously on.
4
standby_mode_on
0
W
Divide internal clock oscillator by 2 to reduce
quiescent current for low power operation
0
1
Normal mode
5
Clk_div2
0
R/W
Internal clock frequency divided by two. All
timings are increased by two. Switching
frequency of all DCDC converters are divided
by two. Reduced transient performance of
DCDC converters.
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Table 127. Internal references Bit definitions
Internal references Bit definitions
Addr:59
These bits control the internal reference mode and internal clk
frequency
Bit
Bit Name
Default Access
Description
Normal mode
0
1
The quiescent current of the following
regulators is divided by approx. two: SD1,
SD2, SD3, RF1, RF2, RF3. The current
capability and performance is also reduce in
that mode. (E.g. Use this bit only to reduce
quiescent current, if system and processor i
in a low power mode)
6
Reg_low_bias_mode
0
R/W
Table 128. Reg standby mode Bit definitions
Reg standby mode
Addr:129
These bits control the on/off function of the regulatrs dring standby
mode
Bit
Bit Name
Default Access
Description
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
RF1 LDO is disabed in standby mode
RF1 O is enabled in standby mode
RF2 DO is disabled in standby mode
R2 LDO is enabled in standby mode
DG1 LDO is disabled in standby mode
DIG1 LDO is enabled in standby mode
DIG2 LDO is disabled in standby mode
DIG2 LDO is enabled in standby mode
Step down 1 is disabled in standby mode
Step down 1 is enabled in standby mode
Step down 2 is disabled in standby mode
Step down 2 is enabled in standby mode
Step down 3 is disabled in standby mode
Step down 3 is enabled in standby mode
Charge pump is disabled in standby mode
Charge pump is enabled in standby mode
0
ldo_rf1_stby_on
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
2
3
4
5
6
7
ldo_rf2_stby_on
ldo_dig1_stby_on
ldo_dig2_stby_on
sd1_stby_on
sd2_stby_on
sd3_stby_on
cp_stbyon
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Table 129. Charger supervision
Fuel Gauge
This bit controls first startup out of power on reset
Addr:14
Bit
Bit Name
Default Access
Description
Switch on Power off mode at first startup(e.g. First
battery insertion or first charger insertion)
Startup of all regulators if battery is inserted,
charger insertion, onkey pressed or rtc alarm.
0
Startup of all regulators only if onkey is
pressed or rtc alarm (no startup on battery
insertion; no startup if charger detectedif
no_charging=0). xon_enable has to be set
bootrom.
Boot
ROM
4
auto_shutdown
R/W
If a charger is detected and the bit
no_charging=0 (defined by ootROM) and
1
ch_pwroff_en=0 the AS368 will start
charging without regulatos statup (fully
autonomous chargg).
If the bit no_chargg=1 nd a charger is
detected, the regulatos are started and the
charging can be enabd with software
corol.
Table 130. Fuel Gauge
FueGuge
Addr:15
Ths bit controls first strtup out of power on reset
Bit
Bit Name
Defalt Access
Description
Swith on Power off mode if low Vsupply is detected
duing active or standby mode (Pin XON= high and bit
xon_enable=0)
Boot
R
If low battery is detected, continuously monitor
5
power_off_at_v_suplow
ROM
0
1
battery voltage and startup if battery voltage is
above ResVoltrise
If low battery is detected, enter power off
mode
10.2.3 Reset Cycle
During a reset cycle the pin XRESET is fed to low for at least RESTIME and all registers are set to their default
values (except the registers markd green in theTable 186 on page 148). During the reset time a normal startup
happens (see Startup on page 29), the reset is active until the reset timer (set by register bits res_timer<2:0>) expires.
Then the voltage on the pin RESET is pulled high by the external resistor and the whole system is leaving the reset
state.
10.2.4 Reset Ctrolres_con
Reset is internally generated from a power supply supervisor and provided to internal logic as well as externally
through the oen-dain pad XRESET. At this point, it could be also forced externally from an external power supply
supervisdditionally Reset can be forced by software.
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10.3 Interrupt Controller
The interrupt controller generates an interrupt request for the host controller as soon as one or more of the bits in the
Interrupt 1…3 register is set by pulling low pin XINT. All the interrupt sources can be enabled in the Interrupt Mask 1…3
register. The Interrupt 1…3 registers are cleared automatically after the host controller has read them. To prevent the
AS3658 device from losing an interrupt event, the register that is read is captured before it is transmitted to the host
controller via the serial interface. As soon as the transmission of the captured value is complete a logical AND
operation with the bit wise inverted captured value is applied to the register to clear all interrupt bits that have already
been transmitted. Clearing the read interrupt bits takes 2 clock cycles, a read access to the same register before the
clearing process has completed will yield a value of ‘0’. Note that an interrupt that has been present at the previous
read access will be cleared as well in case it occurs again before the clearing process has completed.
During a read access to one of the interrupt registers the XINT pin will be released. As soon as the transferred bito
the interrupt register have been cleared the XINT pin will be pulled low in case a new interrupt has occurred in he
meantime. By doing so the interrupt controller will work correctly with host controllers that are edge- and level-sesitive
on their interrupt request input. Multiple byte read access is recommended to avoid reading the Interrupt 1 register
over and over again in response to a new interrupt that has occurred in the same register (and thus pling low pin
XINT) before the Interrupt 2,3 register has been read.
Table 131. Interrupt Status 1 Register
Inerrupt Status1
Addr:50
These bits show the status of the iterrupts
register is t power-on-reset and after each read access
Bit
0
Bit Name
Default Acces
escription
Bit is set whethe fllowing status bits are set or reset:
Trickle, CVM, NoBat
chstate_i
cheoc_i
NA
NA
N
R
R
R
1
Bit is swhen the EOC status bits are set or reset:
Bit is set when charge timeout ( tricke, CV, CC) has
been expired
2
charging_tmax_i
3
4
5
usb_chdet_i
chdet_i
NA
NA
NA
R
R
Bit is set when the USB_ChDet Bit is set or reset.
Bit is set when the ChDet Bit is set or reset.
Bit is set when status XON bit is set or reset.
Onkey_i
Bit is set when the lower temperature threshold
Temp110 of the temperature sensor is exceeded for
6
7
ovtmp_i
Lowsup
NA
NA
R
R
longer than tRESMASK
.
Bit is set when the main supply voltage VSUPPLY has
dropped below VRESFALL for longer than tRESMASK
.
Table 132. Interrupt Status 2 Rgister
Interrupt Status2
Addr51
These bits show the status of the interrupts
register is reset at power-on-reset and after each read access
Bit
Bit Name
Default Access Description
Bit is set when voltage of step down1 drops below low
voltage threshold (1msec debounce timer)
0
sd1_lv_i
NA
NA
R
R
Bit is set when voltage of step down2 drops below low
voltage threshold
2
sd2_lv_i
sd3_lv_i
(1msec debounce timer)
Bit is set when voltage of step down3 drops below low
voltage threshold
NA
R
(1msec debounce timer)
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Table 132. Interrupt Status 2 Register
Interrupt Status2
Addr:51
These bits show the status of the interrupts
register is reset at power-on-reset and after each read access
Bit
Bit Name
Default Access
Description
Bit is set when voltage of LdoDig1 drops below low
voltage threshold
3
dig1_lv_i
NA
R
(1msec debounce timer)
Bit is set when voltage of LdoDig2 drops below low
voltage threshold
4
5
dig2_lv_i
hphcurr_i
NA
NA
R
R
(1msec debounce timer)
Bit is set when output stage of headphone amlifie
exceeds overcurrent limit.
Bit is set when bit bat_hightemp or ba_lowtemp is set
or reset
6
7
bat_temp_i
stpup1_i
NA
NA
R
R
Bit is set when stpup1_oc or stpup_det is set.
Table 133. Interrupt Status 3 Register
nterrupt Status3
Addr:52
Ths show the sttus of the interrupts
register is reet at power-on-reset nd after each read access
Bit
Bit Name
Default Access
Description
Bit is shen voltage of LdoDig3 drops below low
voltage threshold
0
dig3_lv_i
NA
NA
R
R
(1msec debounce timer)
t is set when voltage of LdoDig4 drops below low
voltage threshold
1
dig4_lv_i
(1msec debounce timer)
2
3
4
rtc_alarm_i
rtc_rep_i
NA
NA
NA
R
R
Bit is set by the RTC, if alarm registers=rtc registers
Bit is set by the RTC every second (Bit irq_min=0) or
minute (Bit irq_min=1)
mic_con_i
Bit is set if a microphone is detected on MIC input
Bit is set, if the microphone supply is increased
(remote key press detected) -> measure MICS supply
current
5
mic_rem_i
NA
R
6
7
voxm_i
tpeni
NA
NA
R
R
Bit is set, if voice is detected on MIC input
Bit is set, if the touchpen pendown is detected
Table 134. Interrupt mask Register
Interrupt Mask1
These bits mask the interrupt
Description
Addr47
Bit
Bit Name
Default Access
0
1
0
1
Interrupt is enabled
Interrupt is disabled
Interrupt is enabled
Interrupt is disabled
0
chstate_int_mask
1b
1b
R/W
R/W
1
cheoc_int_mask
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Table 134. Interrupt mask 1 Register
Interrupt Mask1
Addr:47
These bits mask the interrupt
Description
Bit
Bit Name
Default Access
0
1
0
1
0
1
0
1
0
0
1
Interrupt is enabled
2
charging_tmax_int_mask
1b
1b
1b
1b
1b
1b
R/W
R/W
R/W
R/W
R/W
R/W
Interrupt is disabled
Interrupt is enabled
Interrupt is disabled
Interrupt is enabled
Interrupt is disabled
Interrupt is enabled
Interrupt is disabld
Interrupt is enabed
Interrupdisbled
Interrupt is enabled
Interrupt s disabled
3
4
5
6
7
usb_chdet_int_mask
chdet_int_mask
onkey_int_mask
ovtmp_int_mask
LowSup_int_mask
Table 135. Interrupt mask 2 Register
Interupt Mask2
Addr:48
These mask the interrupt
Description
Bit
Bit Name
DfaulAccess
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Interrupt is enabled
0
sd1_lv_int_mask
1b
1b
1b
1b
1b
1b
1b
1b
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
Interrupt is disabled
Interrupt is enabled
Interrupt is disabled
Interrupt is enabled
Interrupt is disabled
Interrupt is enabled
Interrupt is disabled
Interrupt is enabled
Interrupt is disabled
Interrupt is enabled
Interrupt is disabled
Interrupt is enabled
Interrupt is disabled
Interrupt is enabled
Interrupt is disabled
1
2
3
4
5
6
7
sd2_lv_int_mask
sd3_lv_int_mask
dig1_lv_int_mask
dig2_lv_int_msk
hphcrr_in_mask
ba_temp_int_mask
stpup1_int_mask
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Table 136. Interrupt mask 3 Register
Interrupt Mask3
Addr:49
These bits mask the interrupt
Description
Bit
Bit Name
Default Access
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
Interrupt is enabled
0
dig3_lv_int_m
1b
1b
1b
1b
1b
1b
1b
1b
R/W
R/W
R/W
R/W
R/W
R/W
R/W
/W
Interrupt is disabled
Interrupt is enabled
Interrupt is disabled
Interrupt is enabled
Interrupt is disabled
Interrupt is enabled
Interrupt is disabld
Interrupt is enabed
Interrupdisbled
Interrupt is enabled
Interrupt s disabled
Interrupt is enabled
Interrupt is disabled
Interrupt is enabled
Interrupt is disabled
1
2
3
4
5
6
7
dig4_lv_int_m
rtc_alarm_int_m
rtc_rep_int_m
mic_con_int_m
mic_rem_int_m
voxm_intm
tpen_i_m
Table 137. Low voltage status1 Register
Low voltage status1
Addr:53
These bits he low voltage status of the step down and digital
regulators
Bit
0
Bit Name
sd1_lv
sd2_lv
sd3_lv
dig1_v
dig2_lv
-
DefaulAccess
Description
NA
N
NA
NA
NA
-
R
R
R
R
R
-
Step down1 low voltage status bit (-10% voltage drop)
Step down2 low voltage status bit (-10% voltage drop)
Step down3 low voltage status bit (-10% voltage drop)
Ldo Dig1 low voltage status bit (-50mV voltage drop)
Ldo Dig2 low voltage status bit (-50mV voltage drop)
-
1
2
3
4
5
Bit is set by analog part, if overcurrent of DCDC
StepUp1 occurs for more than 5msec (latched state)
6
7
stpp1_oc
stpup1_det
NA
NA
R
R
Current Detection signal of step up 1
Table 13ow voltage status2 Register1
Low voltage status2
Addr:54
These bits show the low voltage status of the step down and digital
regulators
Bit
0
Bit Name
dig3_lv
Default Access
Description
0b
0b
R
R
Ldo Dig3 low voltage status bit (-50mV voltage drop)
Ldo Dig4 low voltage status bit (-50mV voltage drop)
1
dig4_lv
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Table 138. Low voltage status2 Register1
Low voltage status2
Addr:54
These bits show the low voltage status of the step down and digital
regulators
Bit
2
Bit Name
Default Access
Description
dcdc_curr1_lv
dcdc_curr2_lv
dcdc_curr3_lv
bat_lowtemp
bat_hightemp
0b
0b
0b
0b
0b
R
R
R
R
R
Indicates low voltage on dcdc_curr1
3
Indicates low voltage on dcdc_curr2
4
Indicates low voltage on dcdc_curr3
5
Indicates NTC temperature of battery below 0º
Indicates NTC temperature of batter above 45º (50º
6
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10.4 Startup
Figure 56. Startup flow chart
Power on reset
xon_enable=0
batsw_on=0
batsw_mode=0
Reset registers
except
xon_enable
xon_enable=1 and
(chdet=0 or
USBChdet=0)
YES
NO
XON pin pulled
to GND
NO
YES
NO
YES
VBAT>VResVolt
?
Switch on
Battery switch
NO
batsw_on=1
batsw_mode=1
Charger
detected ?
YES
YES
ChEn=1
NO
NO
USB Sup.
detected and
ChDet=0?
S
USB_ChEn=1
VSUPPLY>sVolt
?
YES
Startup Device
Astate
batsw_mode
batsw_on
trickle
0
1
1
1
0
batsw_on=0
batsw_mode=0
Switch on
Switch off
X
power_off=1
NO
YES
YES
YES
NO
batsw_on=0
batsw_mode=0
VSUPPLY<VResVolt
?
NO
force_reset=1
10.4.1 Normal Startup
During a normareset cycle (e.g. after the battery or a charger is inserted; (see Reset generator and XON-Key on page
118)), aV2_5 is above VPOR and Vsupply is above VRESETRISE a normal startup happens:
ꢀ
ꢀ
ꢀ
The external capacitor on CREF is charged to 1.8V
Th3bit A/D conversion is performed to measure the external resistor value RPROGRAM
Startup State machine reads out the internal Boot-ROM (address defined by boot_ctrl), Start sequence of Step-
Down Converter and LDO’s controlled by the Boot-ROM
ꢀ
ꢀ
Reset-Timer is set by the Boot-ROM
The reset is released when the Reset Timer expires (external pin XRESET)
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10.4.2 Startup from Charger
If the voltage on pin VCHARGER is within VSTARTCHARGER, the AS3658 is started (even with VBAT = 0V). This
allows the battery to be charged (even from deeply discharged batteries) and finally a normal startup to happen.
Table 139. Charger Startup Conditions
Symbol
Parameter
Min
Typ
Max
unit
Note
Voltage on
VCHARGER for
system to start
VSTARTCHARGER
4.0
5.0
15
V
on Pin VCHARGER
10.4.3 Programmable Startup Sequences—Boot ROM
The startup- and reset sequences of the device are highly configurable. The configuration of these sequences is
defined by the ratio of the internal trimmed bias resistors and RPROGRAM. At the beginning of each reset cycle a 3 bt
AD-conversion is performed. The result of this conversion is used to select 1 of 8 possible address-ranges of an
internal mask-programmable ROM. The information that is stored in this ROM defines the following prameters:
ꢀ
ꢀ
ꢀ
ꢀ
Voltage levels for all regulators and step down dcdc converters
power-on sequence of RF_1, RF_2, DIG_1, DIG_2, SD1, SD2 and SD3
duration of the reset cycle
several other configuration bits (e.g. charger)
The following values of RPROGRAM are used to select the ssible address ranges (8 different startup voltage /
sequences settings can be used):
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
000: open
001: 320kΩ
010: 160kΩ
011: 80kΩ
100: 40kΩ
101: 20kΩ
110: 10kΩ
111: 0Ω
Table 140. Boot ROM Bits definitions
Boot_status
These bits show the boot status
Default Access Description
Addr:107
Bit
2:0
3
Bit Name
rom_adr
NA
1
R
R
Boot-ROM address
rom_vaid
If ‘1’ Boot-ROM address is valid
Note: For detaied statup sequences see austriamicrosystems AG document AS3658_BootROM_*.
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10.4.4 Additional Startup Settings
Table 141. Boot ROM Bits definitions
LDO_RF2_Voltage
These bits defines the startup sequence
Addr:4
Bit
Bit Name
Default Access
Description
0
1
Normal reset pulse
Apply double reset pulse after the normal rest
pulse that is define by res_timer. (pulse on
XRESET with 2msec high time and 2msec
low time
double_reset
ROM
ROM
R/W
R/W
7
Normal startup of LDOs defined in boot rom
with a separation of 1 milliseconds
0
1
slow_startup
6
Startup of all LDOs defined by boot rom with a
time separation of 4 millseconds
10.4.5 Programmable Startup Sequences with fuse registers—Boot OTP
Its possible to program some startup registers, by using the fuse block
Table 142. ROMF Bit definitions
FUS4
Addr:196
These bitcontrol the startup anare set by factory test
Bit
Bit Name
Default Access
Description
0
1
Fusible startup rom disabled
7
romf_en
0
R
Feasible startup of rom enabled
(UniqueID0.UniqueID10) used for startup
Table 143. ROMF Bit definitions
addrf0
Addr:197
These bits control the startup and are set by factory test
Bit
Bit Name
Default Access
Description
Each bit represents a register address of the bootrom
table (0....31)
Use data of ROM table during startup for the
0
7:0
addrf<7:0>
0
R
according address (0....31)
Use data of fuse register during startup for the
according address, starting with data of
register romf0 (up to register romf6 max.)
1
Table 144. ROMBit dfinitions
addrf0
Addr:198
These bits control the startup and are set by factory test
Bit
Bit Name
Default Access
Description
Each bit represents a register address of the bootrom
table (0....31)
Use data of ROM table during startup for the
0
7:0
addrf<15:8>
0
R
according address (0....31)
Use data of fuse register during startup for the
according address, starting with data of
register romf0 (up to register romf6 max.)
1
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Table 145. ROMF Bit definitions
addrf2
These bits control the startup and are set by factory test
Addr:199
Bit
Bit Name
Default Access
Description
Each bit represents a register address of the bootrom
table (0....31)
Use data of ROM table during startup for the
0
7:0
addrf<23:16>
0
R
according address (0....31)
Use data of fuse register during startup for the
according address, starting with data of
register romf0 (up to register romf6 max.)
1
Table 146. ROMF Bit definitions
addrf3
Addr:200
These bits control the startup and are set by fatory test
Bit
Bit Name
Default Access
Descripion
ach it epresents a register adress of the bootrom
table (0....31)
Use data of ROM table during startup for the
0
7:0
addrf<31:24>
0
R
cording address (0....31)
Use data of fuse register during startup for the
acordig address, starting with data of
regier romf0 (up to register romf6 max.)
1
Table 147. ROMF Bit definitions
romf0
Addr:201
These bits cntrol the startup and are set by factory test
Bit
Bit Name
Default Ac
00h
Description
Data for startup register (used for the first “1” in the
addrf<31:0> register
7:0
romf0
R
Table 148. ROMF Bit definitions
romf1
Addr:202
These bits control the startup and are set by factory test
Bit
Bit Name
Default Access
Description
Data for startup register (used for the second “1” in the
addrf<31:0> register
7:0
romf1
00h
R
Table 149. ROMF it denitions
romf2
Adr:203
These bits control the startup and are set by factory test
Bit
Bit Name
Default Access
00h
Description
Data for startup register (used for the third “1” in the
addrf<31:0> register
70
romf2
R
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Table 150. ROMF Bit definitions
romf3
These bits control the startup and are set by factory test
Addr:204
Bit
Bit Name
Default Access
00h
Description
Data for startup register (used for the fourth “1” in the
addrf<31:0> register
7:0
romf3
R
Table 151. ROMF Bit definitions
romf4
Addr:205
These bits control the startup and are set by factory test
Bit
Bit Name
Default Access
00h
Description
Data for startup register (used for the fifth “1” in he
addrf<31:0> register
7:0
romf4
R
Table 152. ROMF Bit definitions
romf5
Addr:206
These bits cotrol thstartup and are set by factory test
Bit
Bit Name
Default Acc
00h
Description
Data for startup reister (used for the sixth “1” in the
addr31:0> register
7:0
romf5
R
Table 153. ROMF Bit definitions
omf6
Addr:207
These bits control he startup and are set by factory test
Bit
Bit Name
Default Access
00h
Description
Data for startup register (used for the seventh “1” in
the addrf<31:0> register
7:0
romf6
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10.5 Protection Functions
All LDO’s, the DCDC step ups and DCDC step downs have an integrated overcurrent protection. An overtemperature
protection of the chip is also integrated which can be switched on with the serial interface signal temp_pmc_on
(enabled by default; it is not recommended to disable the overtemperture protection). The chip has two signals for the
serial interface: ov_temp_110 and ov_temp_140. The flag ov_temp_110 is automatically reset if the overtemperature
condition is removed, whereas ov_temp_140 has to be reset by the serial interface with the signal rst_ov_temp_140.
If the flag ov_temp_140 is set, an automatic reset of the complete chip is initiated. The flag ov_temp_140 is not
affected by this reset cycle allowing the software to detect the reason for this unexpected shutdown.
Table 154. Overtemperature Detection
Symbol
Parameter
Min
Typ
Max
Unit
Note
ov_temp_110 rising
threshold
T110
95
110
125
ºC
ov_temp_140 rising
threshold
T140
125
140
5
155
ºC
ºC
ov_temp_110 and
ov_temp_140
hysteresis
Thyst
Table 155. Overtermperature detection Bit definition
Overtemperare Control
These bits control the startup anare set by factory test
Addr:106
Bit
Bit Name
Default Access
Description
Switch off of temperature supervision; default: on
ll her bits are only valid if set to ‘1’
Leave at 1, do not disable
0
temp_pmc_on
1
R/W
R
Flg that the overtemperature threshold 1 (T110) has
been reached
1
2
ov_temp_110
ov_temp_140
NA
Flag that the overtemperature threshold 2 (T140) has
been reached – this flag is not reset by a
overtemperature caused reset and has to be reset by
rst_ov_temp_140
NA
0
R
If the overtemperature threshold 2 has been reached,
the flag ov_temp_140 is set and a reset cycle is
started. ov_temp_140 should be reset by writing 1 and
afterward 0 to rst_ov_temp_140
3
rst_ov_temp_140
W
10.5.1 Temperature Supervison
A temperature sensor is impemeted to provide over-temperature protection of the chip. It generates two flags linked
to the two temperature theshods (110 degrees, 140 degrees). Both thresholds have an hysteresis to prevent
oscillation effects.
First threshold (110 egrees) sets the flag ov_temp_110, signalling the serial interface part and software the 110
degrees overtmperature condition. If enabled (ovtmp_int_mask=0), an interrupt can be send (interrupt ‘ovtmp’). Thus
software can ract and can shutdown power consuming functions to decrease temperature.
Thsecd threshold (140 degrees) initiates a reset cycle and sets ov_temp_140: this sets all regulators into power-
down mode and stops charging, and performs the reset cycle of the AS3658.
rst_ov_temp_140 flag
In case of overtemperature and an activated reset (temp_pmc_on=1), the system loses any information about the error
which activated the reset state. Therefore, a flag is implemented, which indicates that the reset was caused by
overtemperature activation (ov_temp_140 is set). This flag is only resetable by writing ‘1’ to rst_ovtemp_140.
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10.6 Watchdog
The purpose of the watchdog is to detect a deadlock of the software. If the watchdog is active, it must receive a
continuous trigger signal within a programmable time window. If there is no signal anymore for a certain time period
from a defined pad or special serial interface bit, it starts either a complete reset cycle or changes the state of an output
pin, which can be used e.g. as an interrupt to the processor.
ꢀ
ꢀ
ꢀ
ꢀ
The watchdog is highly configurable by the following register bits:
The complete block can be switched on by wtdg_on = 1 and off by wtdg_on = 0.
The watchdog time window is defined by the register wtdg_min_timer and wtdg_max_timer.
The trigger signal can be configured by register wtdg_trigger and wtdg_gpio_input. (Pin CURR1-CURR4 (GPIO1-
GPIO4) or register bit)
ꢀ
ꢀ
If the watchdog expires, the system can start automatically a reset cycle if wtdg_reset_on = 1
Any of the general purpose input / outputs can be configured to output the watchdog signal. The Watchdog dlivers
a signal “wtdg_alarm”, which is normal ‘0’ and goes to ‘1’ in the case of a timer-overflow. This signal can be usd as
e.g. a reset or interrupt for a processor.
Table 156. Watchdog Register definitions
Wchdog control
Addr:60
These bits control the watchdog fnctions
Bit
Bit Name
Default Acce
Description
Switcheon the complete watchdog
watchdog off
0
wtdg_on
0
R/W
R/W
0
1
watchdog enabled
If the watchdog expires and wtdg_res_on = 1 a reset
1
2
wtdg_res_on
wtdg_trigger
cycle will be started
Use the register bit wtdg_sw_signal as trigger
0
signal for the watchdog
Use one of the GPIO pins CURR1_GPIO1 …
CURR4_GPIO4 as trigger input for the
0
R/W
watchdog; the actual pin is selected by setting
1
GPIOXIOSF to 01b(watchdog mode) and
GPIOXMode=010b (GPIO digital input)
(X=1...4)
Table 157. Watchdog minimum timer deions
Watchdog_min timer
Addr:61
These bits set the watchdog minimum timer
Bit
Bit ame
Default Access
00h R/W
Description
Defines the minimum watchdog trigger time
(LSB=7.5ms, range: 0 – 1.9s)
7:0
tdg_in_timer
Table 158. Wtchog max timer definitions
Watchdog_max timer
Addr:62
These bits set the watchdog maximum timer
Bit
Bit Name
Default Access
FFh R/W
Description
Defines the maximum watchdog trigger time
(LSB=7.5ms, range: 7.5ms – 1.9s), do not set to (00)h
7:0
Wtdg_max_timer
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Table 159. Watchdog software signal definitions
Watchdog software signal
This bit sets the watchdog software trigger
Addr:63
Bit
Bit Name
wtdg_sw_signal
Default Access
R/W
Description
0
0
Trigger input by the serial interface if wtdg_trigger = 0
Figure 57. Watchdog timing diagram
tmin
tmax
wtdg_trigger
tmin
tmax
10.7 General Purpose 10 Bit ADC
Table 160. ADC Characteristics
Symbol
Parameter
Min
Ty
ax
Unit
Note
Resolution
10
Bit
Input Voltage
Range
Vin
DNL
INL
0
1.8
V
Differential
Nonlinearity
1LSB 1.76mV (depending on
selected channel)
± 0.25
± 0.5
LSB
LSB
LSB
Integral
Nonlinearity
Input Offset
Voltage
Vos
Input Impedance
Input Capacitance
Rin
Cin
10
MΩ
9
pF
Power Supply
Current
Idd
Idd
500
100
µA
nA
During conversion only
Power Down
Current
Transient Parameters (25°C
Conversion Time
Tc
40
µs
internal CLK frequency/8
Programmable:
fclk_int
8
/
Clock Frequency
fc
kHz
0.2 to 0.2875 MHz
Settling timof
S&H
ts
1
µs
DC_Ipll up
current
Pull up current for ADC_IN1, if
adc_idc=1111b
14.25
15
15.75
µA
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Table 161. ADC control Registers bits
ADC_control
This register controls the 10 Bit ADC
Addr:96
Bit
Bit Name
Default Access
Description
Selects an ADC channel
ADC1_IN (LSB = 1.76mV)
ADC2_IN (LSB = 1.76mV)
VBAT Battery voltage (LSB=5.27mV)
0000
0001
0010
0011 VCHARGER (LSB=17. 6mV) clamping at 0
0100
0101
V_USB Voltage (LSB=5.27mV)
not used
3:0
adc_select
0000b
R/W
temperature sensr:
DIE temperature [°C] = ad_reslt * 0.866 –
274
0110
0111
100
01
ADC test chael – o not use
heck voltage on MICS for remote control or
external voltage asrement (LSB=3.52mV)
VCK voltage (LSB=3.52mV)
seleADampling frequency
275kHz (conversion time: 60µs)
70kHz (conversion time: 240µs)
reserved (do not use)
4
5
adc_slow
-
0b
-
R/W
-
0
1
Wring a 1 into this bit continuously activates the ADC
S/H and the input multiplexer. The ADC and the MUX
are also activated for a conversion period when
start_conversion is set to ‘1’ – useful for high
6
7
adc_on
0b
0b
R/W
R/W
impedance input sources on ADC1_IN or ADC2_IN
start_conversion
Writing a 1 into this bit starts one ADC conversion.
Table 162. ADC MSB result register
ADC_MSB result
Addr:97
This register shows the MSB result of the ADC conversion
Bit
0
Bit Name
D3
Default Access
Description
ADC result register
ADC result register
ADC result register
ADC result register
ADC result register
ADC result register
ADC result register
Indicates end of conversion
result is ready
NA
NA
NA
NA
NA
NA
NA
R
R
R
R
R
R
R
1
4
2
D5
3
D6
4
D7
5
D8
6
D9
7
result_not_ready
NA
R
0
1
conversion is running
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Table 163. ADC LSB result register
ADC_LSB result
This register shows the LSB result of the ADC conversion
Addr:98
Bit
0
Bit Name
Default Access
Description
D0
D1
D2
-
NA
NA
NA
-
R
R
R
-
ADC result register
ADC result register
ADC result register
reserved (do not use)
1
2
7:3
Table 164. ADC IDAC register
ADC idac
This register controls the current sink on pin ADC_IN1
Addr:46
Bit
Bit Name
Default Access
Description
Current source at AC_I1 input
Set to 0000 if battery mperture supervision
is enaed.
000
001
...
0µA (crrnt ink disabled)
1µA
0
adc_idac
000b
R/
1111
15 µA
Figure 58. ADC Timing-diagram
start_conversion=1
I2C Bus
1
2
12
13
275kHz
Sample
ADC_ON
start_adc
result_not ready
D<9:0>
old_Data
Data not valid
Data ready
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10.8 Internal References (V, I, fclk)
The internal reference circuits needs the following external components:
Table 165. Reference External Components
Symbol
Parameter
Min
Typ
Max
Unit
Note
Ceramic low-ESR capacitor
between CREF and VSS
CEXT
External filter capacitor -10%
100
+10%
nF
External bias current
-1%
Bias Current set resistor between
RBIAS and VSS
RBIAS
220
+1%
kΩ
set resistor
Table 166. References Parameters
Symbol
Parameter
Min
Typ
Max
Unit
Note
Low noise trimmed voltag
reference – connected to Pad
CREF; do nt load
VCEXT
Reference Voltage
-1%
1.8
+1%
V
Accuracy of Internal
reference clock
Adjustable by srial iterface
regisr clkint
fCLK
-10
fCLK
+10
%
To reduce the current consumption of the chip, the circuit can be set into a special low power mode with the serial
interface bit ‘low_power_on’. All specification parameters except te noise parameters are sl valid for this mode.
Table 167. Internal references Bit definitions
Internal referenceBit definitions
Addr:59
These bits control the internareference mode and internal clk
requency
Bit
Bit Name
DfaulAccess
Description
0
1
Standard mode
0
low_power_on
0b
R/W
Low power mode – all specification except
noise parameters are still valid
Sets the internal CLK frequency fCLK used for fuel
gauge, DCDCs, PWM, charge pump.
All frequencies, timings and delays in this datasheet
are based on 2.2MHz clk_int
000b
001b
010b
011b
100b
101b
110b
111b
1.6 MHz
1.7 MHz
1.8 MHz
3:1
clk_int
110b
R/W
1.9 MHz
2.0 MHz
2.1 MHz
2.2 MHz (default)
2.3 MHz
108.1 w Power Mode
Usbit low_power_on (reg. References Control (see Table 167)) to activate the Low Power Mode. In this mode the
on-chvoltage reference and the temperature supervision comparators are operating in pulsed mode. This reduces
the quiescent current of the AS3658 by 45uA (typ.). Because of the pulsed function some specifications are not fulfilled
in this mode (e.g. increased noise), but still the full functionality is available.
Note: Low power mode can be controlled by the serial interface.
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10.9 Real-Time Clock (RTC) Module
The RTC module provides time information to the system. It is implemented as a 6-bit counter that is incremented
every second - with the 32kHz oscillator delivering the necessary accurate time base – and is reset to 0 each time the
counter value is 60. An additional 24-bit minute counter is incriminated each time the 6-bit counter is reset to 0. Both
counters are set to 0 at a power-on-reset. The host controller can set the counter to any value by setting the RTC 1…4
registers.
To prevent ambiguous time information because of the 30-bit value being incremented before all of the 4 registers
have been read or written, a 30-bit parallel shadow register is implemented. Every time a write/read access via the
serial interface occurs the parallel shadow register is updated with the current value of the 30-bit counter. Any write
access to the RTC 1 register will disable the update of the parallel register and set the value of the appropriate byte of
the parallel register. Any subsequent write access to the RTC 4 register will transfer the current value of the 30-bi
parallel register to the RTC 1…4 registers and the update of the parallel register is enabled again. Similarly, any rea
access to the RTC 1 register will freeze the current value of the parallel register and submit the appropriate byte o the
host controller via the serial interface. Any subsequent read access to the RTC 4 register will enable the update f the
parallel register again. This mechanism makes sure that the maximum error of the value that is written o or read from
the registers is 1 second.
The startup state after power on reset:RTCSecond=3F, RTCMinute1=FF, RTCMinute2=FF, RTCMiute3=FF
To start the RTC, rtc_mode bits have to be set to a non zero vale, anhe RTC registers have o be set.
The RTC stops automatically at its highest value (3F,FF,FF,FF) tpreveoverrun.
Table 168. RTC Second Register
RTCSecod
Addr:64
These bits represents te actal RTC second register
register is reset at power-on-reset only
Bit
5:0
7:6
Bit Name
RTCSecond
-
Defalt Access
Description
0h
-
R/W
Bits 5:0 of the 6-bit RTC second counter
reserved
Table 169. RTC Minute1 Register
RTCMinute1
Addr:65
Tese bits represents the actual RTC Minute1 register
register is reset at power-on-reset only
Bit
Bit Name
efault Access
00h R/W
Description
7:0
RTCMinute1
Bits 7…0 of the 24-bit RTC minute counter
Table 170. RTC Minute2 Regiter
RTCMinute2
Addr:66
These bits represents the actual RTC Minute2 register
register is reset at power-on-reset only
Bit
it Name
Default Access
00h R/W
Description
7:0
RTCMinute2
Bits 15:8 of the 24-bit RTC minute counter
Tble 17RTC Minute3 Register
RTCMinute3
Addr:67
These bits represents the actual RTC Minute3 register
register is reset at power-on-reset only
Bit
Bit Name
Default Access
Description
7:0
RTCMinute3
00h
R/W
Bits 23:16 of the 24-bit RTC minute counter
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The RTC module includes an alarm function. When the content of the RTC 1…4 registers equals the content of the
RTC Alarm 1…4 registers bit RTCAlarm will be set in the Interrupt 1 register. Furthermore the RTC module can
generate an interrupt every second (RTC1Sec will be set) and every minute (RTC1min will be set every time the 6-bit
second counter is reset to 0). For further details on interrupt generation please refer to Interrupt Controller on page
124.
To avoid ambiguous behavior during write access to the RTC Alarm 1…4 registers any write access to the RTC Alarm
1 register will disable the alarm function; any subsequent write access to the RTC Alarm 4 will enable the alarm
function again.
Table 172. RTC Alarm second Register
RTC AlarmSecond
Addr:68
These bits set the RTC Alarm Seconds
register is reset at power-on-reset only
Bit
Bit Name
Default Access
3Fh R/W
Description
5:0
RTCAlarmSecond
Bits 5…0 of 6-bit RTC seconalam value
Table 173. RTC Alarm minute1 Register
RTAlarmMinute1
Addr:69
These its set the RTC Alarm Mnute1
ter is reset at power-on-reset only
Bit
Bit Name
Default Acces
escription
7:0
RTCAlarmMinute1
FFh
Bits 7:0 the 4-bit RTC minute alarm value
Table 174. RTC Alarm minute2 Register
RTC AlarmMinute2
Addr:70
These its set the RTC Alarm Minute2
regiter is reset at power-on-reset only
Bit
Bit Name
Default Ac
FFh
Description
7:0
RTCAlarmMinute2
Bits 15:8 of the 24-bit RTC minute alarm value
Table 175. RTC Alarm minute3Register
RTC AlarmMinute3
Addr:71
These bits set the RTC Alarm Minute3
register is reset at power-on-reset only
Bit
Bit Name
Default Access
Description
7:0
RTCAlarmMnute3
FFh
Bits 23:16 of the 24-bit RTC minute alarm value
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Table 176. RTCT Register
RTCT
Addr:72
These bits set the RTC correction and RTC interrupt mode
register is reset at power-on-reset only
Bit
Bit Name
Default Access
Description
These bits are used to correct the inaccuracy of the
used 32kHz crystal. Correction is done all 8 seconds
by removing or adding two clock cycles.
Trimming register for RTC, 128 steps @ 7.6ppm
100000
100001
- 480.4ppm
-472.8ppm
6:0
RTC_TBC<6:0>
0000000
R/W
111111
000000
000001
-7.6ppm
0ppm(defalt)
7.6pp
01110
011111
0
4728ppm
480.4ppm
generae an interrupt every second
geneate an interrupt every minute
he interrupt has to be enabled by
rtc_rep_int_m=0
7
rtc_irq_mode
0
R/W
1
Table 177. Reset Timer Register
Reset Timer
Addr:22
These bits set RTC modes
Description
Bit
Bit Name
Default Ac
Disables RTC alarm wakeup in power off
0
1
0
mode
4
rtc_alarm_wakeup_en
ROM
ROM
R/W
R/W
Enable RTC alarm wakeup in power off mode
Disables RTC repeated wakeup in power off
mode
5
rtc_rep_wakeup_n
rt_mode
Enable RTC repeated wakeup in power off
mode
1
00
01
10
11
32kHz oscillator off
32kHz oscillator enabled
7:6
ROM
R/W
32kHz oscillator enabled, Pin Q32k enabled
reserved (do not use)
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10.10 Touchpen Interface
The touchpen interface controls a resistive touchpen. It has the following features:
ꢀ
ꢀ
ꢀ
ꢀ
Low Power Pen Detect
Measure pen X,Y position
Measure pen pressure (Z-position)
Interrupt, if X,Y,Z data is available; one dedicated output – CURR4_GPIO4 can be configured to be used as
touchpen interrupt output and/or standard interrupt output XINT
ꢀ
ꢀ
ꢀ
ꢀ
The conversion interval can be adjusted
Up to 16 ADC conversion can be averaged internally
The sample time of the ADC can be adjusted
The pin CURR3_GPIO3 can be configured to enable/disable the ADC conversion (useful if the processor udat
the LCD to avoid parallel reading of the touchpen position)
The touchpen interface shares the pins with the SPDIF output and the I2S Output 3. If the touchpen iterface is used,
the SPDIF and the I2S Output 3 cannot be used (and has to be disabled).
Note: The touchpen interface and the ‘General Purpose 10 Bit ADC’ can be used at the same tie.
Figure 59. Touchpen Block diagram
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The touchpen controller is operating according to the following state diagram:
Figure 60. Touchpen State diagram
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10.10.1 Software guidelines
1. Setup the configuratioregisters (tpen – control 1..3) according the hardware
2. Enable receivng of ouchpen interrupts (either through XINT or GPIO4_CURR4)
3. Upon receiving a touchpen interrupt, readout tpen_xmsb, tpen_ymsb (and if required tpen_pressmsb and
tpen_xypresslsb) wth a single I2C blockread. This ensured, that the x,y,z is correctly readout and all data belong
to one singe tochpen x,y,z conversion
4. Perfoall the required processing with the data (e.g. accept a pen-down only if the pen is forced onto the
touchren with a minimum pressure [z-position])
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Data Sheet Confidential - Detailed Description - System Functions
10.10.2 Touchpen Registers
Table 178. Touchpen Register Map
Register
Addr Default
Definition
Content
Name
b6
b5
XD7
YD7
PD7
0
b4
b3
b2
XD4
YD4
PD4
0
b1
b0
tpen_xmsb
108
109
110
111
NA
NA
NA
NA
XD9
YD9
PD9
PD1
XD8
YD8
PD8
PD0
XD6
YD6
PD6
YD1
XD5
YD5
PD5
YD0
XD3
YD3
PD3
XD1
XD2
YD2
PD2
XD0
tpen_ymsb
tpen_pressmsb
tpen_xypresslsb
tpen_st_ tpen_eo
pen
tpen – control 1
tpen – control 2
tpen – control 3
112
113
114
00h
00h
00h
tpen_avg
tpen_soc
tpen_convint
tpen_pu
tpn_
c
tpen_so tpen_wa tpen_curr
cpd
it
press
tpen_timeo tpen_deb
ut _en ounce
tpen_sample
Note: The cells marked in color are Read only
Table 179. Touchpannel Result Register Bits
Touchpad_XMB result
X-MSB rsuregister
Addr:108
Bit
Bit Name
Defalt
Access
Description
X – MSB Data
7:0
tpen_xmsb
0000000
R
Table 180. Touchpannel Result Register its
Touchpad_YMSB result
Y-MSB result register
Description
Y – MSB Data
Addr:109
Bit
Bit Name
Defaut
Access
7:0
tpen_ymsb
0000000
R
Table 181. Touchpannel Result Register Bits
Touchpad_Pressure result
Pressure result register
Description
Pressure - Data
Addr:110
Bit
Bit Name
Default
Access
7:0
tpen_essmsb
00000000
R
Table 182. TouchnneResult Register Bits
Touchpad_XY - LSB result
X - MSB result register
Description
Adr:111
Bit
1:0
4:3
7:6
Bit Name
tpen_xlsb
Default
00
Access
R
R
R
X – LSB Data
Y – LSB Data
tpen_ylsb
00
tpen_presslsb
00
Pressure – LSB Data
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Table 183. Touchpannel Control Register Bits
Touchpad – control 1
This register controls the different modes of the Touchpad
Addr:112
Bit
Bit Name
Default
Access
Description
Enables Touch Pen Function
OFF (No wakeup on pen down)
0
1
0
tpen_on
0
R/W
Pen Detect enabled ꢁwakes up Pen
Digitizer ꢁCheck Pen_Status -> if pen-
detect or tpen_soc_pd=1 and tpen_soc=1
then perform X,Y,Z measurements
Conversion Interval Timer
00
01
No delay between conversions
every 512 clock periods (,5 ms) ADC –
Averaging limiteto ax. 4
2:1
tpen_convint
00
R/W
every 1024 clock peiods 1ms) ADC –
Averaging imiteto max. 8
10
11
every 10240 clocperiods (10ms)
Start Conversion (x,y, nd z conversion)
No nversion if pen down detected
0
1
3
tpen_soc
tpen_avg
0
0
R
R/W
StarConversion if pen down detected or
ten_sc_pd=1 and tpen_on=1 (X, Y and
Z-Pressure Measurement)
Averaging of x and y measurement
no averaging
0
01
10
11
5:4
4 measurements (per channel)
8 measurements (per channel)
16 measurements (per channel)
ADC - End of Conversion bit
TP in Power down or Conversion ongoing
0
1
6
7
tpen_eoc
0
0
R/W
Valid TP data available (x,y, and pressure)
generates an interrupt on GPIO4_CURR4
and/or XINT; the interrupt is released when
the readout from the tpen_xmsb is started
Pen status
penup
tpen_st_en
R
0
1
pendown
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Revision 1v13
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AS3658
Data Sheet Confidential - Detailed Description - System Functions
Table 184. Touchpannel Control Register Bits
Touchpad – control 2
This register controls the different modes of the Touchpad
Addr:113
Bit
Bit Name
Default
Access
Description
Internal Resistor used for Pen detection
00000
Do not use this Setting
00001
00010
...
4kΩ
8kΩ
00100
...
16kΩ
32kΩ
4:0
tpen_pu
00000
R/W
01000
...
0000
...
64kΩ (st sesitive)
~ 2kΩ
11111
Current ud for pressure measurement
5
6
7
tpen_currpress
tpen_wait
0
0
0
R/
R/W
0
1
0
200µA
400µA
Do not wait until tpen_xmsb is readout
Start next ADC – conversion after data is
read from Register tpen_xmsb
1
0
1
Start conversion only if tpen_st_pen is 1
and tpen_soc=1 and tpen_on=1
tpen_soc_pd
Measure regardless of pen Status (only if
tpen_soc=1 and tpen_on=1)
Table 185. Touchpannel Control Register Bts
Touchpad – control 3
This register controls the different modes of the Touchpad
Addr:114
Bit
Bit Name
Default
Access
Description
Sample Time of ADC
0
1
2
3
0
1
3µs
0:1
pe_sample
00
R/W
10µs
50µs
200µs
Pen-down Debounce Time 100µs
Pen-down Debounce Time = 3ms
2
3
tpen_debounce
0
0
R/W
R/W
Enables Timeout Signal (ADC conversion is
stopped during tiemeout = 1)
tpen_timeout _en
0
off
GPIO3_CURR3 can be configured as input
for the timeout signal – see block diagram
1
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Data Sheet Confidential - Register map
11 Register map
Table 186. Register Map
Register
Definition
Content
Name
b7
b6
b5
b4
b3
b2
b1
b0
Step Down
Voltage1
sd1_clki sd1_freq
0
1
2
3
4
5
6
7
8
9
0h ROM
1h ROM
2h ROM
3h ROM
4h ROM
5h ROM
6h ROM
7h ROM
8h ROM
9h ROM
step_down1_v
step_down2_v
step_down3_v
nv
u
Step Down
Voltage2
sd2_clki sd2_freq
nv
u
Step Down
Voltage3
sd3_clki sd3_freq
nv
u
LDO_RF1
Voltage
rf1_swpr rf1_lcurr
ot_en _en
ldo_rf1_v
LDO_RF2
Voltage
double_r slow_sta rf2_lcurr
eset rtup _en
ldo_rf2_v
ldo__v
LDO_RF3
Voltage
rf3_hotpl rf3_lcurr
ug_en
_en
LDO_DIG1
Voltage
ldo_di1_v
LDO_DIG2
Voltage
ldo_dig2_v
ldo_dig3_v
ldo_dig4_v
LDO_DIG3
Voltage
LDO_DIG4
Voltage
dis_bats
w_tmp
_pro
USB Charger
Control
ext_bas No_char
usb_chg
En
10 Ah ROM
usb_Current
en
ging
Auto
Resume
Charger
Control1
Isolate_b ch_det_ ging usb_hol
CHOVD Ch_pwr
11 Bh ROM
12 Ch ROM
ChEn
at
500ms
_tmax d_chdet
etEn
off_en
Battery voltage
monitor
FastRes SupRes
ResVoltFall
ResVoltRise
ChVoltEOC
En
En
Charger Config 13 Dh ROM
Charger
CholtResume
Vsupply_min
ntc_high auto_sh
14 Eh ROM ntc_e ntc_hyst
ch_timeout
supervision
_temp
utdown
power_o
ff_at_vs
uplow
FuelGauge
15 Fh RM
ntc_on
CalMod
CalReq UpdReq FGEn
Charger
Current
16 10h ROM
17 11h ROM
18 12h ROM
19 13h ROM
20 14h ROM
21 15h ROM
ch_voltage
sdx_1A_mode
ConstantCurrent
sd1_dvm_time
TrickleCurrent
Charge Pump
Control
cp_puls
eskip
cp_freq
gpio1_in
vert
GP
GPIO 2
GPIO 3
GPIO 4
gpio1_pulls
gpio2_pulls
gpio3_pulls
gpio4_pulls
gpio1_iosf
gpio2_iosf
gpio3_iosf
gpio4_iosf
gpio1_mode
gpio2_mode
gpio3_mode
gpio4_mode
gpio2_in
vert
gpio3_in
vert
gpio4_in
vert
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Revision 1v13
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AS3658
Data Sheet Confidential - Register map
Table 186. Register Map
Register
Definition
Content
Name
b7
b6
b5
b4
b3
b2
b1
b0
rtc_rep_ rtc_alar
wakeup m_wake
xon_ena
ble
Reset Timer
22 16h ROM
rtc_mode
res_timer
_en
up_en
Reg Power1
ldo_dig2 ldo_dig1 ldo_rf2_ ldo_rf1_
23 17h ROM cp_on
cp_on
sd3_on sd2_on sd1_on
Ctrl @ 6 msec
_on
_on
on
on
ldo_dig2 ldo_dig1 ldo_rf2_ ldo_rf1_
sd3_on sd2_on sd1_on
Reg Power1
Ctrl @ 7 msec
_on
@ 7
msec
_on
@ 7
msec
on
@ 7
msec
on
@ 7
se
24 18h ROM
25 19h ROM
26 1Ah ROM
27 1Bh ROM
28 1Ch ROM
@ 7
@ 7
msec
@ 7
msec
@ 7
msec
msec
ldo_dig2 ldo_dig1 ldo_rf2_ ldorf1_
cp_on
@ 8
msec
sd3_on sd2_on sd1_on
Reg Power1
Ctrl @ 8 msec
_on
@ 8
msec
_on
@ 8
msec
on
@ 8
mse
on
@ 8
msec
@ 8
msec
@ 8
msec
@ 8
msec
ldo_dig2 ldo_dig1 ldo_rf2_ ldo_rf1_
cp_on
@ 9
msec
sd3_on sd2_on sd1_on
Reg Power1
Ctrl @ 9 msec
_on
@ 9
msec
_o
@ 9
msec
on
@ 9
msec
on
@ 9
msec
@ 9
msec
@ 9
mse
9
msc
ldo_dig2 ldo_dig1 ldo_rf2_ ldo_rf1_
cp_on
@10
msec
sd3_on sd1_on
Reg Power1
Ctrl @ 10 msec
n
@ 1
msec
_on
@10
msec
on
@10
msec
on
@ 10
msec
@ 10
msec
10
mec
@ 10
msec
o_dig2 ldo_dig1 ldo_rf2_ ldo_rf1_
cp_on
@ 11
msec
sd3on sd2_on sd1n
Reg Power1
Ctrl @ 11 msec
_on
@ 11
msec
_on
@ 11
msec
on
@ 11
msec
on
@ 11
msec
@11
sec
@ 11
msec
@ 1
msc
ldo_dig2 ldo_dig1 ldo_rf2_ ldo_rf1_
cp_o
sd3_on sd2on sd1_on
Reg Power1
Ctrl @ 12 msec
_on
_on
on
on
29 1Dh ROM 12
ec
@ 12
msec
@ 12
sec
@ 12
msec
@ 12
msec
@ 12
msec
@ 12
msec
@ 12
msec
Reg Power2
Ctrl
stpup2_ stpup1_
n on
ldo_dig4 ldo_dig3
_on _on
30 1Eh ROM rf3_sw
rf2_sw
rf1_sw
ldo_rf3
ldo_d3 sd3_gpi sd2_gpi sd1_gpi ldo_dig2 ldo_dig1 ldo_rf2_ ldo_rf1_
Reg GPIO Ctrl 31 1Fh ROM
_gpio
o
o
o
_gpio
_gpio
gpio
gpio
Step Up DC/DC
32 20h 00h
Control
stupr
e
stpup2_f stpup2_f stpup1_r
stpup1_f stpup2_
req b_auto es
req
clkinv
stpp1_o
Step Up1 DC/
stpup1_ stpup1_
shortprot clkinv
33 21h 0h c_timeou
t
stpup1_v
stpup2_v
DC Control
Step Up2 DC/
DC Control
stpup2_p
34 2h 00h
rot
stpup2_fb
Step Down
Control1
sd2_nsw
323h 00h
_on
sd2_psw sd1_nsw
sd1_psw
_on
_on
_on
Step Down
Con
sd3_dis_ sd2_dis sd1_dis
sd3_nsw
_on
sd3_psw
_on
36 24h 00h
37 25h 02h
38 26h 40h
39 27h 00h
sdX_lpo
pon
_pon
_pon
Step w
chrger control
sd3_dis sd2_dis sd1_dis
_curmin _curmin _curmin
sdc_pas
s_mode
sdc_freq
u
sdc_pon
Backup Battery
charger
BBCPwr
Save
BBCRes
Off
BBCVolt
BBCCur
BBCMode
DCDC_CURR1
value
dcdc_curr1_current
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Revision 1v13
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AS3658
Data Sheet Confidential - Register map
Table 186. Register Map
Register
Content
b4 b3
Definition
Name
b7
b6
b5
b2
b1
b0
DCDC_CURR2
value
40 28h 00h
dcdc_curr2_current
CURR1 value 41 29h 00h
CURR2 value 42 2Ah 00h
CURR3 value 43 2Bh 00h
CURR4 value 44 2Ch 00h
curr1_current
curr2_current
curr3_current
curr4_current
DCDC_CURR3
45 2Dh 00h
value
dcdc_curr3_current
ADC idac
46 2Eh 00h
adc_ida
usb_chd charging
LowBat_i ovtmp_ onkey_ chdet_
ceoc_i chstate_
nt_m int_m
Interrupt Mask1 47 2Fh FFh
Interrupt Mask2 48 30h FFh
et_
_tmax_i
ntm
nt_m
int_m
int_m
int_m
int_m
stpup1_i bat_tem hphcu_ dig2v_i dig1_lv_i sd3_lv_sd2_lv_i sd1_lv_i
nt_m
p_m
int_m
ntm
nt_m
nt_m
nt_m
nt_m
voxm_in em mic_con rtc_rep_i rtc_alar dig4_lv_i dig3_lv_i
Interrupt Mask3 49 31h FFh
Interrupt
-
t_m
m
_int_m
nm m_int_m nt_m
nt_m
us_chd charging
cheoc_i
chstate_
i
50 32h NA LowBat_i ovtmp_i onkey_i chdet_i
Status1
eti
_tmax_i
Interrupt
Status2
bat_tem hphcurr_
51 33h NA stpup1_i
dig_i dig1_lv_i sd3_lv_i sd2_lv_i sd1_lv_i
p_i
i
Interrupt
Status3
mic_rem mc_con
rtc_alar
m_i
52 34h NA
53 35h NA
54 36h NA
voxm_i
rtc_rep_i
dig4_lv_i dig3_lv_i
sd2_lv sd1_lv
dig4_lv dig3_lv
gpio2 gpio1
_
_i
Low voltage
Status1
st1_d stpup1_
t oc
dig2_lv dig1_lv sd3_lv
Low voltage
Status2
bat_high _lowt dcdc_cu dcdc_cu dcdc_cu
tmp
emp
rr3_lv
rr2_lv
rr1_lv
GPIO Signal
55 37h NA gpio4in gpio3_in gpio2_in gpio1_in gpio4
gpio3
PWM
Frequency
Control High
Time
56 38h 00h
57 39h 00
pwm_h_time
pwm_l_time
PWM
Frequency
Control Low
Time
CURR control 58 3Ah 00h
pwm_div
Reg_low
dcdc_curr3_ctrl
standby
dcdc_curr2_ctrl
clk_int
dcdc_curr1_ctrl
References
59 3Bh 0ch
Control
low_pow
er_on
_bias_m clk_div2 _mode_
ode on
Watog
60 3Ch 02h
Conol
wtdg_tri wtdg_re
wtdg_on
gger
s_on
Wahdog_min
61 3Dh 00h
Tmer
wtdg_min_timer
wtdg_max_timer
Watchdog_max
62 3Eh FFh
Timer
Watchdog
wtdg_
sw_sig
63 3Fh 00h
Software Signal
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AS3658
Data Sheet Confidential - Register map
Table 186. Register Map
Register
Content
b4 b3
Definition
Name
b7
b6
b5
b2
b1
b0
RTCSecond
RTCMinute1
RTCMinute2
RTCMinute3
64 40h 00h
65 41h 00h
66 42h 00h
67 43h 00h
second<7:0>
minute<7:0>
minute<15:8>
minute<23:16>
RTCAlarmSeco
nd
68 44h 3Fh
69 45h FFh
70 46h FFh
71 47h FFh
alarmsecond<7:0>
alarmminute<7:0>
alarmminute<15:8>
alarmminute<23:16>
RTCAlarmMinu
te1
RTCAlarmMinu
te2
RTCAlarmMinu
te3
rtc_irq_
mode
RTCT
SRAM
72 48h 00h
73 49h 00h
rtc_tbc<6:0>
sram<7:0>
m_inv aud_ldo gnd_w
Audio Set1
74 4Ah 00h equ_on mclk256
mix_on dac_on
dith_on
lin_on
rt
_on
on
I2S_mclk I2S_sele
75 4Bh 00h
2S_3_o
n
Audio Set2
Audio Set3
ibr_hph
ibr_dac
_en
ct
linmix_omimix_ dacmix_
voxm_o hp_pulld pll_mod
76 4Ch 00h
agc_off mic_on
f
off
off
n
_en
e
dac_mut
e_off
DAC_L
DAC_R
77 4Dh 00h
78 4Eh 00h
dal_vol
dar_vol
adl_vol
adr_vol
hpr_vol
ad_mut
off
ADC_L
79 4Fh 00h ad_fs2
adc_on
ADC_R
80 50h 00h
81 51h 00h
acmux
hovc_to
adc2dac
hpcm_of
f
HPH out R
HPH out L
Line out R
82 52h 00h hp_mute hp_on hp_mux
hpl_vol
83 53h 0h
84 5h 0h
ibr_line
liner_vol
line_mut
dac2line
_on
Line out L
LINE_IN_R
LINE_IN_
MIR
line_on
linel_vol
lir_vol
e
mute_mi
c_sf
mute_off
_inr
5 5h 00h
6 56h 00h
87 57h 00h
mute_off
_inl
lil_vol
mic_agc
_off
pre_gain
mr_vol
ml_vol
mute_off
_d
MIC_L
88 58h 00h msup_off
rdet_off
sclk_inv sdo3_se spdif_co spdif_m spdif_inv
SPDIF
EQ_LP
89 59h 00h audio_off
90 5Ah 00h
spdif_cntr
ert
lect
py_ok
clk_inv
alid
eq_lp_gain
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AS3658
Data Sheet Confidential - Register map
Table 186. Register Map
Register
Definition
Content
Name
b7
b6
b5
b4
b3
b2
b1
b0
EQ_Band1
EQ_Band2
EQ_Band3
EQ_HP
91 5Bh 00h
92 5Ch 00h
93 5Dh 00h
94 5Eh 00h
95 5Fh 00h
eq_band1_gain
eq_band2_gain
eq_band3_gain
eq_hp_gain
EQ_preamp
eq_ pre_gain
adc_select
start_con
version
adc_slo
w
ADC_control
96 60h 00h
97 61h NA
98 62h NA
adc_on
D9
ADC_MSB
result
result_no
t_ready
D8
D7
D6
D5
D2
D4
D1
D3
ADC_LSB
result
D0
ChargerStatus 99 63h NA ChLinear NoBat
EOC
CVM
Trickle Resue ChAct
ChDet
ChargerStatus_
100 64h NA
usb
ch_ver batsw_o batsw_ USB_Ch USB_Ch
voltage
n
mode
Act
Det
DeltaChargeMS
214
26
214
26
25
213
25
212
2
210
29
28
101 65h NA
102 66h NA
103 67h NA
104 68h NA
sign
B
DeltaChargeLS
27
215
2
24
2
24
2
211
23
22
210
22
21
29
21
20
28
20
B
ElapsedTimeM
SB
ElapsedTimeLS
B
Oy_r
t_5s
xon_inp power_o force_re
ut ff set
Reset Control 105 69h NA
ese_reason
rst_ov_t
emp_14
0
Overtemperatu
106 6Ah NA
re Control
ov_temp ov_temp temp_p
_140
_110
mc_on
rom_
valid
Boot_status 107 6Bh NA
rom_adr
tpen_xmsb
tpen_ymsb
108 6Ch NA
109 6Dh NA
X
D9
PD9
XD8
YD8
PD8
XD7
YD7
PD7
XD6
YD6
PD6
XD5
YD5
PD5
XD4
YD4
PD4
XD3
YD3
PD3
XD2
YD2
PD2
tpen_pressmsb 110 6Eh NA
tpen_xypressls
111 6h NA
b
PD1
PD0
0
YD1
YD0
0
XD1
XD0
tpen_st_ tpen_eo
pen
tpen_so
c
tpen – control 1 12 70h 00h
tpen – contro2 113 71h 00h
en – control 3 114 72h 00h
tpen_avg
tpen_convint
tpen_pu
tpen_on
c
tpen_soc tpen_wa tpen_cur
pd
it
rpress
tpen_tim tpen_de
eout_en bounce
tpen_sample
ASC ID 1
ASIC ID 2
127 7Fh NA
128 80h NA
1
0
1
1
0
0
0
1
1
1
0
1
rev
ldo_dig2 ldo_dig1
_stby_o _stby_o
Reg_ standby
mod
cp_stby_ sd3_stb sd2_stb sd1_stb
ldo_rf2_ ldo_rf1_
stby_on stby_on
129 81h 00h
on
y_on
y_on
y_on
n
n
www.austriamicrosystems.com
Revision 1v13
152 - 157
AS3658
Data Sheet Confidential - Register map
Table 186. Register Map
Register
Content
b4 b3
Definition
Name
b7
b6
b5
b2
b1
b0
Usb_current_tri
m
130 82h
131 83h
00
00
usb_add_trim_current<2:0>
i2s master
control1
i2s_clk_divider<7:0>
sdo_on_
mclk1_e
n
i2s_lrclk
i2s_mas
_sclk_ou
ter_on
i2s master
control2
pcm_mo
de
i2s_mclk
_out_en
132 84h
133 85h
00
00
i2s_clk_divider<10:8>
t_en
step Down
Control3
sd3_uvli sd2_uvli s1_u
mit
mit
mit
UniqueID0,
addrf0
197 C5h NA
198 C6h NA
199 C7h NA
200 C8h NA
201 C9h NA
202 CAh NA
203 CBh NA
204 CCh NA
205 CDh NA
206 CEh NA
207 CFh NA
ID<7:0>, addrf<7:0>
UniqueID1,
addrf1
ID<15:8>, addrf<15:8>
D<23:1>, addrf<23:16>
ID<31:24>, addrf<31:24>
ID<39:32>, omf0
UniqueID2,
addrf2
UniqueID3,
addrf3
UniqueID4,
romf0
UniqueID5,
romf1
ID<40>, romf1
UniqueID6,
romf2
I<55:48>, romf2
UniqueID7,
romf3
ID<63:56>, romf3
UniqueID8,
romf4
ID<71:64>, romf4
UniqueID9,
romf5
ID<79:72>, romf5
UniqueID10,
romf6
ID<87:80>, romf6
Entries marked are read only
Entries are not reset in power off mode
www.austriamicrosystems.com
Revision 1v13
153 - 157
AS3658
Data Sheet Confidential - Package Drawings and Marking
12 Package Drawings and Marking
Figure 61. CTBGA124 8x8 0.5mm pitch
DWG NO.
ISSUE
97SPP01046A
O
Advanced
Semiconductor
Engineering Korea, Inc.
PACKAGE
ASE
OUTLINE
DATE
OCT.010, 2007
TOP VIEW
BOTTOM VIEW
(124 SOLDER BALLS )
SIE VIEW
NOTE
1. GENERAL TOLERANCE : 0.10
Unit : mm
Dimension & Tolerance
ASME Y14.5M
Customer : AMS
COMPANY
SHEET
ASE KOREA
1 OF 2
ITLE : POD for FBGA 8mm X 8mm X 1.09mm,
2L0.65CAP, 124BGA, 0.50PITCH, 0.30BALL
www.austriamicrosystems.com
Revision 1v13
154 - 157
AS3658
Data Sheet Confidential - Package Drawings and Marking
Figure 62. CTBGA124 Marking
Table 187. Package Code AYWWZZZ
A
Y
WW
ZZZ
B ... for Green
year
working week assembly / packaging
free choice
Table 188. Boot ROM revison
x
B, C, D, E, E1 or F
12.1 Pinout Drawing (Top view) CTBGA mm
Figure 63. Pinout drawing
Bottom View (Ball Side
14 13 12 11 10
9
7
6
5
4
2
1
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
K
L
K
L
N
P
M
N
P
Inner Balls PCB Layout
Example shown
with dotted blue lines
c
c
14 13 12 11 10
9
8
7
6
5
4
3
2
1
www.austriamicrosystems.com
Revision 1v13
155 - 157
AS3658
Data Sheet Confidential - Ordering Information
13 Ordering Information
The device is available as the standard products listed in Table 189.
Table 189. Ordering Information
Model
Marking
Descriptiom
Delivery Form
Package
BGA124
8x8mm, 0.5mm
pitch
Tape and Reel in
Dry Pack
Power and Audio Management Unit for Portable
Devices, Boot-ROM Version B
AS3658B-BCTP
AS3658B
BGA124
8x8mm, 0.5mm
pitch
Tape and Reel in
Dry Pack
Power and Audio Management Unit for Portable
Devices, Boot-ROM Version C
AS3658C-BCTP
AS3658D-BCTP
AS3658E-BCTP
AS3658E1-BCTP
AS3658F-BCTP
AS3658C
AS3658D
AS3658E
AS3658E1
AS3658F
BGA12
8x8mm, 0.5m
pitc
Tape and Reel in
Dry Pack
Power and Audio Management Unit for Portable
Devices, Boot-ROM Version D
BGA14
8x8mm, 0.5mm
pitch
Tape and Reel in
Dry Pack
Power and Audio Management Unit for Portable
Devices, Boot-ROM Version E
BGA124
8x8mm, 0.5mm
pitch
Tape and Reein
Dry Pk
Power and Audio Management Unit for Portable
Devices, Boot-ROM Verson E1
BGA124
8x8mm, 0.5mm
pitch
Tape and Reel in
Dry Pak
Power and Audio Management nit for ortable
Devices, Boot-ROM Versin F
Description: AS3658x-BCTP
x: Boot-ROM version
B: Teperature Range: Z = -40ºC to 85ºC
CT: Pacakage: CTBGA
P:Delivery Form: Tape and Reel in Dry Pck
www.austriamicrosystems.com
Revision 1v13
156 - 157
AS3658
Data Sheet Confidential - Ordering Information
Copyrights
Copyright © 1997-2010, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe.
Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged,
translated, stored, or used without the prior written consent of the copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing
in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding
the information set forth herein or regarding the freedom of the described devices from patent infringement.
austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice.
Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG fo
current information. This product is intended for use in normal commercial applications. Applications equiring
extended temperature range, unusual environmental requirements, or high reliability applications, uch s military,
medical life-support or life-sustaining equipment are specifically not recommended without additional rocessing by
austriamicrosystems AG for each application. For shipments of lesthan 100 parts the manuturig flow might show
deviations from the standard production flow, such as test flow otest oation.
The information furnished here by austriamicrosystems AG is belived o be correct and acuate. However,
austriamicrosystems AG shall not be liable to recipient or ird party for any damages, including but not limited to
personal injury, property damage, loss of profits, loss of useterruption of busineor indirect, special, incidental or
consequential damages, of any kind, in connection with or arsing out of the furnhing, performance or use of the
technical data herein. No obligation or liability to recipient or any third party sall arise or flow out of
austriamicrosystems AG rendering of technical or other services.
Contact Information
Headquarters
austriamicrosysteAG
A-8141 Schloss Premstaetten, Austria
Tel: +43 (0) 336 50 0
Fax: +43136 525 01
For Sles Offices, Distributors and Representatives, please visit:
http://www.austriamicrosystems.com/contact
B
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Revision 1v13
157 - 157
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