AS3675 [AMSCO]
Flexible Lighting Management Unit; 灵活的照明管理单元
| 型号： | AS3675 |
| 厂家： | 
AMS(艾迈斯) |
| 描述： | Flexible Lighting Management Unit |
| 文件： | 总81页 (文件大小：5013K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
austriamicrosystems AG
is now
ams AG
The technical content of this austriamicrosystems datasheet is still valid.
Contact information:
Headquarters:
ams AG
Tobelbaderstrasse 30
8141 Unterpremstaetten, Austria
Tel: +43 (0) 3136 500 0
e-Mail: ams_sales@ams.com
Please visit our website at www.ams.com
Datasheet
AS3675
Flexible Lighting Management Unit (Charge Pump, DCDC, 13
Current Sinks, ADC, LED Test, LDO, Audio Controlled Light)
1 General Description
The AS3675 is a highly-integrated CMOS Power and
Lighting Management Unit for mobile telephones, and
other 1-cell Li+ or 3-cell NiMH powered devices.
ꢀ
ꢀ
Led Pattern Generator
- Autonomous driving for Fun RGB LEDs
- Support indicator LEDs
10-bit Successive Approximation ADC
The AS3675 incorporates one Step Up DC/DC Con-
verter for white backlight LEDs, one high-power Charge
Pump, one Analog-to-Digital Converter, 13 current sinks,
the RGB and white LEDs can be controlled by an audio
input, LED in-circuit function test, a two wire serial inter-
face, and control logic all onto a single device. Output
voltages and output currents are fully programmable.
- 27µs Conversion Time
- Selectable Inputs: GPIO, all current sources,
VBAT, CPOUT, DCDC_FB
- Internal Temp. Measurement
- Light Sensor input
ꢀ
ꢀ
ꢀ
Support for automatic LED testin(opn and
shorted LEDs can be identified
The AS3675 is part of to the austriamicrosystems
AS3676, AS3687/87XM and AS3689 lighting mange-
ment units family. It is software compatible to AS3687/
87XM and AS3689 and pin and software compatible to
AS3676.
Support for external Tempture Sensor for high
currenLED protection (CURR3x)
StrobTimeout protecion
- Up to 1600ms
- Three different ming modes
Two General urpose Inputs/Output
ꢀ
2 Key Features
- VANA/GPInput, GPIO Input/Output
- Diginput, Digital Output using VANA/GPI sup-
ply d Tistate
- VANA/GPI internal pull down
GPIO Programmable Pull-Up/Down
ꢀ
High-Efficiency Step Up DC/DC Converter
- Up to 16V/55mA (or 25V/35mA) for Whte LEDs
- Programmable Output Voltage with Extenal Resis-
tors and Serial Interface
- Over voltage Protection
ꢀ
ꢀ
Programmable LDO
ꢀ
High-Efficiency High-Power Charump
- 1.85 to 3.4V, 150mA
- Programmable via Serial Interface
Standby LDO always on
- 1:1, 1:1.5, and 1:2 Mode
- Automatic Up Switching (can be disabled an1:2
mode can be blocked)
- Output Current up to 300mA/500mA plsed
- Efficiency up to 95%
- Very Low effective Resistance (2.5Ω . in 1:1.5)
- Only 4 External Capacitors Require
2 x 1µF Flying Capacitors, 2 x 2.2F Input/Output
Capacitors
- Regulated 2.5V max. output 10mA
- 3µA Quiescent Current
Audio can be used to drive RGB LED or up to four
white LEDs
- RGB Color and Brightness is dependent on audio
input amplitude or frequency
ꢀ
White LEDs can be controlled by amplitude or fre-
quency (different modes like bar-type or two and two
LEDs driven by frequency filters)
- Supports LCD White Bckligt LEDs, or RGB
LEDs
ꢀ
13 Current Snks
ꢀ
ꢀ
ꢀ
ꢀ
Wide Battery Supply Range: 3.0 to 5.5V
Two Wire Serial Interface Control
- All 13 current inks fully Programmable (8-bit)
from: 0.15mA to 38.5mA (up to 75.6mA for
CURR3...CRR33)
- Thurrent sinks are High Voltage capable
(CR, CURR2, CURR6)
Over current and Thermal Protection
WL-CSP30 3x2.5mm, 0.5mm pitch Package
3 Applications
Power- and lighting-management for mobile telephones
and other 1-cell Li+ or 3-cell NiMH powered devices.
Programmable Hardware Control (Strobe, and Pre-
ew or PWM)
- Selectively Enable/Disable Current Sinks
ꢀ
Internal PWM Generation
- 8 Bit resolution
- Autonomous Logarithmic up/down dimming
www.austriamicrosystems.com/AS3675
(ptr)
1v3
1 - 80
AS3675
Datasheet - Applications
Figure 1. Block Diagram
ꢕꢂꢡꢡꢅꢃꢽ
ꢞꢋ
ꢀꢫ
ꢋꢘꢙ
ꢴꢋ
ꢋꢒꢘꢮ
ꢀꢭ
ꢛꢎꢪꢘꢙ
ꢞꢀꢞꢀꢗꢶꢓꢖꢼ
ꢞꢀꢞꢀꢗꢢꢚꢢ
ꢾꢋ
ꢓꢢꢑꢫꢪꢏ
ꢴꢣꢄꢁꢡꢣꢠꢄ
ꢺꢂꢠꢂꢄꢅꢉꢅꢠꢡꢆ
ꢝꢠꢣꢡ
ꢴꢼꢞꢆ
ꢖꢅꢥꢡ
ꢢꢡꢅꢊꢆꢝꢊꢆꢞꢀꢳꢞꢀ
ꢀꢹꢠꢸꢅꢃꢡꢅꢃ
ꢟꢋ
ꢒꢎꢋꢲ
ꢟꢐ
ꢋꢺꢲ
ꢀꢪ
ꢋꢎꢏꢠꢙ
ꢞꢀꢞꢀꢗꢙꢕ
ꢓꢈꢷꢣꢹ
ꢀꢹꢠꢡꢃꢹꢯꢯꢅꢷ
ꢴꢣꢄꢁꢡ
ꢟꢑ
ꢋꢒꢒꢤꢲ
ꢀꢨ
ꢠꢙ
ꢓꢝꢞꢰꢜꢗꢰꢚ
ꢓꢈꢷꢣꢹꢆꢰꢚ
ꢕꢂꢡꢡꢅꢃꢽ
ꢟꢶꢕꢆꣁꢆꢻꢁꢣꢡꢅꢆꢴꢼꢞꢥ
ꢔꢕꢓꢖ
ꢀꢐꢗꢇ
ꢀꢐꢗꢚ
ꢀꢋꢗꢇ
ꢕꢂꢡꢡꢅꢃꢽꢆꢹꢃ
ꢆꢀꢇꢜꢝꢖ
ꢀꢈꢃꢃꢅꢠꢡꢆꢢꢣꢠꢤꢥ
ꢒꢎꢋꢏꢧꢑꢨꢎꢐꢏꢉꢓ
ꢀꢐ
ꢋ
ꢀꢑ
ꢋꢘꢙ
ꢟꢶꢕꢋ
ꢟꢶꢕꢐ
ꢟꢶꢕꢋ
ꢀꢂꢃꢄꢅꢆꢇꢈꢉꢊ
ꢋꢌꢋꢍꢆ
ꢒꢒꢉꢓ
ꢞꢫ
ꢞꢭ
ꢞꢋꢐ
ꢞꢋꢑ
ꢞꢋꢛ
ꢟꢶꢕꢑ
ꢞꢪ
ꢞꢨ
ꢞꢋꢒ
ꢞꢋꢋ
ꢀꢛ
ꢋꢘꢙ
ꢚ
ꢕꢂꢡꢡꢅꢃꢽꢆꢹꢃ
ꢆꢀꢇꢜꢝꢖ
ꢞꢋꢏꢍꢞꢋꢫꢍꢞꢋꢪ
ꢀꢈꢃꢃꢅꢠꢡꢆꢢꢣꢠꢤꢥ
ꢒꢎꢋꢏꢧꢑꢨꢎꢐꢏꢉꢓ
ꢔꢢꢢꢗ
ꢀꢝꢟꢟꢛꢋ
ꢀꢝꢟꢟꢛꢐ
ꢀꢇꢜꢝꢖ
ꢟꢶꢕꢐ
ꢀꢝꢟꢟꢛꢑ
ꢀꢈꢃꢢꢣꢠꢤꢥ
ꢅꢂꢦꢁꢆꢒꢎꢎꢐꢏꢉꢓ
ꢩꢪꢏꢎꢫꢉꢓꢬꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆ
ꢞꢐ
ꢞꢛ ꢞꢏ
ꢞꢑ
ꢞꢋꢨꢍꢞꢋꢭꢍꢞꢐꢒ
ꢨꢕꢣꢡꢆꢇꢻꢺꢆ
ꢶꢅꢠꢅꢃꢂꢡꢹ
ꢀꢝꢟꢟꢑꢒ
ꢆꢆꢀꢏ
ꢐꢎꢐꢘꢙ
ꢓꢈꢡꢹꢉꢂꢡꢣꢦꢆꢞꢣꢉꢉ
ꢂꢠꢷꢆꢼꢞꢡꢡꢅꢃꢠ
ꢅꢠꢅ
ꢀꢝꢟꢟꢑꢋ
ꢀꢝꢟꢟꢑꢐ
ꢀꢝꢟꢟꢑꢑ
ꢔꢕꢓꢖ
ꢟꢅꢱꢅꢃꢅꢠꢦꢅꢥ
ꢂꢠꢷ
ꢔꢐꢗꢏ
ꢮꢔꢆꢀꢈꢃꢃꢅꢠꢡꢆꢢꢣꢠꢤꢥ
ꢅꢂꢦꢁꢆꢒꢎꢋꢏꢧꢑꢨꢎꢐꢏꢉꢓ
ꢖꢅꢉꢊꢅꢃꢂꢡꢈꢃꢅ
ꢢꢈꢊꢅꢃꢸꢣꢥꢣꢹꢠ
ꢀꢋ
ꢋꢘꢙ
ꢀꢝꢟꢟꢋ
ꢀꢝꢟꢟꢐ
ꢀꢝꢟꢟꢫ
ꢔꢕꢓꢖ
ꢶꢇꢰ
ꢔꢓꢚꢓ
ꢔꢓꢚꢓꢳꢶꢇꢰ
ꢞꢜ
ꢋꢏꢧꢑꢎꢛꢔꢆꢳꢆꢋꢏꢒꢉꢓ
ꢀꢋꢒ
ꢐꢎꢐꢘꢙ
ꢿꢅꢃꢹꢆꢇꢹꣀꢅꢃ
ꢞꢅꢸꢣꢦꢅ
ꢻꢂꢤꢅꢈꢊ
ꢔꢐꢗꢏ
ꢔꢞꢞꢗꢰꢳꢙ
ꢔꢡꢅꢉꢊ
ꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢶꢇꢰꢜꢳ
ꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢆꢓꢞꢀ
ꢟꢛ
ꢋꢧꢋꢒꢤꢲ
ꢟꢏ
ꢜ
ꢀꢴꢵ
ꢀꢴꢵ
ꢢꢅꢃꢣꢂꢯ
ꢰꢠꢡꢅꢃꢱꢂꢦꢅ
ꢂꢯꢯꢆꢦꢈꢃꢃꢥꢍꢆꢔꢕꢓꢖꢍ
ꢞꢀꢞꢀꢗꢙꢕꢍ
ꢀꢇꢜꢝꢖ
ꢞꢓꢖꢓ
ꢞꢓꢖꢓ
ꢔꢢꢢ
www.austriamicrosystems.com/AS3675
1v3
2 - 80
AS3675
Datasheet - Applications
Contents
1 General Description ............................................................................................................................1
2 Key Features .......................................................................................................................................1
3 Applications ........................................................................................................................................1
4 Pinout ...................................................................................................................................................4
4.1 Pin Definitions ..............................................................................................................................................5
5 Absolute Maximum Ratings ...............................................................................................................6
6 Electrical Characteristics ...................................................................................................................6
7 Typical Operating Characteristics ...................................................................................................
8 Detailed Description .......................................................................................................................
8.1 Analog LDO ................................................................................................................................................9
8.2 Step Up DC/DC Converter .......................................................................................................................11
8.3 Charge Pump .........................................................................................................................................16
8.4 Current Sinks .........................................................................................................................................24
8.5 General Purpose Input / Output ............................................................................................................46
8.6 LED Test ...............................................................................................................................................51
8.7 Analog-to-Digital Converter ..................................................................................................................53
8.8 Audio controlled LEDs .......................................................................................................................56
8.9 Power-On Reset ....................................................................................................................................65
8.10 Temperature Supervision ........................................................................................................................67
8.11 Serial Interface ....................................................................................................................................67
8.12 Operating Modes ..............................................................................................................................70
9 Register Map .................................................................................................................................71
10 External Components ...............................................................................................................74
11 Package Drawings and Markgs .........................................................................................75
11.1 Tape & Reel Information .........................................................................................................................76
12 Ordering Information ...................................................................................................................77
www.austriamicrosystems.com/AS3675
1v3
3 - 80
AS3675
Datasheet - Pinout
4 Pinout
Table 1. Pin Description for AS3675
Pin
Number
Pin Name
Type
Description
A1
GPIO
AIO
AIO
General Purpose Input Output
A2
VANA/GPI
LDO Output/General Purpose Input
Charge Pump flying capacitor; connect a ceramic capacitor of 500nF to this
pin.
A3
A4
A5
C2_N
C1_P
AIO
AIO
AO
Charge Pump flying capacitor; connect a ceramic capacitor of 500nF to thi
pin.
Output voltage of the Charge Pump; connect a ceramic capacitor of µF
(±20%).
CPOUT
A6
B1
B2
DATA
DIO
AI
Serial interface data input/output.
Audio Input
AUDIO_IN
VSS_CP
GND
Ground Pad for Charge Pump
Charge Pump flying caacitr; onnect a ceramic capaitor of 500nF to this
pin.
B3
B4
C1_N
C2_P
AIO
AIO
Charge Pump flycapacitor; connect a ceramic capacitor of 500nF to this
pin.
B5
B6
C1
C2
C3
C4
C5
C6
D1
D2
D3
D4
D5
D6
E1
E2
E3
E4
E5
DCDC_GATE
CLK
AO
DI
DCDC gatdriver.
Clock input foserial interface.
CURR41
RGB3
AI
Anacurrent sink input
AI
Aalog current sink input
VSS
GND
S
Ground pad
VBAT
Supply pad. Connect to battery.
CURR30
DCDC_SNS
CURR43
RGB1
AI
Analrent sink input, intended for activity icon LED
Sense nput of shunt resistor for Step Up DC/DC Converter.
Analog current sink input
AI
AI
AI
Analog current sink input
CURR33
CURR31
CURR2
DCDC_FB
CURR42
RGB2
AI
Analog current sink input, intended for activity icon LED
Analog current sink input, intended for activity icon LED
Analog current sink input (intended for Keyboard backlight)
DCDC feedback. Connect to resistor string.
Analog current sink input
I
I_HV
AI
AI
AI
Analog current sink input
CURR32
CURR6
CURR1
AI
Analog current sink input, intended for activity icon LED
Analog current sink input (intended for Keyboard backlight)
Analog current sink input (intended for Keyboard backlight)
AI_HV
AI_HV
Output voltage of the Low-Power LDO; always connect a ceramic capacitor of
1µF (±20%) or 2.2µF (+100%/-50%).
E6
V2_5
AO3
Do not load this pin during device startup.
www.austriamicrosystems.com/AS3675
1v3
4 - 80
AS3675
Datasheet - Pinout
4.1
Pin Definitions
Table 2. Pin Type Definitions
Type
DI
Description
Digital Input
Digital Output
DO
Digital Input/Output
Analog Pad
DIO
AIO
AI
Analog Input
High-Voltage (15V) Pin
Analog Output (3.3V)
Supply Pad
AI_HV
AO3
S
Ground Pad
GND
www.austriamicrosystems.com/AS3675
1v3
5 - 80
AS3675
Datasheet - Absolute Maximum Ratings
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 3 may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in Table 4, “Operating
Conditions,” on page 6 is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
Table 3. Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Units
Comments
Applicable for high-voltage
current sink pins CURR1,
CURR2, CURR6
VIN_HV
15V Pins
-0.3
17
V
Applicable for 5V pins
VBAT, CURR30-3,
CURR41-43, RGB1-3, C1_N,
C2_N, C1_P, C2_P, CPOUT,
DCDC_FB, CDC_GATE,
CK, DATA;
VIN_MV
VIN_LV
5V Pins
-0.3
-0.3
7.0
5.0
V
V
Applicable or 3.3V pins
V2; DCDC_SNS, GPIO,
VAA/GPI, AUDIO_IN
3.3V Pins
Input Pin Current
Storage Temperature Range
Humidity
-25
5
5
+5
125
85
mA
ºC
%
At ºC, Norm: JEDEC 17
Tstrg
IIN
Non-condensing
Norm: MIL 883 E Method
3015
VESD
Pt
Electrostatic Discharge
Total Power Dissipatio
Peak Body Temperature
-2000
2000
05
260
V
TA = 70 ºC, Tjunc_max =
125ºC
W
ºC
T = 20 to 40s, in accordance
with IPC/JEDEC J-STD 020.
TBODY
6 Electrical Characteristics
Table 4. Operating Conditions
Symbol
Parameter
Condition
Min
Typ
Max
Unit
General Operating Conditions
Alicable for high-voltage current sink pins
CURR1, CURR2 and CURR6.
VHV
VBAT
VPERI
V2_5
High Voltage
0.0
3.0
1.5
2.4
-30
15.0
5.5
5.5
2.6
85
V
V
Battery Voltag
Pin VBAT
3.6
PeripherSuply
Voltge
For serial interface pins.
Internally generated
V
Voge oPin V2_5
2.5
25
V
Operating
Temperature Range
TAMB
ºC
Normal Operating current (see Operating
Modes on page 71)
IACT
Battery current
35
8
µA
µA
µA
Current consumption in standby mode. Only
2.5V regulator on, interface active
ISNDBY Standby Mode Current
13
3
Shutdown Mode
ISHUTDOWN
interface inactive (CLKand DATA set to 0V)
0.1
Current
www.austriamicrosystems.com/AS3675
1v3
6 - 80
AS3675
Datasheet - Typical Operating Characteristics
7 Typical Operating Characteristics
Figure 2. DCDC Step Up Converter: Efficiency of +15V,
Figure 3. Charge Pump: Efficiency vs. VBAT
Step Up to 15V vs. Load Current at VBAT=3.8V
100
90
80
70
60
50
40
30
20
10
0
90
VOUT=14.2V
VOUT=14.2V
fclk=550kHz
ILOAD=150mA
85
80
75
70
65
VOUT=22V
VOUT=17.2V
ILOAD=305mA
ILOAD=80mA
I
=40mA
LOAD
8
3
3.2
3.4
6
8
4
4.2
0
0.01
0.02
0.03
0.04
0.05
0.06
VBAT [V
Load Current [A]
Figure 4. Charge Pump: Battery Current vs. VBAT
Figure Current Sink CURR1 vsV(CURRx)
40.0
600
500
400
ICURR1=38.25mA
35.0
30.0
25.0
ILOA D=3mA
ICURR1=19.2mAm
300
20
5.0
10.0
200
ILO150mA
ILOA D=80mA
ILOA D=40mA
100
0
5.0
0.0
ICURR1=2.4mA
2.8
3
3.2
3.4
3.6
3.8
4
4.2
0.0
0.5
1.0
1.5
2.0
VBat[V]
VCURR1 [V]
Figure 6. Current Sink CURR1 Protectiourrent
Figure 7. Current Sink CURR3x vs. VBAT
3,0
40.0
curr_prot1_on=1
CURR30
I
=38.25mA
35.0
30.0
25.0
20.0
15.0
10.0
5.0
2,5
2,0
1,5
1,0
CURR30
I
=19.2mAm
4. 5uA
curr_prot1_on=0
0
0,0
CURR30
I
=2.4mA
0.0
0,0
5,0
10,0
15,0
20,0
0.0
0.5
1. 0
1. 5
2. 0
V(CURR1) [V]
CURR30
V
[V]
www.austriamicrosystems.com/AS3675
1v3
7 - 80
AS3675
Datasheet - Typical Operating Characteristics
Figure 8. Charge Pump Input and Output Ripple
1:1.5 Mode, 100mA load
Figure 9. Charge Pump Input and Output Ripple
1:2 Mode, 100mA load
ꢘꢜꢝ !ꢎ ꢀꢂꢛꢘꢅꢆꢇꢈ!
ꢝ"#$ꢚꢌ%&ꢊꢆ
ꢀꢋꢌꢍ ꢎꢂꢏꢐꢇꢀꢑꢅꢒꢓꢎ
ꢌꢔꢕꢖꢃꢗꢘꢙꢆꢅ
ꢘꢔ"'() ꢙ!ꢎ*ꢂꢂ ꢛꢘꢅꢆꢇꢈ!
ꢝ"#$ꢚꢌ%&ꢊꢆ
ꢀꢚꢔꢛꢜꢝꢍꢁꢎꢂ ꢏꢐꢇꢀꢑꢅꢒꢓꢎ
ꢌꢔꢕꢖꢃꢗꢘꢙꢆꢅ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈ
ꢉꢊꢋꢄꢌꢍꢊꢆꢎꢏꢇꢐꢑꢎꢒꢋꢐꢐꢊꢍꢓꢎꢔꢕꢖꢗꢘꢙꢎꢚꢃꢎꢆꢊꢛꢚꢒꢚꢋꢍꢆ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈ
ꢉꢊꢋꢄꢌꢍꢊꢆꢎꢏꢇꢐꢑꢎꢒꢋꢐꢐꢊꢍꢓꢎꢔꢕꢖꢂꢀꢂꢃꢄꢂꢅꢆꢃꢈꢃꢅ
Figure 10. Characteristics frequency mode, BP filter 512/2048Hz
BP Gain +6/+4/+2/0/-2/-4/-6dB
0.04
0. 035
0.03
0. 025
0.02
0. 015
0.01
0. 005
0
10
100
1000
10000
100000
Frequency[Hz]
VBAT = 3.6V, TA = +25ºC (unless otherwise secified).
www.austriamicrosystems.com/AS3675
1v3
8 - 80
AS3675
Datasheet - Detailed Description
8 Detailed Description
8.1
Analog LDO
The LDO is a general purpose LDO and the output pin is shared with the general purpose input (GPI) connected to
VANA/GPI. The design is optimized to deliver the best compromise between quiescent current and regulator perfor-
mance for battery powered devices.
Stability is guaranteed with ceramic output capacitors (of 1µF ±20% (X5R) or 2.2µF +100/-50%(Z5U). The low ESR of
these capacitors ensures low output impedance at high frequencies. The low impedance of the power transistor
enables the device to deliver up to 150mA even at nearly discharged batteries without any decrease in performance.
The LDO is off by default after start-up.
Figure 11. Analog LDO Block Diagram
ꢀꢁꢂꢂꢃꢄꢅ
ꢆꢀꢇꢈ
ꢎꢏ
ꢀ
ꢆꢇꢉꢇꢊꢋꢌꢍ
ꢐꢑ
ꢏꢒꢏꢓꢔ
AS3675
Table 5. Electrical Characteristics
Symbol
VBAT
Parameter
Condtion
Min
Typ
Max
Unit
Supply Voltage
Range
3.0
5.5
V
RON
On Resistance
@150mA, ull operating temperature range
@150mAldoana_lpo (see page 10)= 0
@50mA, ldo_ana_lpo= 0
1.0
150
50
Ω
mV
mV
mV
µA
VDROPOUT
Dropout Voltage
@5mA, ldo_ana_lpo= 1
500
Without load
50
3
Without load, ldo_ana_lpo= 1
ldo_ana only
ION
Supply Currnt
With 150mA load
Without load
150
IOFF
tstart
Shutdown Current
tart-up Time
100
200
nA
µs
Output Voltage
Tolerance
Vout_tol
VOU
-3
+3
%
VBAT > 3.0V and IOUT=150mA
Full Programmable Range
1.8
1.8
2.85
3.35
V
V
Output Voltage
LDO Current Limit
ldo_ana_lpo= 0
Pin VANA. LDO acts as current source if the
output current exceeds ILIMIT.
4502
8
300
4
mA
mA
1
ILIMIT
LDO Current Limit
ldo_ana_lpo= 1
VBAT-VANA≥0.2V
www.austriamicrosystems.com/AS3675
1v3
9 - 80
AS3675
Datasheet - Detailed Description
1. Not production tested – guaranteed by design and laboratory verification
2. During startup of the LDO the current limit is half the value of ILIMIT
8.1.1 LDO Registers
Table 6. Reg. control Register
Reg. control
Addr: 00
This register enables/disables the LDOs, Charge Pumps, Charge Pump LEDs
current sinks, the Step Up DC/DC Converter, and low-power mode.
Bit
Bit Name
Default Access
Description
0
1
0
Analog LDO is switched off
Analog LDO is switched on
Normal Operation
ldo_ana_on
0
0
0
R/W
R/W
Low-power mode; current consumptin is reduced by
about 75µA. Reduced performancof LDO: max 5mA
lod, internal oscillator is swied o. The device will
xit low-ower mode automaticly, if blocks requiring
the oscillatr are enabled.
ldo_ana_lpo
7
1
Table 7. LDO ANA1 Voltage Register
LDO ANA1 Voltae
Addr: 07h
This register sets the outpuvoltage (VANA) for the LDO.
Bit
Bit Name
Default Access
Description
Controls LDO voltage selection.
00000
..
1.85V
LSB=50mV
3.4V
ldo_ana_voltage
4:0
0000b
R/W
111b
www.austriamicrosystems.com/AS3675
1v3
10 - 80
AS3675
Datasheet - Detailed Description
8.2
Step Up DC/DC Converter
The Step Up DC/DC Converter is a high-efficiency current mode PWM regulator, providing output voltage up to e.g.
25V/35mA or e.g. 16V/55mA. A constant switching-frequency results in a low noise on the supply and output voltages.
Figure 12. Step Up DCDC Converter Block Diagram Option: Current Feedback with Over voltage protection
-ꢏꢊꢊꢈꢇ0
ꢀꢚ
ꢁ$%
1ꢁ
ꢁꢒ$ꢄ
ꢞꢁ
ꢀ!
"ꢓ#$%
ꢞꢀꢞꢀ'*ꢙ+,
ꢞꢀꢞꢀ'ꢋ(ꢋ')
&ꢁ
ꢋꢊꢈꢛꢆꢂꢛꢆꢞꢀꢜꢞꢀ
ꢀꢝꢉ ꢈꢇꢊꢈꢇ
ꢀꢁ
ꢒꢓꢁ/
ꢀꢃ
ꢁ./
ꢀ#
ꢁꢓꢔꢉ%
ꢞꢀꢞꢀ'%-
ꢀꢗ
ꢁꢉ%
ꢀꢖ
ꢁꢒꢒꢍ/
ꢞꢚ
ꢞ#
ꢞꢗ
ꢞ!
ꢞꢁꢃ
ꢞꢁꢖ
ꢞꢁ"
ꢞꢁꢒ
ꢞꢁꢁ
ꢄꢅꢆꢀꢈꢇꢇꢈꢉꢆꢌꢉꢍ
ꢈꢏꢐꢑꢆꢒꢓꢁꢔꢕꢖꢗꢓꢔꢘꢙ
ꢀ ꢀꢁ
ꢀꢃ
ꢀꢂꢀꢀꢚ
AS3675
Table 8. Step Up DC/DC Converter Paraers
Symbol
Parameter
Condition
Min
Typ
Max
Unit
IVDD
Quiescent Curret
Pulse skipping mode.
140
µA
Feedback Voltae for
External Resistor
Dvider
For constant voltage control.
VFB1
VFB2
1.20
0.4
1.25 1.30
V
V
step_up_res = 1
Feedack Voltage for
Current Sink
on CURR1, CURR2 or CURR6 in regulation.
0.5
0.6
step_up_res = 0
Regulation
Additional Tuning
Current at Pin
Adjustable by software using Register DCDC
control1
0
31
6
µA
%
DCDC_FB and over
voltage protection
1µA step size (0-31µA)
IDCC_FB
V
PROTECT = 1.25V +
IDCDC_FB * R2
Accuracy of Feedback
Current at full scale
-6
www.austriamicrosystems.com/AS3675
1v3
11 - 80
AS3675
Datasheet - Detailed Description
Table 8. Step Up DC/DC Converter Parameters
Symbol
Parameter
Condition
Min
Typ
Max
Unit
e.g., 0.66A for 0.1Ω sense resistor.
46
66
85
Current Limit Voltage
at R1
For fixed startup time of
500us
Vrsense_max
25
30
33
43
43
mV
If Step up_lowcur= 1
ON-resistance of external switching transistor.
At 16V output voltage
57
1
RSW
ILOAD
fIN
Switch Resistance
Load Current
Ω
mA
MHz
µF
0
0
55
35
1.1
At 25V output voltage
Switching Frequency
Output Capacitor
Internally trimmed
0.9
1
Ceramic, ±20%. Use nominal 4.7µF capacitors
to obtain at least 0.7µF under all conditions
(voltage dependence of capacitors)
COUT
0.7
7
4.7
Use inductors with small Cparasitic (<100pF) to
get high efficiency.
L
Inductor
10
3
µH
tMIN_ON
Minimum on Time
Maximum Duty Cycle
Voltage ripple >20kHz
Voltage ripple <20kHz
Efficiency
90
88
14
1
190
ns
%
MDC
160
40
mV
mV
%
Vripple
Cout=4.7µF,Iout=mA, VBAT=3.0...42V
Iout=20mA,Vou=17V,VBAT=3.8V
Efficiency
85
To ensure soft startup of the dcdc converter, the oecurent limits are reced or a fixed time after enabling the dcdc
converter. The total startup time for an output vtage of e.g. 25V is leshan 2ms.
8.2.1 Feedback Selection
Register DCDC control1 and DCDC cotrol2 selects the type f feeback for the Step Up DC/DC Converter.
The feedback for the DC/DC converten be selected eby current sinks (CURR1, CURR2, CURR6) or by a volt-
age feedback at pin DCDC_FB. If the register bit step_uauto is set, the feedback path is automatically selected
between CURR1, CURR2 and CURR6 (the lowest voltage of these current sinks is used).
Setting step_up_fb enables feedback on the pins CURR1, CURR2 or CURR6. The Step Up DC/DC Converter is regu-
lated such that the required current at the fedback path can be supported. (Bit step_up_res should be set to 0 in this
configuration)
Note: Always choose the path with the est voltage drop as feedback to guarantee adequate supply for the other
(unregulated) paths or enable the register bit step_up_fb_auto.
8.2.2 Over voltage Protetion in Current Feedback Mode
The over voltage protection in current feedback mode (step_up_fb = 01, 10 or 11 or step_up_fb_auto = 1) works as fol-
lows: Only resistor R2 and C7/C8 is soldered and R3 is omitted. An internal current source (sink) is used to generate a
voltage drop acrss the resistor R2. If then the voltage on DCDC_FB is above 1.25V, the DCDC is momentarily dis-
abled to avoid too hgh voltages on the output of the DCDC converter.
The protectiovoltage can be calculated according to the following formula:
VPROTECT = 1.25V + IDCDC_FB * R2
(EQ 1)
Nte: Te voltage on the pin DCDC_FB is limited by an internal protection diode to VBAT + one diode forward volt-
age (typ. 0.6V).
If the over voltage protection is not used in current feedback mode, connect DCDC_FB to ground.
www.austriamicrosystems.com/AS3675
1v3
12 - 80
AS3675
Datasheet - Detailed Description
Figure 13. Step Up DC/DC Converter Detail Diagram; Option: Regulated Output Current, Feedback is
automatically selected between CURR1, CURR2, CURR6 (step_up_fb_auto=1); over voltage protection
is enabled (step_up_prot=1); 1MHz clock frequency (step_up_frequ=0)
#ꢏꢊꢊꢈꢇ&
ꢀꢚ
ꢁꢗꢘ
'ꢁ
ꢁꢒꢗꢄ
ꢚꢁ
ꢎꢊꢈ(ꢛꢈ(ꢛ3ꢇꢈ7
ꢁ$ꢄ8
ꢔꢒꢒꢍꢄ8
ꢐ9ꢍ
ꢀꢕ
2ꢓꢖꢗꢘ
ꢝ5$
'+*ꢌꢐ
ꢏꢊꢈ
ꢚꢇꢌ)ꢈꢇ
ꢚꢀꢚꢀꢛ ꢙ!"
ꢚꢀꢚꢀꢛꢋꢜꢋꢛꢝ
ꢙꢁ
+)ꢛꢐꢈꢇꢇ
ꢅꢇꢎꢈꢉꢎꢈꢛꢘꢏ6
ꢀꢁ
ꢒꢓꢁ%
ꢀꢃ
ꢁ$%
ꢀꢖ
ꢁꢓꢔꢉꢘ
ꢎꢊꢈ(ꢛꢈ(ꢛ)ꢊꢈꢉꢌꢉ*
ꢚꢀꢚꢀꢛꢘ#
ꢀꢗ
ꢁꢔꢉꢘ
ꢀꢖ
ꢁꢒꢒꢍ%
ꢁꢓꢃꢔꢅ
ꢎꢊꢈ(ꢛꢈ(ꢛ(ꢇ+ꢊ
ꢚꢚ
ꢚ
ꢚꢗ
ꢚꢕ
ꢚꢁꢃ
ꢚꢁꢖ
ꢚꢁ2
ꢇꢏꢘ(
+)ꢈꢇꢎꢑ++ꢊꢆꢐ+ꢘ(
ꢀ
ꢁꢓꢖꢔꢅ
ꢒꢓꢗꢅ
ꢚꢁꢒ
ꢚꢁꢁ
ꢁꢓꢃꢔꢅ
ꢒꢓꢔꢅ
ꢈꢇꢇ+ꢇꢆ+ꢊꢏ
ꢎꢊꢈ(ꢛꢈ(ꢛ34
ꢄꢅꢆꢀꢈꢇꢇꢊꢆꢋꢌꢉꢎ
ꢈꢏꢐꢆꢁꢔꢕꢖꢗꢔꢘꢙ
ꢎꢊꢈ(ꢛꢈ(ꢛ34ꢛꢏꢈꢊ+
ꢀꢂꢀꢁ
ꢀꢃ
ꢀꢂꢀꢀꢚ
ꢙꢈꢊ+ꢘꢏꢊꢌꢐ
3ꢈꢈ:4ꢏꢐꢍꢆꢎꢈ9ꢈꢐꢊ
;ꢀꢂꢀꢀꢁ<ꢃ<ꢚ=
ꢀꢂꢀꢀ>ꢆ+ꢉꢆꢏꢉ:
ꢐꢈꢇꢇ>ꢛ+ꢉꢛꢐ(?ꢒ
AS3675
8.2.3 Voltage Feedback
Setting bit step_up_fb (see pae 15= 00 enables voltage feedback at pin DCDC_FB.
The output voltage is reguatd to a constant value, given by (Bit step_up_res should be set to 1 in this configuration)
UStep up_out = (R2+R3)/R3 *1.25 + IDCDC_FB * R2
If R4 is not used, ouut voltage is by (Bit step_up_res should be set to 0 in this configuration)
UStep up_out = 1.25 + IDCDC_FB * R2
(EQ 2)
(EQ 3)
Where:
ep p_out = Step Up DC/DC Converter output voltage
R2 = Feedback resistor R2
R3 = Feedback resistor R3
www.austriamicrosystems.com/AS3675
1v3
13 - 80
AS3675
Datasheet - Detailed Description
IDCDC_FB = Tuning current at ball DCDC_FB; 0 to 31µA
Table 9. Voltage Feedback Example Values
UStep up_out
UStep up_out
IDCDC_FB
µA
0
R2 = 1MΩ, R3 not used
R2 = 500kΩ, R3 = 50kΩ
-
13.75
14.25
14.75
15.25
15.75
16.25
16.75
1.25
17.75
18.25
18.75
19.25
19.75
20.25
20.75
21.25
…
1
-
2
-
3
-
4
-
5
6.25
7.25
8.25
9.25
10.25
11.25
15
13
14.2
15.25
16.25
…
6
7
8
9
10
11
12
13
14
15
…
30
31
31.2
28.75
29.25
Note: The voltage on CURR1, CURR2 and CURR6 must not exceed 15V (see page 25)
8.2.4 PCB Layout Hints
To ensure good EMC performance of the DCDconverter, keep its external power components C6, R1, L1, Q1, D1
and C9 close together. Connect the grounf C6, R1 and C9 locally together and connect this with a short path to
AS3675 VSS. This ensures that local higequency currents will not flow to the battery.
8.2.5 Step up Registers
Table 10. Reg. control Registr
Reg. control
Add00
This register enables/disables the Charge Pump and the Step Up DC/DC
Converter.
Bit
Bit Name
Default Access
Description
Enable the step up converter
Disable the Step Up DC/DC Converter
Enable the Step Up DC/DC Converter
step_up_on
0b
1b
3
0
R/W
www.austriamicrosystems.com/AS3675
1v3
14 - 80
AS3675
Datasheet - Detailed Description
Table 11. DCDC control1 Register
DCDC control1
Addr: 21h
This register controls the Step Up DC/DC Converter.
Bit
Bit Name
Default Access
Description
Defines the clock frequency of the Step Up DC/DC
Converter.
step_up_frequ
R/W
R/W
0
0
0
1
1MHz
500kHz
Controls the feedback source if step_up_fb_auto = 0
DCDC_FB enabled (external resistor divider
00
Set step_up_fb=00 (DCDC_FB)
step_up_fb
2:1
00
01
10
11
CURR1 feedback enabled (feedback via LDs)
CURR2 feedback enabled (eedack via LEDs)
CURR6 feedback enabled (feeback via LEDs)
Defines the tuning current pin DCDC_FB.
0000
0001
010
....
0 µA
1 µA
2 µA
step_up_vtuning
7:3
00000
R/W
10000
.....
15 µA
31 µA
11111
Table 12. DCDC control2 Register
DCDC control2
Addr: 22h
This registecontrols the Step Up DC/DC Converter and low-voltage current
sinks CURRx.
Bit
Bit Name
Defalt Access
Description
Gain selection for Step Up DC/DC Converter
Select 0 if Step Up DC/DC Converter is used
with current feedback (CURR1, CURR2,
CURR6) or if DCDC_FB is used with current
feedback only – R2, C7, C8 connected, R3 not
used
0
1
step_up_res
0
0
R/W
Select 1 if DCDC_FB is used with external
resistor divider using 2 resistors: R2 and R3
Step Up DC/DC Converter output voltage at low loads,
when pulse skipping is active
skip_fast
1
2
0
1
R/W
R/W
0
1
Accurate output voltage, more ripple
Elevated output voltage, less ripple
Step Up DC/DC Converter protection
No over voltage protection
0
1
step_up_prot
Over voltage protection on pin DCDC_FB
enabled voltage limitation =1.25V on DCDC_FB
www.austriamicrosystems.com/AS3675
1v3
15 - 80
AS3675
Datasheet - Detailed Description
Table 12. DCDC control2 Register
DCDC control2
Addr: 22h
This register controls the Step Up DC/DC Converter and low-voltage current
sinks CURR3x.
Bit
Bit Name
Default Access
Description
Step Up DC/DC Converter coil current limit
Normal current limit
Step up_lowcur
3
1
0
R/W
R/W
0
1
Current limit reduced by approx. 33%
step_up_fb select the feedback of the DCDC
converter
0
The feedback is automatically chosen withn the
current sinks CURR1, CURR2 and CURR6
(never DCDC_FB). Only those are used for this
selection, which are enabled (cuX_mode must
not be 00) and not connectd to he charge
pump (currX_on_cp mut be 0).
step_up_fb_auto
7
1
8.3
Charge Pump
The Charge Pump uses two external flying capacitors C3, C4 to enerae output voltages higer than the battery volt-
age. There are three different operating modes of the chapump itself:
ꢀ
ꢀ
ꢀ
1:1 Bypass Mode
- Battery input and output are connected by a low-impednce switch
- battery current = output current.
1:1.5 Mode
- The output voltage is up to 1.5 times thbatery voltage (witout ld), but is limited to VCPOUTmax all the time
- battery current = 1.5 times output curen.
1:2 Mode
- The output voltage is up to 2 tmehe battery voltage (wihout load), but is limited to VCPOUTmax all the time
- battery current = 2 times output rent
As the battery voltage decreases, the Charge Pump muswitched from 1:1 mode to 1:1.5 mode and eventually in
1:2 mode in order to provide enough supply for thcurrent sinks. Depending on the actual current the mode with best
overall efficiency can be automatically or manually eleted:
Examples:
ꢀ
ꢀ
ꢀ
Battery voltage = 3.7V, LED dropout vage = 3.5V. The 1:1 mode will be selected and there is 200mV drop on the
current sink and on the Charge Pump itch. Efficiency 95%.
Battery voltage = 3.5V, LED dopout voltage = 3.5V. The 1:1.5 mode will be selected and there is 1.5V drop on the
current sink and 250mV on the Chrge Pump. Efficiency 66%.
Battery voltage = 3.8V, LED ropout voltage = 4.5V (Camera Flash). The 1:2 mode can be selected and there is
600mV drop on the currensink and 2.5V on the Charge Pump. Efficiency 60%.
The efficiency is dependenon the LED forward voltage given by:
Eff=(V_LED*Iout)/(Uin*Iin)
(EQ 4)
The charge pump moe switching can be done manually or automatically with the following possible software settings:
ꢀ
ꢀ
ꢀ
Automatic up al modes allowed (1:1, 1:1.5, 1:2)
- Stith 1:1 mode
- Swih up automatically 1:1 to 1:1.5 to 1:2
utomatic up, but only 1:1 and 1:1.5 allowed
- Start with 1:1 mode
- Switch up automatically only from 1:1 to 1:1.5 mode; 1:2 mode is not used
Manual
- Set modes 1:1, 1:1.5, 1:2 by software
www.austriamicrosystems.com/AS3675
1v3
16 - 80
AS3675
Datasheet - Detailed Description
Figure 14. Charge Pump Pin Connections
!ꢂꢀꢀꢅꢃꢁ
ꢔꢂꢃꢖ
ꢀꢐꢗꢇ
ꢀꢐꢗꢅ
ꢀꢋꢗꢇ
ꢀꢋꢗꢅ
ꢀꢐ
ꢀꢄ
ꢀꢆ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢊ
ꢋꢌꢋꢍꢆꢋꢌꢋꢎꢏꢍꢆꢋꢌꢐ
ꢀꢇꢇꢈꢖ
ꢆꢆꢀꢏ
AS3675
The Charge Pump requires the external components listed in the flowing table:
Table 13. Charge Pump External Components
Symbol
Parameter
Coition
Min
Typ
Max
Unit
External Decoupling
Capacitor
Ceramic low-ESR capacitor betweepins
VAT and VSS.
C2
1.0
µF
Ceramilow-ESR capacor been pins
C1and C1_N, betweeins C2_P and
C2N and between VBAT and VSS
External Flying
Capacitor (2x)
C3, C4
C5
1.0
2.2
µF
µF
Ceramic low-ESR caacitobetween pins
OUT and VSS, pins COUT and VSS. Use
nominal 2.2µacitors (size 0603)
External Storage
Capacitor
Note: The connections of the external capacitors C2, C3, C4 and C5 should be kept as short as possible.
The maximum voltage on the flying apacitors C3 and C4 is VBAT.
Table 14. Charge Pump Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Unit
Output Currnt
Continuous
Depending on PCB layout
0.0
300
mA
ICPOUT
max. 200ms
VCPOUT=
VBAT * CPMODE – ILOAD * RCP
Output urrent
ulsed
0.0
60
500
mA
VCPOUTmax
Ouut Voltage
Efficiency
Internally limited, Including output ripple
5.6
90
V
Including current sink loss;
ICPOUT < 100mA.
η
%
ICP5
ICP1_2
Power Consumption
without Load
1:1.5 Mode
3.4
3.8
mA
1:2 Mode
fclk = 1 MHz
Rcp1_1
Rcp1_1.5
Rcp1_2
1:1 Mode; VBAT ≥ 3.5V
1:1.5 Mode; VBAT ≥ 3.3V
1:1.2 Mode; VBAT ≥ 3.1V
0.57
2.65
3.25
Effective Charge
Pump Output
Resistance (Open
Loop, fclk = 1MHz)
Ω
Accuracy of Clock
Frequency
fclk Accuracy
-10
10
%
www.austriamicrosystems.com/AS3675
1v3
17 - 80
AS3675
Datasheet - Detailed Description
Table 14. Charge Pump Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Unit
CURR1, 2, 6
minimum voltage
currhv_switch
0.45
V
CURR30-33, RGB1-
3, CURR41-3
If the voltage drops below this threshold, the
charge pump will use the next available
mode
0.2
0.4
V
V
minimum voltage
CURR30-33
0-75.6mA range
for strobe if
curr3x_strobe_high=
1
currlv_switch
(1:1 -> 1:1.5 or 1:1.5 -> 1:2)
cp_start_debounce=0
240
µse
ec
CP automatic up-
switching debounce
time
tdeb
After switching on CP (cp_on set to 1), if
cp_start_debounce=1
2000
8.3.1 Charge Pump Mode Switching
If automatic mode switching is enabled (cp_mode_switching (see page 20) = 00 or cp_mode_swithing = 01) the
charge pump monitors the current sinks, which are connected via a led o the output CPOUT. o identify these current
sources (sinks), the registers CP mode Switch1 and CP mode Switch2 (gister bits curr30_on_cp (see page 21) …
curr33_on_cp, rgb1_on_cp … rgb3_on_cp, curr1_on_cp, curr2_o_cp, curr41_on_cp … curr3_on_cp and
curr6_on_cp) should be setup before starting the charge p(cp_on (see page 20) = 1). If any of the voltage on
these current sources drops below the threshold (currlv_sw, currhv_switch), thnext higher mode is selected after
the debounce time.
To avoid switching into 1:2 mode (battery current = 2 times output current), st cp_mode_switching = 01.
If the currX_on_cp=0 and the according current sink is onnected to tharge pump, the current sink will be func-
tional, but there is no up switching of the chage ump, if the voltacoplince is too low for the current sink to sup-
ply the specified current.
www.austriamicrosystems.com/AS3675
1v3
18 - 80
AS3675
Datasheet - Detailed Description
Figure 15. Automatic Mode Switching
-)ꢈꢈꢒꢁ.
&-/0ꢄꢀ*ꢐ
ꢀꢑꢄ*
ꢀꢑ
ꢀꢋ
ꢀꢑꢄ,
ꢀꢐꢄ*
ꢀꢐꢄ,
ꢀꢂ)ꢁꢘꢒꢖ*ꢀ ꢏ
ꢔꢍꢕꢒꢖꢗꢆꢇꢈꢉꢂꢇꢎꢘ
ꢖ
ꢐꢙꢐꢖꢚꢛꢖꢐꢙꢐꢜꢝ
ꢐꢙꢐꢜꢝꢖꢚꢛꢖꢐꢙꢑ
ꢐꢙꢐ+ꢖꢐꢙꢐꢜꢝ+ꢖꢐꢙꢑ
ꢉꢏꢄ ꢍꢕꢒ!ꢐꢙꢌꢛ
ꢀ%
&ꢗꢗꢄꢀ*
ꢀꢉꢊꢋꢌ
ꢍꢍꢍꢍꢀꢎ
ꢀꢋꢏꢏꢑ
ꢀꢋꢏꢏꢐꢒ
ꢉꢀꢁꢁꢋꢌꢄꢍꢎꢄꢉꢏ
ꢉꢀꢁꢁꢋꢐꢄꢍꢎꢄꢉꢏ
ꢀꢋꢏꢏꢐꢓ
ꢀꢋꢏꢏꢐꢐ
ꢉꢀꢁꢁꢋꢑꢄꢍꢎꢄꢉꢏ
ꢉꢀꢁꢁꢋꢋꢍꢎꢄꢉꢏ
#1-ꢐ
#1-ꢑ
ꢁꢘꢓꢍꢎꢄꢉꢏ
ꢁꢘꢓꢑꢄꢍꢎꢄꢉꢏ
ꢁꢘꢓꢋꢄꢍꢎꢄꢉꢏ
#1-ꢋ
ꢞꢒꢓꢍꢀꢎꢉꢒ
ꢀ"##%ꢐ
ꢀ"##%ꢑ
ꢉꢀꢁꢁ%ꢄꢍꢎꢉꢏ
ꢉꢀꢁꢁ%ꢑꢄꢍꢎꢄꢉꢏ
ꢉꢀꢁꢁ%ꢋꢄꢍꢎꢄꢉꢏ
ꢀ"##%ꢋ
ꢑꢌꢌ &
'ꢉꢀꢁꢁ(ꢃꢄꢅꢆꢇꢈꢉꢂꢊ
ꢉꢀꢁꢁꢐꢄꢍꢎꢄꢉꢏ
ꢉꢀꢁꢁꢑꢄꢍꢎꢄꢉꢏ
ꢀꢋꢏꢏꢒ
ꢀꢋꢏꢏꢓ
ꢔꢎꢑꢕꢖ
ꢗꢘꢀꢁꢁꢂꢃꢄꢅꢆꢇꢈꢉꢂꢊ
ꢉꢀꢁꢁ$ꢄꢍꢎꢄꢉꢏ
ꢀ"##$
AS3675
8.3.2 Soft Start
An implemented soft start mechanism reduces the inrush current. Battery current is smoothed when switching the
charge pump on and also at each switching condition. This precaution reduces electromagnetic radiation significantly.
www.austriamicrosystems.com/AS3675
1v3
19 - 80
AS3675
Datasheet - Detailed Description
8.3.3 Charge Pump Registers
Table 15. Reg. control Register
Reg. control
This register controls the Charge Pump.
Default Access Description
Addr: 00h
Bit
Bit Name
Set Charge Pump into 1:1 mode (off state) unless
0
cp_auto_on is set
cp_on
2
0
R/W
1
Enable manual or automatic mode switching
Table 16. CP control Register
CP control
Addr: 23h
This register enables/disables the Charge Pump and the Step Up DC/DC
Converter.
Bit
Bit Name
Default Access
Description
Clock frequency sectio.
1 MHz
cp_clk
0
0
R/W
0
1
500 kz
rge Pump mode manual mode sets this mode, in
automatic modrepothe actual mode used)1
00
01
10
11
1:1 mode
cp_mode
2:1
00b
RW
1:1.5 mode
1:2 mode
NA
Set the mode switching algorithm
Automatic Mode switching; 1:1, 1:1.5 and 1:2
allowed
0
01
10
Automatic Mode switching; only 1:1 and 1:1.5
allowed
cp_mode_switching
4:3
00b
RW
Manual Mode switching; register cp_mode defines
the actual charge pump mode used
11
0
Reserved
Mode switching debounce timer is always 240µs
Upon startup (cp_on set to 1) the mode switching
debounce time is first started with 2ms then
reduced to 240µs
cp_start_debunc
cp_auto_on
5
6
0
0
R/W
R/W
1
0
Charge Pump is switched on/off with cp_on
Charge Pump is automatically switched on if a
current sink, which is connected to the charge
pump (defined by registers CP Mode Switch 1 & 2)
is switched on
1
1. Dect switching from 1:1.5 mode into 1:2 in manual mode and vice versa is not allowed. Always switch over 1:1
mode.
www.austriamicrosystems.com/AS3675
1v3
20 - 80
AS3675
Datasheet - Detailed Description
Table 17. CP mode Switch1 Register
CP mode Switch1
Setup which current sinks are connected (via leds) to the charge pump; if set to
‘1’ the correspond current source (sink) is used for automatic mode selection of
the charge pump
Addr: 24h
Bit
Bit Name
Default Access
Description
current Sink CURR30 is not connected to charge
pump
0
1
0
1
0
1
0
1
0
1
0
curr30_on_cp
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
current sink CURR30 is connected to charge pump
current Sink CURR31 is not connected to charge
pump
curr31_on_cp
curr32_on_cp
curr33_on_cp
rgb1_on_cp
rgb2_on_cp
rgb3_on_cp
1
2
3
4
5
6
current sink CURR31 is connected to charge pump
current Sink CURR32 is not connected to charge
pump
current sink CURR32 is connecteto carge pump
current Sink CURR33 is t conected to charge
pump
curret sink CURR33 s conected to charge pump
current Sink RGB1 is not connected to charge
pump
current sink GB1 is connected to charge pump
current Snk RGB2 is not connected to charge
pump
urrent sink RGB2 is connected to charge pump
current Sink RGB3 is not connected to charge
pump
current sink RGB3 is connected to charge pump
Table 18. CP mode Switch2 Register
CP mode Switch2
Setup hich current sinks are connected (via LEDs) to the charge pump; if set
t‘the correspond current source (sink) is used for automatic mode selection
of the charge pump
Addr: 25h
Bit
Bit Name
Default Access
Description
current Sink CURR1is not connected to charge
pump
0
1
0
1
0
1
0
1
curr1_on_p
0
0
0
0
0
R/W
R/W
R/W
R/W
current sink CURR1 is connected to charge pump
current Sink CURR2 is not connected to charge
pump
cur2_on_cp
curr41_on_cp
curr42_on_cp
1
2
3
current sink CURR2 is connected to charge pump
current Sink CURR41 is not connected to charge
pump
current sink CURR41 is connected to charge pump
current Sink CURR42 is not connected to charge
pump
current sink CURR42 is connected to charge pump
www.austriamicrosystems.com/AS3675
1v3
21 - 80
AS3675
Datasheet - Detailed Description
Table 18. CP mode Switch2 Register (Continued)
CP mode Switch2
Setup which current sinks are connected (via LEDs) to the charge pump; if set
to ‘1’ the correspond current source (sink) is used for automatic mode selection
of the charge pump
Addr: 25h
Bit
Bit Name
Default Access
Description
current Sink CURR43 is not connected to charge
pump
0
1
0
1
curr43_on_cp
curr6_on_cp
4
0
0
R/W
R/W
current sink CURR43 is connected to charge pump
current Sink CURR6 is not connected to charge
pump
7
current sink CURR6 is connected to charge ump
Table 19. Curr low voltage status1 Register
Curr low voltage status1
Indicates the low voltage status of the current sinks. the urrX_low_v bit is
set, the voltage on the urrensink is too low, to drive the selected output
current
Addr: 2Ah
Bit
Bit Name
Default Access
Description
0
1
0
1
0
0
1
0
1
0
1
0
1
voltage of cunt Sink CURR30 >currlv_switch
voltage ocrent Sink CURR30 <currlv_switch
voltage of current Sink CURR31 >currlv_switch
voge f current Sink CURR31 <currlv_switch
oltage of current Sink CURR32 >currlv_switch
voltage of current Sink CURR32 <currlv_switch
voltage of current Sink CURR33 >currlv_switch
voltage of current Sink CURR33 <currlv_switch
voltage of current Sink RGB1 >currlv_switch
voltage of current Sink RGB1 <currlv_switch
voltage of current Sink RGB2 >currlv_switch
voltage of current Sink RGB2 <currlv_switch
voltage of current Sink RGB3 >currlv_switch
voltage of current Sink RGB31 <currlv_switch
voltage of current Sink CURR6 >currlv_switch
voltage of current Sink CURR6 <currlv_switch
curr30_low_v
curr31_low_v
curr32_low_v
curr33_low_v
rgb1_low_v
rgb2_low_v
rgb3_low_v
curr6_lw_v
0
NA
NA
A
NA
NA
N
NA
NA
R
R
R
R
R
R
R
1
2
3
4
5
6
7
Table 20. Curlow voage status2 Register
Curr low voltage status2
Indicates the low voltage status of the current sinks. If the currX_low_v bit is
set, the voltage on the current sink is too low, to drive the selected output
current
Addr: 2Bh
Bit
Bit Name
curr1_low_v
Default Access
Description
0
1
voltage of current Sink CURR1 >currhv_switch
voltage of current Sink CURR1 <currhv_switch
0
NA
R
www.austriamicrosystems.com/AS3675
1v3
22 - 80
AS3675
Datasheet - Detailed Description
Table 20. Curr low voltage status2 Register (Continued)
Curr low voltage status2
Indicates the low voltage status of the current sinks. If the currX_low_v bit is
set, the voltage on the current sink is too low, to drive the selected output
current
Addr: 2Bh
Bit
Bit Name
Default Access
Description
0
1
0
1
0
1
0
1
voltage of current Sink CURR2 >currhv_switch
voltage of current Sink CURR2 <currhv_switch
voltage of current Sink CURR41 >currlv_switch
voltage of current Sink CURR41 <currlv_swith
voltage of current Sink CURR42 >currlv_sitch
voltage of current Sink CURR42 <currlv_swch
voltage of current Sink CURR43 >urrlv_switch
voltage of current Sink CURR43 currlv_switch
curr2_low_v
curr41_low_v
curr42_low_v
curr43_low_v
1
NA
NA
NA
NA
R
R
R
R
2
3
4
www.austriamicrosystems.com/AS3675
1v3
23 - 80
AS3675
Datasheet - Detailed Description
8.4
Current Sinks
The AS3675 contains general purpose current sinks intended to control RGB LEDs, white LEDs (e.g. backlights) and
can also be used for buzzers or vibrators. All current sinks have an integrated over voltage protection.
CURR1, CURR2 and CURR6 are also used as feedback for the Step Up DC/DC Converter (regulated to 0.5V in this
configuration) see Feedback Selection on page 12.
ꢀ
Current sinks CURR1, CURR2 and CURR6 are high-voltage compliant (15V) current sinks, used e.g., for series of
white LEDs
ꢀ
Current sinks CURR3x (CURR30, CURR31, CURR32 and CURR33) are parallel 5V current sinks, used for back-
lighting, indicator LEDs or RGB LEDs.
ꢀ
ꢀ
Current sinks RGB1, RGB2, and RGB3 are general purpose current sinks e.g. for a fun LED.
Current sinks CURR4x (CURR41, CURR42, and CURR43) are general purpose current sinks.
Table 21. Current Sink Function Overview
Max.
Current Sink Voltage
(V)
Max.
Current
(mA)
Resolution
Software
Current
Control
Can be assignto
Auio Controlled
LEChannel
Hardware On/Off
Control
(Bits)
(mA)
CURR1
ch1
ch2
ch3
LED Pattern;
Internal PWM
CURR2
CURR6
15.0
38.25
8
8
0.15
Searate
CURR30
CURR31
CURR32
38.25
Flash ED Strobe
(CUR1 or
CRR30) &
Prview
(CURR2);
Internal PWM;
ombined in
Strobe/
Preview
or
Completely individual
assignment of the
audio channels
ch1,ch2 and ch3 to the
outputs
(75.6mA
for strobe
if
curr3x_str
obe_high=
1)
0.15
Separate
LED Pattern
CURR33
RGB1
VBAT
(5.5V)
ch1
ch2
ch3
ch1
ch2
ch3
LED Pattern;
Internal PWM
RGB2
38.25
38.25
8
8
0.15
0.15
Searate
Separate
RGB3
CURR41
CURR42
CURR43
LED Pattern;
Internal PWM
www.austriamicrosystems.com/AS3675
1v3
24 - 80
AS3675
Datasheet - Detailed Description
8.4.1 High Voltage Current Sinks CURR1, CURR2, CURR6
The high voltage current sinks have a resolution of 8 bits. Additionally an internal protection circuit monitors with a volt-
age divider (max 3µA @ 15V) the voltage on CURR1, CURR2 and CURR6 and increases the current in off state in
case of over voltage.
Table 22. HV Current Sinks Characteristics
Symbol
IBIT7
Parameter
Condition
Min
Typ
19.2
9.6
Max
Unit
Current sink if Bit7 = 1
Current sink if Bit6 = 1
Current sink if Bit5 = 1
Current sink if Bit4 = 1
Current sink if Bit3 = 1
Current sink if Bit2 = 1
Current sink if Bit1 = 1
Current sink if Bit0 = 1
matching Accuracy
absolute Accuracy
IBIT6
IBIT5
4.8
IBIT4
2.4
For V(CURRx) > 0.45V
CURR1,CURR2,CURR6
mA
IBIT3
1.2
IBIT2
0.6
IBIT1
03
IBIT0
0.15
Δm
-10
-15
+10
+15
15
%
%
V
Δ
VCURR1,2,6x
Voltage compliance
Over voltage
0.45
At 13V, indepennt of curr1_prot_on,
curr2_prot_oor curr6_prot_on
Ov_prot_13V Protection of current
sink CURR1,2,6
3.0
4.0
µA
A1V, step_up_on=1,
curr1_prot_on=1 for CR1,
urr2_prot_on=1 or CR,
curr6_prot_on=1 foCURR6
Over voltage
Ov_prot_15V Protection of current
sink CURR1,2,6
0.8
mA
High Voltage Current Sinks CURRCURR2, CURR6 Rgisters
Table 23. Curr1 current Register
Curr1 current
Thiregister controls the High voltage current sink current.
Addr: 09h
Bit
Bit Name
DefauAccess
Description
Defines current into current sink curr1
00h
01h
....
0 mA
0.15 mA
....
curr1_curren
7:0
0
R/W
FFh
38.25 mA
www.austriamicrosystems.com/AS3675
1v3
25 - 80
AS3675
Datasheet - Detailed Description
Table 24. Curr2 current Register
Curr2 current
Addr: 0Ah
This register controls the High voltage current sink current.
Bit
Bit Name
Default Access
Description
Defines current into current sink curr2
00h
01h
....
0 mA
0.15 mA
....
curr2_current
7:0
0
R/W
FFh
38.25 mA
Table 25. curr6 current Register
curr6 current
Addr: 2Fh
This register controls the High voltage current sink curret.
Bit
Bit Name
Default Access
Description
Defies current into current ink CURR6
00h
....
0 A
0.15 mA
....
curr6_current
7:0
0
R/W
FFh
38.25 mA
Table 26. curr12 control Register
curr12 control
Addr: 01h
his register select the mode of the current sinks controls High voltage current
sink current.
Bit
Bit Name
Default Acces
Description
Select the mode of the current sink curr1
00b
01b
10b
11b
off
curr1_mode
on
PWM controlled
1:0
0
0
R/W
R/W
LED pattern controlled
Select the mode of the current sink curr2
off
00b
01b
10b
11b
curr2_mde
on
3:2
PWM controlled
LED pattern controlled
www.austriamicrosystems.com/AS3675
1v3
26 - 80
AS3675
Datasheet - Detailed Description
Table 27. curr rgb control Register
curr rgb control
Addr: 02h
This register select the mode of the current sinks CURR6.
Bit
Bit Name
Default Access
Description
Select the mode of the current sink CURR6
00b
01b
10b
11b
off
on
curr6_mode
7:6
0
R/W
PWM controlled
LED pattern controlled
Table 28. DCDC control2 Register
DCDC control2
Addr: 22h
This register controls the Step Up DC/DC Converter and lo-volge current
sinks CURR3x.
Bit
Bit Name
Default Access
Descriptio
0
0
1
0
1
No over voltage protection
Pull down current on CURR1 switched on, if
voltage CURR1 exceeds 13.75V, and
step_up_on=1
curr1_prot_on
4
0
0
0
R/W
R/W
R/W
Nover voltage protection
don current on CURR2 switched on, if
oltage exceeds on CURR2 13.75V, and
step_up_on=1
curr2_prot_on
curr6_prot_on
5
6
No over voltage protection
Pull down current on CURR6 switched on, if
voltage on CURR6 exceeds 13.75V, and
step_up_on=1
8.4.2 Current Sinks CURR30, CURR31, URR32, CURR33
These current sinks have a resolution of 8 its and can sink up to 38.25mA. The current values can be controlled indi-
vidually with curr30_current – curr33_current r common with curr3x_strobe or curr3x_preview.
Table 29. Current Sinks CURR30,31,3,3Parameters
Symbol
IBIT7
IBIT6
IBIT5
IBIT4
IBIT3
IBIT2
IB
IBIT0
Δm
Parameter
Condition
For V(CURR3x) > 0.2V
CURR30-33
Min
Typ
19.2
9.6
Max
Unit
Current sink if Bit= 1
Current sinif B6 = 1
Current nk if Bit5 = 1
rensink if Bit4 = 1
Currnt sink if Bit3 = 1
Crrent sink if Bit2 = 1
Current sink if Bit1 = 1
Current sink if Bit0 = 1
matching Accuracy
4.8
2.4
mA
1.2
0.6
0.3
0.15
-10
-15
0.2
0.4
+10
+15
%
%
Δ
absolute Accuracy
CPO
UT
VCURR3X
Voltage compliance
V
curr3x_strobe_high=1 and strobe function
www.austriamicrosystems.com/AS3675
1v3
27 - 80
AS3675
Datasheet - Detailed Description
Current Sinks CURR3x Registers
Table 30. Curr3 control2 Register
Curr3 control2
Addr: 12h
This register selects the modes of the current sinks30..33 current.
Bit
Bit Name
Default Access
Description
Select the switch off mode after strobe pulse
normal preview/strobe mode
0
1
preview_off_after strobe
0
0b
R/W
R/W
switch off preview after strobe duration has
expired. To reinitiate the torch mode the
preview_ctrl has to be set off and on agan
Preview is triggered by
off
00b
01b
software trigger (setting thibit utomatically
triggers previe)
preview_ctrl
2:1
00b
10b
11
CURR2 active higet gi_curr2_en=1
CURR2 active low; sepi_curr2_en=1
Double current on CURR0...CURR33
during strobe function
curr3x_strobe_high
strobe_pin
5
7
0b
R/W
R/W
0
1
normal trobe current (0-37.8mA)
oublstrobe current (0-75.6mA)
Select stronput pin and current sink outputs (only if
strobe_ctrl=10 or 11)
CURR1 is strobe input; CURR30...CURR33
0
0
flash output; set gpi_curr1_en=1
CURR30 is strobe input; CURR1, CURR2,
CURR6 flash output; set gpi_curr30_en=1
1
Table 31. Curr3 strobe control Register
Curr3 strobe control
Addr: 11h
his register selects the modes of the current sinks30..33 current.
Bit
Bit Name
Delt Access
Description
Strobe is triggered by
off
00b
01b
software trigger (setting this bit automatically
triggers strobe)
strobectrl
1:0
00b
R/W
CURR1 (or CURR30 see strobe_pin)
active high
10b
11b
CURR1 (or CURR30 see strobe_pin)
active low
Selects strobe mode
Mode1 (Tstrobe=Ts; strobe trigger signal ≥
00b
10µs)
strobe_mode
3:2
00b
R/W
01b
10b
11b
Mode 2 (Tstrobe=max Ts)
Mode 3 (Tstrobe = strobe signal)
not used
www.austriamicrosystems.com/AS3675
1v3
28 - 80
AS3675
Datasheet - Detailed Description
Table 31. Curr3 strobe control Register (Continued)
Curr3 strobe control
This register selects the modes of the current sinks30..33 current.
Addr: 11h
Bit
Bit Name
Default Access
Description
Selects strobe time (Ts)
100 msec
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000
100b
1010b
11b
100b
1101b
1110b
1111b
200 msec
300 msec
400 msec
500 msec
600 msec
700 mse
strobe_timing
7:4
0000b
R/W
800 msec
900 sec
1000 msec
1100 msec
1200 msec
1300 msec
1400 msec
1500 msec
1600 msec
Table 32. Curr3x strobe Register
Curr3x strobe
This egister selects the strobe current of the current sinks30..33
Addr: 0Eh
Bit
Bit Name
Default Access
Description
Defines Strobe current of Current sinks curr30-33
00h
01h
....
0 mA
curr3x_strobe
5:0
00
R/W
0.6 mA (1.2mA if curr3x_strobe_high=1)
....
3Fh
37.8 mA (75.6mA if curr3x_strobe_high=1)
Table 33. Curr3previw Register
Curr3x preview
Addr: 0Fh
This register selects the preview current of the current sinks30..33
Bit
Bit Name
Default Access
Description
Defines Preview current of Current sinks curr30-33
00h
01h
....
0 mA
0.6 mA
....
curr3x_preview
5:0
00
R/W
3Fh
37.8 mA
www.austriamicrosystems.com/AS3675
1v3
29 - 80
AS3675
Datasheet - Detailed Description
Table 34. Curr3x other Register
Curr3x other
Addr: 10h
This register selects the current of the current sinks30..33
Bit
Bit Name
Default Access
Description
Selects curr30 current, if curr30 is not used for strobe/
preview (curr30_mode=11b)
00h
01h
....
0 mA
0.6 mA
....
curr3x_other
5:0
00
R/W
3Fh
37.8 mA
Table 35. Curr30 current Register
Curr30 current
This register selects the current of the currensin30
Addr: 40h
Bit
Bit Name
Default Access
Descriptio
Selcts cur0 current, if cur30 is not used for strobe/
preview (curr3_moe=11b)
h
01h
....
0 mA
0.15 mA
....
curr30_current
7:0
00
R/W
FFh
38.25 mA
Table 36. Curr31 current Register
Curr31 current
This er selects the current of the current sink31
Addr: 41h
Bit
Bit Name
Default Access
Description
Selects curr30 current, if curr30 is not used for strobe/
preview (curr31_mode=11b)
00h
01h
....
0 mA
0.15 mA
....
curr31_current
7:0
R/W
FFh
38.25 mA
Table 37. Curr32 current Register
Curr32 current
This register selects the current of the current sink32
Addr: 42h
Bit
Bit Name
Default Access
Description
Selects CURR32 current, if CURR32 is not used for strobe/
preview (curr32_mode=11b)
00h
01h
....
0 mA
0.15 mA
....
curr32_current
7:0
00
R/W
FFh
38.25 mA
www.austriamicrosystems.com/AS3675
1v3
30 - 80
AS3675
Datasheet - Detailed Description
Table 38. Curr33 current Register
Curr33 current
Addr: 43h
This register selects the current of the current sink33
Bit
Bit Name
Default Access
Description
Selects curr33 current, if curr33 is not used for strobe/
preview (curr33_mode=11b)
00h
01h
....
0 mA
0.15 mA
....
curr33_current
7:0
00
R/W
FFh
38.25 mA
Table 39. curr3 control1 Register
curr3 control1
This register select the mode of the current sinks30 33
Addr: 03h
Bit
Bit Name
Default Access
Descriptio
Selecthe mode of thcurrent sink curr30
off
00b
1b
10b
strobe/preview
curr30_mode
1:0
0
0
0
R/W
R/W
R/W
curr30_currnt or curr3x_other PWM controlled
curr30current or curr3x_other - don’t use
curr3x_other if softdim_pattern=1, use
curr30_current instead
11b
Selct the mode of the current sink curr31
b
1b
10b
off
strobe/preview
curr31_mode
3:2
curr31_current or curr3x_other PWM controlled
curr31_current - don’t use curr3x_other if
softdim_pattern=1, use curr31_current instead
11b
Select the mode of the current sink CURR32
00b
01b
10b
off
strobe/preview
curr32_mode
5:4
curr32_current or curr3x_other PWM controlled
curr32_current or curr3x_other - don’t use
curr3x_other if softdim_pattern=1, use
curr32_current instead
11b
Select the mode of the current sink curr33
00b
01b
10b
off
strobe/preview
curr33_mode
7:6
0
R/W
curr33_current or curr3x_other PWM controlled
curr33_current or curr3x_other- don’t use
curr3x_other if softdim_pattern=1, use
curr33_current instead
11b
www.austriamicrosystems.com/AS3675
1v3
31 - 80
AS3675
Datasheet - Detailed Description
Table 40. Pattern control Register
Pattern control
Addr: 18h
This register controls the LED pattern
Description
Bit
Bit Name
Default Access
Additional CURR33 LED pattern control bit
CURR30 controlled according curr30_mode
curr30_pattern
4
0b
0b
0b
0b
R/W
R/W
R/W
R/W
0b
register
1b
CURR30 controlled by LED pattern generator
Additional CURR33 LED pattern control bit
CURR31 controlled according curr31_mode
register
curr31_pattern
curr32_pattern
curr33_pattern
5
6
7
0b
1b
CURR31 controlled by LED pattern genetor
Additional CURR33 LED patterconrol bit
CURR32 controlled accoding curr33_mode
reister
0b
1b
CRR32 controlled by LD pattern generator
ddiional CURR33 LED patern control bit
CURR33 ntrolled according curr33_pattern
register
b
1b
CURR33 cntrolled by LED pattern generator
8.4.3 Current Sinks RGB1, RGB2, RGB3
These current sinks have a resolution of 8 bs and can sink up to .25mA.
Table 41. Current Sinks RGB1, RGB2, RB3 Parameters
Symbol
IBIT7
IBIT6
IBIT5
IBIT4
IBIT3
IBIT2
IBIT1
IBIT0
Δm
Parameter
Conition
Min
Typ
19.2
9.6
Max
Unit
Current sink if Bit7 =
Current sink if Bit6 = 1
Current sink if Bit5 = 1
Current sink if Bit4 = 1
Current sink if Bit3 = 1
Current sink if Bit= 1
Current sink iBit1 = 1
Current snif Bit0 = 1
matching Accuracy
4.8
2.4
For V(RGBx) > 0.2V
RGB1, RGB2, RGB3
mA
1.2
0.6
0.3
0.15
-10
-15
+10
+15
%
%
Δ
bsolte Accuracy
CPO
UT
VRGBX
Voltage compliance
0.2
V
www.austriamicrosystems.com/AS3675
1v3
32 - 80
AS3675
Datasheet - Detailed Description
RGB Current Sinks Registers
Table 42. curr rgb control Register
curr rgb control
Addr: 02h
This register select the mode of the current sinks RGB1, RGB2, RGB3
Bit
Bit Name
Default Access
Description
Select the mode of the current sink RGB1
00b
01b
10b
11b
off
rgb1_mode
1:0
0
0
0
R/W
R/W
R/W
on
PWM controlled
LED pattern controlled
Select the mode of the current sink RGB2
00b
01b
10b
11b
off
rgb2_mode
rgb3_mode
3:2
5:4
on
PWM cotrolled
LED pattern controlled
Select the mode of the current sink RGB3
off
0b
01b
10b
11b
on
PWM controlled
LED pattern controlled
Table 43. Rgb1 current Register
Rgb1 current
Addr: 0Bh
Thiter controls the RGB current sink current.
Bit
Bit Name
Default Acess
Description
Defines current into Current sink RGB1
00h
01h
....
0 mA
0.15 mA
....
rgb1_current
7:0
R/W
FFh
38.25 mA
Table 44. Rgb2 current Rgister
Rgb2 current
Addr: 0Ch
This register controls the RGB current sink current.
Bit
Bit Name
Default Access
Description
Defines current into Current sink RGB2
00h
01h
....
0 mA
0.15 mA
....
rgb2_current
7:0
0
R/W
FFh
38.25 mA
www.austriamicrosystems.com/AS3675
1v3
33 - 80
AS3675
Datasheet - Detailed Description
Table 45. Rgb3 current Register
Rgb3 current
Addr: 0Dh
This register controls the RGB current sink current.
Bit
Bit Name
Default Access
Description
Defines current into Current sink RGB3
00h
01h
....
0 mA
0.15 mA
....
rgb3_current
7:0
0
R/W
FFh
38.25 mA
8.4.4 General Purpose Current Sinks CURR4x
These low voltage current sinks have a resolution of 8 bits and can sink up to 38.25mA.
Table 46. CURR4x Sinks Characteristics
Symbol
IBIT7
IBIT6
IBIT5
IBIT4
IBIT3
IBIT2
IBIT1
IBIT0
Δm
Parameter
Condition
Min
Typ
19.2
9.6
Max
Unit
Current sink if Bit7 = 1
Current sink if Bit6 = 1
Current sink if Bit5 = 1
Current sink if Bit4 = 1
Current sink if Bit3 = 1
Current sink if Bit2 = 1
Current sink if Bit1 = 1
Current sink if Bit0 = 1
matching Accuray
4.8
2.4
For V(CRRx) > 0.2V
CURRCURR2
mA
1.2
0.6
0.3
0.15
-10
-15
+10
+15
%
%
Δ
absolute Accuracy
CPO
UT
VCURR41,42,43x Voltage compliance
0.2
V
General Purpose Current Sinks CURR4Registers
Table 47. curr4 control Register
curr4 control
Addr: 04h
This register selects the mode of the current sinks CURR41, CURR42,
CURR43
Bit
Bit Nme
Default Access
Description
Select the mode of the current sink CURR41
00b
01b
10b
11b
off
on
crr41_mode
1:0
0
R/W
PWM controlled
LED pattern controlled
www.austriamicrosystems.com/AS3675
1v3
34 - 80
AS3675
Datasheet - Detailed Description
Table 47. curr4 control Register (Continued)
curr4 control
Addr: 04h
This register selects the mode of the current sinks CURR41, CURR42,
CURR43
Bit
Bit Name
Default Access
Description
Select the mode of the current sink CURR42
00b
01b
10b
11b
off
curr42_mode
3:2
0
0
R/W
R/W
on
PWM controlled
LED pattern controlled
Select the mode of the current sink CURR43
00b
01b
10b
11
off
on
curr43_mode
5:4
PWM ontroed
LED pattern ontrolled
Table 48. Curr41 current Register
Curr41 currnt
Addr: 13h
This register controls the curr1 current sink current.
Bit
Bit Name
Default Accs
Description
Defis crrent into Current sink CURR41
00h
1h
....
0 mA
0.15 mA
....
curr41_current
7:0
0
R/W
FFh
38.25 mA
Table 49. Curr42 current Register
Curr42 current
Addr: 14h
This register controls the curr42 current sink current.
Bit
Bit Name
Default Access
Description
Defines current into Current sink CURR42
00h
01h
....
0 mA
0.15 mA
....
curr42_curent
7:0
0
R/W
FFh
38.25 mA
www.austriamicrosystems.com/AS3675
1v3
35 - 80
AS3675
Datasheet - Detailed Description
Table 50. Curr43 current Register
Curr43 current
Addr: 15h
This register controls the curr43 current sink current.
Bit
Bit Name
Default Access
Description
Defines current into Current sink CURR43
00h
01h
....
0 mA
0.15 mA
....
curr43_current
7:0
0
R/W
FFh
38.25 mA
8.4.5 LED Pattern Generator
The LED pattern generator is capable of producing a pattern with 32 bits length and 1 second duration (31.25ms for
each bit). The pattern itself can be started every second, every 2nd, 3rd up to 7th second1.
With this pattern all current sinks can be controlled. The pattern itself switches the configured current surces between
0 and their programmed current.
If everything else is switched off, the current consumption in this mode iACTIVE. (excluding currnt through switched
on current source) and the charge pump, if required. The charge pmp cn be automaticlly swtched on/off depending
on the pattern (set register cp_auto_on on page 20=1) to ce the overall current consumption.
Figure 16. LED Pattern Generator AS3675 for pattern_colo= 0
%ꢆꢝꢉꢀꢆꢚꢂ"ꢁꢂ"ꢉꢇꢂꢉꢀꢇꢗꢆꢂꢈꢆꢇꢄ#ꢂꢅꢆ$ꢉꢈꢇꢆꢅꢂ#ꢙꢇꢇꢆꢅꢀ&ꢚꢙꢇ
ꢉꢀꢂꢇꢗꢉꢈꢂꢆ'ꢙꢘ#ꢛꢆꢂꢇꢂꢃꢜꢆꢂꢉꢈꢂꢋ ꢋꢋꢋ ꢋꢋꢔ
ꢕ
2ꢀꢁꢂꢃꢄꢅꢅꢆꢀꢇꢂꢈꢉꢀꢊ
ꢂ
ꢋ ꢌ ꢍ ꢎ ꢏ ꢐ ꢒ ꢓ
ꢍꢌ ꢋ ꢌ ꢍ ꢎ ꢏ ꢐꢑ ꢒ ꢓ
ꢔ
ꢔ
ꢇ
ꢍꢋꢔꢌꢏꢘꢈ
(ꢌꢏ ꢘꢈꢂꢉꢝꢂ#ꢙꢇꢇꢆꢅꢀ&ꢈꢛꢜ)*ꢋ+
ꢖꢇꢂꢇꢗꢉꢈꢂꢇꢉꢘꢆꢂꢜꢝꢂ ꢈ!ꢋꢈ!ꢌꢈ!ꢔꢔꢔ!ꢒꢈ!ꢋꢐꢈ!ꢌꢎꢈ!ꢍꢌꢈ!ꢎ ꢈ!ꢎꢒꢈ!ꢏꢐꢈ
ꢃꢙꢀꢂ"ꢆꢂ#ꢅꢜ$ꢚ
To select the different current sinks to be controlled y the LED pattern generator, see the ‘xxxx’_mode registers
(where ‘xxxx’ stands for the to be controlled urrent sink, e.g. curr1_mode for CURR1 current sink). See also the
description of the different current sinks.
To allow the generator of a color patterns the bit pattern_color to ‘1’. Then the pattern can be connected to CURRx
as follows:
Figure 17. LED Pattern Generaor AS3675 for pattern_color = 1
%ꢘꢕꢔꢚꢘ&ꢓ'(ꢓ'ꢔꢎꢓꢔꢚꢓꢎ)ꢘꢓꢐꢘꢎ*ꢖꢓꢙꢘ+ꢔꢐꢎꢘꢙꢓꢖꢗꢎꢎꢘꢙꢚꢛ&ꢗꢎꢗ
ꢔꢚꢓꢎ)ꢔꢐꢓꢘ,ꢗꢏꢖꢜꢘꢓꢎ)ꢘꢓ-ꢝ&ꢘꢓꢔꢐꢓꢆꢆꢆꢆꢆꢁꢁꢁꢆꢁꢆꢆꢆꢆꢆꢁꢁꢁꢆꢆꢁꢆꢆꢆꢎꢎꢎ
ꢍ
ꢎꢎꢎ
ꢎꢎꢎ
ꢎꢎꢎ
ꢀꢂ33ꢁ"ꢀꢂ3ꢀꢁꢂꢀꢃꢄꢄꢅꢆꢂꢄꢇꢈꢆ
ꢀꢃꢄꢄꢉꢂꢀꢃꢄꢀꢃꢄꢄꢅꢉꢂꢄꢇꢈꢉ
ꢃꢄꢄꢃꢄꢀꢉꢋꢀꢀꢂꢀꢃꢄꢄꢅꢀꢂꢄꢇꢈꢀ
ꢆ ꢅ #
ꢉꢒ ꢆ ꢅ #
ꢎꢎꢎ
ꢉ $ ꢒ
ꢀ ꢊ ꢌ
ꢉꢌ ꢉ $ ꢒ
ꢀꢁ ꢀ ꢊ ꢌ
ꢎꢎꢎ
ꢎꢎꢎ
ꢎ
ꢆꢁꢁꢏꢐ
ꢑꢒꢁꢁꢏꢐꢓꢔꢕꢓꢖꢗꢎꢎꢘꢙꢚꢛꢐꢜꢝ !ꢆ"
.ꢎꢓꢎ)ꢔꢐꢓꢎꢔꢏꢘꢓꢗꢓ&ꢘꢜꢗ(ꢓꢝꢕꢓꢁꢐꢋꢆꢐꢋꢉꢐꢋꢎꢎꢎꢋꢒꢐꢋꢆꢊꢐꢋꢉꢅꢐꢋꢀꢉꢐꢋꢅꢁꢐꢋꢅꢒꢐꢋ$ꢊꢐ
-ꢗꢚꢓ'ꢘꢓꢖꢙꢝ+ꢙꢗꢏꢏꢘ&
1. All times can be extended by a factor of 8 by setting pattern_slow=1 (this result in a delay of up to 56s)
www.austriamicrosystems.com/AS3675
1v3
36 - 80
AS3675
Datasheet - Detailed Description
Only those current sinks will be controlled, where the ‘xxxx’_mode register is configured for LED pattern.
If the register bit pattern_slow is set, all pattern times are increased by a factor of eight. (bit duration: 250ms if
pattern_color=0 / 800ms if pattern_color=1, delays between pattern up to 56s).
Soft Dimming for Pattern
The internal pattern generator can be combined with the internal pwm dimming modulator to obtain as shown in the fol-
lowing figure:
Figure 18. Soft dimming Architecture for the AS3675 (softdim_pattern=1 and pattern_color = 1)
ꢙꢂꢅ
ꢆꢎꢅ
ꢆꢎꢅ
ꢆꢎꢅ
ꢌꢘ
ꢃꢂꢙꢂꢅ ꢙꢕꢈꢍꢋꢙꢕꢆꢍ
ꢚꢛꢌꢌꢜꢝꢚꢛꢌꢌ !ꢝꢚꢛꢌꢌ"ꢜꢝꢌꢁ#ꢜ
ꢚꢛꢌꢌ$ꢝꢚꢛꢌꢌ ꢜꢝꢚꢛꢌꢌ"$ꢝꢌꢁ#$
ꢚꢛꢌꢌ%ꢝꢚꢛꢌ $& ꢚꢛꢌꢌ" ꢝꢌꢁ#
ꢙꢂꢅ
ꢌꢘ
ꢃꢂꢙꢂꢅ ꢙꢕꢈꢍꢋꢙꢕꢆꢍ
/ꢁꢂꢂꢃꢄꢀ
ꢁꢂꢀꢂꢃꢄꢅꢆꢃ
ꢙꢂꢅ
ꢌꢘ
ꢃꢂꢙꢂꢅ ꢙꢕꢈꢍꢋꢙꢕꢆꢍ
ꢖꢂꢃꢆ
ꢇꢂꢅꢂꢗꢅ
ꢗꢆꢀꢅꢃꢕꢙꢋꢗꢂꢀꢅꢋꢙꢆꢎꢃꢗꢂꢙꢋ'ꢆꢀꢝꢆ(()ꢋ(ꢆꢃ
ꢗꢎꢃꢃꢂꢀꢙꢆꢎꢃꢂꢋꢐ*ꢂꢃꢂ
ꢋꢗꢎꢃꢃ+,ꢉꢏꢂꢋ-ꢋ./ꢇꢋꢍꢄꢅꢅꢂꢃꢀ
ꢇꢈꢉꢉꢈꢀꢊꢋꢋꢋ
ꢌꢄꢉꢍ
ꢁꢂꢀ
ꢎꢍꢋꢏꢆꢐꢀ
ꢒꢓ
ꢔꢆꢏꢎꢕꢄꢃ
ꢑ
With the AS3675 smooth fade-in and fade-out effects cn be automaticgenerated.
As there is only one dimming ramp generatoanone pwm moduor flowing constraints have to be considered
when setting up the pattern (applies only ipaern_color=1):
Figure 19. Soft dimming example Wavorm for CURR30-32
ꢑꢊꢔꢔꢍꢈꢕꢊꢖꢋꢊꢗꢀꢂꢃꢃꢀꢅꢘꢊꢙꢚꢈꢊꢎꢐ
ꢌꢉꢚꢜꢉꢐꢛꢊꢉꢝꢐꢊꢓꢍꢔꢔꢍꢈꢕꢊ
ꢓꢆꢒꢈꢊꢗꢀꢂꢃꢃꢀꢁꢘꢊꢍꢌꢊꢜꢍꢈꢍꢌꢝꢐꢓ
ꢀꢃꢄꢄꢀꢁ
ꢆꢇ
ꢀꢂꢃꢃꢀꢄ
ꢀꢂꢃꢃꢀꢅ
ꢆꢇ
ꢈꢆꢉꢊꢋꢆꢌꢌꢍꢎꢏꢐ
ꢑꢊꢈꢐꢒꢊꢓꢍꢔꢔꢍꢈꢕꢊꢖꢋꢊꢗꢀꢂꢃꢃꢀꢅꢘꢊꢙꢚꢈꢈꢆꢉꢊꢎꢐ
ꢌꢉꢚꢛꢉꢐꢓꢊꢚꢜꢉꢐꢛꢊꢆꢛꢊꢒꢝꢍꢏꢐꢊꢆꢈꢐꢊꢙꢝꢚꢈꢈꢐꢏꢊꢗꢀꢂꢃꢃꢀꢁꢘ
ꢍꢌꢊꢓꢍꢔꢔꢍꢈꢕꢊꢖꢋ
However ng the identical dimming waveform for two channels is possible as shown in the following figure:
www.austriamicrosystems.com/AS3675
1v3
37 - 80
AS3675
Datasheet - Detailed Description
Figure 20. Soft dimming example Waveform for CURR30-32
ꢂꢃꢄꢄꢅꢆ
ꢂꢃꢄꢄꢅꢇ
ꢂꢃꢄꢄꢅꢈ
ꢀ
ꢁꢀ
ꢁꢀ
LED Pattern Registers
Table 51. Pattern data0...Pattern data3 Registers
Pattern data0, Pattern data1, Pattern data2, Pattern data3
Addr: 19h,1Ah,1Bh,1Ch
This registers contains the pattern data for the current sinks.
Bit
Bit Name
Default Access
Description
pattern_data[7:0]1
7:0
7:0
7:0
7:0
0
0
0
0
R/W
R/W
R/W
R/W
Pattern data0
pattern_data[15:8]11111
pattern_data[23:16]11111
pattern_data[31:24]11111
Pattern dat
Pattern data
Pattern data3
1. Update any of the pattern register only if none of the curret sources is conneced to the pattern generator
('xxxx'_mode must not be 11b). The pattern generator is automatically startd at the same time when any of the
current sources is connected to the pattern generato
Table 52. Pattern control Register
Pattern control
Addr: 18h
is register controls the LED pattern
Bit
Bit Name
Default Access
Description
Defines the pattern type for the current sinks
single 32 bit pattern (also set currX_mode = 11)
0b
1b
pattern_color
0
0
R/W
R/W
R/W
RGB pattern with each 10 bits (set all
currX_mode = 11)
Delay between pattern, details (see Table 55); together with
pattern_delay2 sets the delay time between patterns
pattern_delay
2:1
3
00b
0b
Enable the ‘soft’ dimming feature for the pattern generator
Pattern generator directly control current
softdim_pttern1
0
sources
1
‘Soft Dimming’ is performed (see page 37)
1. If softdim_ptter=1, don’t set curr30_mode, curr31_mode, curr32_mode or curr33_mode to 11b.
Tble 53. gpo current Register
Addr: 2Ch
Bit Name
gpio current
Description
Bit
Default Access
Delay between pattern (see Table 55 on page 39); together
with pattern_delay sets the delay time between patterns
pattern_delay2
4
0
R/W
www.austriamicrosystems.com/AS3675
1v3
38 - 80
AS3675
Datasheet - Detailed Description
Table 53. gpio current Register (Continued)
Addr: 2Ch
gpio current
Description
Bit
Bit Name
Default Access
Pattern timing control
normal mode
0b
1b
pattern_slow
6
0
R/W
slow mode (all pattern times are increased by a
factor of eight)
Table 54. Pattern End Register
Addr: 54h
Pattern End
Description
Bit
Bit Name
Default Access
pattern_end is toggled from 0 to 1 (or from 1 to 0) at ach
end of the pattern just before restarting f the internal
pattern generator at the first bit of te paern data
(can be used to synchronize the basebansoftware to the
pattern_end
0
0
R
pattern genertor)
1. pattern_end toggles whenever the AS3675 is in active mode ee Secon 8.12 Operaing Modes on page 71)
even if no pattern data has been setup.
Table 55. LED Pattern timing
pattern_delay2 pattern_delay[1..0]
bit duratin [m]
pattern
duration [s]
(total cycle
time:
pattern +
delay)
delay[s]
between
patterns
pattern_slow
delay between pattens
pattern_lorpattern_color=1
01
1
0
0
00
31
100
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
1
1
1
1
01
10
11
0
1
10
11
00
01
10
11
00
01
10
11
31
31
100
100
100
100
100
100
100
800
800
800
800
800
800
800
800
2
3
2
31
3
4
31
4
5
31
5
6
31
6
7
31
7
8
250
250
250
250
250
250
250
250
0
8
8
16
24
32
40
48
56
64
16
24
32
40
48
56
1. Even by setting 000 for pattern delay, there is a small delay before the new patterns starts.
8.4.6 PWM Generator
www.austriamicrosystems.com/AS3675
1v3
39 - 80
AS3675
Datasheet - Detailed Description
The PWM generator can be used for any current sink. The setting applies for all current sinks, which are controlled by
the pwm generator (e.g. CURR1 is pwm controlled if curr1_mode = 10). The pwm modulated signal can switch on/off
the current sinks and therefore depending on its duty cycle change the brightness of an attached LED.
Internal PWM Generator
The internal PWM generator uses the 2MHz internal clock as input frequency and its dimming range is 6 bits digital
(2MHz / 2^6 = 31.3kHz pwm frequency) and 2 bits analog. Depending on the actual code in the register pwm_code the
following algorithm is used:
If pwm_code bit 7 = 1
Then the upper 6 bits (Bits 7:2) of pwm_code are used for the 6 bits PWM generation, which controls the selected cu
rents sinks directly
If pwm_code bit 7 =0 and bit 6 = 1
Then bits 6:1 of pwm_code are used for the 6 bits PWM generation. This signal controls the selected current sins, but
the analog current of these sinks is divided by 2
If pwm_code bit 7 and bit 6 = 0
Then bits 5:0 of pwm_code are used for the 6 bits PWM generation. This signal controls the selected currnt sinks, but
the analog current of these sinks is divided by 4
Figure 21. PWM Control
ꢖꢗꢗꢆꢘꢒꢈꢙꢑꢘꢚꢛꢙꢜꢈꢐꢖꢘꢝ ꢄ!
ꢃꢖꢗꢗꢆꢘꢒꢙꢈꢝꢗꢆꢈꢅꢑ"ꢑꢅꢆꢅꢈꢐꢋ
ꢏ
ꢏ
ꢏ
ꢉꢈꢐꢑꢒꢈꢓꢔꢕ
ꢉꢈꢐꢑꢒꢈꢓꢔꢕ
ꢒꢄꢈꢃꢖꢗꢗꢆꢘꢒꢈꢙꢑꢘꢚꢛꢜꢈꢐꢖꢒꢘꢝ ꢄ!
ꢃꢖꢗꢗꢆꢘꢒꢙꢈꢝꢗꢆꢈꢅꢑ"ꢆꢅꢈꢐ#ꢈꢍ
ꢒꢄꢈꢗꢆꢘꢘꢚꢜ
ꢉꢈꢐꢑꢒꢈꢓꢔꢕ
ꢇꢈꢈꢉꢈꢈꢊꢈꢈꢋꢈꢈꢌꢈꢈꢍꢈꢈꢏ
ꢙꢀꢁꢂꢃꢆ
Automatic Up/Down Dimming
If the register pwm_dim_mode is set to 01 (up diming) or 10 (down dimming) the value within the register pwm_code
is increased (up dimming) or decreased (don dimming) every time and amount (either 1/4th or 1/8th) defined by the
register pwm_dim_speed. The maximum alue of 255 (completely on) and the minimum value of 0 (off) is never
exceeded. It is used to smoothly and atoically dim the brightness of the LEDs connected to any of the current
sinks. The PWM code is readable all the e (also during up and down dimming).
The waveform for up dimming loos as ollows (cycles omitted for simplicity):
Figure 22. PWM Dimming Wveform for up dimming (pwm_dim_mode = 01); currX_mode = PWM controlled (not
all steps show
$
ꢁꢂꢃꢃꢄꢅꢁꢂꢃꢃꢆꢇꢀ
ꢈꢉꢊ
ꢈꢉꢋ
ꢀ
ꢇꢆꢘꢀꢌꢙꢀꢆꢐꢚꢌꢈꢉꢊꢌꢍꢎꢀꢏ
ꢛꢓꢔꢌꢕꢂꢀꢖꢌꢁꢖꢁꢗꢆ
ꢈꢉꢋꢌꢍꢎꢀꢏꢌꢂꢐꢌꢀꢑ
ꢒꢓꢓꢔꢌꢕꢂꢀꢖꢌꢁꢖꢁꢗꢆ
The internal pwm modulator circuit controls the current sinks as shown in the following figure:
www.austriamicrosystems.com/AS3675
1v3
40 - 80
AS3675
Datasheet - Detailed Description
Figure 23. PWM Control Circuit (currX_mode = 10b (PWM controlled)); X = any current sink
ꢗꢃꢃꢍꢈꢙ)ꢂ! ꢊ
ꢊꢄꢈꢈꢋꢌꢆꢃꢃꢍꢈ
ꢊꢄꢈꢈꢋꢌꢊꢄꢈꢈꢍꢎꢇ
ꢝ
ꢘꢝꢜꢜꢋ
ꢏꢐ
ꢏꢑ
ꢕꢖꢗꢘꢙꢙꢙ
ꢉ
ꢝ
ꢝ
ꢝ
#ꢈꢂꢔꢙ$ꢍꢈ ꢆꢅ
ꢕꢎꢇꢍꢈ%ꢆꢊꢍ
ꢝ
$ꢄ&ꢋꢌꢍꢎ
ꢒꢓꢔꢌꢊꢂꢃꢍ
ꢒꢀꢁ
ꢁꢂꢃꢄꢅꢆꢇꢂꢈ
ꢆꢃꢃꢍꢈꢌꢊꢄꢈꢈꢍꢎꢇꢋ
ꢐꢁꢚꢛ
AS3675
ꢖ ꢔꢔ ꢎ!ꢙꢙꢙ
ꢜꢆꢔꢒ
"ꢍꢎ
%ꢙꢒꢓꢔꢌꢃ ꢔꢌꢔꢂꢃꢍꢙ'ꢙꢉ(ꢙꢂꢈꢙ(ꢉ
The adder logic (available for all current sinks) is intended to allow dimming not only from 0% to 10% (o100% to 0%)
of currX_current, but also e.g. from 10% to 110% (or 110% to 10%) of currX_current. The starting cuent or up dim-
ming is defined by 0 + currX_adder and the end current is defined by currX_current + currX_adde
An overflow of the internal bus (8 Bits wide to the IDAC) has to e avod by the register settins (currX_current +
currX_adder must not exceed 255).
If the register subX_en is set, the result from the pwm motor is inverted logically. That means for up dimming the
starting current is defined by currX_adder - 1 and the end nt is defined by cX_adder - currX_current - 1. An
overflow of the internal bus (8 Bits wide to the IDAC) has to e avoided by the registr settings (currX_adder -
currX_current - 1 must not be below zero).
Its purpose is to dim one channel e.g. CURR30 frm e.. 110% to 10% ocurr3_current and at the same time dim
another channel e.g. CURR31 from 20% to 120% of curr31_current.
Note: The adder logic operates indepenent of the currX_mode setng, but its main purpose is to work together with
the pwm modulator (improved up/dwn dimming)
If the adder logic is not used aore, set the bit rX_dder to 0. (Setting adder_currentX to 0 is not suffi-
cient)
At the end of up/down dimming, the pwm_code register keeps its final value (for up-dimming 255 and for down-
dimming 0). This can be used to identify thexact time, when up/down dimming is finished.
Table 56. PWM Dimming Table
Decrease by 1/4th
every step
ecrease by 1/8th
every step
Seconds
Seconds
Seconds
Seconds
50msec/
Step
25msec/
Step
5msec/
Step
2.5msec/
Step
Step
%Dimming
PW
%Dimming
PWM
1
2
100,0
75,3
,5
42,4
31,8
23,9
18,0
13,7
10,6
8,2
25
192
144
108
81
100,0
87,8
76,9
67,5
59,2
52,2
45,9
40,4
35,7
31,4
27,5
255
224
196
172
151
133
117
103
91
0,00s
0,05s
0,10s
0,15s
0,20s
0,25s
0,30s
0,35s
0,40s
0,45s
0,50s
0,00s
0,03s
0,05s
0,08s
0,10s
0,13s
0,15s
0,18s
0,20s
0,23s
0,25s
0,000s
0,005s
0,010s
0,015s
0,020s
0,025s
0,030s
0,035s
0,040s
0,045s
0,050s
0,000s
0,003s
0,005s
0,008s
0,010s
0,013s
0,015s
0,018s
0,020s
0,023s
0,025s
3
4
5
6
61
7
46
8
35
9
27
10
11
21
80
6,3
16
70
www.austriamicrosystems.com/AS3675
1v3
41 - 80
AS3675
Datasheet - Detailed Description
Table 56. PWM Dimming Table
Decrease by 1/4th
every step
Decrease by 1/8th
every step
Seconds
Seconds
Seconds
Seconds
50msec/
Step
25msec/
Step
5msec/
Step
2.5msec/
Step
Step
%Dimming
PWM
%Dimming
PWM
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
4,7
3,5
2,7
2,4
2,0
1,6
1,2
0,8
0,4
0,0
12
9
7
6
5
4
3
2
1
0
24,3
21,6
19,2
16,9
14,9
13,3
11,8
10,6
9,4
62
55
49
43
38
34
30
27
24
21
19
1
14
13
12
11
10
0,55s
0,60s
0,65s
0,70s
0,75s
0,80s
0,85s
0,90s
0,95s
1,00s
1,5s
1,10s
1,15s
1,20s
1,2
1,s
,35s
1,40s
1,45s
1,50s
1,55s
1,60s
1,65s
1,70s
1,75s
1,80s
1,85s
1,90s
0,28s
0,30s
0,33s
0,35s
0,38s
0,40s
0,43s
0,45s
0,48s
0,50s
0,53s
0,55s
,58s
0,60s
0,63s
0,65s
0,68s
0,70s
0,73s
0,75s
0,78s
0,80s
0,83s
0,85s
0,88s
0,90s
0,93s
0,95s
0,055s
0,060s
0,065s
0,070s
0,075s
0,080s
0,085s
0,90s
0095s
0,10s
0,105s
0,110s
0,115s
0,120s
0,125s
0,130s
0,135s
0,140s
0,145s
0,150s
0,155s
0,160s
0,165s
0,170s
0,175s
0,180s
0,185s
0,190s
0,028s
0,030s
0,033s
0,035s
0,03s
0,040s
0,043s
0,045s
0,048s
0,050s
0,053s
0,055s
0,058s
0,060s
0,063s
0,065s
0,068s
0,070s
0,073s
0,075s
0,078s
0,080s
0,083s
0,085s
0,088s
0,090s
0,093s
0,095s
8,2
7,5
6,7
5,9
5,5
5,1
,7
4,
3,9
3,5
3,1
2,7
7
2,4
6
2,0
5
1,6
4
1,2
3
0,8
2
0,4
1
0,0
0
www.austriamicrosystems.com/AS3675
1v3
42 - 80
AS3675
Datasheet - Detailed Description
PWM Generator Registers
Table 57. Pwm control Register
Pwm control
This register controls PWM generator
Description
Addr: 16h
Bit
Bit Name
Default Access
Selects the dimming mode
no dimming; actual content of register
00b
01b
pwm_code is used for pwm generator
logarithmic up dimming (codes are increased)
Start value is actual pwm_code
pwm_dim_mode
2:1
00b
R/W
logarithmic down dimming (codes ar
decreased). Start value is actual pwm_ce;
switch off the dimmed curret source after
dimming is finished to avoid unecessary
quiescent currnt
10b
11b
NA
Defins dimng speed by increase/ecrease pwm_code
by 1/4th every 50 msec (total dim time 1.0s)
000b
by 1/8th evry 50 msec (total dim time 1.9s)
1b
by 1th evry 25 msec (total dim time 0.5s)
010b
1/8th every 25 msec (total dim time 0.95s)
011b
pwm_dim_speed
5:3
000b
R/W
by 1/4th every 5 msec (total dim time 100ms)
100b
by 1/8th every 5 msec (total dim time 190ms)
11b
by 1/4th every 2.5 msec (total dim time 50ms)
10b
by 1/8th every 2.5 msec (total dim time 95ms)
111b
Table 58. pwm code Register
pwm code
This register controls the Pwm code.
Description
Addr: 17h
Bit
Bit Name
efault Access
Selects the PWM code
00h
....
0% duty cycle
....
pwm_coe
7:0
00b
R/W
FFh
100% duty cycle
www.austriamicrosystems.com/AS3675
1v3
43 - 80
AS3675
Datasheet - Detailed Description
Table 59. Adder Current 1 Register
Adder Current 1
Addr: 30h
This register defines the current which can be added to CURR1, CURR30,
CURR41, RGB1
Bit
Bit Name
Default Access
Description
Selects the added current value – do not exceed together
with currX_current the internal 8 Bit range (see text)
00h
....
0 (represents 0mA)
....
adder_current1
7:0
00b
R/W
FFh
255 (represents 38.25mA)
Table 60. Adder Current 2 Register
Adder Current 2
Addr: 31h
This register defines the current which can be added to CUR2, CURR31,
CURR42, RGB2
Bit
Bit Name
Default Access
Description
Selecthe aded current vaue – do not exceed together
with crrX_current the internal 8 Bit range (see text)
h
....
0 (represents 0mA)
....
adder_current2
7:0
00b
R/W
FFh
255 (represents 38.25mA)
Table 61. Adder Current 3 Register
Adder Current 3
Addr: 32h
This register defines te current which can be added to CURR6, CURR32,
CURR43, RGB3
Bit
Bit Name
Default Access
Description
Selects the added current value – do not exceed together
with currX_current the internal 8 Bit range (see text)
00h
....
0 (represents 0mA)
....
adder_current3
7:0
00b
R/W
FFh
255 (represents 38.25mA)
Table 62. Adder Current 4 Regier
Adder Current 4
This register defines the current which can be added to CURR33
Addr: 52h
Bit
it Name
Default Access
Description
Selects the added current value – do not exceed together
with currX_current the internal 8 Bit range (see text)
00h
....
0 (represents 0mA)
....
adder_current4
7:0
00b
R/W
FFh
255 (represents 38.25mA)
www.austriamicrosystems.com/AS3675
1v3
44 - 80
AS3675
Datasheet - Detailed Description
Table 63. Adder Enable 1 Register
Adder Enable 1
Addr: 33h
Enables the adder circuit for the selected current sources
Bit
Bit Name
Default Access
Description
Enables adder circuit for current source RGB1
Normal Operation of the current source
0
1
rgb1_adder
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
/W
R/W
adder_current1 gets added to the current
source current
Enables adder circuit for current source RGB2
Normal Operation of the current source
0
1
rgb2_adder
rgb3_adder
1
2
3
4
5
adder_current2 gets added to the currnt
source current
Enables adder circuit for current ourcRGB3
Normal Operation of the cuent source
0
1
adder_current3 getdded to the current
source curent
Enbles adder circuit for urret source CURR41
Normaperation of the current source
curr41_adder
curr42_adder
curr43_adder
addercurre1 gets added to the current
source current
1
Enables er crcuit for current source CURR42
0
Nrmal Operation of the current source
adder_current2 gets added to the current
source current
1
Eables adder circuit for current source CURR43
Normal Operation of the current source
adder_current3 gets added to the current
source current
Table 64. Adder Enable 2 Register
Adder Enable 2
Addr: 34h
Enables the adder circuit for the selected current sources
Bit
Bit Name
Default Access
Description
Enables adder circuit for current source CURR1
Normal Operation of the current source
0
1
crr1adder
0
0
0
0
R/W
R/W
R/W
adder_current1 gets added to the current
source current
Enables adder circuit for current source CURR2
Normal Operation of the current source
0
1
curr2_adder
curr6_adder
1
2
adder_current2 gets added to the current
source current
Enables adder circuit for current source CURR6
Normal Operation of the current source
0
1
adder_current3 gets added to the current
source current
www.austriamicrosystems.com/AS3675
1v3
45 - 80
AS3675
Datasheet - Detailed Description
Table 64. Adder Enable 2 Register (Continued)
Adder Enable 2
Addr: 34h
Enables the adder circuit for the selected current sources
Bit
Bit Name
Default Access
Description
Enables adder circuit for current source CURR30
0
Normal Operation of the current source
curr30_adder
3
0
0
0
0
R/W
R/W
R/W
R/W
adder_current1 gets added to the current
source current
1
Enables adder circuit for current source CURR31
0
Normal Operation of the current source
curr31_adder
curr32_adder
curr33_adder
4
5
6
adder_current2 gets added to the currnt
source current
1
Enables adder circuit for current surce CURR32
0
Normal Operation of the cuent source
adder_current3 getdded to the current
source curent
1
Enbles adder circuit for urret source CURR33
Normaperation of the current source
addercurre4 gets added to the current
source current
1
Table 65. Subtract Enable Register
Subtract Enable
Addr: 35h
Enable the inversiofrom the signal from the pwm generator
Bit
Bit Name
fault Access
Description
Inverts the signal from the pwm generator
Direct Operation (no inversion)
0
1
sub_en1
0
0
0
0
R/W
R/W
R/W
The signal from the pwm generator for which
the adder is enabled (curr1_adder = 1,
curr30_adder = 1, rgb1_adder = 1,
curr41_adder = 1) is inverted
Inverts the signal from the pwm generator
Direct Operation (no inversion)
0
1
sub_en
sub_en3
1
2
The signal from the pwm generator for which
the adder is enabled (curr2_adder = 1,
curr31_adder = 1, rgb2_adder = 1,
curr42_adder = 1) is inverted
Inverts the signal from the pwm generator
Direct Operation (no inversion)
0
1
The signal from the pwm generator for which
the adder is enabled (curr6_adder = 1,
curr32_adder = 1, rgb3_adder = 1,
curr43_adder = 1) is inverted
www.austriamicrosystems.com/AS3675
1v3
46 - 80
AS3675
Datasheet - Detailed Description
Table 65. Subtract Enable Register (Continued)
Subtract Enable
Addr: 35h
Enable the inversion from the signal from the pwm generator
Bit
Bit Name
Default Access
Description
Inverts the signal from the pwm generator
Direct Operation (no inversion)
0
1
sub_en4
3
0
R/W
The signal from the pwm generator for which
the adder is enabled (curr33_adder = 1)
is inverted
8.5
General Purpose Input / Output
The GPIO is a highly-configurable general purpose input/output pin which can be used for the following functionlity:
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Digital Schmitt Trigger Input
Digital Output with 4mA Driving Capability at 2.8V Supply (VANA)
Tristate Output
Analog Input to the ADC
Default Mode for GPIO and VANA/GPI is Input (Pull-Down)
Table 66. GPIO Pin Function Summary
GPIO Pin
Configuration
Additional Function
ADC Input
Digital Input, Totem-Pole Output (Psh/Pull),
Open Drain (PMOS or NMOS), High-Z, Pull-
Down or Pull-Up Resistor
GPIO
VANA/GPI
DigitInput
ADC Input, LDO output
Figure 24. GPIO and VANA/GPI Blockdiram
AS3675
ꢋꢛꢜꢝ
"#ꢀ
ꢋꢜ ꢜ!"#ꢀ
ꢁ
ꢄꢅꢆꢇꢈꢉꢅꢊꢋ
ꢌꢌꢌꢌꢏꢐꢑꢒꢓꢎꢐꢔꢕꢑꢌꢖꢗꢓꢘꢐꢔꢙꢓꢚ
ꢋꢜ ꢜ
$ꢄ%
&ꢅ&'(
ꢙꢓꢏ)ꢌꢒꢑ*ꢗꢔꢒꢑ+ꢌꢔꢖ
ꢌꢂꢃꢁꢌꢔ,ꢌꢗ,ꢑ+-ꢌꢓꢙꢐꢌ
ꢗ,ꢑ+ꢌꢖꢙꢒꢌ"#ꢀꢌꢔꢓ.ꢗꢐ
"#ꢀꢁꢌꢛꢏꢙꢘ4
/.ꢔ0ꢔꢓ
/.ꢔꢙ0ꢙꢗꢐ1ꢄ
ꢎꢓ+ꢌ/.ꢔꢙ02ꢙ+ꢑ1%ꢄꢌꢙꢒꢌꢄꢄ
ꢎꢓ+ꢌꢍꢓꢙꢐꢌ/.ꢔꢙ0.ꢗꢏꢏ,1ꢄꢄꢚ
ꢙꢓ
ꢙꢓ
/.ꢔ0ꢑꢓ
ꢐꢙꢌꢜꢃ$
2ꢎ3
/.ꢔꢙ0.ꢗꢏꢏ,
/.ꢔꢙ0ꢔꢓ
ꢋ&0ꢇ
/.ꢔꢙ0ꢏꢙ50ꢘꢗꢒꢒ
**ꢀꢁ
ꢓꢙꢐꢌ/.ꢔꢙ0.ꢗꢏꢏ,1ꢄꢄ
/.ꢔꢙ0ꢙꢗꢐ1%
ꢎꢓ+ꢌ/.ꢔꢙ02ꢙ+ꢑ1%ꢄꢌꢙꢒꢌꢄ%
ꢎꢓ+ꢌꢍꢓꢙꢐꢌ/.ꢔꢙ0.ꢗꢏꢏ,1ꢄꢄꢚ
ꢐꢙꢌꢜꢃ$
ꢍꢗ,ꢑꢌ/.ꢔꢙ0.ꢗꢏꢏ,1ꢄꢄꢚ
8.5.1 Unused GPIO Pin
If the pin GPIO is not used, they can be left open (an internal pulldown, which is enabled by default, will pull them to
GND).
www.austriamicrosystems.com/AS3675
1v3
47 - 80
AS3675
Datasheet - Detailed Description
8.5.2 GPIO Characteristics
Table 67. GPIO DC Characteristics
Symbol
Rpull
Parameter
Condition
enabled by gpio_pulls
=VANA/GPI
Min
30
Typ
Max
75
Unit
kΩ
V
Pull up/Pull down
Resistance
VGPIO
Supply Voltage
1.5
3.4
0.7·VANA
min.
1.75V
High Level Input
Voltage
VIH
V
V
0.3·
VANA
min.
Low Level Input
Voltage
VIL
0.75V
0.1·
VANA
min.
VHYS
Hysteresis
V
250mV
ILEAK
VOH
Input Leakage Current To V2_5 or VANA/GPI and VSS
-5
5
µ A
V
High Level Output
at Iout
0.8·VANA
Voltage
Low Level Output
at Io
0.2·
VANA
VOL
V
Voltage
VANA/GPI = .8V,
gpio_low_curr = 1
4
IOUT
Driving Capability
mA
pF
VANA/GPI = 2.8V,
pio_low_curr = 0
16
CLOAD
Capacitive Load
50
8.5.3 GPIO Registers
Table 68. GPIO output 1 Register
GPIO output 1
Addr: 05h
This register controls GPIO outputs.
Bit
Bit Name
DefaulAccess
Description
Enables the CURR1 input
input disabled
gpi_curr1_en
0
0
0
0
R/W
R/W
R/W
0
1
input enabled
Enables the CURR2 input
input disabled
gpi_curr2en
gpi_curr6_en
1
0
1
input enabled
Enables the CURR6 input
input disabled
2
4
0
1
input enabled
not used
Enables the CURR30 input
input disabled
gpi_curr30_en
0
R/W
0
1
input enabled
www.austriamicrosystems.com/AS3675
1v3
48 - 80
AS3675
Datasheet - Detailed Description
Table 68. GPIO output 1 Register (Continued)
GPIO output 1
This register controls GPIO outputs.
Description
Addr: 05h
Bit
Bit Name
Default Access
Enables the CURR31 input
gpi_curr31_en
5
0
0
0
R/W
R/W
R/W
0
1
input disabled
input enabled
Enables the CURR32 input
input disabled
gpi_curr32_en
gpi_curr33_en
6
7
0
1
input enabled
Enables the CURR33 input
input disabed
0
1
input enabled
Table 69. GPIO signal 1 Register
PIO signal 1
Addr: 06h
register controlGPIO outputs.
Bit
0
Bit Name
gpi_curr1_in
gpi_curr2_in
gpi_curr6_in
Default Access
Decription
N/A
N/A
N/A
NA
/A
N/A
N/A
N/A
R
R
R
Reads a logic sigal from pin CURR1; if gpi_curr1_en=1
Reads a loignal from pin CURR2; if gpi_curr2_en=1
Reads logic signal from pin CURR6; if gpi_curr6_en=1
not used
1
2
3
gpi_curr30_in
gpi_curr31_in
gpi_curr32_in
gpi_curr33_in
4
R
R
R
Reada logic signal from pin CURR30; if gpi_curr30_en=1
ds a logic signal from pin CURR31; if gpi_curr31_en=1
Reads a logic signal from pin CURR32; if gpi_curr32_en=1
Reads a logic signal from pin CURR33; if gpi_curr33_en=1
5
6
7
Table 70. GPIO output 2 Register
GPIO output 2
This register controls GPIO outputs.
Description
Addr: 50h
Bit
Bit Name
Default Access
Writes a logic signal to pin GPIO; this is independent of any
other bit setting e.g., gpio_mode Table 72.
gpio_ut
0
0
R/W
Enables the VANA/GPI input
gpi_en
1
3
0
R/W
0
1
input disabled
input enabled
Enables the RGB1 input
input disabled
gpi_rgb1_en
gpi_rgb2_en
0
0
R/W
R/W
0
1
input enabled
Enables the RGB2 input
input disabled
0
1
input enabled
www.austriamicrosystems.com/AS3675
1v3
49 - 80
AS3675
Datasheet - Detailed Description
Table 70. GPIO output 2 Register (Continued)
GPIO output 2
This register controls GPIO outputs.
Description
Addr: 50h
Bit
Bit Name
Default Access
Enables the RGB3 input
gpi_rgb3_en
4
0
0
0
0
R/W
R/W
R/W
R/W
0
1
input disabled
input enabled
Enables the CURR41 input
input disabled
gpi_curr41_en
gpi_curr42_en
gpi_curr43_en
5
6
7
0
1
input enabled
Enables the CURR42 input
input disabed
0
1
input enabled
Enables the CUR3 inpt
input disabled
0
1
input enabled
Table 71. GPIO signal 2 Register
GPIO ignal 2
Addr: 51h
This registontrols GPIO outputs.
Bit
Bit Name
Defat Acess
Description
Reads logic signal from pin GPIO; this is independent of
ny oter setting e.g.,Table 72 except gpio_pulls=11
gpio _in
0
N/
R
gpi_ in
1
2
3
4
5
6
7
N/A
N/A
N/A
N/
NA
N/A
R
R
R
R
R
R
R
Reads a logic signal from pin VANA/GPI; if gpi_en=1
Reads a logic signal from pin RGB1; if gpi_rgb1_en=1
Reads a logic signal from pin RGB2; if gpi_rgb2_en=1
Reads a logic signal from pin RGB3; if gpi_rgb3_en=1
Reads a logic signal from pin CURR41; if gpi_curr41_en=1
Reads a logic signal from pin CURR42; if gpi_curr42_en=1
Reads a logic signal from pin CURR43; if gpi_curr43_en=1
gpi_rgb1_in
gpi_rgb2_in
gpi_rgb3_in
gpi_curr41_in
gpi_curr42_in
gpi_curr43_in
Table 72. GPIO control Regiser
GPIO control
Adr: 1E
This register controls GPIO and GPIO1 pin functions.
Bit
Bit Name
Default Access
Description
Defines the direction for pin GPIO
Input only
00
01
Output (push and pull)
gpio_mode
1:0
00
R/W
Output (open drain, only push; only NMOS is
active)
10
11
Output (open drain, only pull; only PMOS is
active)
www.austriamicrosystems.com/AS3675
1v3
50 - 80
AS3675
Datasheet - Detailed Description
Table 72. GPIO control Register (Continued)
GPIO control
Addr: 1Eh
This register controls GPIO and GPIO1 pin functions.
Bit
Bit Name
Default Access
Description
Adds the following pullup/pulldown to pin GPIO; this is
independent of setting of bits gpio_mode
00
01
10
None
Pulldown
Pullup
gpio_pulls
3:2
01
R/W
ADC input (gpio_mode = XX); recommended f
analog signals
11
Table 73. GPIO driving cap Register
GPIO driving cap
Addr: 20h
This register enables low current mode or GIOs.
Bit
Bit Name
Default Access
Description
Defnes the driving capabily of pin GPIO
gpio_low_curr
0
0
R/W
1
Iout
Iout /4
www.austriamicrosystems.com/AS3675
1v3
51 - 80
AS3675
Datasheet - Detailed Description
8.6
LED Test
Figure 25. LED Function Testing
ꢇꢋꢓꢋꢑꢓꢆꢘꢙꢐꢏꢓꢋꢎꢆꢖꢗꢇꢊ
ꢇ$
ꢚꢏꢐꢛꢆꢇꢀꢇꢀ
ꢘꢓꢋꢕꢆꢃꢕ
ꢀꢐꢍꢜꢋꢏꢓꢋꢏ
ꢀꢀ
"#
$%&
ꢒ(ꢊꢓꢋꢕ! ꢕ!ꢜꢓ ꢍ)ꢍꢝ*
ꢇꢀꢇꢀ!ꢚꢈ
ꢀꢁꢂꢃꢄ
ꢚꢏꢐꢛꢆꢀꢙꢉꢏꢝꢋꢆ
ꢁ ꢛꢕ
ꢆꢆꢀ
ꢈꢉꢊꢋꢌꢉꢍꢎ
ꢁꢏꢐꢑꢋꢊꢊꢐꢏ
ꢆꢇꢀ
ꢒꢍꢓꢋꢏꢔꢉꢑꢋ
AS3675
ꢇꢋꢓꢋꢑꢓꢆꢂꢕꢋꢍꢆꢖꢗꢇꢊ
The AS3675 supports the verification of the funtionality of all the conned LEDs (open and shorted LEDs can be
detected). This feature is especially useful in prodction test to vethe correct assembly of the LEDs, all its connec-
tors and cables. It can also be used in thfield o verify if any of the LDs is damaged. A damaged LED can then be
disabled (to avoid unnecessary currens).
The current sources, charge pump, dcconverter and thnteral ADC are used to verify the forward voltage of the
LEDs. If this forward voltage is within the specified limitLEDs, the external circuitry is assumed to operate.
8.6.1 Function Testing for single LEDs conncted to the Charge Pump
For any current source connected to the carge pump (CURR30-33) where only one LED is connected between the
charge pump and the current sink (see Figur1) use:
Table 74. Function Testing for LEDs cnned to the Charge Pump
Step
Action
Example Code
Switch on the chrge ump and set it into manual
1:2 mode (to avod automatic mode switching
duing measurements)
Reg 23h ≤ 14h (cp_mode = 1:2, manual)
Reg 00h ≤ 04h (cp_on = 1)
1
e.g. for register CURR31set to 9mA use
Reg 10h ≤ 0Fh (curr3x_other = 9mA)
2
3
Swih on he current sink for the LED to be tested
Mesure with the ADC the voltage on CPOUT
Reg 03h ≤ 0ch (curr31_mode = curr31_other)
Reg 26h ≤ 95h (adc_select=CPOUT,start ADC)
Fetch the ADC result from Reg 27h and 28h
Measure with the ADC the voltage on the switched
on current sink
Reg 26h ≤ 8bh (adc_select=CURR31,start ADC)
4
Fetch the ADC result from Reg 27h and 28h
Switch off the current sink for the LED to be tested
Reg 03h ≤ 00h (curr31_mode = off)
Compare the difference between the ADC
measurements (which is the actual voltage across
the tested LED) against the specification limits of
the tested LED
6
Calculation performed in baseband uProcessor
www.austriamicrosystems.com/AS3675
1v3
52 - 80
AS3675
Datasheet - Detailed Description
Table 74. Function Testing for LEDs connected to the Charge Pump
Step
Action
Example Code
Do the same procedure for the next LED starting
from point 2
7
Jump to 2. If not all the LEDs have been tested
Switch off the charge pump
set charge pump automatic mode
Reg 00h ≤ 00h (cp_on = 0)
Reg 23h ≤ 00h
8
8.6.2 Function Testing for LEDs connected to the Step Up DCDC Converter
For LEDs connected to the DCDC converter (usually current sinks CURR1,CURR2 and CURR6) use the following pr-
cedure:
Table 75. Function Testing for LEDs connected to the DCDC converter
Step
Action
Example Code
e.g. Test LEDs on CURR1:
Reg 01h ≤ 01h (curr1_moe=on)
Reg 09h ≤ 3ch (curr1_curnt = 9mA)
Switch on the current sink for the LED string to be
tested (CURR1,2 or 6)
1
Select the feedback path for the LED string to be
tested (e.g. step_up_fb = 01 for LED string on
CURR1)
2
3
Reg 21h ≤ 02h (st_up_b=curr1)
Set the current for step_up_vtuning exactly above
the maximum forward voltage of the tested
string + 0.6V (for the current sink) + 0.25V; ad
margin (accuracy of step_up_vtuning); this sethe
maximum output voltage limit for the DCDC
converter
e.g. 4 LEDs with UfMAX = 41V gives 17.25V +6% =
18.29V; if R=1MΩ and R3 = open, then select
step_up_vtuni= 18 (Reg 21h ≤ 92h; results in
19.25V over voltagprotection voltage – Table 9 on
page 14)
4
5
6
Set step_up_prot = 1
Reg 22h ≤ 04h
Reg 00h ≤ 08h
Switch on the DCDC onvrter
Wait 80ms (DCDC_Fsetting time)
Reg 26h ≤ 96h (adc_select=DCDC_FB, start ADC;
7
8
9
Measure the voltage DCDC_FB (ADC)
Fetch the ADC result from Reg 27h and 28h)
If the voltage on DCDC_FB is above 1.0
tested LED string is broken – then skip the following
steps
(Code >199h)
Switch off the over voltae protection
(step_up_prot=0
Reg 22h ≤ 00h
Reduce step_up_vtuning sby step until the
measured voltage on DCDFB (ADC) is above
1.0V.
e.g.: Reg 21h ≤ 62h (step_up_vtuning=12): ADC
10
result=1,602V
After changing step_u_vuning always wait 80ms,
befoe AD-conversion
11
12
Masurvoltage on DCDC_FB
Switch off the DCDC converter
e.g. DCDC_FB=1.602V
Reg 00h ≤ 00h
The vltage on the LED string can be calculated
now as follows (R4 = open):
VLEDTRING = V(DCDC_FB) + I(step_up_vtuning) *
R2 – 0.5V (current sinks feedback voltage: VFB2).
V(DCDC_FB) = ADC Measurement from point 11
I(step_up_vtuning) = last setting used for point 10
13
1
e.g.: VLED = (1.602V + 12V – 0.5V) / 4 = 3.276V
Compare the calculated value against the
specification limits of the tested LEDs
Note: With the above described procedures electrically open and shorted LEDs can be automatically detected
www.austriamicrosystems.com/AS3675
1v3
53 - 80
AS3675
Datasheet - Detailed Description
8.7
Analog-to-Digital Converter
The AS3675 has a built-in 10-bit successive approximation analog-to-digital converter (ADC). It is internally supplied
by V2_5, which is also the full-scale input range (0V defines the ADC zero-code). For input signals exceeding V2_5
(typ. 2.5V) a resistor divider with a gain of 0.4 (Ratioprescaler) is used to scale the input of the ADC converter. Conse-
quently the resolution is:
Table 76. ADC Input Ranges, Compliances and Resolution
Channels (Pins)
Input Range
VLSB
Note
DCDC_FB, GPIO, AUDIO_IN, VANA/
GPI, audio controlled LED buffer
output
0V-2.5V
2.44mV
VLSB=2.5/1024
ADCTEMP_CODE
-30°C to 125°C
0V-5.5V
1 / ADCTC
6.1mV
junction temperature
CURR30-33, CURR4x, RGBx
VBAT, CPOUT
VLSB=2.5/1024 * 1/0.4; intenal
resistor divider used
CURR1, CURR2, CURR6
0V-1.0V
2.44mV
VLSB=2.51024
Table 77. ADC Parameters
Symbol
Parameter
Conditon
Min
Typ
Max
Unit
Resolution
10
Bit
see
Table
76
VIN
Input Voltage Range
VSU= V2_5
VSS
V
Differential Non-
Linearity
DNL
± 0.25
LSB
INL
Vos
Rin
Cin
Integral Non-Linearity
Input Offset Voltage
Input Impedance
± 0.5
LSB
LSB
MΩ
pF
± 0.25
100
Input Capacitance
9
VSUPPLY
Power Supply Range
± 2%, nally trimmed.
Durig conversion only.
2.5
V
(V2_5)
Idd
Idd
Power Supply Current
Power Down Current
500
100
µ A
nA
Temperature Sensor
Accuracy
TTOL
ADCTOFFSET
ADCTC
@ 25 °C
-10
+10
°C
°C
ADC temperatre
measurement oset
value
375
Code temprature
cofficient
1.293
9
°C/
Code
Temperature change per ADC LSB
For all low voltage current sinks, CPOUT
and VBAT
RatioPRESCALE
R
atio f Prescaler
0.4
Transient Prameters (2.5V, 25 ºC)
Tc
fc
ts
Conversion Time
Clock Frequency
27
1.0
16
µs
MHz
µs
All signals are internally generated and
triggered by start_conversion
Settling Time of S&H
The junction temperature (TJUNCTION) can be calculated with the following formula (ADCTEMP_CODE is the adc conver-
sion result for channel 04h selected by register adc_select = 000100b):
TJUNCTION [°C] = ADCTOFFSET - ADCTC · ADCTEMP_CODE
(EQ 5)
www.austriamicrosystems.com/AS3675
1v3
54 - 80
AS3675
Datasheet - Detailed Description
ADC Registers
Table 78. ADC_MSB result Register
ADC_MSB result
Addr: 27h
Together with Register 27h, this register contains the results (MSB) of an ADC
cycle.
Bit
Bit Name
Default Access
Description
ADC results register.
D9:D3
6:0
N/A
N/A
R
R
Indicates end of ADC conversion cycle
Result is ready
result_not_ready
7
0
1
Conversion is running
Table 79. ADC_LSB result Register
ADC_LSB result
Addr: 28h
Together with Register 28h, this register contains the resus (LB) of an ADC
cycle
Bit
Bit Name
Default Access
N/A
Description
D2:D0
2:0
R
ADC result regiter
www.austriamicrosystems.com/AS3675
1v3
55 - 80
AS3675
Datasheet - Detailed Description
Table 80. ADC_control Register
ADC_control
Addr: 26h
This register input source selection and initialization of ADC
Bit
Bit Name
Default Access
Description
Selects input source as ADC input
000000 (00h)
AUDIO_IN
000001 (01h)
000010 (02h)
000011 (03h)
000100 (04h)
000101 (05h)
000110 (06h)
000111 (07h)
001000 (08h)
00100(09h)
1010(0Ah)
011 (0Bh)
00100 (0Ch)
001101 (0Dh)
001110 (0Eh
001111 (0F)
01000 (0h)
0001 (11h)
010 (12h)
010011 (13h)
010100 (14h)
010101 (15h)
010110 (16h)
010111 (17h)
VANA/GPI
GPIO
audio controlled LED buffer output
reserved
RGB1
RGB
RGB3
CRR1
CURR2
CURR30
CURR31
adc_select1
5:0
03h
R/W
CURR32
CURR33
CURR41
CURR42
CURR43
reserved
reserved
CURR6
VBAT
CPOUT
DCDC_FB
ADCTEMP_CODE (junction temperature)
011xxx,
1xxxxx
reserved
NA
6
7
st_coversion
N/A
W
Writing a 1 into this bit starts one ADC conversion cycle.
1. See Table able 6 for ADC ranges and resultion.
www.austriamicrosystems.com/AS3675
1v3
56 - 80
AS3675
Datasheet - Detailed Description
Figure 26. ADC Circuit
ꢘꢔꢙꢃꢗꢅ*ꢗꢖꢄꢑꢗꢕꢕꢒꢙꢅ45ꢉ
ꢂꢔ66ꢒꢑꢅꢗꢔꢄ#ꢔꢄ
ꢇꢛꢉ/0ꢍ/2
ꢋꢇ2ꢇ3.)/
.)/0
ꢋꢌꢍꢎ
ꢊꢛꢈꢈꢀ
ꢊꢛꢈꢈꢌ
ꢊꢛꢈꢈꢜ
ꢉꢊꢉꢊꢍꢝ
ꢉꢏꢐꢉꢁ
++++ꢀꢁꢂꢃꢄꢅꢆꢇꢈ
ꢅꢅꢅꢅꢇꢉꢊ
!ꢄꢒ"#
ꢑꢒꢓꢔꢕꢄꢍꢖꢗꢄꢍꢑꢒꢘꢙꢚ
ꢈ. ꢀ
ꢈ. ꢌ
ꢈ. '
ꢀ+,-
ꢊꢛꢈꢈ'ꢁ
ꢊꢛꢈꢈ'ꢀ
ꢊꢛꢈꢈ'ꢌ
ꢊꢛꢈꢈ''
ꢊꢛꢈꢈ1ꢀ
ꢊꢛꢈꢈ1ꢌ
ꢊꢛꢈꢈ1'
ꢋ ꢇ(
ꢘꢙ*ꢍꢓꢒꢕꢒ*ꢄ
ꢊꢗꢖꢄꢑꢗꢕ
ꢓꢄꢘꢑꢄꢍ*ꢗꢖ!ꢒꢑꢓꢃꢗꢖ
ꢋꢊ)
ꢖ*
ꢀ$ꢁ%&
ꢀꢌꢁ%&
AS3675
8.8
Audio controlled LEDs
Up to four RGB LEDs and/or up to 13 LEDs (number of LEDis fully configurab) can be controlled by an audio
source (connected to the pin AUDIO_IN). The audio controlled LED block caoperate in two modes:
Amplitude Mode: The color of the RGB LED(s) or the bghtness of the le color LED(s) is depending on the input
amplitude. For the RGB LEDs it starts from bactransitions to blue, grn, yan, yellow, red and for high amplitudes
white is used (internal lookup table if audio_clor=000b).
Frequency Mode: Three internal fully configurable filters define the brightness of the single color LED(s) or the color of
the RGB LED(s). Each of the filters an e configured individuay in amplitude, frequency response and type (lowpass
filter, bandpass filter, highpass filter).
www.austriamicrosystems.com/AS3675
1v3
57 - 80
AS3675
Datasheet - Detailed Description
Figure 27. Audio controlled LED internal circuit
ꢒꢆꢇꢈꢉꢃꢐꢒꢈꢙꢊꢊꢊꢊ)ꢋꢍꢇ$ꢌꢌꢌ*ꢜꢝꢇ$
@ꢂꢀꢁꢂꢃꢁꢄ
ꢉ"ꢑꢈꢉꢙꢒꢓ
ꢖ ꢋ
ꢖ ꢍ
ꢅꢆꢇꢈꢉꢊꢁꢄ
ꢀꢈꢐꢈꢑꢒꢓ
ꢊꢊꢊꢅꢀꢏ
ꢔꢕꢉꢖꢗꢘꢘꢈꢙꢐ ꢖ ꢜ
ꢋꢌꢍꢏꢎ
ꢒꢇꢖꢃꢘꢗꢓꢗꢖꢑ
ꢏꢚꢛꢛꢜꢝ
ꢏꢚꢛꢛꢜꢋ
ꢏꢛꢛꢜꢍ
ꢏꢚꢛꢛꢜꢜ
ꢒꢆꢇꢃ%ꢆ+ꢃꢉꢙ
ꢉꢑ ꢗꢕꢊ!ꢉꢇꢗꢘ
ꢛ#$ꢋ
ꢛ#$ꢍ
ꢉꢑ ꢗꢕꢊ!ꢉꢇꢗꢘ
ꢉꢑ ꢗꢕꢊ!ꢉꢇꢗꢘ
ꢖ ꢋ
ꢖꢆꢕꢕꢜꢝꢃꢒꢆꢇꢃꢘꢕꢖ
ꢖ ꢍ
ꢖ ꢜ
ꢛ#$ꢜ
ꢉꢑ ꢗꢕꢊ!ꢉꢇꢗꢘ
ꢉꢑ ꢗꢕꢊ!ꢉꢇꢗꢘ
ꢖꢆꢕꢕꢜꢋꢃꢒꢆꢇꢃꢘꢕꢖ
ꢕꢐ%&ꢃꢒꢆꢇꢃꢉꢙ
ꢏꢚꢛꢛꢋ
ꢏꢚꢛꢛꢍ
ꢉꢑ ꢗꢕꢊ!ꢉꢇꢗꢘ
ꢖ ꢋ
ꢖ ꢍ
ꢉꢑ ꢗꢕꢊ!ꢉꢇꢗꢘ
ꢉꢑ ꢗꢕꢊ!ꢉꢇꢗꢘ
ꢏꢚꢛꢛ'
ꢉꢑ ꢗꢕꢊ!ꢉꢇꢗꢘ
ꢖꢆꢕꢕꢜꢍꢃꢃꢘꢕ
ꢜ
ꢖꢆꢕꢕꢋꢍ'ꢃꢒꢆꢇꢃꢉꢙ
ꢉꢑ ꢗꢕꢇꢗꢘ
ꢏꢚꢛꢛ(ꢋ
ꢏꢚꢛꢛ(ꢍ
ꢉꢑ ꢗꢕꢊ!ꢉꢇꢗꢘ
ꢑ ꢗꢕꢊ!ꢗꢘ
ꢖ ꢋ
ꢖ ꢍ
ꢖꢆꢕꢕꢜꢜꢃꢒꢆꢇꢃꢘꢕꢖ
ꢏꢚꢛꢛ(ꢜ
ꢉꢑ ꢗꢕꢊ!ꢉꢇꢗꢘ
ꢖ ꢜ
AS3675
ꢖꢆꢕꢕ(&ꢃꢒꢆꢇꢃꢉꢙ
The audio controlled LED block is enabled if any othe registers curr30_aud_src[1:0]...curr33_aud_src[1:0],
curr126_aud_on, rgbx_aud_on or curr4x_aud_on ot eual zero.
The audio input amplifier (enabled by aud_uf_on=1) is used to allow the attenuation (or amplification of the input sig-
nal) and has the following parameters:
Table 81. Audio input Parameters
Symbol
VIN
Parameter
Condition
Min
Typ
Max
Unit
V
Input Voltage Range
min. Input Ipedance
0
2.5
Rin_min
at max. input gain (30dB)
20
kΩ
The signal is conered with the ADC (If the audio controlled LED is active, the internal ADC is continuously running at
a sample frequency of 45.4kHz. In this case the ADC cannot be used for any other purpose). The digital processing
converts this sgnal into 3 channels (ch1, ch2, ch3):
www.austriamicrosystems.com/AS3675
1v3
58 - 80
AS3675
Datasheet - Detailed Description
Figure 28. Audio controlled LED digital processing internal circuit
ꢀꢚꢙꢚꢉꢎꢈꢋꢗꢘꢅꢊꢃ))ꢚ'ꢙ
ꢑꢄꢕꢈꢚꢉꢐꢏꢃꢋ&ꢅꢏꢃ
ꢇꢃꢆꢃꢈ
ꢀꢃꢉꢃꢊꢉꢋꢌ
ꢍꢎꢏꢃꢅꢐꢉ
ꢇꢅꢅꢓ
ꢔꢕ
ꢖꢎꢖꢈꢃ
ꢑꢒꢁ
ꢎꢐꢏꢚꢅ%)ꢕꢃꢃꢏ
ꢎꢙꢊ%ꢊꢉꢘꢈ
ꢎꢐꢏꢚꢅ%ꢊꢅꢈꢅꢘ
ꢎꢐꢏ%ꢎꢄꢕꢈꢚꢉꢐꢏꢃ
ꢀꢁ
ꢂꢃꢄꢅꢆꢃ
#ꢘꢅꢄ
ꢑꢀꢁ
ꢍꢘꢃ$ꢐꢃ'ꢊ(ꢋ&ꢅꢏꢃ
ꢇꢃꢆꢃꢈ
ꢀꢃꢉꢃꢊꢉꢋꢌ
ꢍꢎꢏꢃꢅꢐꢉ
ꢊ"ꢛ
ꢊ
ꢊ"!
ꢗꢘꢅꢙꢘꢎꢄꢄꢎꢖꢈꢃꢋꢍꢚꢈꢉꢃꢘꢋꢛ
ꢝꢗ
ꢇꢗ
ꢜꢗ
ꢇꢃꢆꢃꢈ
ꢀꢃꢉꢃꢊꢉꢋꢌ
ꢍꢎꢏꢃꢅꢐꢉ
ꢗꢘꢅꢙꢘꢎꢄꢄꢎꢖꢈꢃꢋꢍꢚꢈꢉꢃꢘꢋ
ꢑꢒꢁ
ꢝꢗ
ꢇꢗ
ꢜꢗ
ꢇꢃꢆꢃꢈ
ꢀꢃꢉꢃꢊꢉꢋꢌ
ꢎꢏꢃꢅꢐꢉ
ꢎꢙꢊ%ꢊꢉꢘꢈ
ꢗꢘꢅꢙꢘꢎꢄꢄꢎꢖꢈꢃꢋꢍꢚꢈꢉꢃ!
#ꢘꢃ$%ꢅꢏꢃ
ꢝꢗ
ꢇꢗ
ꢜꢗ
#ꢚꢈꢉ*ꢛ+ +!,%*ꢑ-+ꢖ-+ꢖꢛ+ꢖꢎꢛ+ꢎ , ꢎꢐꢏꢚꢅ%)ꢕꢃꢃꢏ
AS3675
These three output channels (ch1, ch2, ch3) can e oued to any of the rrensources according to Figure 27.
The digital processing can be done in two diferet operating mods (dneby the register bit freq_mode):
8.8.1 Amplitude Mode
This mode is selected by freq_mod=0
The input amplitude is mapped into dient colors for RD(s) or brightness for single color LED(s). The mapping
is controlled by the register audio_color. If audio_color = then the mapping is done as follows:
Very low amplitudes are mapped to black, for highr amlitudes, the color smoothly transitions from blue, green, cyan,
yellow, red and eventually to white (for high input amplitudes).
www.austriamicrosystems.com/AS3675
1v3
59 - 80
AS3675
Datasheet - Detailed Description
8.8.2 Frequency Mode
This mode is selected by freq_mode=1.
The input signal is frequency filtered by three digital filters. The filters are 2nd order biquad IIR (infinite impulse
response filters). Each of these filters has the following structure (sampling frequency = 45.4kHz / internal clock of
1MHz divided by 22):
Figure 29. Audio controlled LED frequency filter
ꢈꢉꢊꢋꢉꢇꢌꢌꢇꢅꢍꢎꢁꢏꢐꢍꢑꢎꢉ
ꢅꢀꢁꢁꢁ
ꢃꢄ
ꢂꢁꢁ
ꢅꢄꢁꢁꢁ
ꢅꢆꢁꢁꢁ
ꢁꢁꢁꢃꢇꢄ
ꢁꢁꢁꢃꢇꢆ
ꢃꢄ
ꢂꢁꢁ
The mathematical formula for these filters is:
y(n) = A0(x(n) + b1 x(n-1) + b2 x(n-2)) – a1 y(n-1) – a2 y(n-2)
(EQ 6)
The internal calculation is preformed using 12bts coefficients (state vales (z-1) are rounded to 12bit, the output
uses 8bits). All coefficients can be set individally or each of the te fiers (filter1, filter2, filter3). (see Audio Con-
trolled LED Registers on page 62), registrs fil_type (70h) and registrs 71h to 82h. It is recommended to use austri-
amicrosystems ‘Demoboard Software’ for smple control of the filtecutoff frequencies and filter type.
Note: Do not set filter cutoff frequenbelow 500Hz.
8.8.3 AGC
The AGC (available in amplitude and frequency mde) iused to ‘compress’ the input signal and to attenuate very low
input amplitude signals (this is performed tensure no light output for low signals especially for noisy input signals).
The AGC monitors the input signal amplitude nd filters this amplitude with a filter with a short attack time, but a long
decay time (decay time depends on threter agc_ctrl). This amplitude measurement (represented by an integer
value from 0 to 15) is then used to amplifattenuate the input signal with one of the following amplification ratios
(output to input ratio) – the curve , B, r C is selected depending on the register agc_ctrl:
www.austriamicrosystems.com/AS3675
1v3
60 - 80
AS3675
Datasheet - Detailed Description
Figure 30. AGC curve A (x-axis: input amplitude, y-axis: output amplitude; actual value: gain between output to
input)
ꢀ
Figure 31. AGC curve B (x-axis: input amplitude, y-axis: output mplitude; actual value: gain etween output to
input)
Figure 32. AGC curve C (x-axis: input amude, y-axis: output amplitude; actual value: gain between output to
input)
www.austriamicrosystems.com/AS3675
1v3
61 - 80
AS3675
Datasheet - Detailed Description
8.8.4 Audio Controlled LED Registers
Table 82. Audio Control Register
Audio Control
Addr: 46h
Audio Sync Mode control
Bit
Bit Name
Default Access
Description
Audio input buffer enable
off; for audio direct input to ADC use
adc_select = 00h (AUDIO_IN)
aud_buf_on
0
0b
R/W
0
1
on; set adc_select = 03h (buffer output)
audio controlled LED color selection (amplitude mde)
audio_color
freq_mode
4:2
5
000b
0b
R/W
R/W
000
color scheme defined by lookup tabl
001-111
single color scheme (b2=R, 1=G, b0=B)
audio controlled LED mode sectio
0
1
amplitde mde
frequency ode
Audio controlled LEperistence time
01
10
11
none
audio_speed
7:6
00b
R/W
200ms
400ms
800ms
Table 83. Audio input Register
Audio input
Addr: 47h
Audio Sync input control
Description
Bit
Bit Name
Default Access
Audio input buffer gain control
000
001
010
011
100
101
110
111
-12dB
-6dB
0dB
audio_gain
2:0
000b
R/W
+6dB
+12dB
+18dB
+24dB
+30dB
www.austriamicrosystems.com/AS3675
1v3
62 - 80
AS3675
Datasheet - Detailed Description
Table 83. Audio input Register (Continued)
Audio input
Addr: 47h
Audio Sync input control
Bit
Bit Name
Default Access
Description
Audio input buffer AGC function controls AGC switching
threshold
000
AGC off
Attenuate low amplitude signals otherwise linear
response (to remove e.g. noise)
001
010
011
100
101
110
111
AGC curve A; slow decay of amplitude detection
AGC curve A; fast decay of amplitude detecon
AGC curve B; slow decay of amplitude detectn
AGC curve B; fast decay of amplitue detection
AGC curve C; slow decay of amplitde detection
AGC curve C; fast decay amplude detection
agc_ctrl
5:3
000b
R/W
Sttup Cotrol of audio inut buffer (used to charge
opional external dc blockng capacitor)
audio_man_start1
audio_dis_start2
6
7
0b
0b
R/W
R/W
1
tomatic prechging 300us (if audio_dis_start = 0)
continuousprearging (if aud_buf_on = 1)
Disable Startup ontrol of audio input buffer (used to
charge ionaexternal dc blocking capacitor)
0
1
precharging enabled
precharging disabled
1. Its safe to keep default value
2. Its safe to keep default value
Table 84. Audio output Register
Audio output
Audio Sync input control
Description
Addr: 48h
Bit
Bit Name
Dult Access
LED(s) output amplitude control (in percent of selected
output current)
000
001
010
011
100
101
110
111
6.25%
12.5%
25%
aud_amplitude
2:0
000b
R/W
50%
75%
87.5%
93.75%
100%
www.austriamicrosystems.com/AS3675
1v3
63 - 80
AS3675
Datasheet - Detailed Description
Table 84. Audio output Register (Continued)
Audio output
Addr: 48h
Audio Sync input control
Bit
Bit Name
Default Access
Description
Audio controlled LED enable for CURR1, CURR2, CURR6
curr126_aud_on
4
0b
0b
0b
R/W
R/W
R/W
0
1
off
on, audio controlled LED is enabled
Audio controlled LED enable for RGB1-RGB3
off
rgbx_aud_on
5
6
0
1
on, audio controlled LED is enable
Audio controlled LED enable for CURR41-CURR
curr4x_aud_on
0
1
off
on, audio controlled LED s enabled
Table 85. CURR3x audio source Register
CURR3x audio soure
Controls CURR3033 audio outputand enables audio controlled LED
Addr: 53h
Bit
Bit Name
Default Access
Decription
Audio conrolled LED source for CURR30
All other modes
00
01
ch1 connected to CURR30, audio controlled
LED on
curr30_aud_src[1:0]
1:0
0b
00b
R/W
R/W
R/W
ch2 connected to CURR30, audio controlled
LED on
0
11
ch3 connected to CURR30, audio controlled
LED on
Audio controlled LED source for CURR31
All other modes
00
01
ch1 connected to CURR31, audio controlled
LED on
curr31_aud_src[1:0]
3:2
ch2 connected to CURR31, audio controlled
LED on
10
11
ch3 connected to CURR32, audio controlled
LED on
Audio controlled LED source for CURR32
All other modes
00
01
ch1 connected to CURR32, audio controlled
LED on
curr32_aud_src[1:0]
5:4
ch2 connected to CURR32, audio controlled
LED on
10
11
ch3 connected to CURR32, audio controlled
LED on
www.austriamicrosystems.com/AS3675
1v3
64 - 80
AS3675
Datasheet - Detailed Description
Table 85. CURR3x audio source Register (Continued)
CURR3x audio source
Controls CURR30,31,32,33 audio outputs and enables audio controlled LED
Addr: 53h
Bit
Bit Name
Default Access
Description
Audio controlled LED source for CURR33
All other modes
00
01
ch1 connected to CURR33, audio controlled
LED on
curr33_aud_src[1:0]
7:6
00b
R/W
ch2 connected to CURR33, audio controlled
LED on
10
11
ch3 connected to CURR33, audio contrlled
LED on
Table 86. filt_type Register
filt_type
Addr: 70h
efine requency filter types
Bit
Bit Name
Default Access
Descrption
nes filter1 (for ch1) characteristics and filter coefficients
1 and b2
00
01
10
11
don’t use
filt1_type[1:0]
filt2_type[1:0]
filt3_type[1:0
1:0
00b
00b
00b
R/W
R/W
R/W
lopass filter; filt1_b1=2, filt1_b2=1
high pass filter; filt1_b1=-2, filt1_b2=1
band pass filter; filt1_b1=0, filt1_b2=-1
Defines ter2 (for ch2) characteristics and filter coefficients
b1 and b2
00
01
10
11
don’t use
3:2
5:4
low pass filter; filt2_b1=2, filt2_b2=1
high pass filter; filt2_b1=-2, filt2_b2=1
band pass filter; filt2_b1=0, filt2_b2=-1
Defines filter3 (for ch3) characteristics and filter coefficients
b1 and b2
00
01
10
11
don’t use
low pass filter; filt3_b1=2, filt3_b2=1
high pass filter; filt3_b1=-2, filt3_b2=1
band pass filter; filt3_b1=0, filt3_b2=-1
Registers 71h to 82h efine the filter coefficients filt{1,2,3}_{A0,a1,a2}. Each of the coefficients is 12 bits wide and is
calculated acording to the following formula (2s complement number):
- Bitused as sign bit 0…positive number, 1…negative number
- Bitis multiplied by 2^0
Bit9 is multiplied by 2^-1
- …
- Bit 1 is multiplied by 2^-9
www.austriamicrosystems.com/AS3675
1v3
65 - 80
AS3675
Datasheet - Detailed Description
- Bit 0 is multiplied by 2^-10
Table 87. Filter Definitions Register
Register
Content
b4 b3
Definition
Addr
Name
b7
b6
b5
b2
b1
b0
filt1_A0[11:8]
filt1_a1[11:8]
filt1_a2[11:8]
filt2_A0[18]
fit2_a111:8]
filt_a2[11:8]
filt3_A0[11:8]
filt3_a1[11:8]
filt3_a2[11:8]
filt1_A0_MSB
filt1_A0_LSB
filt1_a1_MSB
filt1_a1_LSB
filt1_a2_MSB
filt1_a2_LSB
filt2_A0_MSB
filt2_A0_LSB
filt2_a1_MSB
filt2_a1_LSB
filt2_a2_MSB
filt2_a2_LSB
filt3_A0_MSB
filt3_A0_LSB
filt3_a1_MSB
filt3_a1_LSB
filt3_a2_MSB
filt3_a2_LSB
71h 00h
72h 00h
73h 00h
74h 00h
75h 00h
76h 00h
77h 00h
78h 00h
79h 00h
7ah 00h
7bh 00h
7ch 00h
7dh 00h
7eh 00h
filt1_A0[7:0]
filt1_a1[7:0]
filt1_a2 [7:0]
filt2_A0[7:0]
fil2_a1[7:0]
filt2_a2 [7:]
filt3_A[7:0]
filt3_a1[7:0]
filt3_a2[7:0]
7fh
00h
80h 00h
81h 00h
82h 00h
8.9
Power-On Reset
The internal reset is controlled by two sources:
ꢀ
ꢀ
VBAT Supply
Serial interface state (CLK, DATA)
The internal reset is forced if VBAT is low both interface pins (CLK, DATA) are low for more than tPOR_DEB (typ.
100ms)2. Then device enters shutown mode.
The reset levels control the stae of all registers. As long as VBAT and CLK/DATA are below their reset thresholds, the
register contents are set to defau. Access by serial interface is possible once the reset thresholds are exceeded.
2. Only if shutdwn_enab=1
www.austriamicrosystems.com/AS3675
1v3
66 - 80
AS3675
Datasheet - Detailed Description
Figure 33. Zero Power Device Wakeup block diagram
AS3675
#ꢋꢝꢀꢁꢐꢋꢆꢛꢇꢋꢛꢂꢆꢇꢀꢁꢆꢃꢄ
ꢁꢀꢈꢀꢁꢀꢆꢉꢀ%ꢛꢃꢆ'ꢛꢓ*ꢗ$ꢛꢊꢔ+
ꢓ,ꢘꢙ
ꢚꢀꢁꢋꢛꢜꢋꢝꢀꢁ
ꢔꢀ ꢂꢉꢀꢛ!ꢃꢑꢀ"#
ꢓ,ꢘꢙ
ꢓ,ꢘꢙ
%&"ꢇ'ꢆꢗ'ꢂ%ꢃ(
'ꢀ(ꢋ"ꢆꢉꢀ
ꢇꢂ)ꢀꢁ
ꢏ)%ꢕꢏꢒꢒ)%
ꢋꢆ
ꢓꢔꢔꢗꢅꢕꢙ
ꢈꢃ%ꢇꢗ%&"ꢇ'ꢝꢆ
ꢍꢎ
ꢏꢐꢏꢒꢑꢒ
ꢍ$
ꢓ*ꢗ$
ꢓ*ꢗ$
ꢔꢘꢙꢘ
ꢔꢘꢙꢘ
ꢒꢀꢁꢂꢃꢄ
ꢅꢆꢇꢀꢁꢈꢃꢉꢀ
ꢊꢋꢌꢂꢉ
ꢓ*ꢗ$
ꢖꢊꢗ
ꢖꢊꢗ
ꢓꢙ
Table 88. Audio input Parameters
Symbol
Parameter
Condition
Min
Typ
Max
2.41
1.38
Unit
Overall Power-On
Reset
Montor voltage on V2_5powon eset for
all internal funions.
VPOR_VBAT
1.8
2.15
V
Reset Level for pins
CLK, DATA
VPOR_PERI
Monitor voltage on pis CLK, DATA
0.29
1.0
V
Reset debounce tim
for pins CLK, DATA
tPOR_DEB
tstart
80
4
100
6
120
8
ms
ms
Interface Startup Time
1. Guaranteed by design - min./max. limits ot production tested
8.9.1 Reset control register
Table 89. Overtemp control Regier
Overtemp control
This register reads and resets the overtemperature flag.
Default Access Description
Addr: 29h
Bit
BiName
Enable Shutdown mode and serial interface reset.
Serial Interface reset disabled. Device does not
0
enter Shutdown mode
shutdwn_enab
4
0
R/W
Serial Interface reset enabled, device enters
shutdown when SCL and SDA remain low for
min. 120ms
1
8.10 Temperature Supervision
An integrated temperature sensor provides over-temperature protection for the AS3675. This sensor generates a flag
if the device temperature reaches the overtemperature threshold of 140º. The threshold has a hysteresis to prevent
oscillation effects.
www.austriamicrosystems.com/AS3675
1v3
67 - 80
AS3675
Datasheet - Detailed Description
If the device temperature exceeds the T140 threshold all current sources, the charge pump and the dcdc converter is
disabled and the ov_temp flag is set. After decreasing the temperature by THYST operation is resumed.
The ov_temp flag can only be reset by first writing a 1 and then a 0 to the register bit rst_ov_temp.
Bit ov_temp_on = 1 activates temperature supervision Table 91. It is recommend to leave this bit set (default state).
Table 90. Overtemperature Detection
Symbol
T140
Parameter
Condition
Min
Typ
140
5
Max
Unit
ºC
ov_temp Rising
Threshold
THYST
ov_temp Hysteresis
ºC
Table 91. Overtemp control Register
Overtemp control
This register reads and resets the overtemperaturflag.
Default Access Description
Addr: 29h
Bit
Bit Name
Activates/deactivates device temperture upervision.
DefaultOff - all other bits are only alid ithis bit is set to 1
Tmperature supervision is disabled. No reset
ov_temp_on
0
1
W
0
1
will be generateithdevice temperature
exceeds 140ºC
Tempeature supervision is enabled
Indicates hat the overtemperature threshold
has ben reached; this flag is not cleared by an
erteperature reset. It has to be cleared
using rst_ov_temp
ov_temp
1
2
N/A
0
R
1
The ov_temp flag is cleared by first setting this bit to 1, and
then setting this bit to 0.
rst_ov_temp
R/W
8.11 Serial Interface
The AS3675 is controlled using serial interface pins CLK DATA:
Figure 34. Serial interface block diagram
ꢓꢔꢔꢗꢅꢕꢙ
ꢍꢎ
ꢏꢐꢏꢒꢑꢒ
AS3675
ꢍꢓ
ꢔꢘꢙꢘ
ꢔꢘꢙꢘ
-ꢀꢁꢂꢃꢄ
ꢅꢆꢇꢀꢁꢈꢃꢉꢀ
ꢊꢋꢌꢂꢉ
ꢖꢊꢗ
ꢖꢊꢗ
www.austriamicrosystems.com/AS3675
1v3
68 - 80
AS3675
Datasheet - Detailed Description
The clock line CLK is never held low by the AS3675 (as the AS3675 does not use clock stretching of the bus).
Table 92. Serial Interface Timing
Symbol
Parameter
Condition
Min
Typ
Max
Unit
High Level Input
Voltage
VIHI/F
1.38
VBAT
V
Low Level Input
Voltage
VILI/F
0.0
0.52
V
Pins DATA and CLK
VHYSTI/F
tRISE
Hysteresis
Rise Time
0.1
V
0
0
1000
300
ns
ns
ns
ns
tFALL
Fall Time
tCLK_FILTER
tDATA_FILTER
Spike Filter on CLK
Spike Filter on DATA
100
300
The AS3675 is compatible to the NXP two wire specification http://www.nxp.com/acrobat_downlod/liteature/9398/
39340011.pdf, Version 2.1, January 2000 for standard and fast mode (no high speed mode) with the ollowing excep-
tion:
Data set-up time for fast mode: tSU;DAT=250ns (instead of 100ns rom le 5, p32)
8.11.1 Serial Interface Features
ꢀ
ꢀ
ꢀ
Fast Mode Capability (Maximum Clock Frequency is 4z
7-bit Addressing Mode
Write Formats
- Single-Byte Write
- Page-Write
ꢀ
ꢀ
Read Formats
- Current-Address Read
- Random-Read
- Sequential-Read
DATA Input Delay and CLK spike filtering by integracomponents
8.11.2 Device Address Selection
The serial interface address of the AS3675 has the following address:
ꢀ
ꢀ
80h – Write Commands
81h – Read Commands
Figure 35. Complete Serial Data ransfer
DATA
CLK
8
9
1-7
8
9
1-7
1-7
8
9
P
S
Stop
Condition
Start
Condition
Address R/W
ACK
Data
ACK
Data
ACK
Serial Data Transfer Formats
www.austriamicrosystems.com/AS3675
1v3
69 - 80
AS3675
Datasheet - Detailed Description
Definitions used in the serial data transfer format diagrams are listed in the following table:
Table 93. Serial Data Transfer Byte Definitions
Symbol
Definition
Start Condition after Stop
Repeated Start
R/W (AS3675 Slave)
Note
S
Sr
R
R
R
R
R
W
R
R
R
R
R
1 bit
1 bit
10000000b (80h).
10000001b (81h)
8 bits
DW
DR
Device Address for Write
Device Address for Read
Word Address
WA
A
Acknowledge
1 bit
N
Not Acknowledge
1 bit
reg_data
data (n)
P
Register Data/Write
Register Data/read
Stop Condition
8 bits
1 it
8 bits
WA++
Increment Word Address Internally
ring Acknowledge
Figure 36. Serial Interface Byte Write
S
DW
A
WA
A
reg_data
A P
Writegister
WA++
AS3675
AS367
(e) ceives data
(= Slavetransmits data
Figure 37. Serial Interface Page Write
n
S
DW
A
WA
reg_data 1
A
reg_ta 2
A
…
reg_data
A P
ister
WA++
Write Register
WA++
Write Register
WA++
AS3675
AS3675
(= Slave) receives data
(= Slave) transmits data
Byte Write and Page Write formats are usd to rite data to the slave.
The transmission begins with the START dition, which is generated by the master when the bus is in IDLE state
(the bus is free). The device-write ddress is followed by the word address. After the word address any number of data
bytes can be sent to the slave. Thwod address is incremented internally, in order to write subsequent data bytes on
subsequent address locations.
For reading data from the slavdevice, the master has to change the transfer direction. This can be done either with a
repeated START condition ollowed by the device-read address, or simply with a new transmission START followed by
the device-read adesswhen the bus is in IDLE state. The device-read address is always followed by the 1st register
byte transmitted frothe slave. In Read Mode any number of subsequent register bytes can be read from the slave.
The word addess is incremented internally.
The followng diagrams show the serial read formats supported by the AS3675.
Fure 38Serial Interface Random Read
S
DW
A
WA
A
Sr
DR
A
data
N P
Read Register
WA++
AS3675
AS3675
(= slave) receives data
(= slave) transmits data
www.austriamicrosystems.com/AS3675
1v3
70 - 80
AS3675
Datasheet - Detailed Description
Random Read and Sequential Read are combined formats. The repeated START condition is used to change the
direction after the data transfer from the master.
The word address transfer is initiated with a START condition issued by the master while the bus is idle. The START
condition is followed by the device-write address and the word address.
In order to change the data direction a repeated START condition is issued on the 1st CLKpulse after the ACKNOWL-
EDGE bit of the word address transfer. After the reception of the device-read address, the slave becomes the transmit-
ter. In this state the slave transmits register data located by the previous received word address vector. The master
responds to the data byte with a NOT ACKNOWLEDGE, and issues a STOP condition on the bus.
Figure 39. Serial Interface Sequential Read
n
S
DW
A
WA
A
Sr
DR
A
data 1
A
data 2
...
A
data
N
Read Register
WA++
AS3675
AS3675
(= slave) receives data
(= slave) transmits data
Sequential Read is the extended form of Random Read, as multiple register-data bytes are subsquetly transferred.
In contrast to the Random Read, in a sequential read the transfered register-data bytes are repondd by an acknowl-
edge from the master. The number of data bytes transferred in oe sequnce is unlimited (considthe behavior of the
word-address counter). To terminate the transmission the master as to send a NOT ACKOWLEDGE following the
last data byte and subsequently generate the STOP cond
Figure 40. Serial Interface Current Address Read
n
S
DR
A
data 1
A
data 2
A
data
N P
Read Register
WA++
Read Register
WA++
Read Register
WA++
AS3675
(= slave) eceives data
AS3675
(= e) transmits data
To keep the access time as small as possible, this formws a read access without the word address transfer in
advance to the data transfer. The bus is idle and the master issues a START condition followed by the Device-Read
address.
Analogous to Random Read, a single byte ansfer is terminated with a NOT ACKNOWLEDGE after the 1st register
byte. Analogous to Sequential Read an unlimid number of data bytes can be transferred, where the data bytes must
be responded to with an ACKNOWLEDGE om the master.
For termination of the transmission the mter sends a NOT ACKNOWLEDGE following the last data byte and a sub-
sequent STOP condition.
8.12 Operating Modes
If the voltage on CLK anDATA is less than 1V (for > tPOR_DEB), the AS3675 is in shutdown mode and its current con-
sumption is minimized (IBAT = ISHUTDOWN) and all internal registers are reset to their default values.
If the voltage at CLor DATA rises above 1V, the AS3675 serial interface is enabled and the AS3675 and the standby
mode is selected. The AS3675 is switched automatically from standby mode (IBAT = ISTANBY) into normal mode (IBAT =
IACTIVE) and bck, one of the following blocks are activated:
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Chapump
Step p rgulator
ny current sink
ADC conversion started
PWM active
Pattern mode active.
If any of these blocks are already switched on the internal oscillator is running and a write instruction to the registers is
directly evaluated within 1 internal CLK cycle (typ. 1µs)
www.austriamicrosystems.com/AS3675
1v3
71 - 80
AS3675
Datasheet - Detailed Description
If all these blocks are disabled, a write instruction to enable these blocks is delayed by 64 CLK cycles (oscillator will
startup, within max 200µs).
www.austriamicrosystems.com/AS3675
1v3
72 - 80
AS3675
Datasheet - Register Map
9 Register Map
Table 94. Registermap
Register
Content
b4 b3
Definition
Name
b7
b6
b5
b2
b1
b0
ldo_ana
_lpo
step_up
_on
ldo_ana
_on
cp_on
Reg. control
00h
00
curr2_mode
curr1_mode
rgb1_mode
curr12 control
curr rgb control
curr3 control1
curr4 control
01h 00h
02h 00h
03h 00h
04h 00h
curr6_mode
rgb3_mode
rgb2_mode
curr31_mode
curr42_mode
curr33_mode
curr32_mode
curr43_mode
curr30_mode
curr41_mode
gpi_curr
32_en
gpi_curr
30_en
gpi_curr
6_en
gpi_curr
1_en
gpi_curr
g_curr
gpi_curr
GPIO output 1
GPIO signal 1
05h 00h
06h 00h
07h 00h
31_en
2_n
33_en
gpi_curr
32_in
gpi_curr
30_in
gpi_curr
6_n
gpi_curr
1_in
gpi_curr
31_in
gpicurr
2_in
gpi_curr
33_in
LDO ANA1
Voltage
ldo_ana_voltage
curr1_current
Curr1 current
Curr2 current
Rgb1 current
Rgb2 current
Rgb3 current
Curr3x strobe
Curr3x preview
Curr3x other
09h 00h
0Ah 00h
0Bh 00h
0Ch 00h
0Dh 00h
0Eh 00h
0Fh 00h
10h 00h
curr2_current
rgb1_crren
rgcurrent
rg3_urrent
curr3x_strobe
curr3x_preview
curr3x_other
Curr3 strobe
control
stobe_timing
strobe_mode
strobe_ctrl
11h 00h
12h 00h
curr3x_s
trobe_hi
gh
preview_
off_after
strobe
strobe_p
in
preview_ctrl
Curr3 control2
curr41_current
Curr41 current
Curr42 current
Curr43 current
Pwm control
pwm code
13h 00h
14h 00h
15h 00
16h 0h
1h 00h
curr42_current
curr43_current
pwm_dim_speed
pwm_code
curr33_p curr32_p curr31_p curr30_p softdim_
pwm_dim_mode
pattern_delay
pattern_
color
Pattern control
18h 00h
attern attern attern attern pattern
pattern_data[7:0]
Pattern dat0
Pattdaa1
attern data2
Pattern data3
GPIO control
19h 00h
1Ah 00h
1Bh 00h
1Ch 00h
1Eh 44h
pattern_data[15:8]1111
pattern_data[23:16]1111
pattern_data[31:24]1111
gpio_pulls
gpio_mode
gpio_low
_curr
GPIO driving cap 20h 00h
www.austriamicrosystems.com/AS3675
1v3
73 - 80
AS3675
Datasheet - Register Map
Table 94. Registermap
Register
Content
b4 b3
Definition
Name
b7
b6
b5
b2
b1
b0
step_up
_frequ
step_up_vtuning
step_up_fb
DCDC control1
DCDC control2
21h 00h
Step
up_lowc
ur
step_up curr6_pr curr2_pr curr1_pr
step_up
_prot
step_up
_res
skip_fast
22h 04h
23h 00h
_fb_auto ot_on
ot_on
ot_on
cp_start
_deboun
ce
cp_auto
_on
cp_mode_switchin
g
cp_mode
cp_clk
CP control
rgb3_on rgb2_on rgb1_on curr33_o curr32_o curr31_o cur30_
CP mode Switch1 24h 00h
CP mode Switch2 25h 00h
_cp
_cp
_cp
n_cp
n_cp
n_cp
ncp
curr6_on
_cp
curr43_o curr42_o curr41_o cur2_on curr1_on
n_cp
n_cp
n_cp
_c
_cp
start_co
nversion
adc_on
adc_select
D9:D3
ADC_control
26h 03h
result_n
ot_ready
ADC_MSB result 27h
ADC_LSB result 28h
NA
NA
D2:D0
shutdwn
_enab
rst_ov_t
emp
ov_temp
_on
ov_temp
Overtemp control 29h 01h
curr6_lo rgb3_low rgb2_low rgb1_low curr33_l curr32_l curr31_l curr30_l
Curr low voltage
2Ah NA
status1
w_v
_
_v
_v
w_v
ow_v
ow_v
ow_v
curr_l curr42_l curr41_l curr2_lo curr1_lo
Curr low voltage
2Bh NA
status2
w_v
ow_v
ow_v
w_v
w_v
pattern_
slow
pattern_
delay2
gpio current
curr6 current
2Ch 00h
2Fh 00h
curr6_current
adder_current1
(cn be enabled for CURR30, CURR1, RGB1, CURR41)
Adder Current 1 30h 00h
Adder Current 2 31h 00h
Adder Current 3 32h 00h
adder_current2
(can be enabled for CURR31, CURR2, RGB2, CURR42)
adder_current3
(can be enabled for CURR32, CURR6, RGB3, CURR43)
curr43_a curr42_a curr41_a rgb3_ad rgb2_ad rgb1_ad
dder dder dder der der der
Adder Enable 1
Adder Enable 2
33h 00h
34h 00h
curr33_a curr32_a curr31_a curr30_a curr6_ad curr2_ad curr1_ad
dder
dder
dder
dder
der
der
der
sub_en4 sub_en3 sub_en2 sub_en1
Subtract Enable 3h 00h
ASIC ID1
3Eh CBh
3Fh 5Xh
40h 00h
41h 00h
42h 00h
43h 00h
1
0
1
1
0
0
0
1
1
0
1
1
ASIC ID
revision
curr30_current
curr31_current
curr32_current
curr33_current
Curr3rrent
Curr31 current
Cur32 current
Curr33 current
freq_mo
de
aud_buf
_on
audio_speed
audio_color
Audio Control
46h 00h
www.austriamicrosystems.com/AS3675
1v3
74 - 80
AS3675
Datasheet - Register Map
Table 94. Registermap
Register
Content
b4 b3
agc_ctrl
Definition
Name
b7
b6
b5
b2
b1
b0
audio_di audio_m
s_start an_start
audio_gain
Audio input
Audio output
GPIO output 2
GPIO signal 2
47h 00h
curr4x_a rgbx_au curr126_
ud_on d_on aud_on
aud_amplitude
48h 00h
50h 00h
51h 00h
gpi_curr gpi_curr gpi_curr gpi_rgb3 gpi_rgb2 gpi_rgb1
43_en 42_en 41_en _en _en _en
gpi_en gpio_out
gpi_ in gpio _i
gpi_curr gpi_curr gpi_curr gpi_rgb3 gpi_rgb2 gpi_rgb1
43_in 42_in 41_in _in _in _in
adder_current4
(can be enabled for CURR33)
Adder Current 4 52h 00h
curr33_aud_src[1:0 curr32_aud_src[1:0 curr31_aud_src[1:0 curr0_aud_src[1:0
CURR3x audio
53h 00h
source
]
]
]
]
pattern_
end
Pattern End
54h 00h
filt3_pe[1:0
filt2_type[1:0]
filt1_type[1:0]
filt_type
70h 00h
71h 00h
72h 00h
73h 00h
74h 00h
75h 00h
76h 00h
77h 00h
78h 00h
79h 00h
7ah 00h
7bh 00h
7ch 00h
7dh 00h
7eh 00h
filt1_A0[11:8]
filt1_A0_MSB
filt1_A0_LSB
filt1_a1_MSB
filt1_a1_LSB
filt1_a2_MSB
filt1_a2_LSB
filt2_A0_MSB
filt2_A0_LSB
filt2_a1_MSB
filt2_a1_LSB
filt2_a2_MSB
filt2_a2_LSB
filt3_A0_MSB
filt3_A0_LSB
filt3_a1_MSB
filt3_a1_LSB
filt3_a2_MSB
filt3_a2_LSB
filt1_A0[7:0]
filt1_a1[11:8]
filt1_a2[11:8]
filt2_A0[11:8]
filt2_a1[11:8]
filt2_a2[11:8]
filt3_A0[11:8]
filt3_a1[11:8]
filt3_a2[11:8]
filt1_a1[:0]
ilt1_a2 [7:0]
filt2_A0[7:0]
filt2_a1[7:0]
filt2_a2 [7:0]
filt3_A0[7:0]
filt3_a1[7:0]
filt3_a2[7:0]
7fh
00h
8000
8h 00h
82h 00h
Note: If writinto register, write 0 to unused bits
ite to read only bits will be ignored
yellow color = read only
www.austriamicrosystems.com/AS3675
1v3
75 - 80
AS3675
Datasheet - External Components
10 External Components
Table 95. External Components List
Value
tol.
(min.)
Rating
(max)
Package
(min.)
Part Number
Min
Max
Notes
Typ
Ceramic, X5R (V2_5 output)
(e.g. Taiyo Yuden
C1
1µF
±20%
±20%
±20%
±20%
±20%
±20%
±20%
±20%
6.3V
6.3V
6.3V
6.3V
.3V
6.3V
25V
0402
0402
002
0402
0403
0402
0402
0402
JMK105BJ105KV-F)
Ceramic, X5R (VBAT) (e.g.
Taiyo Yuden JMK105BJ105KV-
F)
C2
C3
C4
C5
C6
C7
C8
1µF
1µF
Ceramic, X5R (Charge Pump)
(e.g. Taiyo Yuden
JMK105BJ105KV-F)
Ceramic, X5R (Charge Pup)
(e.g. Taiyo Yuden
1µF
JMK105BJ105KV-F)
Ceramic, X5R (Charge ump
Output) (e.g. TaiyYuden
JMK107BJ225MAT)
2.2µF
1µF
Ceramic, X5R (Step Up DCDC
input) (e.g. Taiyo Yuden
JM105BJ105KV-F)
Cerm, X5R (Step Up DCDC
eedbck, 150pF for over
voltage protection)
1.5nF
15nF
Ceamic, X5R (Step Up DCDC
Feedback, 1.5nF for over
voltage protection)
6.
Ceramic, X5R, X7R (Step Up
DCDC output)
3.2x1.6x
1.25mm
C9
4.7µF
±20
±20%
25V
(e.g. Taiyo Yuden
TMK316BJ475KG)
Ceramic, X5R (Vana1 output)
(e.g. Taiyo Yuden
C10
2.2µF
6.3V
0403
JMK107BJ225MA-T)
only required if LDO is used
R1
R2
100mΩ
1MΩ
±5%
±1%
Shunt Resistor
0603
0201
Step Up DC/DC Converter
Voltage Feedback
Step Up DC/DC Converter
Voltage Feedback - not
required for over voltage
protection
R3
00kΩ
±1%
±1%
0201
DATA Pullup resistor – usually
already inside master
R4
R5
1-10kΩ
0201
0201
CLKPullup resistor – usually
already inside master
Recommended Type:
Murata LQH3NPN100NJ0,
Panasonic ELLSFG100MA
or TDK VLF3012A
3x3x1.2m
m
L1
10µH
±20%
Integrated NMOS and Schottky MicroFET
Q1 (+ D1)
D2:D14
FDFMA3N109
LED
diode
2x2mm
As required by application
www.austriamicrosystems.com/AS3675
1v3
76 - 80
AS3675
Datasheet - Package Drawings and Markings
11 Package Drawings and Markings
Figure 41. WL-CSP30 3x2.5mm 6x5 Balls Package Drawing
ꢙꢅꢚꢃꢕꢛ
ꢜꢚꢔꢅꢝꢑꢉꢁꢋ
ꢀꢁꢂꢃꢄꢅꢆꢇꢃꢈꢉꢊꢋꢁꢌꢍꢊꢎ
ꢏꢁꢉꢉꢁꢐꢃꢄꢅꢆꢇꢃꢈꢏꢑꢒꢒꢃꢓꢅꢔꢆꢎ
#
" ! ꢛ
ꢛ
!
"
#
$
$
ꢕ
ꢏ
ꢖ
ꢗ
ꢘ
ꢕ
ꢏ
ꢖ
ꢗ
ꢘ
ꢕ
ꢏ
ꢖ
ꢗ
ꢘ
ꢕ
ꢏ
ꢖ
ꢗ
ꢘ
3675
<Code>
ꢛ
!
"
#
$
$
#
"
!
ꢛ
Note:
Line 1:
Line 2:
Line 3:
austriamicrosystems logo
3675
<Code>
Encode datecode 4 characters
Figure 42. WL-CSP30 3x2.5mm 6x5 Balls Detail Dimensions
ꢜꢐꢝꢄꢒꢓꢔꢕꢄꢖꢑ !ꢐ"# ꢛ
ꢏꢐꢊꢄꢒꢕꢄꢖꢏꢗꢘꢘꢄꢙꢓꢚꢔꢛ
ꢙꢓꢚꢔꢄꢒꢓꢔꢕ
ꢀꢃꢁ ꢈꢃꢁ
ꢅꢆꢇ'ꢁ ꢅꢆꢇꢈꢁ
$ꢓ%ꢄ&'
(%ꢚꢓ)ꢗꢑꢐ!
&ꢙꢀꢂꢎꢃꢆ&ꢙꢀꢂꢎꢂ
ꢈꢌꢈꢍꢃ
ꢉꢊ
ꢈꢌꢈꢍꢃ
ꢉꢊ
ꢃꢉꢊ
ꢃꢁꢁꢉꢊ
ꢃꢁꢁꢉꢊ
ꢃꢁꢁꢉꢊ
ꢃꢁꢁꢉꢊ
ꢉꢊ
ꢉꢊ
&ꢙꢀꢂꢌꢎ
&'
ꢏ'
*'
+'
,'
&ꢈ
ꢏꢈ
*ꢈ
+ꢈ
,ꢈ
&ꢀ
ꢏꢀ
*ꢀ
+ꢀ
,ꢀ
&ꢋ
ꢏꢋ
*ꢋ
+ꢋ
,ꢋ
ꢏꢃ
*ꢃ
+ꢃ
,ꢃ
&ꢂ
ꢏꢂ
*
+ꢂ
,ꢂ
ꢏꢂ
*ꢂ
+ꢂ
,ꢂ
&ꢃ
&ꢋ
ꢏꢋ
*ꢋ
+ꢋ
,ꢋ
&ꢀ
ꢏꢀ
*ꢀ
+ꢀ
,ꢀ
&ꢈ
ꢏꢈ
*ꢈ
+ꢈ
,ꢈ
&'
ꢏ'
*'
+'
,'
ꢏꢃ
*ꢃ
+ꢃ
,ꢃ
ꢉꢊ
ꢁ
ꢁ
4ꢀ
ꢀꢁꢂꢃꢈꢁꢉꢊ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢁꢉꢊ
ꢂꢁꢁꢄꢅꢆꢇꢀꢁꢉꢊ
ꢏꢗꢘꢘ-ꢄ&ꢀꢇ&ꢂ.ꢄꢏꢀꢇꢍꢍꢍꢄꢑꢐꢄ,ꢀꢇ,ꢂꢄꢗ!ꢔꢄꢝꢓ%ꢇ)ꢐꢊꢝꢗꢑꢓ/ꢘꢔ
ꢑꢐꢄ&ꢙꢀꢂꢌꢎ0ꢄꢄꢗꢄ-ꢓ%#ꢘꢔꢄ$*ꢏꢄ)ꢗ%ꢄ"-ꢔꢄꢑ ꢔꢄꢓꢚꢔ%ꢑꢓ)ꢗꢘ
ꢘꢗ1ꢐ"ꢑꢄ2ꢐ!ꢄ&ꢙꢀꢂꢌꢎꢄꢗ%ꢚꢄ&ꢙꢀꢂꢎꢃꢆꢎꢂꢄꢗ%ꢚꢄ-ꢐꢘꢚꢔ!ꢄ&ꢙꢀꢂꢌꢎ
ꢐ!ꢄ&ꢙꢀꢂꢎꢃꢆꢎꢂꢄꢚꢔꢝꢔ%ꢚꢓ%#ꢄꢐ%ꢄꢑ ꢔꢄ2"%)ꢑꢓꢐ%-ꢄ!ꢔ3"ꢓ!ꢔꢚ
www.austriamicrosystems.com/AS3675
1v3
77 - 80
AS3675
Datasheet - Package Drawings and Markings
11.1 Tape & Reel Information
Figure 43. Tape & Reel Dimensions
www.austriamicrosystems.com/AS3675
1v3
78 - 80
AS3675
Datasheet - Ordering Information
12 Ordering Information
The devices are available as the standard products shown in Table 96.
Table 96. Ordering Information
Model
Description
Delivery Form
Package
AS3675
30pin WL-CSP
(3x2.5mm)
RoHS compliant / Pb-Free
Wafer Level Chip Scale Package,
size 3x2.5mm, 6x5 balls, 0.5mm pitch,
Pb-Free
AS3675-ZWLT
Tape & Reel
Note: AS3675-ZWLT
AS3675-
Z
Temperature Range: -30ºC - 85ºC
WL Package: Wafer Level Chip Scale Package (WL-CSP) 3x2.5mm
Delivery Form: Tape & Reel
T
www.austriamicrosystems.com/AS3675
1v3
79 - 80
AS3675
Datasheet - Ordering Information
Copyrights
Copyright © 1997-2010, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe.
Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, trans-
lated, stored, or used without the prior written consent of the copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing
in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regadin
the information set forth herein or regarding the freedom of the described devices from patent infringement. autria
crosystems AG reserves the right to change specifications and prices at any time and without notice. Therefre, prior
to designing this product into a system, it is necessary to check with austriamicrosystems AG for curent information.
This product is intended for use in normal commercial applications. Applications requiring extendetemperature
range, unusual environmental requirements, or high reliability applications, such as military, medical le-support or life-
sustaining equipment are specifically not recommended without adional processing by auramrosystems AG for
each application. For shipments of less than 100 parts the manufcturiflow might show deviaons from the standard
production flow, such as test flow or test location.
The information furnished here by austriamicrosystems Aelieved to be correct and acurate. However, austriami-
crosystems AG shall not be liable to recipient or any third pfor any damages, cluding but not limited to personal
injury, property damage, loss of profits, loss of use, interruptn of business or iirecspecial, incidental or conse-
quential damages, of any kind, in connection with or arising out of the furnisng, prformance or use of the technical
data herein. No obligation or liability to recipient oy hird party shall e or ow out of austriamicrosystems AG
rendering of technical or other services.
Contact Informati
Headquarters
austriamicrosstems AG
Tobelbarasse 30
Shloss emstätten
A-841 Austria
Tel: +43 (0) 3136 500 0
Fax: +43 (0) 3136 525 01
For Sales Offices, Distributors and Representatives, please visit:
http://www.austriamicrosystems.com/contact
www.austriamicrosystems.com/AS3675
1v3
80 - 80
相关型号：
AS3677
Triple Channel Lighting Management Unit with DCDC step/up, ALS, 2xDLS(=DBC) and RGB Driver
AMSCO
AS3677-ZWLT
Triple Channel Lighting Management Unit with DCDC step/up, ALS, 2xDLS(=DBC) and RGB Driver
AMSCO
©2020 ICPDF网 联系我们和版权申明