AS5215-HQFT [AMSCO]
Programmable 360º Magnetic Angle Encoder with Buffered SINE & COSINE Output Signals; 可编程360°磁性角度编码器与缓冲正弦余弦和输出信号
| 型号： | AS5215-HQFT |
| 厂家： | 
AMS(艾迈斯) |
| 描述： | Programmable 360º Magnetic Angle Encoder with Buffered SINE & COSINE Output Signals |
| 文件： | 总24页 (文件大小：739K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet
AS5215
Programmable 360º Magnetic Angle Encoder with Buffered SINE &
COSINE Output Signals
1 General Description
The AS5215 is a redundant, contactless rotary encoder sensor for
accurate angular measurement over a full turn of 360º and over an
extended ambient temperature range of -40ºC to +150ºC.
2 Key Features
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Contactless angular position encoding
High precision analog output
Buffered Sine and Cosine signals
Based on an integrated Hall element array, the angular position of a
simple two-pole magnet is translated into analog output voltages.
The angle information is provided by means of buffered sine and
cosine voltages. This approach gives maximum flexibility in system
design, as it can be directly integrated into existing architectures and
optimized for various applications in terms of speed and accuracy.
SSI Interface
Low power mode
Two programmable output modes: Differential or Single ended
Wide magnetic field input range: 20 – 80 mT
Wide temperature range: -40ºC to +150ºC
Fully automotive qualified to AEC-Q100, grade 0
Thin punched 32-pin QFN (7x7mm) package
With two independent dies in one package, the device offers true
redundancy. Usually the bottom die, which is exposed to slightly less
magnetic field is employed for plausibility check.
An SSI Interface is implemented for signal path configuration as well
as a one time programmable register block (OTP), which allows the
customer to adjust the signal path gain to adjust for different
mechanical constraints and magnetic field.
3 Applications
The AS5215 is ideal for Electronic Power Steering systems and
general purpose for automotive or industrial applications in
microcontroller-based systems.
Figure 1. AS5215 Block Diagram
OTP Register
PROG
AS5215
Digital Part
CS
VDD
VSS
POWER
MANAGEMENT
SSI Interface
DCLK
DIO
BUFFER Stage
BUFFER Stage
SINP/SINN
SINN/SINP/CM_SIN
COSP/COSN
Hall Array
&
Frontend
COSN/COSP/CM_COS
Amplifier
Note: This Block Diagram presents only one die.
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AS5215
Data Sheet - Contents
Contents
1 General Description ..................................................................................................................................................................
2 Key Features.............................................................................................................................................................................
3 Applications...............................................................................................................................................................................
4 Pin Assignments .......................................................................................................................................................................
4.1 Pin Descriptions....................................................................................................................................................................................
5 Absolute Maximum Ratings ......................................................................................................................................................
6 Electrical Characteristics...........................................................................................................................................................
6.1 Timing Characteristics..........................................................................................................................................................................
7 Detailed Description..................................................................................................................................................................
7.1 Magnet Diameter and Vertical Distance ...............................................................................................................................................
1
1
1
3
3
5
6
7
8
8
7.1.1 The Linear Range........................................................................................................................................................................ 8
7.1.2 Magnet Thickness...................................................................................................................................................................... 11
7.1.3 Axial Distance (Airgap) .............................................................................................................................................................. 12
7.1.4 Angle Error vs. Radial and Axial Misalignment.......................................................................................................................... 12
7.1.5 Mounting the Magnet................................................................................................................................................................. 12
7.1.6 Summary ................................................................................................................................................................................... 14
8 Application Information ........................................................................................................................................................... 15
8.1 Sleep Mode ........................................................................................................................................................................................ 15
8.2 SSI Interface....................................................................................................................................................................................... 15
8.3 Device Communication / Programming.............................................................................................................................................. 16
8.4 Waveform – Digital Interface at Normal Operation Mode................................................................................................................... 18
8.5 Waveform – Digital Interface at Extended Mode ................................................................................................................................ 18
8.6 Waveform – Digital Interface at Analog Readback of the Zener Diodes ............................................................................................ 19
8.7 EasyZapp OTP Content ..................................................................................................................................................................... 19
8.8 Analog Sin/Cos Outputs with External Interpolator ............................................................................................................................ 20
8.9 OTP Programming.............................................................................................................................................................................. 21
9 Package Drawings and Markings ........................................................................................................................................... 22
10 Ordering Information............................................................................................................................................................. 24
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AS5215
Data Sheet - Pin Assignments
4 Pin Assignments
Figure 2. Pin Assignments (Top View)
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
DIO_1
DIO_2
24
23
22
21
20
19
18
17
NC
NC
TC_1
NC
TC_2
NC
AS5215
A_TST_1
A_TST_2
PROG_1
PROG_2
NC
NC
COSN_2 / COSP_2 / CM_COS_2
COSP_2 / COSN_2
9
10 11 12 13 14 15 16
4.1 Pin Descriptions
Table 1. Pin Descriptions
Pin Name
DIO_1
Pin Number
Description
1
Data I/O for digital interface
Test coil
DIO_2
2
3
4
5
6
7
8
TC_1
TC_2
A_TST_1
A_TST_2
PROG_1
PROG_2
Analog test pin
OTP Programming Pad
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AS5215
Data Sheet - Pin Assignments
Table 1. Pin Descriptions
Pin Name
Pin Number
Description
VSS_1
9
Supply ground
VSS_2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Switchable buffered analog output
SINP_1 / SINN_1
Switchable buffered analog or common mode output
Switchable buffered analog output
SINN_1 / SINP_1 / CM_SIN_1
SINP_2 / SINN_2
Switchable buffered analog or common mode output
Switchable buffered analog output
SINN_2 / SINP_2 / CM_SIN_2
COSP_1 / COSN_1
Switchable buffered analog or common mode output
Switchable buffered analog output
COSN_1 / COSP_1 / CM_COS_1
COSP_2 / COSN_2
Switchable buffered analog or common mode output
COSN_2 / COSP_2 / CM_COS_2
NC
NC
NC
NC
------
NC
NC
NC
NC
VDD_1
VDD_2
DCLK_1
DCLK_2
CS_1
CS_2
Digital + analog supply
Clock input for digital interface
Clock input for digital interface
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AS5215
Data Sheet - Absolute Maximum Ratings
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of
the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 6 is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Table 2. Absolute Maximum Ratings
Parameter
Min
-0.3
Max
7
Units
V
Comments
Supply voltage (VDD)
Input pin voltage (V_in)
VSS - 0.5
-100
7
V
Input current (latchup immunity), I_scr
Electrostatic discharge (ESD)
100
±2
275
27
mA
kV
Norm: EIA/JESD78 Class II Level A
Norm: JESD22-A114E
Total power dissipation (Ptot
)
mW
ºC/W
ºC
Package thermal resistance (Θ_JA)
Velocity =0; Multi Layer PCB; Jedec Standard Testboard
Storage temperature (T_strg)
-65
150
Norm: IPC/JEDEC J-STD-020C.
The reflow peak soldering temperature (body temperature)
specified is in accordance with IPC/JEDEC J-STD-020C
“Moisture/Reflow Sensitivity Classification for Non-
Hermetic Solid State Surface Mount Devices”.
The lead finish for Pb-free leaded packages is matte tin
(100% Sn).
Package body temperature (T_body)
Humidity non-condensing
260
85
ºC
%
5
MSL = 3
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AS5215
Data Sheet - Electrical Characteristics
6 Electrical Characteristics
Unless otherwise noted all in this specification defined tolerances of parameters are assured over the whole operation conditions range and also
over lifetime.
Table 3. Operating Conditions
Symbol
VDD
Parameter
Condition
Min
4.5
0.0
-40
Typ
Max
5.5
Unit
V
Positive Supply Voltage
Negative Supply Voltage
Ambient temperature
VSS
0.0
V
T_amb
150
ºC
Table 4. DC/AC Characteristics for Digital Inputs and Outputs
Symbol
Parameter
Condition
Min
Typ
Max
Unit
CMOS Input
0.7 *
VDD +
V_IH
V_IL
High level Input voltage
V
VDD
0.5
VDD -
0.5
VDD +
0.5
Low level Input Voltage
Input Leakage Current
V
I_LEAK
1
µA
CMOS Output
VDD -
0.5
V_OH
V_OL
High level Output voltage
Low level Output Voltage
4 mA
4 mA
V
V
VSS +
0.4
C_L
Capacitive Load
Slew Rate
35
30
15
pF
ns
ns
t_slew
t_delay
Time Rise Fall
CMOS Output Tristate
I_OZ
Tristate Leakage Current
1
µA
Table 5. Magnetic Input Specification
Symbol
Parameter
Condition
Min
Typ
Max
Unit
Two pole cylindrical magnet, diametrically magnetized:
dMAG
Bpp
Diameter
4
20
0
6
mm
mt
Magnetic input field amplitude
Rotational speed
200 – 800 Gauss
Max 30000 RPM
50
80
frot
500
Hz
Table 6. Electrical System Specifications
Symbol
tpower_on
tprop
Parameter
Power up time
Condition
Min
200
18
Typ
500
22
Max
700
30
Unit
µs
Propagation delay
Magnetic Sensitivity
-40 to 150ºC
1G = 0.1 mT
µs
M
1
6
mV/G
Vss+
0.25
Vdd-
0.5
Vout
Analog output range
V
SF=SF25C
- (AP1_1/
AP2_1)
Amplitude ratio tracking accuracy
over temperature
-40 to 150ºC
Revision 1.8
-1
+1
%
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AS5215
Data Sheet - Electrical Characteristics
Table 6. Electrical System Specifications
Symbol
Parameter
Condition
Min
Typ
Max
Unit
SF=AP1_ Amplitude ratio mismatch at room
-2
2
%
1/AP2_1
Voffset1
Voffset2
DCoffdrift
THD
temperature
DC Offset
0.294
0.49
-50
0.3
0.5
0.306 V / VDD
Ratiometric to VDD
0.51
+50
0.2
V / VDD
µV/ºC
%
DC Offset Drift
Total Harmonic Distortion
Slew Rate
-40 to 150ºC
SR
1
V/µs
pF
CLOAD
Capacitive Load
1000
6.1 Timing Characteristics
Table 7. Timing Characteristics
Symbol
t1_3
Parameter
Condition
Min
30
0
Typ
Max
Unit
ns
Chip select to positive edge of DCLK
Chip select to drive bus externally
-
-
t2_3
ns
Setup time command bit
Data valid to positive edge of DCLK
t3
t4
t5
30
15
-
-
-
ns
ns
ns
Hold time command bit
Data valid after positive edge of DCLK
Float time
DCLK/
2+0
Positive edge of DCLK for last command bit to bus float
Bus driving time
Positive edge of DCLK for last command bit to bus
drive
DCLK/
2+0
t6
-
ns
Data valid time
Positive edge of DCLK to bus valid
DCLK/
2+0
DCLK/
2+30
t7
t8
ns
ns
ns
ns
ns
ns
ns
Hold time data bit
Data valid after positive edge of DCLK
DCLK/
2+0
-
-
Hold time chip select
Positive edge DCLK to negative edge of chip select
DCLK/
2+0
t9_3
t10_3
t11
Bus floating time
Negative edge of chip select to float bus
-
30
-
Setup time data bit at write access
Data valid to positive edge of DCLK
30
15
-
Hold time data bit at write access
Data valid after positive edge of DCLK
t12
-
Bus floating time
Negative edge of chip select to float bus
t13_3
30
Remark: The digital interface will be reset during the low phase of the CS signal.
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AS5215
Data Sheet - Detailed Description
7 Detailed Description
The AS5215 is a redundant rotary encoder sensor front end. Based on an integrated Hall element array, the angular position of a simple two-pole
magnet is translated into analog output voltages. The angle information is provided by means of sine and cosine voltages. This approach gives
maximum flexibility in system design, as it can be directly integrated into existing architectures and optimized for various applications in terms of
speed and accuracy.
With two independent dies in one package, the device offers true redundancy. Usually the bottom die, which is exposed to slightly less magnetic
field is employed for plausibility check.
An SSI (SPI standard) protocol is implemented for internal test access to the different circuit blocks and for signal path configuration.
A One Time Programmable register block (OTP) allows the customer to adjust the signal path gain to adjust for different mechanical constraints
and magnetic field strengths. Furthermore, for internal use, the test mode can be enabled and the system oscillator is trimmable, DC offset of the
output signal can be set to either 1.5V or 2.5V. A unique chip ID is stored to ensure traceability.
For operating point control, a band gap circuit is implemented together with a central bias block to distribute all reference bias currents for the
analog signal conditioning. The digital signal part is based on a 2MHz system, CLK derived via. divider from a 4MHz system oscillator.
Figure 3. Typical Arrangement of AS5215 and Magnet
7.1 Magnet Diameter and Vertical Distance
Note: Following is just an abstract taken from the elaborate application note on the Magnet.
For more detailed information, please visit our homepage www.austriamicrosystems.com → Magnetic Rotary Encoders → Magnet
Application Notes
7.1.1 The Linear Range
The Hall elements used in the AS5000-series sensor ICs are sensitive to the magnetic field component Bz, which is the magnetic field vertical to
the chip surface. Figure 4 shows a 3-dimensional graph of the Bz field across the surface of a 6mm diameter, cylindrical NdFeB N35H magnet at
an axial distance of 1mm between magnet and IC.
The highest magnetic field occurs at the north and south poles, which are located close to the edge of the magnet, at ~2.8mm radius (see Figure
5). Following the poles towards the center of the magnet, the Bz field decreases very linearly within a radius of ~1.6mm. This linear range is the
operating range of the magnet with respect to the Hall sensor array on the chip. For best performance, the Hall elements should always be within
this linear range.
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AS5215
Data Sheet - Detailed Description
Figure 4. 3D-Graph of Vertical Magnetic Field of a 6mm Cylindrical Magnet
BZ; 6mm magnet @ Z=1mm
area of X- Y-misalignment from cen-
ter: ±0.5mm
circle of Hall elements on chip
Bz [mT]
Y -displacement [mm]
X -displacement [mm]
As shown in Figure 5 (grey zone), the Hall elements are located on the chip at a circle with a radius of 1mm. Since the difference between two
opposite Hall sensors is measured, there will be no difference in signal amplitude when the magnet is perfectly centered or if the magnet is
misaligned in any direction as long as all Hall elements stay within the linear range.
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AS5215
Data Sheet - Detailed Description
For the 6mm magnet (shown in Figure 5), the linear range has a radius of 1.6mm, hence this magnet allows a radial misalignment of 0.5mm
(1.6mm linear range radius; 1mm Hall array radius). Consequently, the larger the linear range, the more radial misalignment can be tolerated. By
contrast, the slope of the linear range decreases with increasing magnet diameter, as the poles are further apart. A smaller slope results in a
smaller differential signal, which means that the magnet must be moved closer to the IC (smaller airgap) or the amplification gain must be
increased, which leads to a poorer signal-to-noise ratio. More noise results in more jitter at the angle output. A good compromise is a magnet
diameter in the range of 5…8mm.
Small Diameter Magnet (<6mm)
Large Diameter Magnet (>6mm)
+ stronger differential signal =
good signal / noise ratio,
larger airgaps
+ wider linear range =
larger horizontal misalignment area
- weaker differential signal =
poorer signal / noise ratio,
smaller airgaps
- shorter linear range =
smaller horizontal misalignment area
Figure 5. Vertical Magnetic Field Across the Center of a Cylindrical Magnet
Bz; 6mm magnet @ y=0; z=1mm
Hall elements (side view)
X -displacement [mm]
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AS5215
Data Sheet - Detailed Description
7.1.2 Magnet Thickness
Figure 6 shows the relationship of the peak amplitude in a rotating system (essentially the magnetic field strength of the Bz field component) in
relation to the thickness of the magnet. The X-axis shows the ratio of magnet thickness (or height) [h] to magnet diameter [d] and the Y-axis
shows the relative peak amplitude with reference to the recommended magnet (d=6mm, h=2.5mm). This results in an h/d ratio of 0.42.
Figure 6. Relationship of Peak Amplitude vs. Magnet Thickness
Bz amplitude vs. magnet thickness
of a cylindrical diametric magnet with 6mm diameter
160%
140%
120%
100%
80%
60%
d= 6mm x h= 2.5mm ref. magnet:
h/d = 0.42
Rel. amplitude = 100%
40%
20%
0%
0,0
0,2
0,4
0,6
0,8
1,0
1,2
1,4
1,6
1,8
thicknessto diameter [h/d] ratio
As the graph in Figure 6 shows, the amplitude drops significantly at h/d ratios below this value and remains relatively flat at ratios above 1.3.
Therefore, the recommended thickness of 2.5mm (at 6mm diameter) should be considered as the low limit with regards to magnet thickness.
It is possible to get 40% or more signal amplitude by using thicker magnets. However, the gain in signal amplitude becomes less significant for h/
d ratios >~1.3. Therefore, the recommended magnet thickness for a 6mm diameter magnet is between 2.5 and ~8 mm.
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AS5215
Data Sheet - Detailed Description
7.1.3 Axial Distance (Airgap)
Figure 7. Sinusoidal Magnetic Field Generated by the Rotating Magnet
B
vertical
field
0
360º
The recommended magnetic field, measured at the chip surface on a radius equal to the Hall sensor array radius (typ 1mm) should be within a
certain range. This range lies between 45 and 75mT or between 20 and 80mT, depending on the encoder product.
Linear position sensors are more sensitive as they use weaker magnets. The allowed magnetic range lies typically between 5 and 60mT.
7.1.4 Angle Error vs. Radial and Axial Misalignment
The angle error is the deviation of the actual angle vs. the angle measured by the encoder. There are several factors in the chip itself that
contribute to this error, mainly offset and gain matching of the amplifiers in the analog signal path. On the other hand, there is the nonlinearity of
the signals coming from the Hall sensors, caused by misalignment of the magnet and imperfections in the magnetic material.
Ideally, the Hall sensor signals should be sinusoidal, with equal peak amplitude of each signal. This can be maintained, as long as all Hall
elements are within the linear range of the magnetic field Bz (see Figure 5).
7.1.5 Mounting the Magnet
Generally, for on-axis rotation angle measurement, the magnet must be mounted centered over the IC package. However, the material of the
shaft into which the magnet is mounted, is also of big importance.
Magnetic materials in the vicinity of the magnet will distort or weaken the magnetic field being picked up by the Hall elements and cause
additional errors in the angular output of the sensor.
Figure 8. Magnetic Field Lines in Air
Figure 8 shows the ideal case with the magnet in air. No magnetic materials are anywhere nearby.
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AS5215
Data Sheet - Detailed Description
Figure 9. Magnetic Field Lines in Plastic or Copper Shaft
If the magnet is mounted in non-magnetic material, such as plastic or diamagnetic material, such as copper, the magnetic field distribution is not
disturbed. Even paramagnetic material, such as aluminium may be used. The magnet may be mounted directly in the shaft (see Figure 9).
Note: Stainless steel may also be used, but some grades are magnetic. Therefore, steel with magnetic grades should be avoided.
Figure 10. Magnetic Field Lines in Iron Shaft
If the magnet is mounted in a ferromagnetic material, such as iron, most of the field lines are attracted by the iron and flow inside the metal shaft
(see Figure 10). The magnet is weakened substantially.
This configuration should be avoided!
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AS5215
Data Sheet - Detailed Description
Figure 11. Magnetic Field Lines with Spacer Between Magnet and Iron Shaft
If the magnet has to be mounted inside a magnetic shaft, a possible solution is to place a non-magnetic spacer between shaft and magnet, as
shown in Figure 11. While the magnetic field is rather distorted towards the shaft, there are still adequate field lines available towards the sensor
IC. The distortion remains reasonably low.
7.1.6 Summary
ꢀ
Small diameter magnets (<6mm Ø) have a shorter linear range and allow less lateral misalignment. The steeper slope allows larger axial
distances.
ꢀ
Large diameter magnets (>6 mm Ø) have a wider linear range and allow a wider lateral misalignment. The flatter slope requires shorter axial
distances.
ꢀ
ꢀ
The linear range decreases with airgap; Best performance is achieved at shorter airgaps.
The ideal vertical distance range can be determined by using magnetic range indicators provided by the encoder ICs. These indicators are
named MagInc, MagDec, MagRngn, or similar, depending on product.
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AS5215
Data Sheet - Application Information
8 Application Information
8.1 Sleep Mode
The target is to provide the possibility to reduce the total current consumption. No output signal will be provided when the IC is in sleep mode.
Enabling or disabling sleep mode is done by sending the SLEEP or WAKEUP commands via. the SSI interface. Analog blocks are powered
down with respect to fast wake up time.
8.2 SSI Interface
The setup for the device is handled by the digital interface. Each communication starts with the rising edge of the chip select signal. The
synchronization between the internal free running analog clock oscillator and the external used digital clock source for the digital interface is
done in a way that the digital clock frequency can vary in a wide range.
Table 8. SSI Interface Pin Description
Port
Chip select
Symbol
CS
Function
Indicates the start of a new access cycle to the device
CS = LO → reset of the digital interface
Clock source for the communication over the digital interface
DCLK
DCLK
DIO
Command and data information over one single line
The first bit of the command defines a read or write access
Bidirectional data input output
Table 9. SSI Interface Parameter Description
Symbol Parameter
Notes
Min
Typ
Max
Unit
f_DCLK Clock frequency at normal operation
no limit
5
6
MHz
The nominal value for the clock frequency can
be derived from a 10MHz oscillator source.
Clock frequency at easy zap read
f_EZ_RW
no limit
200
5
-
6
kHz
kHz
write access
Correct access to the programmable zener
diode block needs a strict timing – the zap pulse
is exact one period.
f_EZ_PR Clock frequency at easy zap access
650
OG
program OTP
The nominal value for the clock frequency can
be derived from a 10MHz oscillator source.
20pF external load allowed.
f_EZ_AR Clock frequency at easy zap analog
readback
no limit
156.3
162.5
kHz
B
The nominal value for the clock frequency can
be derived from a 10MHz oscillator source.
Interface General at normal mode
Protocol: 5 command bit + 16 data input output
Command
5 bit command: cmd<4:0> ← bit<21:16>
16 bit data: data<15:0> ← bit<15:0>
Data
Interface General at extended mode
Protocol: 5 command bit + 33 data input output
Command
5 bit command: cmd<4:0> ← bit<38:34>
34 bit data: data<33:0> ← bit<33:0>
Data
Interface Modes
Normal read operation mode
Extended read operation mode
Normal write operation mode
Extended write operation mode
cmd<4:0> = <00xxx> → 1 DCLK per data bit
cmd<4:0> = <01xxx> → 4 DCLK per data bit
cmd<4:0> = <10xxx> → 1 DCLK per data bit
cmd<4:0> = <11xxx> → 4 DCLK per data bit
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AS5215
Data Sheet - Application Information
8.3 Device Communication / Programming
Table 10. Digital Interface at Normal Mode
#
command
bin
mode
write
write
15
go2sleep
1
14
gen_rst
0
13 12 11 10
9
analog_sig
0
8
OB_bypassed
0
7
6
5
4
3
2
1
0
WRITE CONFIG
1
23
16
10111
10000
EN_PROG
0
0
1
1
1
0
1
0
1
1
1
0
Name
Functionality
Enter/leave low power mode (no output signals)
Generates global reset
go2sleep
gen_rst
Switches the channels to the test bus after the PGA
Disable and bypass output buffer for testing purpose
analog_sig
OB_bypassed
Table 11. Digital Interface at Extended Mode
Factory Settings
User Settings
<9> <8:7>
#
command
bin
mode
<43:
26>
<22:2 <19:1 <17:1
<45:44>
<25:23>
<13> <12>
<11>
<10>
<6>
<5:0>
0>
8>
4>
lock_O
n.c.
invert_
dc_
hall_
bias
WRITE OTP
PROG_OTP
31
25
11111 xt write otp test
11001 xt write otp test
ID 10µbiastrim
ID 10µbiastrim
ID 10µbiastrim
vref
osc
cm_sin cm_cos
cm_sin cm_cos
cm_sin cm_cos
gain
gain
gain
TP
channel
offset
lock_O
n.c.
invert_
channel
dc_
offset
hall_
bias
vref
vref
osc
osc
TP
lock_O
n.c.
invert_
channel
dc_
offset
hall_
bias
RD_OTP
15
9
01111 xt read
otp test
TP
RD_OTP_ANA
01001 xt read
Remark:
1. Send EN PROG (command 16) in normal mode before accessing the OTP in extended mode.
2. OTP assignment will be defined/updated.
Name
Otp_test
ID
Functionality
Dummy fuse bit used in production test
Part identification
Not connected
n.c.
10µ bias current trim bits
Bias Block reference voltage trim bits
Oscillator trimming bits
10µbiastrim
vref
osc
To disable the programming of the factory bits <45…14>
lock_OTP
Inverts SIN and COS channel before the PGA for inverted output function (0...SIN/COS, 1...SINN/
COSN)
invert_channel
Common mode voltage output enabled at SINN / CM pin (0...differential, 1...common)
Common mode voltage output enabled at COSN / CM pin (0...differential, 1...common)
PGA gain setting (influences overall magnetic sensitivity), 2bit
Output DC offset (0…1.5V, 1…2.5V)
cm_sin
cm_cos
gain
dc_offset
Hall_b
Hall bias setting (influences overall magnetic sensitivity), 6bit
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Revision 1.8
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AS5215
Data Sheet - Application Information
Figure 12. Sensitivity Gain Settings - Relative Sensitivity in %
Magnetic Sensitivity vs. OTP Hall Current & PGA Gain Setting
600
550
500
450
400
350
300
250
200
150
100
M_PGA_00
M_PGA_01
M_PGA_10
M_PGA_11
0
10
20
30
40
50
60
Hall Current OTP setting (6 bits)
The amplitude of the output signal is programmable via sensitivity (6bit) and/or gain (2bit) settings (see Figure 12).
Figure 13. Sensitivity Gain Settings - Sensitivity [mV/mT]
Magnetic Sensitivity vs. OTP Hall Current & PGA Gain Setting
70
60
50
40
30
20
10
0
M_PGA_00
M_PGA_01
M_PGA_10
M_PGA_11
0
10
20
30
40
50
60
Hall Current OTP setting (6 bits)
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Revision 1.8
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AS5215
Data Sheet - Application Information
8.4 Waveform – Digital Interface at Normal Operation Mode
Figure 14. Digital Interface at Normal Operation Mode
CMD_PHASE
DATA_PHASE
DCLK
CS
t9_3
t1_3
t5
t6
t2_3
DIO
DIO
CMD
CMD4
t3
CMD3
CMD2
CMD1
CMD0
t7
t10_3
D0
t8
D14
t4
READ
D15
D13
t11
t13_3
D0
t12
D14
DIO
WRITE
D15
D13
8.5 Waveform – Digital Interface at Extended Mode
In the extended mode, the digital interface needs four clocks for one data bit. During this time, the device is able to handle internal signals for
special access (e.g. the easy zap interface).
Figure 15. Digital Interface at Extended Mode
CMD_PHASE
DATA_PHASE
DCLK
t1_3
t9_3
CS
t7
t5
t2_3
DIO
CMD4
CMD0
CMD2
CMD3
CMD1
CMD
t10_3
t13_3
t8
t3
t6
t4
DIO
DIO
READ
D45
D44
D0
t11
t12
WRITE
D45
D44
D0
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Revision 1.8
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AS5215
Data Sheet - Application Information
8.6 Waveform – Digital Interface at Analog Readback of the Zener Diodes
To be sure that all Zener-Diodes are correctly burned, an analog readback mechanism is defined. Perform the ‘READ OTP ANA’ sequence
according to the command table and measure the value of the diode at the end of each phase.
Figure 16. Digital Interface at Analog Readback of Zener Diodes
CMD_PHASE
DATA_PHASE_EXTENDED
EXT D1
EXT D0
EXT D44
EXT D45
DCLK
CS
DIO
CMD4 CMD3 CMD2 CMD1 CMD0
OTP D45
OTP D43
OTP D0
OTP D44
PROG
perform analog measurements at PROG
Table 12. Serial Bit Sequence (16-bit read / write)
Write Command
Read / Write Data
C4 C3 C2 C1 C0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
8.7 EasyZapp OTP Content
Each AS5215 die has an integrated 32-bit OTP ROM (Easyzapp) for trimming and configuration purposes. The PROM can be programmed via.
the serial interface. For irreversible programming, an external programming voltage at PROG pin is needed. For security reasons, the factory
trim bits can be locked by a lock bit.
Name
Hall Bias
DC offset
gain
Bit Count OTP Start OTP End
Access
Comments
Sets overall sensitivity
6
1
2
1
0
6
5
6
user
user
Output DC offset setting
Programmable gain amplifier setting
Set in production test
7
8
user
Lock
13
13
austriamicrosystems
Inverts SIN and COS channel before the
PGA for inverted output function
invert_channel
cm_sin
1
1
1
11
10
9
11
10
9
user
user
user
Common mode voltage output enabled at SINN /
CM pin
Common mode voltage output enabled at COSN /
CM pin
cm_cos
Remark: OTP assignment will be defined/updated.
Note: For more information, refer to the document “IP Easyzapp Application Note Rev C”.
http://intranet.office.amsiag.com/engineering/ipr/Datasheets/easyzapp_application_note_revc.pdf
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Revision 1.8
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AS5215
Data Sheet - Application Information
8.8 Analog Sin/Cos Outputs with External Interpolator
Figure 17. Sine and Cosine Outputs for External Angle Calculation
+5V
VDD
100k
PROG
VDD
SINP_1/SINN_1
VDD
D
A
A
A
A
SINN_1/SINP_1/CM_SIN_1
SINP_2 / SINN_2
D
D
Micro
SINN_2/SINP_2/CM_SIN_2
Controller
100n
COSP_1/COSN_1
COSN_1/COSP_1/CM_COS_1
COSP_2/COSN_2
D
COSN_2/COSP_2/CM_COS_2
VSS
VSS
VSS
Notes:
1. We recommend to use a 100k pull-up resistance.
2. Default conditions for unused pins are: DCLK_1/2, CS_1/2, DIO_1/2, TC_1/2, A_TST_1/2, TBO_1/2, TB1_1/2, TB2_1/2,
TB3_1/2 connect to VSS
The AS5215 provides analog Sine and Cosine outputs (SINP, COSP) of the Hall array front-end for test purposes. These outputs allow the user
to perform the angle calculation by an external ADC + µC, e.g. to compute the angle with a high resolution. The output driver capability is 1mA.
The signal lines should be kept as short as possible, longer lines should be shielded in order to achieve best noise performance.
Through the programming of one bit, you have the possibility to choose between the analog Sine and Cosine outputs (SINP, COSP) and their
inverted signals (SINN, COSN). Furthermore, by programming the bits <9:10> you can enable the common mode output signals of SIN and
COS.
The DC bias voltage is 1.5 or 2.5 V.
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Revision 1.8
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AS5215
Data Sheet - Application Information
8.9 OTP Programming
Figure 18. OTP Programming Connection
+5V
VDD
CS_1
Output
VDD
VDD
DCLK_1
DIO_1
CS_2
Output
I/O
Output
100n
Output
I/O
DCLK_2
DIO_2
Micro
Controller
8.0 - 8.5V
+
PROG
100n
10µF
VSS
VSS
VSS
maximum
parasitic cable
inductance
V
SUPPLY
L<50nH
VDD
V
zapp
V
prog
PROG
GND
C1
C2
PROM Cell
100nF
10µF
For programming of the OTP, an additional voltage has to be applied to the pin PROG. It has to be buffered by a fast 100nF capacitor (ceramic)
and a 10µF capacitor. The information to be programmed is set by command 25. The OTP bits 16 until 45 are used for AMS factory trimming and
cannot be overwritten.
Symbol
VDD
Parameter
Supply Voltage
Ground level
Min
5
Max
5.5
0
Unit
V
Note
GND
0
V
V_zapp
T_zapp
f_clk
Programming Voltage
Temperature
8
8.5
85
V
At pin PROG
At pin DCLK
0
ºC
kHz
CLK Frequency
100
Remark: For normal operation, after programming, apply 100k pull up resistor at PROG pin!
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Revision 1.8
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AS5215
Data Sheet - Pack age Drawings and Markings
9 Package Drawings and Markings
The devices are available in a 32-pin QFN (7x7mm) package.
Figure 19. 32-pin QFN (7x7mm) Package
AS5215
17919-001
AYWWIZZ
25
32
24
1
8
17
16
9
Note: The distance between both dies is 150µm.
Table 13. Package Dimensions
mm
inch
Typ
Symbol
Min
Typ
7 BSC
7 BSC
4.28
Max
Min
Max
D
E
0.28 BSC
0.28 BSC
0.169
D1
E1
L
4.18
4.18
0.45
0.25
4.38
4.38
0.65
0.35
0.165
0.165
0.018
0.010
0.172
0.172
0.026
0.014
4.28
0.169
0.55
0.022
b
0.30
0.012
e
0.65 BSC
0.90
0.026 BSC
0.035
A
0.80
1.00
0.031
0.039
A1
0.203 REF
0.008 REF
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Revision 1.8
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AS5215
Data Sheet - Revision History
Revision History
Revision
Date
Owner
Description
April 29, 2008
July 03, 2008
Initial revision
1.0
Redundancy Coding topic deleted.
Updated Key Features, Table 1 - Pin Descriptions, Figure 1 and
Figure 17.
1.1
1.2
July 15, 2008
July 14, 2009
Updated min, typ, max values for ‘Power up time’ parameter in Table 6.
Updated the following parameters in Table 6:
- Values and conditions updated for
1. Propagation delay
July 31, 2009
2. Amplitude ratio tracking accuracy over temperature
3. DC Offset Drift
1.3
apg
- Deleted the ‘Output Offset’ parameter from the table.
Updated following bits related information on page 16 - invert_channel,
cm_sin, cm_cos, gain, dc_offset, Hall_b
Aug 24, 2009
Inserted Figure 12 and updated Applications and Figure 17.
Inserted Figure 13, Added a note in Package Drawings and Markings.
Deleted ‘Displacement’ parameter from Table 5.
1.4
1.5
1.6
Aug 26, 2009
Sept 01, 2009
Sept 02, 2009
Hall Array Radius value updated from 1.1mm to 1mm
Updated Figure 13
1.7
1.8
Nov 26, 2009
Dec 11, 2009
Updated values for ‘Magnetic Sensitivity’ parameter in Table 6.
Note: Typos may not be explicitly mentioned under revision history.
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Revision 1.8
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AS5215
Data Sheet - Ordering Information
10 Ordering Information
The devices are available as the standard products shown in Table 14.
Table 14. Ordering Information
Ordering Code
Description
Delivery Form
Package
AS5215-HQFT
Sine and cosine analog output magnetic rotary encoder
Tape & Reel
32-pin QFN (7x7mm)
Note: All products are RoHS compliant and Pb-free.
Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect
For further information and requests, please contact us mailto:sales@austriamicrosystems.com
or find your local distributor at http://www.austriamicrosystems.com/distributor
Copyrights
Copyright © 1997-2009, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®.
All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of
the copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale.
austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding
the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at
any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for
current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range,
unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are
specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100
parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location.
The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not
be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use,
interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing,
performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of
austriamicrosystems AG rendering of technical or other services.
Contact Information
Headquarters
austriamicrosystems AG
Tobelbaderstrasse 30
A-8141 Unterpremstaetten, Austria
Tel: +43 (0) 3136 500 0
Fax: +43 (0) 3136 525 01
For Sales Offices, Distributors and Representatives, please visit:
http://www.austriamicrosystems.com/contact
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Revision 1.8
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