AS8501T&R [AMSCO]
High precision voltage and current measurement sensor interface; 高精确度的电压和电流测量传感器接口
| 型号： | AS8501T&R |
| 厂家： | 
AMS(艾迈斯) |
| 描述： | High precision voltage and current measurement sensor interface |
| 文件： | 总40页 (文件大小：470K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AS8501
Preliminary Data Sheet
High precision voltage and current measurement sensor interface
REF
AGND
VDDA
VSSA
1
Features
INTERNAL TEMPERATURE
1.26 V
REFERENCE
16 bits resolution
Differential inputs
Single + 5V supply
Low power 15 mW
VDDD
VSSD
CALIBRATION
DATA
ETR
ETS
BUF
INPUT MUX
CHOPPER
SOIC16 package
DSP
CONTROLLER
FILTER
INT. CLOCK
TIMER
CLK
VBAT
RSHH
Self- and system-calibration
with auto-calibration on power up
16 kHz maximum sampling frequency
Internal temperature measurement
Internal factory trimmed precision reference
Programmable current sources
Digital comparator
Active wake-up
PGA gains 1, 6, 24, 50, 100
Zero offset
Zero offset TC
Extremely low noise
Internal oscillator with comparator for active wake up
3-wire serial interface, μP compatible
Temperature range – 40 to + 125 °C
Individual 24-bit serial number
16 BIT - CONVERTER
PROTECTION
EZPRG
PGA
and
LEVEL SHIFT
COMPARATOR
RSHL
CURRENT
SOURCES
SERIAL INTERFACE / CONTROL REGISTERS
SCLK
SDAT
INTN
Figure 1: Functional Block Diagram
the high internal chopping frequency the system is free of 1/f-noise down
to DC.The 0-10 Hz noise is typical below 1 µV i.e. as good or better than
any other available chopper amplifier.
For high speed synchronous measurements the chip can run in an
automatic switching mode between two input channels with pre-
programmed parameter sets.
The circuit has been optimised for the application in battery management
systems in automotive systems. As a front end data acquisition system it
allows an high quality measurement of current, voltage and temperature
of the battery.
2
Applications
Battery management for automotive systems
Power management
mV/µV-meter
High-precision voltage and current measurement
3
General description
With a high quality 100 μΩ resistor the system can handle the starter
current of up to 1500 A, a continuous current of ± 300 A as well as the
very low idle current of a few mA in the standby mode.
For external temperature measurement the chip can use a wide variety of
different temperature sensors such as RTD, PTC, NTC, thermocouples or
even diodes or transistors. A built-in programmable current source can be
switched to any input and activate these sensors without the need of
other external components.
The AS8501 is a complete, low power data acquisition system
for very small signals (i.e. voltages from shunt resistors,
thermocouples) that operates on a single 5 V power supply. The
chip powers up with a set of default conditions at which time it
can be operated as a read-only-converter. Reprogramming is at
any time possible by just writing into two internal registers via
the serial interface.
The measurement of the chip temperature with the integrated internal
temperature sensor allows in addition the temperature compensation of
sensitive parameters which increases the total accuracy considerably.
The AS8501 has four ground refering inputs which can be
switched separately to the internal PGA. Two input channels can
also be operated as a fully differential ground free input. The
system can measure both positive and negative input signals.
Sensor specific data can be stored in the internal Zener-Zap memory and
are used to calibrate each measurement in the internal data processing
unit before transmission to the external µC via the serial SDI interface.
The flexibility of the system is further increased by a digital comparator
that can be assigned to any measured property
The PGA amplification ranges from 6 to 100 which enables the
system to measure signals from 7mV to 120 mV full scale range
with high accuracy, linearity and speed.
The chip contains a high precision bandgap reference and an
active offset compensation that makes the system offset free
(better than 0,5 μV) and the offset-TC value negligible. The built-
in programmable digital filter allows an effective noise
(current, voltage, temperature) and an active wake-up in the sleep-mode.
All analog input-terminals can be checked for wire break via the SDI-
interface.
suppression if the high speed is not necessary in the application.
The input noise density is only 35 nV /
and due to
Hz
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AS8501 - Preliminary Data Sheet
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CONTENTS
1
2
3
4
5
6
7
FEATURES.........................................................................................................................................................................................1
APPLICATIONS .................................................................................................................................................................................1
GENERAL DESCRIPTION.................................................................................................................................................................1
PIN FUNCTION DESCRIPTION FOR SOIC 16 PACKAGE...............................................................................................................3
ABSOLUTE MAXIMUM RATINGS.....................................................................................................................................................4
ELECTRICAL CHARACTERISTICS..................................................................................................................................................5
FUNCTIONAL DESCRIPTION ...........................................................................................................................................................9
7.1 POWER ON RESET ...........................................................................................................................................................................9
7.2 ANALOG PART, GENERAL DESCRIPTION .............................................................................................................................................9
7.2.1
7.2.2
7.2.3
Reference voltage .............................................................................................................................................................10
Current sources.................................................................................................................................................................11
Internal temperature sensor ..............................................................................................................................................12
7.3 DIGITAL PART.................................................................................................................................................................................12
7.3.1
7.3.2
Sampling rate ....................................................................................................................................................................12
Calibration .........................................................................................................................................................................13
7.4 MODES OF OPERATION ...................................................................................................................................................................13
7.5 REGISTER DESCRIPTION .................................................................................................................................................................15
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
7.5.6
7.5.7
7.5.8
7.5.9
OPM operation mode register ( 4 bits ) .............................................................................................................................16
CRG general configuration register ( 28 bits )...................................................................................................................16
CRA measurement channel A configuration register ( 17 bits ) ......................................................................................17
CRB measurement channel B configuration register ( 17 bits ) .......................................................................................19
ZZR Zener-Zap register (188 bits )...................................................................................................................................20
CAR calibration register ( 110 bits ) .................................................................................................................................22
TRR trimming register ( 20 bits ) .......................................................................................................................................22
THR alarm (Wake-up) threshold register ( 17 bits ) .........................................................................................................25
MSR measurement result register ( 18 bits )....................................................................................................................25
8
DIGITAL INTERFACE DESCRIPTION.............................................................................................................................................25
8.1 CLK..............................................................................................................................................................................................25
8.2 INTN ............................................................................................................................................................................................25
8.3 SDI BUS OPERATION ......................................................................................................................................................................26
8.4 DATA TRANSFERS ..........................................................................................................................................................................27
8.5 SDI BUS TIMING .............................................................................................................................................................................28
8.6 SDI ACCESS TO OTP MEMORY........................................................................................................................................................29
8.6.1
8.6.2
ZZR register bit mapping...................................................................................................................................................29
Stored ZZR-register mapping............................................................................................................................................33
9
GENERAL APPLICATION HINTS ...................................................................................................................................................34
9.1 GROUND CONNECTION, ANALOG COMMON .......................................................................................................................................34
9.2 THERMAL EMF ..............................................................................................................................................................................34
9.3 NOISE CONSIDERATIONS.................................................................................................................................................................35
9.4 SHIELDING, GUARDING....................................................................................................................................................................35
10 TYPICAL PERFORMANCE CHARACTERISTICS ..........................................................................................................................36
11 PACKAGE DIMENSIONS ................................................................................................................................................................38
12 REVISION HISTORY........................................................................................................................................................................38
13 ORDERING INFORMATION ............................................................................................................................................................38
14 CONTACT.........................................................................................................................................................................................39
14.1
14.2
HEADQUARTERS .......................................................................................................................................................................39
SALES OFFICES........................................................................................................................................................................39
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4
PIN function description for SOIC 16 package
PIN
Name
description
Comment
analog common for VBAT, ETS and ETR; return for internal
current source
1
2
3
RSHL
anlalog input from shunt resistor low side
anlalog input from shunt resistor high side
analog input with reference to RSHL
analog input for differential input ETS-VBAT
analog output for current-source
RSHH
ETS
4
5
VBAT
VSS
analog input with reference to RSHL
analog input for differential input ETS-VBAT
analog output for current-source
0V-power supply for analog part
This input must be open or connected to VDDD. It is not intended,
that OTP content is modified by the user.
6
7
EZPRG digital power input for programming Zener fuses.
VSSD
0V-power supply and ground reference point for digital part
external clock typical 8.192 MHz; during MWU-mode external
connection must be high impedance or connected to VDDD to
reduce current consumption
8
9
CLK
digital input for external clock, master clock input
serial port clock input for SDI-port
serial data in- and output
SCLK
SDAT
INTN
the user must provide a serial clock on this input
10
11
Digital I/O for interrupt from comparator
signal wake-up to external µC
conversion ready flag for external interupt and synchronisation in normal mode
+ 5V digital power supply
12
13
14
VDDD
VDDA
REF
+ 5V analog power supply
reference input/output
must be connected to VSS with a 30 nF capacitor
this PIN must be connected with a 50-100nF-capacitor to VSS;
no direct connection to VSSD/VSS allowed
15
16
AGND
ETR
analog ground, ground reference for ADC
analog input with reference to RSHL
analog output for current-source
Table 1: Pin Description
Figure 2: Schematic Package outline SOIC 16
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5
Absolute Maximum Ratings
Stress beyond those listed under “Absolute Maximum Ratings“ may cause permanent damage to the device. These are stress ratings only. Functional
operation of the device at these or any other conditions beyond those indicated under “Operating Conditions” is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability. All voltages are defined with respect to VSS and VSSD. Positive currents
flow into the IC.
Absolute maximum ratings (TA = -40°C to 125°C unless otherwise specified)
Nr.
PARAMETER
Supply voltage
Analogue VDDA and digital VDDD
Input pin voltage
SYMBOL
MIN
TYP
MAX
UNIT
NOTE
Polarity inversion externally
protected
0
VDD
-0.3
7.0
V
V
1
2
-0.3
VDD +0.3
100
V
in
Input current
ISCR
-100
mA
JEDEC 17
(latch-up immunity)
Electrostatic discharge
1)
3
4
ESD
TA
-2
2
kV
OC
Ambient temperature
-40
-55
125
(Tj = 150°C)
5
6
7
8
9
Storage temperature
Soldering conditions
Humidity, non-condensing
Thermal resistance
Power dissipation
TSTRG
TLEAD
150
260
85
OC
°C
2)
5
%
RthJA
PTOT
75
K/W
mW
350
Notes:
1)
MIL 883 E method 3015, HBM: R =1.5 kΩ, C =100pF.
Jedec Std – 020C, lead free
2)
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6
Electrical characteristics
VDDA=5V +/-0.1 V, fclk=8.192 MHz, chopping ratio MM=4 (see 7.5.3), oversampling frequency=2.048 MHz, oversampling ratio=128
temperature range : -40 to 125°C if not otherwise noted
symbol
parameter
conditions
min
typ
max
units
input characteristics
for gain 1 the input signal is connected directly to th input of the converter, this is not possible for the RSHH-RSHL
input
G1
Gain
AC_g6
1)
2)
gains of PGA
6, 24, 50, 100
Accuracy at gain 6
0 to 85 °C
-40 to 125°C
0 to 85 °C
-40 to 125°C
0 to 85 °C
0 to 85 °C
G1
G6
G24
G50
G100
1.0
1.5
0.5
1.5
1.0
% @-120mV
% @-120mV
% @+-20mV
% @+-20mV
% @+-10mV
% @+-5mV
mV
mV
mV
mV
mV
3),4)
2)
AC_g24
Accuracy at gain 24
0.08
0.3
3) 4)
4)
AC_g50
AC_g100
Vin
Accuracy at gain 50
Accuracy at gain 100
input voltage ranges
(with reference to RSHL)
4)
1.0
5) 6)
5) 7)
5) 7)
5) 8)
5) 8)
-350
-200
-40
-20
-10
-300 to + 800
+/- 120
+/- 30
900
160
40
20
10
+/- 15
+/- 7.5
Notes:
1) the absolute gain values are subjected to a manufacturing spread of +/-30% max in the full temperature range. all gain values can be digitally
calibrated together with the external circuitry with a resolution better than 0.065%
2)
Current measurement paths for G6 and G24 are trimmed for minimum Temperature coefficient. The trimm algorithm is based on a 2 temperature
measurement at 23°C and 60°C.
Accuracy is mainly determined by bandgap characteristic and gain variation over temperature.
A TC shift of typically -15 ppm/K will occure during solder process which is compensated by a systematic offset during trimming.
3) due to a nonlinear behaviour of the gain and reference voltage over temperature the accuracy is lower for the extended temperature range.
4) The minimum limits for G50, G100 are derived from device characterization and not tested. Towards 125°C the TC values are higher.
therefore it is recommended to use these gain settings only for applications in the temperature range 0 to 85°C.
5)
if not otherwise specified the ranges are calibrated to the typical values. The maximum and minimum value represent the maximum usable span
accepting linearity deviation up to 1000 digits. Min, max limits are tested at room temperature only!
6) this gain range is not using the internal PGA, the input is directely connected to the AD-converter. Therefore the input resistance is lower then for
other gain ranges.
It has been designed mainly for positive input voltages up to 0.8 V i.e. for measurements of temperature with transistors and diodes.
The limitation for negative input voltages is due to the onset of conduction of the input protection diodes.
7) the ASIC is optimised for G6 and G24 concerning linearity, speed and TC, therefore these ranges are recommended whenever possible.
8) because of higher TC value at elevated temperature G50 and G100 are recommended for applications in the temperature range 0 to 85°C
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Electrical characteristics (continued)
VDDA=5V +/-0.1 V, fclk=8.192 MHz, chopping ratio MM=4 (see 7.5.3), oversampling frequency=2.048 MHz, oversampling ratio=128
temperature range : -40 to 125°C if not otherwise noted
symbol
cal_err
parameter
conditions
G1, 720 mV
G6, 120 mV
G24, 30 mV
min
typ
max
0.2
units
%
1)
calibration error
for 30 000 digits output at
full range
0.1
G50, 15 mV
G100, 7.5 mV
2)
2)
2)
2)
lin_err
nonlinearity
gain 6 @ room temp
gain 24 @ room temp
gain 50 @ room temp
gain 100 @ room temp
all gains
0.1
0.03
0.05
0.05
1
0.3
0.05
0.07
0.1
5
% or 30 digits
% or 10 digits
% or 15 digits
% or 20 digits
ppm/K
3)
4)
lin_errTC
Vos
TC of linearity error
offset voltage:
RSHH_RSHL
-40 to 125°C
-0.5
0.2
0.5
µV
offset voltage: ETS, ETR,
VBAT
4)
4)
-40 to 85°C
85 to 125°C
-2
-4
0.5
1
1
2
µV
µV
Offset voltage drift: RSHH-
RSHL
input bias/leakage current,
all channels
voltage noise density
(G=24)
current noise density
(G=24)
dVos/dT
Ib
-40 to 85 °C
room temperature
f=0 to 1 kHz
f=10 Hz
0.002
0.2
µV/K
nA
5)
6)
-1
1
Vndin
35
50
nV//Hz
6)
6)
6)
Indin
en p_p
5
2
0.5
20
3
1
100
5
1.5
fA//Hz
µV
µV
voltage noise, peak (G=24) 0 to 100 Hz
0 to 10 Hz
en_RMS
SNR
voltage noise, RMS (G=24) 1000 Hz
signal to noise (G=24,
1.5
2
µV
G4.8)
room temperature
room temperature
90
100
dBmin
signal to distortion (G24,
G4.8)
SDR
CCI
PSRR
80
-70
-50
100
-90
-60
dBmin
dBmax
dBmax
chanel to chanel insulation room temperature
power supply rejection ratio 4.9 to 5.1 V
Notes:
1) at room temperature / corresponding calibration factors are stored within the ZZR-register
2) whatever is lower. Maximum limits for gains 50 and 100 are derived from device characterization and are not tested.
3) this value measured in raw mode at room temperature and at 60°C. Maximum limits over temperature range are derived from device characterization.
4) TC variations are included in the above given maximum limit of linearity error. Max value is derived from device characterization and not tested
5) Leakage current is specified for all gain settings (except G1) for positive input voltages below 200 mV. Test is done at different input voltages with
subsequent extrapolation for 200mV. In the temperature range 85-125°C it may be as high as 5 nA at the upper limit. In normal operation a
temperature independent digital offset of -0.7 digits is present due to internal rounding.
6) This parameter is not measured directly. It is measured indirectly via gain measurement of the whole path at room temperature
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AS8501 - Preliminary Data Sheet
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Electrical characteristics (continued)
VDDA=5V +/-0.1 V, fclk=8.192 MHz, chopping ratio MM=4 (see 7.5.3), oversampling frequency=2.048 MHz, oversampling ratio=128
temperature range : -40 to 125°C if not otherwise noted
symbol
data conversion
RES
parameter
conditions
min
typ
max
units
1) 2)
3)
resolution
reference voltage
temperature coefficient of Vref
internal resistance of Vref
clock frequency
oversamplig ratio
conversions during chopper cycle
bandwidth
all channels
room temperature
16
1.21
bits
V
ppm/K
Ohm
MHz
Vref
1.13
-50
1.30
50
4)
Vref_TC
Vref_Ri
fovs
R1
MM
BW
av
fclk
CLK_extdiv
DR_clk
int_fclk
analog inputs
Rin
Rload > 50 kOhm
200
4.096
128
4
1000
4
8.192
2
50
64
8
7.8
1
0.05
16000
1024
10
Hz
cycles
MHz
internal averaging
5)
external clock frequency
clock division factor
duty ratio of external clock
internal clock frequency
4
%
kHz
180
250
330
30
RSHH, VBAT, ETS, ETS
Ue < 150 mV
input resistance
input capacitance at gain 24
50
8
100
15
MOhm
pF
Cin
internal temperature sensor
6)
7)
7)
7)
T_out20
T_sl
output at 23°C
slope
G 6, typical
-20 to 100°C
22500
73
23 000
75
0.5
23500
77
2
digits
digits/degC
degC
Terr85
Terr125
current source
Icurr_rshh
error of temperature measurement 0 to 85°C
-40 to 125°C
output to RSHH, RSHL
1
3
degC
1.5
2
3
µA
Notes:
1)
with external averaging the resolution can be increased up to 21 bits with an effective sampling rate below 10 Hz
2) the system works in overflow condition without degradation of accuracy up to 1.4 * range width.
This means that the overflow bit can work as bit no.17 in this range.
the absolute value will be trimmed digitally to (1.28*/-0.01) V at 23°C, if not otherwise specified
the TC-value will be trimmed digitally to end up with a typical TC-value of the output ( total measurement path) at G24 better than 20 ppm/K the
3)
4)
TC- value of the
reference voltage after trimming may be typically as high as 50 ppm/K due to manufacturing spread. Min,max limits are not tested but derived
from device
characterization
5)
in the temperature range 0 - 85°C the clock frequency can be increased to 12 MHz
6) value trimmed to +/- 30 digits during final test and stored into ZZR
7)The slope of the sensor is measured on sample basis per lot and not tested per device. The specified limits are derived from device
characterization.
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AS8501 - Preliminary Data Sheet
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Electrical characteristics (continued)
VDDA=5V +/-0.1 V, fclk=8.192 MHz, chopping ratio MM=4 (see 7.5.3), oversampling frequency=2.048 MHz, oversampling ratio=128
temperature range : -40 to 125°C if not otherwise noted
symbol
parameter
conditions
min
typ
max
units
programmable current source
output to Vbat, ETS, or ETR
Icurr_ON
I_steps
Dcurr
TC_CS
Icurr_OFF
Icurr_Ri
current level
current steps
accuracy, room temperature
temperature coefficient
current when off
0
6
248
10
0.5
1000
0.01
µA
µA
%
ppm/K
µA
8
0.2
900
0.001
10
248 µA
1 )
830
room temperature
internal resistance of current source Ua < 2 V
MOhm
digital CMOS inputs with pull up and schmidt-trigger
input PINs CLK and SCLK
3.5
Vih
Vil
Iih
Iil
high level input voltage
low level input voltage
current level
VDDD=5V
VDDD=5V
VDDD=5V, Vih=5V
VDDD=5V, Vil=0
V
1.5
1
120
V
µA
µA
-1
30
current level
digital CMOS outputs
output PINs SDAT and INTN
Voh
Vol
Cl
high level output voltage
low level output voltage
capacitive load
VDDD=5V, -633uA
VDDD=5V, 564uA
4.5
V
V
pF
0.4
20
Tristate digital I/O
Voh
Vol
high level output voltage
low level output voltage
tristate leakage current to
VDDD,VSSD
high level input voltage
low level input voltage
VDDD=5V, -633uA
VDDD=5V, 564uA
4.5
V
V
0.4
1
Ioz
Vih
Vil
VDDD=5V
VDDD=5V
VDDD=5V
-1
3.5
µA
V
V
1.5
EZPRG input
programming voltage - for factory
programming only
2)
Vprg
VDDD=5V
-
-
-
V
supply current
Isup
Iaw
supply voltage
VDDA
VDDD
VSS, VSSD
Power On Reset
Vporhi
normal operation
active wake-up
VDDD=VDDA=5V
VDDD=VDDA=5V
3
40
5
100
mA
µA
3)
4)
positive analog supply voltage
positive digital supply voltage
negative supply voltage
4.7
4.5
5.0
5.0
0
5.3
5.5
V
V
V
5)
5)
Power on reset Hi
Hysteresis
2.5
0.1
4.1
0.3
V
V
Vhyst
Notes:
1) not tested, derived from device characterization
2) for factory calibration only. During normal operation this PIN must be connected to VDDD.
3) the average current is dependent on the on-time of the measurement system i.e. it can be programed via the CRA register
4) stability of analog supply should be within +/- 0.1 V
5) tested at room temperature only
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7
Functional Description
Power on Reset
7.1
The power on reset is iniciated during each power up of the ASIC and can be triggered purpously by reducing the analog supply voltage (VDDA) to a
value lower than Vporlo for a time interval longer than 0.5 µsec.
During power on reset sequence the following steps are performed automatically:
-
-
-
The chip goes to mode MZL (see 7.4)
Internal clock is enabled
The calibration constants are loaded from Zener-zap memory to the appropriate registers (ZTR=>TRR, ZCL=>CAR). The load procedure is
directed by the internal clock and can be monitored on INTN pin. 188 clock pulses are generated from the internal oscillator source. Pulse period
is equal to internal clock period.
After the power-on reset sequence is finished:
-
-
-
-
the operation continues with internal clock if no external clock is detected. In this case the ASICs switches to mode MWU with default value of
threshold register ( 214
)
If external clock is available the ASIC switches to mode current measurement MMS (default measurement with default configuration: gain=100,
fovs=4.096MHz, R1=64, MM=4, R2=1, NTH=214).
The microcontroller can communicate via SDI interface whenever appropriate, i.e. CAR and TRR register can be rewritten from the µC if
necessary.
Because the automatic selected calibration factor (CGI4) is loaded with zeros, the ASIC delivers constant zero at the output to allow the µC to
check for an unwanted POR. To bring the ASIC back into normal operation for current
measurement with gain100 the µC has to copy the CAU4 content into the CGI4 factor in the CAR-register.
(see also 7.5.5 and 8.6.2)
7.2
Analog part, general description
The input signals are level shifted to AGND (+ 2.5 V) then switched by the special high quality MUX- which contains also the chopper – to the input of
the programmable gain amplifier (PGA). This low noise amplifier is optimised for best linearity, TC- value and speed at gain 24.
The systems contains an internal bandgap reference with high stability, low noise and low TC-value. The output of a programmable current source can
be switched to the analog inputs VBAT, ETS and ETR for testing the sensor connections
or for external activation of resistors, bridges or sensors (RTD, NTC). The voltage drop generated by the current is measured at the corresponding
input/output PIN.
For the wire break test of the RSHH and RSHL inputs special low noise current sources are implemented.
The integrated temperature sensor can also be switched to the PGA by the MUX and measured any time. The chip temperature can be used for the
temperature compensation of
the gain of the different channels in the external µC, which increases the absolute accuracy considerably.
The offset of the amplifier itself is already fairly low, but to guarantee the full dynamic range it can be trimmed via the digital interface to nearly zero
independent of the autozero chopping function.
In the same way the manufacturing spread of the absolute value of the reference voltage can be eliminated and the TC-value set to nearly zero by a
trimming process via the SDI interface.
For more details of the input multiplexer see the following schematic. The position of all switches is defined by writing into the registers CRA, CRB and
CRG via the SDI bus, which is explained in 7.5.2 through 7.5.4.
INTERNAL
CURRENT
TEMPERA-
M 7
SOURCE
M 6
M 8
TURE
ETR
ETS
M 9
M 15
M 2
M 14
VBAT
M 10
M 4
M 3
M 5
AD-
CON-
RSHH
RSHL
PGA
M 1
VERTER
M 12
AUXILIARY
CURRENT
SOURCE
M 13
Figure 3: Multiplexer
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7.2.1
Reference voltage
The ASIC contains a highly sophisticated precision reference voltage. Its typical temperature dependence is a slight parabola shaped curve and is
shown in figure 21. This reference voltage is used mainly for the internal AD-converter, but can also be used for external purposes if the impedance of
the external circuitry is high enough.
1,26
1,24
1,22
1,20
1,18
m easurem ent
open loop value
1,16
1,14
1,12
10
30
50
70
90
110
resistance load in kOhm
Figure 4: Reference voltage as function of resistance load
The absolute value and its temperature coefficient (TC) is given by the content of the TRR register. This opens the possibility to calibrate the reference
voltage to the optimum absolute value (i.e. 1.28 V) and the TC value to zero thus eliminating fully the production spread.
Writing into subregister TRIMBV of TRR changes the absolute value linearly by 5.1 mV per digit as shown in the following graph and described in full
detail in 7.5.7
1 ,36
1 ,32
1 ,28
75 °C
24 °C
1 ,24
1 ,20
1 ,16
0
5
1 0
15
20
25
30
co n ten t o f T R IM B V in b its
Figure 5: Reference voltage as function of temperature
Trimming the TC value is similarly done by writing into subregister TRIMBTC. Since the TC trimming is also changing the absolute value it is important
to trim the TC first and then the absolute value.
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200
150
100
50
0
change 12.7 ppm /K
per step
-50
-100
-150
-200
-250
0
5
10
15
20
25
30
35
setting of subregister TR IM B TC of TR R
Figure 6: Temperature coefficient as function of TRIMBTC setting
The TC trimming also opens the unique possibility to change the TC-value within the time of reprogramming of the TRR-register (i.e. within µsec) to
allow the compensation of
different TC-values of the external circuitry for different channels.
In addition it can be used for very fast autocalibration of the total TC of a given channel. An external reference voltage is applied to the channel to be
checked. Then all numbers from 0 to 31 are written into subregister TRIMBTC and a reading is done for the input voltage and the internal temperature
as well. The same is repeated at any temperature above RT. From these data the TRIMBTC setting for a minimum drift can be easily calculated.
7.2.2
Current sources
The AS8501 contains several current sources which can be used for checking all input lines for wire brake, to control external circuitry or to activate
external sensors.
Main current source
The main current source can be digitally controlled via the content of the CRG register in 31 steps of 8 µA in the range of 0 to 248 µV. Its absolute
value can be calibrated by writing in the subregister TRIMC of TRR.
The current source can be switched to the inputs VBAT, ETR or ETS to activate external sensors like RTDs, NTCs or resistance briges and strain
gages. It can also be used to detect a wire breake of external connected sensors. Performing a measurement with a high and a low (or zero) current
opens the possiblity to eliminate thermal EMF voltages in external sensors.
Secondary current sources
The ASIC contains two other high quality current sources supplying a current of approx. 2µA at the inputs RSHL and RSHH. These current sources can
be switched on and off at any time to check the correct connection of both terminals. During off state they must not interfere with the high sensitive
voltage inputs, especially the noise level should not be increased. If one of the terminals is an open connection the amplifier goes into saturation and
the overflow bit is set.
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7.2.3
Internal temperature sensor
The ASIC contains a high sensitive precision temperature sensor which can be used at any time. The sensor supplies a very linear voltage signal with
an offset at 23 degC, which is calibrated and stored in the ZZR-register. The voltage can be measured using the internal circuitry with gain 6, with free
selection of all other parameters defining the sampling rate.
35000
30000
25000
20000
15000
100
75
50
25
0
-25
-50
-75
-100
output signal
25
linearity deviation
cubic fit
-50
-25
0
50
75
100
125
150
175
Temperature in deg C
Figure 7: Measurement of internal temperature sensor over oil bath temperature
The slope of the curve is approx. 75 digits per degC.
The calculation of the temperature has to be done in the external µC acc. to the following simple formula:
Tint=( Uint(T)-Uint(23) ) / 75 + 23°C
Uint(T) is the measured result and Uint(23) is the reference value at 23°C, which is stored as an 11 bit-word in the ZZR-register.
Bits 15, 14 ,13 and 12 will always be the same at room temperature (0101 bin or 20480 dec), therefore it makes no sense to store them for each single
part. In addition we dont need the high resolution of one digit, which means 1/71.3 = 14 milli Kelvin. Therefore we cut the last bit and achieve a word of
11 bit length, which finally is stored in the ZZR-register as shown in the ‚stored ZZR-register mapping‘ given in 8.6.2
Example:
value stored in the ZZR-register:
1060 dez or 10000100100 bin
Uint(23) = 0101 10000100100
Add register content Add
0
= 22600 dec
If your measured value is : Uint(T) = 23767 dec
Ti[°C]= ((23767-22600) / (75 digits / °C)) + 23 °C
= 15.6 °C + 23 °C = 38.6 °C
7.3
Digital part
In the digital part the result of the AD-converter is processed, i.e. calibration, active offset cancellation and filtering is done. In addition the
communication via the serial SDI interface is handled and all circuit functions (like voltage and current path settings, chopping, dechopping) are
controlled.
Whenever the power supply line returns from below 2.0 V to above 3.5 V a power-up circuitry is activated which loads the internal calibration registers
from the Zener-Zap memory into the working register and starts the chip in a special default mode.
7.3.1
Sampling rate
the sampling rate (SR) is defined by the setting of parameters in register CRA or CRB. The oversampling frequency (OSF), the oversampling ratio
(OSR), the chopping ratio (MM) and the averaging number (AV). The sampling rate can be calculated acc. to the following formula:
SR= OSF/(OSR*MM*AV)
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For an clock frequency of 8.192 MHz it can vary between
16 000 kHz and 1.95 Hz.
In the dual mode the ASIC is switching automatically between the two channels and it needs at least one measurement for each polarity to get a valid
measurement. In addition the ASIC needs some time to reprogram the internal registers and switches. Therefore the maximum sampling frequency is
limited to 7.5 kHz for the above given clock frequency. The internal averaging is not working in the dual mode, but the sampling frequency can be
different for each channel.
7.3.2
Calibration
The calibration of the ASIC is done by a test setup as follows:
-
-
-
room temperature calibration of the internal temperature sensor
absolute input-output calibration for all gain settings
TC calibration for the measurement path for gain 24
The absolute input-output calibration of the gain ranges is done that way that for a given input voltage 30 000 digits at the output are produced:
Table 7.2.2
gain
input/mV
output/digits
1
6
720
120
30
30 000
30 000
30 000
30 000
30 000
24
50
100
15
7.5
In addition the ASIC receives an individual 24-bit serial number.
The TC-value of the output (total measurement path) for G24 is trimmed to a minimum value by selecting the best setting of the TRIMBTC subregister
of the TRR register (see 7.5.7).
A similar calibration is done for the other subregisters TRIMBV, TRIMA and TRIMC for the absolute value of the reference voltage, the offset of the PGA
and the current source respectively.
All these data are stored in the ZZR register according to the ‚stored ZZR-register mapping‘ given in 8.6.2
7.4
Modes of operation
The AS8501 can run in different operation modes, which are selected and activated via the serial interface.
Detailed description:
Mode 0: MZL
In power-on reset sequence, which is initiated by the on-chip power-on reset circuit whenever the power is connected , the registers are loaded from the
Zener-Zap memory.
Mode 1: MMS
Measurement mode where the definition is taken from the registers CRA and CRG defined later on. The measurements are continuous and measured
results are available after the ready flag (INTN pin) is set to LO. The result can be read by the µC any time after this bit is set to LO. However, to obtain
the best noise performances the result should be read when INTN pin is at LO state. All modules are in power-up.
Mode 2: MMD
Dual channel measurement mode. Two consecutive different measurements are performed according to the settings in the configuration registers CRA,
CRB and CRG defined later (usually CRA defining current measurements and CRB voltage measurement). One complete measurement is performed
with each setting. CRG register holds common settings.
The measurements are continuous (A,B,A,B). The 17th bit in the output register defines, which measurement has been executed according to the
definition LO=A, HI=B.
The number of consecutive measurements with equal configuration is defined in register CRG (bits s3,s2,s1,s0). All modules are in power-up.
Mode 3: MWU
In this wake-up mode the internal clock finclk=256kHz is running and one complete measurement is performed in the period from 1 to 1.5 s with the
parameter settings of the CRA register. Before the actual measurement is performed the logic powers up all internal circuits especially the AGND and
the Vref. If the external load is higher than 70 kOhms both signals can be used for external triggering or even as interrupt for the µC.
If the external clock is not running, this input should be high impedance. To achieve a stable low idle current the oversampling ratio should be set to
R1=128 and the CFG register must be programmed to x00003, see also 7.5 ‘Register description’. It is assumed that the threshold level in the THR
register is defined within the 16 bit range, if not the default value is 210
After one measurement is finished all modules except the on- board oscillator and divider are switched into power down condition to save power. The
MSR register is updated with the last measurement result. Whenever this value exceeds the digital threshold the (wake-up) INTN pin goes LO for one
clock cycle to trigger the wake-up event in the external µC.
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After that the circuit returns in power-down for approximately 1s. During this time the last measurement (MSR register) is available on the SDI interface.
In this intermediate sleep-mode all modules except internal oscillator and divider are in power-down mode. The SDI interface works independent which
means that the measurement result is available by reading the MSR register. At any time the microprocessor can start any other mode via SDI. In such
a case the external clock must be switched on first.
The chip goes in MWU mode (mode 3) after it received the command for that. After that command 6 or more additional CLK pulses are needed before
external clock may go to power down mode (no CLK pulses, high level because of internal pull-up resistors). This 6 CLK pulses are needed for
synchronisation. On the way back to normal mode this restriction is not needed.
Mode 4: MAM
In this alarm mode the measurement defined in CRA is going on. The channel bit in the THR register must be cleared (channel A). The threshold value
may be positive or negative. Whenever the measured value exceeds the digital threshold value in the THR register the pin INTN (in this mode its
function is to signal alarm-condition) goes LO for one clock cycle. For negative threshold value the signed measurement result must be more negative
than the THR value to activate the alarm. During measurements the signal INTN is high. All modules are in power-up, measurements are continuously
going on.
Mode 5: MZP
Zener-Zap programming/reading. This mode for factory programming only and should not be used by the customer.
Mode 6: MPD
Power down mode. Individual analog blocks can be disabled/enabled. The data acquisition system is not running during this mode is activated.
Mode 7: MSI
The operation in this mode is exactly the same as in MMS mode except that the internal clock is used.
The SDI interface signals can become active whenever appropriate. This mode can be used if no external clock CLK is available. The measuring speed
is reduced by a factor of 16.
Modes 8-15: These modes are reserved for testing purposes and should not be used by the customer. Reading and writing of some registers is only
possible in these higher modes. Write to registers CAR (calibration register) and TRR (trimming register) is allowed only in test modes.
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Modes of operation, register OPM
Mode
Name
MZL
Description
Power on, loading from Zener-Zap
memory
mo3
mo2
mo1
mo0
0
0
0
0
0
1
2
MMS
MMD
Single measurement
0
0
0
0
0
1
1
0
Double measurement
(A,B,A,B …)
3
4
MWU
MAM
MZP
MPD
MSI
Wake-up
0
0
0
0
0
1
0
1
1
1
1
x
1
0
0
1
1
x
1
0
1
0
1
x
Alarm
5
Zener program/read
Power down
6
7
1)
8-15
Reserved for testing
Notes:
1) Register addresses 12, 13, 14 and 15 are reserved for testing and future options; operations on these
registers must be avoided
7.5
Register description
In the following sections the register contents and their functions are described in detail. Since the length of some
registers is too long to present clearly, the registers are logically subdivided according to their functions and described
separately.
All internal functions are controlled by the contents of these registers which can be reloaded via the serial SDI interface at
any time. The AS8501 contains the following registers:
REGISTER
ADDRESS
SIZE
Contents
Detailled description see
OPM
CRA
Operating mode register
7.5.1
0
4
17
17
28
18
188
110
20
17
20
Measurement A configuration register
Measurement B configuration register
General configuration register
Measurement result register
Zener-Zap register
7.5.3
7.5.4
7.5.2
1
CRB
2
CRG
MSR
ZZR
3
4
7.5.9
7.5.5
5
CAR
6
Calibration register
7.5.6
7.5.7
7.5.8
TRR
Trimming register
7
8
THR
Alarm or wake-up threshold register
Test and special configuration register
Test registers
1)
CFG
9
reserved
10-12
1)
Note:
This register is reserved for testing modes. Writing is possible only in mode 8. In order to assure
stable conditions in power-down modes MWU(3), MPD(6), TMSS(8) and MSI(13) the default
setting of the CFG register must be changed to x00003. It is not necessary to change this value
during normal operation.
Write commands not supported in a certain mode can be released immediately after the register address. The ASIC will
resume operation with the next start condition. Registers CAR and TRR are not buffered. Any read operation of the CAR
or TRR register may generate transients in the analog circuitry; further accurate measurements require a delay time for
settling.
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7.5.1
OPM operation mode register ( 4 bits )
no.
Bit
mo3
mo2
mo1
mo0
Note
1)
0
default
0
0
0
0
1) This register has been described in detail under 7.4
7.5.2
CRG general configuration register ( 28 bits )
no.
CRG bits
27-22 21-11
CRS CRI
10-7
6-0
NOTE
0
CRV
CRP
subregister CRS: Sequence length, dechop and chop ( 6 bits )
Nr.
Bits
5
4
3
2
1
0
NOTE
1)
2)
0
CRS bit
names
Default
s3
s2
s1
s0
d
c
1
0
0
0
1
1
1
Notes:
1)
This register defines the sequence length, chopping (c) and dechopping (d) of the input signal
Default power-up state before any setting
2)
Sequence length bits ( 4bits)
Nr.
No. of measurements
s3 s2 s1 s0
NOTE
1)
0
16
0
0
0
0
1
…
1
0
0
0
1
default
…
14
15
…
1
…
1
…
1
…
0
14
15
1
1
1
1
Notes:
1)Number of consecutive measurements of A and B with settings defined in CRA,CRB
and other settings in CRG register. This setting is used only for mode MMD.
DECHOPPING BIT
Nr.
Dechopping
d
NOTE
0
No dechopping
0
1
Dechopping
1
CHOPPING BIT
Nr.
Chopping
c
NOTE
0
No chopping
0
1
chopping
1
subregister CRI: Current configuration ( 11 bits )
Nr.
Bits
10
9
8
7
6
5
4
3
2
1
0
NOTE
1),3)
0
CRI bit
names
Default
M14
M13
M12
M11
M8
M6
i4
i3
I2
i1
i0
2)
1
2
0
0
0
0
0
0
0
0
0
0
0
output
VBAT
RSHL
RSHH
no
ETS
ETR
Notes:
1) whenever M1=1 in (CRA,CRB) it is good practice to set all M6 to M14 to zero, but it is not mandatory
2) default logic state after power up and before any setting
3) All bits with names M14 to M1 represent control signals of the multiplexer with positive logic (for example M14=1
means that corresponding switch is closed).
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Current source setting bits (5 bits)
Nr.
Current [uA]
i4
i3
i2
i1
i0
NOTE
0
0
0
0
0
0
0
1
2
8
16
24
32
…
0
0
0
0
0
0
0
0
0
1
1
0
3
0
0
1
1
4
0
1
0
0
…
31
…
1
…
1
…
1
…
1
248
1
subregister CRV: Voltage configuration (4 bits )
Nr.
Bits
3
2
1
0
NOTE
1),3)
2)
0
CRV bit
names
Defaults
M15
M10
M9
M7
1
2
0
0
0
0
channel
VBAT- VBAT-ETS ETS-RSHL ETR-
RSHL differential RSHL
Notes:
1)
This register defines the connection of the analog voltage- bus to the input-PINs and to the A/D converter
Default logic state after power-up and before any setting
2)
subregister CRP: Power down configuration ( 7 bits )
Nr.
Bits
p6
p5
p4
p3
p2
p1
p0
NOTE
1),3)
0
CRP bit
names
Defaults
pdosc
pda
pdm
pdb
pdc
pdi
pdg
2)
1
2
0
0
0
0
1
0
0
block
oscillator amplifier modu- ref. bias current internal analog
lator
source
temp.
GND
Notes:
1)
This register defines the power-down signals of the building blocks
Default power-up state before any setting
The logic is positive (pdosc=1 means the corresponding block is in power-down)
2)
3)
7.5.3
CRA measurement channel A configuration register ( 17 bits )
Nr.
Bits
16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
NOTE
1), 3)
0
CRA bit
names
Defaults
cu2 cu1 cu0 M5 M4 M3 M2 M1 g1 g0
f
r
mm n3 n2 n1 n0
2)
1
2
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
subreg.
CRU
CRM
GN
OSF OSR MM
CRN
Notes:
1)
This register defines the measurement channel A configuration
Default power-up state before any setting
2)
3) Bit M1 is control signal of the multiplexer for current input
(for example M1=1 means that corresponding switch is closed).
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subregister CRU: calibration constant selection for voltage path ( 3 bits) in registers CRA,CRB
Nr.
Calibration const. U
cu2 cu1 cu0 NOTE
0
CAU0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
3
4
5
6
7
CAU1
CAU2
CAU3
CAU4
CAU5
1548
1548
subregister CRM: measurement path for registers CRA,CRB
Nr.
Bits
13 12 11 10
9
NOTE
1), 2)
CRA bit
names
Defaults
M5 M4 M3 M2 M1
measurement RSHH-RSHL
voltage bus
1
0
0
0
0
1
1
1
0
1
1
1
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
1
0
0
0
0
0
0
2
voltage bus, internal temperature
voltage bus, reference low=RSHL
voltage bus, gain=1
3
4
5
voltage bus,gain=1, internal temperature
voltage bus, gain=1, reference low=RSHL
6
7
Notes:
1) these bits define the inner part of the voltage path settings
2) only the listed combinations are allowed
subregister GN: gain definition bits, Registers CRA,CRB
Nr.
GAIN
g1 g0
NOTE
0
6
0
0
1
1
0
1
0
1
1
2
3
24
50
100
subregister OSF: oversampling frequency bit, Registers CRA,CRB
Nr.
Fovs (fclk=8MHz)
Fovs (internal osc)
f
NOTE
1)
1)
0
2.048MHz
132kHz
0
1
4.096MHz
264kHz
1
Notes:
1)
For internal oscillator typical values
subregister OSR: oversampling ratio bit, Registers CRA, CRB
Nr.
R1
r
NOTE
0
64
0
1
128
1
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subregister MM: chopping ratio bit, Registers CRA, CRB
Nr.
MM
mm NOTE
0
4
0
1
2
8
1
1
1)
x
Notes:
1) For c=0 and d=0 , chopping and dechopping is switched off and every cycle is active regardless
of mm, i.e. the sampling frequenzy is higher by a factor of 4
subregister CRN: averaging bits ( 4 bits), registers CRA,CRB
Nr.
R2
n3 n2 n1 n0
NOTE
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
x
0
0
1
1
0
0
1
1
0
0
1
x
0
1
0
1
0
1
0
1
0
1
0
x
1
2
2
4
3
4
8
16
5
32
6
64
128
7
8
256
9
512
10
11-14
15
1024
1)
2)
Reserved for test
raw mode
1
1
1
Note:
1)
combinations from B to E are reserved for test
this mode delivers the AD-values without calibration and averaging but multiplied by a factor which is dependent on the
2)
setting of the oversampling ratio. It can be used for high resolution measurements of very low signals since it eliminates
the internal rounding error.
The ratio between raw result (Nr) and normal result (Nn) is given by: Nr/Nn = 2^(11+x)/CAL where x=6 for R=128 and x=3
for R=64. CAL is the calibration constant used.
7.5.4
CRB measurement channel B configuration register ( 17 bits )
Nr.
Bits 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
NOTE
1), 3)
0
CRB bit cu2 cu1 cu0 M5 M4 M3 M2 M1 g1
names
g0
f
r
mm n3 n2 n1 n0
2)
1
2
Defaults
0
0
0
0
1
1
0
0
0
1
1
0
0
0
0
0
0
subreg.
CRU
CRM
GN
OSF OSR MM
CRN
Notes:
1)
This register defines the measurement channel B configuration, the functions of the subregisters are the same as
described above for measurement channel A
Default power-up state before any setting
2)
3) In this mode the chip cannot measure the current sensing input RSHH-RSHL, therefore M1=0 for all settings
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AS8501 - Preliminary Data Sheet
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7.5.5
ZZR Zener-Zap register (188 bits )
Nr.
ZZR bits
183-187
163-182
53-162
0-52
ZTC1)
NOTE
2)
0
ZLO
ZTR
ZCL
Notes:
1) 5 bits are reserved for:
- 1 bit eventually destroyed during testing,
- 2 bits for testing programmed 0 and 1
- 2 bits reserved for locking
2) due to a limited driving capability of the ZZR-cells the maximum reading speed is limited to 500 kHz
subregister ZLO: Zener spare bits ( 5 bits )
Nr.
Name
SYMBOL
WORD WIDTH
Default Hex
ZLO
1
Reserved bits
5
F
subregister ZTR: trimming bits (20 bits)
Nr.
PARAMETER
SYMBOL
WORD
WIDTH
Default
Dec1)
0
UNIT
NOTE
0
1
2
TC of reference
TRIMBTC
TRIMBV
TRIMA
5
Bits
Bits
Bits
absolute value of reference
amplifier offset
5
5
0
0
3
current source for external
temperature
TRIMC
5
0
Bits
Bits
4
∑ trim bits
TRIMREG
20
Notes:
1)
Default values must be written before start of the test
subregister ZCL: calibration bits ( 110 bits )
Nr.
PARAMETER
SYMBOL
WORD
WIDTH
Default
Dec3)
UNIT
NOTE
1),4)
1),4)
1),4)
1),4)
1),4)
1),4)
1),4)
1),4)
1),4)
2),4)
CGI1
CGI2
CGI3
CGI4
CAU0
CAU1
CAU2
CAU3
CAU4
CAU5
ZCL
0
1
Calibration G=6, I
Calibration G=24, I
Calibration G=50, I
Calibration G=100, I
Calibration U0
Calibration U1
Calibration U2
Calibration U3
Calibration U4
Calibration U5
∑ cal. Bits
11
1548
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
11
11
11
11
11
11
11
11
11
110
1548
1548
1548
1548
1548
1548
1548
1548
1548
2
3
4
5
6
7
8
9
10
Notes:
1)
Decimal default value of the calibration constant for voltage and current is calculated
/N =(V *1024)/(V *G )=1548
using formula: CG =N
2)
def max ADdef ref in max
Default calibration constant for absolute value of the voltage proportional to absolute
temperature is the same as for any other range because it uses the same amplifier and
max voltage at max. temperature is approx. 150mV and the gain selected must be g0.
3)
Default values must be written before start of the test
4)
Calibration constants are selected dependent on state of M1 ( see table below). For M1=1 one of
CGI1 to CGI4 is selected according to selected gain of amplifier. For M1=0 the selection of the
calibration constants is defined by bits (cu2,cu1,cu0), which are part of CRA and CRB registers and
are defined via SDI interface independently of any other selection.
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Calibration constant selection truth table
Nr.
cu2 cu1 cu0 M1 g1 g0
CAL CONST
NOTE
1)
1)
1)
1)
2)
2)
2)
2)
2)
2)
x
x
x
x
0
0
0
0
1
1
1
1
x
x
x
x
0
0
1
1
0
0
1
1
x
x
x
x
0
1
0
1
0
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
x
x
x
x
x
x
x
x
0
1
0
1
x
x
x
x
x
x
x
x
CGI1
0
CGI2
CGI3
CGI4
CAU0
CAU1
CAU2
CAU3
CAU4
CAU5
1548
1
2
3
4
5
6
7
8
9
10
11
1548
Notes:
1) CGIx calibration constants are selected when M1=1 according to selected gain
2) CGUx calibration constants are selected when M1=0 according to bits cu2 to cu0 defined via SDI in CRA and/or CRB
registers.
Subregister ZTC: see register mapping 8.2.6
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AS8501 - Preliminary Data Sheet
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7.5.6
CAR calibration register ( 110 bits )
The calibration register holds the calibration constants that are used by the internal DSP for the correction of each
measurement. At power-up sequence the Zener-Zap subregister ZCL is copied into the CAR register as shown in fig.
7.4.6.1. The register can be read or written in mode 8 via the SDI bus at any time. In particular it is possible to write
preliminary calibration constants with CAR or overwrite the loaded ZCL data, if a calibration has been changed.
Nr.
CAR bits 109-99 98-88 87-77 76-66 65-55 54-44 43-33 32-22 21-11 10-0
NOTE
1), 2)
0
Subregister CGI1 CGI2 CGI3 CGI4 CAU0 CAU1 CAU2 CAU3 CAU4 CAU5
1
default
1548 1548 1548 1548 1548 1548 1548 1548 1548 1548
Notes:
1)
Calibration register is composed of the following constants each having 11 bits:
CGI1, CGI2, CGI3, CGI4, CAU0, CAU1, CAU2, CAU3, CAU4, CAU5
This register can be read or written at any time via the SDI bus. In particular it is possible to write
2)
preliminary
calibration constants with CAR or overwrite the loaded ZCL data, if a calibration has been
changed.
7.5.7 TRR trimming register ( 20 bits )
In the TRR register the calibration constants for the reference voltage, for the amplifier-offset trim and for the current source setting are stored.
At power-up sequence the Zener-Zap subregister ZTR is loaded into the TRR register. This register can be read or written in mode 8 via the
SDI bus. In particular it is possible to write preliminary calibration constants into TRR or overwrite the loaded ZTR data, if a calibration has been
changed. The trimming of the TRR-registors is usually done at the factory before supplying the part.
Nr.
TRR bits
19-15
14-10
9-5
4-0
NOTE
1)
0
Subregister
TRIMC
TRIMA
TRIMBV
TRIMBTC
1
default
0
0
0
0
Notes:
1)writing into TRR register is done as usual with the MSB first
subregister TRIMC
change of current source output with TRIMC bits
Nr.
trimcs
trimc3
trimc2
trimc1
trimc0
dI/Io
%
Notes
1),2)
1),2)
1),2)
0
1
0
0
0
..
0
0
1
1
1
..
1
1
0
0
0
..
1
1
0
0
0
..
1
1
0
0
0
..
1
1
0
0
0
..
1
1
0
0
1
..
1
1
0
0
1
..
1
1
0
1
0
..
0
1
0
1
0
..
0
1
0
-1*2.3
-2*2.3
..
2
..
1),2)
1),2)
1),2)
14
15
16
17
18
..
–14*2.3
–15*2.3
16*2.3
15*2.3
14*2.3
..
1),2)
1),2)
30
31
2*2.3
1*2.3
Notes:
1) Io is the current in µA at TRIMC = 00000
2) The output current of the internal current source can be controlled in a wide range via the bit setting in CRG. In some applications it may be
necessary to trim the current in the rang of +/- 30% for an optimum result of the external temperature measurement. This trimming is achieved
with writing into subregister TRIMC of the TRR register. The trimming is done in % for all ranges selected in CRG register.
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AS8501 - Preliminary Data Sheet
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subregister TRIMA
change of amplifier offset with TRIMA bits
The offset of the PGA should be trimmed to a mimimum absolute value to guarantee the
full dynamic range with all gain settings.
Nr.
trimas
trima3
trima2
trima1
trima0
Voffset
mV
Notes
1),2) ,3)
0
1
0
0
0
..
0
0
1
1
1
..
1
1
0
0
0
..
1
1
0
0
0
..
1
1
0
0
0
..
1
1
0
0
0
..
1
1
0
0
1
..
1
1
0
0
1
..
1
1
0
1
0
..
0
1
0
1
0
..
0
1
Uos
1),2)
1),2)
Uos -1*1.34
Uos -2*1.34
..
2
..
1),2)
1),2)
1),2)
14
15
16
17
18
..
Uos –14*1.34
Uos –15*1.34
Uos
Uos +1*1.34
Uos +2*1.34
..
1),2)
1),2)
30
31
Uos +14*1.34
Uos +15*1.34
Notes:
1) Uos is the input offset voltage in mV at TRIMA = 00000
2) Every step of TRIMA settings brings Δoffset=1.34 mV change in absolute value of the input offset voltage.
If the measured value is Uos then the number that should be written into the TRIMA for minimum
final absolute value is calculated as TRIMA=int((Uos)/1.34) for Uos above zero and
TRIMA=16+int(-Uos)/1.34) for Uos below zero.
3) The input offset voltage can be measured with chopping and dechopping bits being cleared in register CRG.
Any input channel as well as gain settings can be used. The input should be shorted to avoid any external voltages to interfere with the
measurement. If the measured output voltage is Va then the offset voltage is calculated acc. Vos = Va/gain.
subregister TRIMBV
change of reference voltage Uo with TRIMBV bits
Nr.
trimbvs
trimbv3
trimbv2
trimbv1
trimbv0
VREF
mV
Notes
1),2)
1),2)
1),2)
0
1
0
0
0
..
0
0
1
1
1
..
1
1
0
0
0
..
1
1
0
0
0
..
1
1
0
0
0
..
1
1
0
0
0
..
1
1
0
0
1
..
1
1
0
0
1
..
1
1
0
1
0
..
0
1
0
1
0
..
0
1
Ua
Ua -1*5.1
Ua -2*5.1
..
2
..
1),2)
1),2)
1),2)
14
15
16
17
18
..
Ua –14*5.1
Ua –15*5.1
Ua
Ua +1*5.1
Ua +2*5.1
..
1),2)
1),2)
30
31
Ua +14*5.1
Ua +15*5.1
Notes:
1) Ua is the reference voltage in mV at TRIMBTC = 00000, the optimum value is 1.232V.
2) Every step of TRIMBV settings brings ΔBV=5.1 mV change in absolute value of the reference voltage.
For trimming the TC value and absolute value of the reference voltage it is recommended to trim the TC
value first and then trim the absolute value since TRIMBTC is changing both TC and absolute value, whereas
TRIMBV is changing only the absolute value.
If the measured absolute value is Uam then the number that should be written into the TRIMBV for optimum
final absolute value is calculated as TRIMBV=int((Uam-1.231)/0.0051) for Uam above the ideal value and
TRIMBV=16+int(-(Uam-1.232)/0.0051) for Uam below the ideal value.
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AS8501 - Preliminary Data Sheet
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subregister TRIMBTC
change of reference voltage Uo and TC-value with TRIMBTC bits
Nr.
trimbtcs
trimbtc3 trimbtc2 trimbtc1 trimbtc0
VREF
mV
TC
ppm/K
Notes
1
1
1),2)
1),2)
1),2)
0
1
0
0
0
..
0
0
1
1
1
..
1
1
0
0
0
..
1
1
0
0
0
..
1
1
0
0
0
..
1
1
0
0
0
..
1
1
0
0
1
..
1
1
0
0
1
..
1
1
0
1
0
..
0
1
0
1
0
..
0
1
Uo
TCo
Uo -1*5.2
Uo -2*5.2
..
TCo -1*12.7
TCo -2*12.7
2
..
1),2)
1),2)
1),2)
14
15
16
17
18
..
Uo –14*5.2
Uo –15*5.2
Uo
TCo -14*12.7
TCo -15*12.7
Uo +1*5.2
Uo +2*5.2
..
TCo +1*12.7
TCo -2*12.7
..
1),2)
1),2)
30
31
Uo +14*5.2
Uo +15*5.2
TCo -14*12.7
TCo -15*12.7
Notes:
1) Uo is the reference voltage in mV and TCo is the TC value in ppm/K at TRIMBV = 00000
2) Every step of TRIMBTC settings brings ΔBTC=5.2 mV change in absolute value of the reference voltage and
S=12.7 ppm/K change in the slope of temperature dependence. So for trimming the temperature coefficient of
the band-gap reference 2 measurements are recommended ( at T1=25oC and at T2=125oC ). If the measured TC
value is TCm then the number that should be written into the TRIMBTC for minimum final TC is calculated as
trimBTC=int(TCM/12.7) for positive values and trimBTC=16+int(-TCM/12.7) for negative values.
The absolute voltage is also changed in this way, which must be compensated by bringing back the absolute value by changing the TRIMBV
register. Usually the TRIMBVx=-TRIMBTCx+1 is sufficient. If further accuracy or change of absolute value is necessary it can be adjusted by
making some more measurements and adjustments.
ZZR REGISTER:
ZLO
5
ZTR
20
ZCL
110
ZTC
53
188
R/W
TRR
reg.7
CAR
reg.6
bit0
data in
bit0
CAR
TRR
ZLO
bit0
bit0
Figure 8: Copying of ZCL and ZTR registers into CAR and TRR registers
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AS8501 - Preliminary Data Sheet
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7.5.8
Nr.
THR alarm (Wake-up) threshold register ( 17 bits )
MR16 MR15 MR14 MR13 MR12 MR11 … MR1
MR0 NOTE
0
A/B
0
s
Msb
1
lsb
1)
default
0
0
0
0
Notes:
1) _ All measurements are performed in channel A therefore MR16 must be set to zero. When channel B is selected
no interrupt will be generated.
- The signed value is used. For positive THR values the ASIC will initiate an interrupt whenever the measured
value is bigger than the THR value. For negtive THR values the interrupt will be generated for a negative
result with an absolute value bigger than the absolute value of the THR register.
7.5.9
Nr.
MSR measurement result register ( 18 bits )
MR17
MR16 MR15 MR14 MR13 MR12
MR11 … MR1
MR0
NOTE
1)
Overflow/un A/B
derflow
S
msb
lsb
Notes:
1)
- Result word length is 16 bits because of calibration accuracy
and to maintain all possible resolutions ( different setting ).
- A/B bit signifies which measurement was performed: the one defined in CRA or CRB:
MR16=0 -> A
MR16=1 -> B
- Overflow/underflow bit is set whenever the result after multiplication by calibration
constant is bigger than 32767 or smaller than –32767.
In Wake-up or Alarm mode the overflow/underflow always sets INTN signal to LO.
8
Digital interface description
The digital interface of the AS8501 consists of two input pins (CLK and SCLK) and two I/O pins (INTN and SDAT). The SCLK and SDAT pins
are used as universal serial data interface (SDI). SDI operates only if external clock signal (CLK) is running.
8.1
CLK
In all operating modes except the Wake-up mode this pin must be connected to 8 MHz clock signal. In the Wake-up mode (MWU) the CLK pin
must be connected to logic HI or float.
8.2
INTN
The INTN pin is used to signal various conditions to the microcontroller, depending on the operating mode.
application modes of the INTN pin
Mode
Signal
Direction
Purpose
Note
1)
2)
0
Load clock (internal)
Output
Indicates progress of the Zener-Zap load process
1, 2,7 SDI clock disable
Output
Signals new result and suggests when to disable SCLK in
high-precision measurement phase
3
4
idle / wake-up not
Output
Output
Input
Signals the wake-up condition
idle / alarm not
PW1
Signals the alarm condition
Shows the programming pulse width
No purpose
5
6,8,9
10
10
Logic ‘0’
t12
Output
Output
Output
Test mode
t18
Test mode
Notes:
1) 188 clock pulses are generated from the internal oscillator source during the loading time.
2) In measurement modes (MMS and MMD) the INTN pin is used to synchronize the SDI bus operations (See Fig. 9).
The trailing edge of INTN signals the start of a new measurement.
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AS8501 - Preliminary Data Sheet
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i-1
start measurement i
Tcnv
i+1
INTN
available
results on SDI
i-2
i-1
i
Tres
Figure 9: INTN pin in modes 1 and 2
The determination of Tcnv and Tres from the parameter settings is:
Tcnv ≅ R1/(fovs*2)
Tres = MM*Tcnv*R2*2
with R1=OSR and R2=number of averages
8.3
SDI bus operation
SDI bus is a 2-line bi-directional interface between one master and one slave unit. Typically the master unit is a microcontroller with software-
implemented SDI protocol. The ASIC is always the slave unit. SDI bus operation is presented on Figure 10.
During data transfers the sdat signal changes while sclk is low. The sdat signal can change while sclk is high only to generate start or
exception conditions.
Direction
Address
Register data
sclk
SDAT
Start
Data transfer
Exception
Figure 10: SDI bus operation
Strobe ASIC
The master unit always generates the sclk signal.
The master unit generates the sdat signal in start, direction, address, master-write data and exception conditions. The master sdat pin is in
high-impedance state in master-read data condition.
The slave unit drives the sdat signal only in master-read data condition. In all other cases the slave sdat pin is in high-impedance state. During
data transfer in read condition the internal AD-conversion in continuing but the data in the MSR-register is not updated and the output of the
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AS8501 - Preliminary Data Sheet
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INTN signal is suppressed. Only after the completion of the reading cycle the ASIC returns to the normal condition and updates the MSR-
register immediately if a new AD-conversion has been finished during data transfer.
The master unit does not detect any bus conditions since it generates them. Data transfer conditions (direction, register address and register
data) must not be changed until the current condition is over. The slave unit does not detect start and exception condition when master-read is
in progress.
The exception condition is reserved for future use and should be avoided.
8.4
Data transfers
Generally the SDI interface is active in all ASIC modes. For security reasons some write operations are restricted to certain modes. Read
operations are never disabled in order to keep consistent sdat driving conditions.
Writing to the result, trimming and calibration registers (MSR, CAR and TRR) is allowed only in test modes.
Writing to the Zener-Zap register is allowed only in mode MZP.
The first data bit after the start condition in each data transfer defines the data direction: sdat=high is used for master-read data (mr) condition
and sdat=low for master-write data (mw) condition.
Data is transferred with the most significant bit (MSB) first. Data bits are composed of register address and register data bits. Register address
is transmitted first, followed by the register data bits. The register address is always 4 bits long. The number of register data bits in table 7.5 is
implied by the register address.
sclk
mr
sdat
a3
a2
a1
a0
MSB
LSB
mw
Direction
Register address
Register data
Figure 11: SDI Data transfer
The ASIC supports the data transfers presented in Table 8.1.
master read-write operations
REGISTER
ADDRESS
Contents
read
allowed in
modes
All
write allowed in
page
modes
0
1
2
3
4
5
6
7
8
OPM
CRA
CRB
CRG
MSR
ZZR
CAR
TRR
THR
operating mode
All
All
All
All
>7
5
measurement set-up A
measurement set-up B
general measurement conditions
measurement result
All
All
All
All
All
All
All
All
Zener-Zap data
calibration register
>7
>7
All
trimming register
alarm or wake-up threshold register
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AS8501 - Preliminary Data Sheet
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8.5
SDI bus timing
Timing definitions for SDI bus are based on software-implemented master unit protocol
MDE
DV_m
PW_sclk
DV_m
TS_m
LO_sclk
TS_m
sclk
(uP)
master sdat
(uP)
HI - Z
slave sdat
(ASIC)
HI - Z
TS_s
DV_s
TS
CDD
strobe ASIC
strobe µC
Figure 12: SDI Bus timing
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AS8501 - Preliminary Data Sheet
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SDI bus timing
Nr.
PARAMETER
SYMBOL
MIN
TYP
MAX Unit
Conditions
NOTE
PW_sclk
LO_sclk
MDE
0
1
2
SCLK pulse width
SCLK low
120
120
120
ns
ns
ns
All
All
All
5), 6)
Master SDAT exception
after SCLK
1)
DV_m
DV_s
3
4
Master SDAT valid
before/after SCLK
Slave SDAT not valid
after SCLK
120
TSW
TSW
ns
All
120
120
ns
Master read
TS_m
TS_s
CDD
5
6
7
Master 3-state ON/OFF
TS_s
ns
ns
ns
Master read
Master read
Master read
Slave 3-state ON/OFF
3)
Bus condition detection
disabled in slave unit
Notes:
1)TSW is typical time required by the microcontroller program to change or to read the state of
the I/O pin
3) Start detection is disabled when slave unit transmits data
5) LO_sclk>300ns and PW_sclk> 2µsec required to read ZZR.
6) LO_sclk > (3/2)*TCLK = (3/2)/f CLK = (3/2)/8MHz=187.5ns required for results synchronisation in MSR.
8.6
SDI can read the OTP memory in any mode by reading the register ZZR.
8.6.1 ZZR register bit mapping
SDI access to OTP memory
Cell index
0
1
2
3
4
5
6
7
pos B 2)
4)
Purpose
ZZR field
ZZR bit
pos A 1)
pos C 3)
lock A
lock B 5)
trimcs
trimc3
ZTR
181
trimc2
ZLO
186
ZLO
ZLO
185
ZLO
184
ZLO
183
ZTR
182
ZTR
180
187 (msb)
1) Always programmed to '0' during the production test
2) Always programmed to '0' during the production test
3) Always programmed to '1' during the production test
4) Reserved
5) Reserved
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AS8501 - Preliminary Data Sheet
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Cell index
8
9
10
11
12
13
14
15
trimc0
Purpose
trimc1
trimas
trima3
trima2
trima1
trima0
trimbvs
ZTR
178
ZZR field
ZZR bit
ZTR
179
ZTR
177
ZTR
176
ZTR
175
ZTR
174
ZTR
173
ZTR
172
Cell index
16
17
18
19
20
21
22
23
trimbv2
Purpose
trimbv3
trimbv1
trimbv0
trimbtcs
trimbtc3
trimbtc2
trimbtc1
ZTR
170
ZZR field
ZZR bit
ZTR
171
ZTR
169
ZTR
168
ZTR
167
ZTR
166
ZTR
165
ZTR
164
Cell index
24
25
26
27
28
29
30
31
cgi1_10
Purpose
trimbtc0
cgi1_9
cgi1_8
cgi1_7
cgi1_6
cgi1_5
cgi1_4
ZCL
162
ZZR field
ZZR bit
ZTR
163
ZCL
161
ZCL
160
ZCL
159
ZCL
158
ZCL
157
ZCL
156
Cell index
32
33
34
35
36
37
38
39
cgi1_2
Purpose
cgi1_3
cgi1_1
cgi1_0
cgi2_10
cgi2_9
cgi2_8
cgi2_7
ZCL
154
ZZR field
ZZR bit
ZCL
155
ZCL
153
ZCL
152
ZCL
151
ZCL
150
ZCL
149
ZCL
148
Cell index
40
41
42
43
44
45
46
47
cgi2_5
Purpose
cgi2_6
cgi2_4
cgi2_3
cgi2_2
cgi2_1
cgi2_0
cgi3_10
ZCL
146
ZZR field
ZZR bit
ZCL
147
ZCL
145
ZCL
144
ZCL
143
ZCL
142
ZCL
141
ZCL
140
Cell index
48
49
50
51
52
53
54
55
cgi3_8
Purpose
cgi3_9
cgi3_7
cgi3_6
cgi3_5
cgi3_4
cgi3_3
cgi3_2
ZCL
138
ZZR field
ZZR bit
ZCL
139
ZCL
137
ZCL
136
ZCL
135
ZCL
134
ZCL
133
ZCL
132
Cell index
56
57
58
59
60
61
62
63
cgi3_0
Purpose
cgi3_1
cgi4_10
cgi4_9
cgi4_8
cgi4_7
cgi4_6
cgi4_5
ZCL
130
ZZR field
ZZR bit
ZCL
131
ZCL
129
ZCL
128
ZCL
127
ZCL
126
ZCL
125
ZCL
124
Cell index
64
65
66
67
68
69
70
71
cgi4_3
Purpose
cgi4_4
cgi4_2
cgi4_1
cgi4_0
cau0_10
cau0_9
cau0_8
ZCL
122
ZZR field
ZZR bit
ZCL
123
ZCL
121
ZCL
120
ZCL
119
ZCL
118
ZCL
117
ZCL
116
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AS8501 - Preliminary Data Sheet
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Cell index
72
73
74
75
76
77
78
79
Purpose
cau0_7
cau0_5
cau0_4
cau0_3
cau0_2
cau0_1
cau0_0
cau0_6
ZZR field
ZZR bit
ZCL
115
ZCL
113
ZCL
112
ZCL
111
ZCL
110
ZCL
109
ZCL
ZCL
114
108
Cell index
Purpose
80
81
cau1_9
82
83
84
85
86
87
cau1_10
ZCL
cau1_8
ZCL
cau1_7
ZCL
cau1_6
ZCL
cau1_5
ZCL
cau1_4
ZCL
cau1_3
ZCL
ZZR field
ZCL
106
ZZR bit
107
105
104
103
102
101
100
Cell index
88
89
90
91
92
93
94
95
Purpose
cau1_2
cau1_0
cau2_10
cau2_9
cau2_8
cau2_7
cau2_6
cau1_1
ZZR field
ZZR bit
ZCL
99
ZCL
97
ZCL
96
ZCL
95
ZCL
94
ZCL
93
ZCL
92
ZCL
98
Cell index
96
97
98
99
100
101
102
103
Purpose
cau2_5
cau2_3
cau2_2
cau2_1
cau2_0
cau3_10
cau3_9
cau2_4
ZZR field
ZZR bit
ZCL
91
ZCL
89
ZCL
88
ZCL
87
ZCL
86
ZCL
85
ZCL
84
ZCL
90
Cell index
104
105
106
107
108
109
110
111
Purpose
cau3_8
cau3_6
cau3_5
cau3_4
cau3_3
cau3_2
cau3_1
cau3_7
ZZR field
ZZR bit
ZCL
83
ZCL
81
ZCL
80
ZCL
79
ZCL
78
ZCL
77
ZCL
76
ZCL
82
Cell index
112
113
114
115
116
117
118
119
Purpose
cau3_0
cau4_9
cau4_8
cau4_7
cau4_6
cau4_5
cau4_4
cau4_10
ZZR field
ZZR bit
ZCL
75
ZCL
73
ZCL
72
ZCL
71
ZCL
70
ZCL
69
ZCL
68
ZCL
74
Cell index
120
121
122
123
124
125
126
127
Purpose
cau4_3
cau4_1
cau4_0
cau5_10
cau5_9
cau5_8
cau5_7
cau4_2
ZZR field
ZZR bit
ZCL
67
ZCL
65
ZCL
64
ZCL
63
ZCL
62
ZCL
61
ZCL
60
ZCL
66
Cell index
128
129
130
131
132
133
134
135
cau5_5
Purpose
cau5_6
cau5_4
cau5_3
cau5_2
cau5_1
cau5_0
tcu1_8
ZZR field
ZZR bit
ZCL
59
ZCL
57
ZCL
56
ZCL
55
ZCL
54
ZCL
53
ZTC
52
ZCL
58
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AS8501 - Preliminary Data Sheet
austriamicrosystems
Cell index
136
137
138
139
140
141
142
143
Purpose
tcu1_7
tcu1_5
tcu1_4
tcu1_3
tcu1_2
tcu1_1
tcu1_0
ZTC
44
tcu1_6
ZZR field
ZZR bit
ZTC
51
ZTC
49
ZTC
48
ZTC
47
ZTC
46
ZTC
45
ZTC
50
Cell index
144
145
146
147
148
149
150
151
Purpose
tcu0_8
tcu0_6
tcu0_5
tcu0_4
tcu0_3
tcu0_2
tcu0_1
tcu0_7
ZZR field
ZZR bit
ZTC
43
ZTC
41
ZTC
40
ZTC
39
ZTC
38
ZTC
37
ZTC
36
ZTC
42
Cell index
152
153
154
155
156
157
158
159
Purpose
tcu0_0
trt0_9
trt0_8
trt0_7
trt0_6
trt0_5
trt0_4
trt0_10
ZZR field
ZZR bit
ZTC
35
ZTC
33
ZTC
32
ZTC
31
ZTC
30
ZTC
29
ZTC
28
ZTC
34
Cell index
160
161
162
163
164
165
166
167
Purpose
trt0_3
trt0_1
trt0_0
tcn3_7
tcn3_6
tcn3_5
tcn3_4
trt0_2
ZZR field
ZZR bit
ZTC
27
ZTC
25
ZTC
24
ZTC
23
ZTC
22
ZTC
21
ZTC
20
ZTC
26
Cell index
168
169
170
171
172
173
174
175
Purpose
tcn3_3
tcn3_1
tcn3_0
tcn2_7
tcn2_6
tcn2_5
tcn2_4
tcn3_2
ZZR field
ZZR bit
ZTC
19
ZTC
17
ZTC
16
ZTC
15
ZTC
14
ZTC
13
ZTC
12
ZTC
18
Cell index
176
177
tcn2_2
ZTC
178
179
180
181
182
183
Purpose
tcn2_3
tcn2_1
tcn2_0
tcn1_7
tcn1_6
tcn1_5
tcn1_4
ZZR field
ZZR bit
ZTC
11
ZTC
9
ZTC
8
ZTC
7
ZTC
6
ZTC
5
ZTC
4
10
Cell index
184
185
186
187
tcn1_2
Purpose
tcn1_3
tcn1_1
tcn1_0
ZTC
2
ZZR field
ZZR bit
ZTC
3
ZTC
1
ZTC
0
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AS8501 - Preliminary Data Sheet
austriamicrosystems
8.6.2
Stored ZZR-register mapping
ZZR-Register
bit no. in subregister
ZZR-bits
remarks
ZZR subregister
10
9
8
7
6
5
4
3
2
1
0
msb
lsb
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
187 183
182 178
177 173
172 168
167 163
162 152
151 141
140 130
129 119
118 108
107 97
96 86
85 75
74 64
63 53
52 44
43 35
34 24
23 16
ZLO
ZTR
TRIMC
TRIMA
TRIMBV
TRIMBTC
CGI1
CGI2
CGI3
CGI4
CAU0
CAU1
CAU2
CAU3
CAU4
CAU5
TCU1
TCU0
TRT0
current source calibration
PGA offset calibration
reference voltage calibration
TC calibration
c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0
c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1
c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2
gain 6
currrent 1500A
current 300 A
current 150 A
current 75 A
ZCL
gain 24
gain 50
gain100
0
0
0
0
0
0
0
0
0
0
0
c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1
calibration factor for gain 24
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4
c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3
ct ct ct ct ct ct ct ct ct ct ct
calibration factor for gain 1
calibration factor for gain 100
calibration factor for internal temperature
8 bits for checksum
1
1
t
cs cs cs cs cs cs cs cs
1)
2)
ZTC
1
t
n23
n
1
t
n
n
n
fi
t
n
n
n
fi
t
n
n
n
fi
t
n
n
n
fi
t
n
n
n
fi
t
n
n
n
fi
t
n
n
n0
6 bits for internal clock
t
t
11 bits for internal temperature at 23°C
high byte for serial number
medium byte for serial number
low byte for serial number
TCN3
TCN2
TCN1
15
7
8
0
n
x
c0
c1
0
ct
cs
fi
=
=
=
=
=
these fields are written during calibration
these fields are written during calibration of G6
these fields are written during calibration of G24 (i.e. 30 mV = 30 000 digits)
Zero value of calibration constant for detection of unwanted POR
calibration factor for slope of Tint : 75 digits/deg
8-Bit checksum for ZZR-register
=
=
6-bit for calibration of internal clock
t
nr
=
=
11 bits for Tint value at 23 °C
24 bits serial number
Notes:
1) The checksum contains the added value of all bits in the ZZR register without the 6 checksum bits
2) Tthe internal clock frequency can be calculated int_fclk= (240 + 6-bit fi-number) kHz
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AS8501 - Preliminary Data Sheet
austriamicrosystems
9
General application hints
Since the AS8501 is optimised for low voltage applications extreme care should be taken that the signal is not disturbed by influences like bad ground
reference, external noise pick-up, thermal EMFs generated at the transition of different materials or ground loops. The influence of these error sources
can be quite high and they may completely shadow the excellent properties of the device if not handled properly. The following sections are supposed
to supply additional informations to the design engineer how to get around some of these problems.
9.1
Ground connection, analog common
The analog common terminal where all voltages are referring to is RSHL. All ground lines of the external circuitry of VBAT, ETS and ETR as well as the
voltage sense line of the low ohmic current sensing resistor should be connected to each other in a star like ground point. It is recommended that this
point is as close as possible situated to the low side sense terminal of the current sensing resistor. It should also be connected to the VSS and VSSD
terminal, but the return line of both must leave this point separately. Also the power decoupling capacitors should be connected to the analog common.
To give an example of the magnitude of possible errors consider that the ground return of the power supply is not connected properly and 5 mm of a
copper track 35µm thick and 0.1 mm wide are within the measuring circuit with a current flow of 5 mA. This will result in an offset of 120 µV which is
more than 500 times higher than the typical offset of the ASIC. In addition the current fluctuations will act as an extra noise voltage which is also way
above that of the device itself.
9.2
Thermal EMF
another major source of error for low level measurements are thermal voltages (electromotive force, thermal EMF) or Seebeck voltages which are
principally produced by any junction of two dissimilar materials. On PC-boards pairs of dissimilar materials may consist of the copper tracks and the
solder, the leads of different components or different materials used in the construction within the components. Any temperature difference between
two connection produces a voltage which is superimposed to the measuring voltage.
A number of strategies are known to detect or minimise their influence on the measuring result:
-
in cases were a current has to be measured directly or a current is to be used to activate a resistive sensor (like
Ohm-meter or temperature measurement with RTDs, NTC or PTC) a switch in the circuit could be used to interrupt or invert the current thus
producing a current change dI. In the difference of the two voltage states dU the EMFs as well as the Offset voltages of the amplifier are fully
eliminated. For resistance measurements this method is known as ‘true Ohm’ measurement.
-
-
in applications were this is not possible and the problematic device (i.e. the input resistor of an amplifier) can be located it may help to place a
dummy device of the same type in the circuit as close and thermally connected as good as possible to compensate the influence of the first one.
Since the thermal EMFs are proportional to the temperature difference it is important to maintain a homogeneous temperature distribution in the
vicinity of the sensitive area. This is possible by keeping this area as small as possible, by avoiding any heat sources nearby or by increasing the
heat conductivity of the substrate, i.e. wide and thick copper tracks, multilayer board or even metal substrate.
-
The best solution of all however is to avoid the thermal EMFs by using only components which are matched to the copper world which means
that their thermo-electrical power against copper is zero. This is specially important for current measurements in the range of 10- 1000A. In this
case the resistance value has to be very low (down to 100µOhms) to limit the measuring power and avoid an overheating of the sensing resistor.
On the other hand the voltages to be detected are extremely low if a high resolution is required. If for instance a current of 10 mA has to be
measured with a 100µOhm resistor, the resolution of the measuring system must be better than 1µV and the error voltages due to thermal EMFs
must be below this limit. Quite often people are trying to use the well known Konstantan (CuNi44) for current sensing resistors. This is a bad
choice since the thermal EMF versus copper is very high.
With –40µV/deg already a temperature difference of
2.5 K is enough to produce an error which is 100 times lager than the required resolution. Or vice versa a temperature fluctuation of only 1/100 K
produces a ‘thermal noise’ which is equivalent to the required resolution.
With such materials and high currents of 10A and above the other thermoelectric effect, the so called Peltier-effect, can also play an important
role. Under current flow this effect generates heat in one junction and destroys the same amount of heat in the other junction. The amount of
heat is proportional to the current and its direction. The result is a temperature difference which in turn generates a thermal EMF proportional to it.
Finally this means that such a resistor produces its own error voltage and it is never possible to measure better than 1-2% with such badly
matched materials. The precision resistance materials Manganin, Zeranin and Isaohm are perfectly matched to the copper world and resistors
made from these materials can achieve the high quality that is necessary for low
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AS8501 - Preliminary Data Sheet
austriamicrosystems
level measurements and high resolution.
9.3
Noise considerations
for every low level measuring system it is essential to know the origin of noise and to accept the limitations given by it. Three major sources of noise
have to be considered. The input voltage noise and the input current noise of the amplifier and the thermal noise (Johnson noise) of resistors in the
external circuitry around the amplifier. Due to the fact that these three sources are not correlated they can be added in the well known square root
equation.
In most applications the input resistor or input divider is low ohmic (i.e. below 10 kOhms) which mean that the noise voltage produced by the input
current noise is negligible compared to the input voltage noise. The input noise density (En) of the AS8501 is with only 35 nV/sqr(Hz) extremely low.
This could be achieved with a special internal analog and digital chopper circuitry which eliminates the CMOS typical 1/f-noise completely. Even though
the overall noise will be dominated by the input amplifier as long as the external resistors are below 10 kOhm.
The total noise voltage generated at a given frequency resp. in a given frequency band (BW) is given by:
Un= En*sqr(BW)
This square root dependence can be seen very nicely in fig. 9.10. The typical square-root shaped dependence is found for both the peak to peak noise
as well as for the equivalent RMS noise.
The bandwidth resp. the sampling frequency of the AS8501 can be adapted to the requirements of the application by programming the internal digital
filter via the SDI bus. For a sampling frequency of 16kHz the input voltage RMS noise is less than 5µV, whereas at 500 Hz already 1µV (or 1LSB) is
reached.
If the customer needs even higher resolution at a lower measuring speed the internal integration time can be further increased but due to the limitation
of the digital noise ( 1LSB) it is better to perform an external averaging in the attached µC. In this way the resolution of the system can be considerably
increased to less than 0.1 µV for sampling rates of 5 Hz and below which corresponds to an effective AD-converter width of more than 20 bits. (see fig.
9.10)
9.4
Shielding, guarding
In many applications it is difficult to gain full benefit from the AS8501 performance since a number of external error sources can disturb the
measurement. To achieve the maximum performance the design engineer has to take care specially of the layout of the PC-board and the sense
connections to the external components. To avoid noise pick-up from external magnetic fields all tracks on the PC-board should be parallel strip lines
and they should be traced as close as possible to each other. External sensing cables should be twisted and kept away from current carrying cables as
far as possible. For longer cables a shielding is sometimes helpful but care should be taken that the shield is not connected to one of the sense leads.
For an optimum performance it should be open on one side, the other side should be connected to the central (star like) analog common point.
In very sensitive applications it may be wise to use a guard ring around both inputs and it should be connected again to the analog common point. This
procedure minimises leakage currents and parasitic capacitances between different terminals and components on the PC-board.
EMV interferences can be affectively avoided in most cases by using standard SMD-type high frequency filters in the analog input lines
as well as in the digital output lines.
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AS8501 - Preliminary Data Sheet
austriamicrosystems
10 Typical performance characteristics
parameters: 300A, G24, AV4, OSF 2.048, OSR 128
parameters: 300A, G24, AV32, OSF 2.048, OSR 128
250 A
15 mA
0 A
-150 A
-250 A
10
5
0,5
0,3
0
0,0
-5
-10
-0,3
-0,5
0
500
1000
1500
2000
-25,0
0,0
25,0
50,0
75,0
100,0
125,0
measurement no.
temperature in deg C
Figure 14: Linearity deviation for different currents over
temperature
Figure 13: Resolution and noise at zero input, sampling rate: 1kHz
parameters: 300A, G24, AV4, OSF 2.048, OSR 128
parameters: 300A, G24, AV4, OSF 2.048, OSR
128
0,03
0,02
0,01
0,00
30010
30005
30000
29995
29990
-400
-0,01
-300
-200
-100
0
100
200
300
400
-0,02
-0,03
0
500
1000
1500
2000
measurement no.
input current in A
Figure 15: Linearity deviation over input signal
Figure 16: Resolution and noise at 95% full scale,
sampling rate: 1kHz
G24,AV=4,1000Hz, external averaging
10
dual channel measurement, sampling rate f=8
RSHH-RSHL 100Hz square
kHz
VBAT
220Hz sine
10000
5000
0
p
p
1
0,1
sigma
2.048 MHz
4.096 MHz
'best chopper OPA of the world'
peak to peak
-5000
0,01
-10000
1
10
100
final frequency in Hz
1000
10000
200
220
240
260
280
measurement number
Figure 17: Dual mode measurement
Figure 18: Output voltage noise over sampling rate
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AS8501 - Preliminary Data Sheet
austriamicrosystems
2,0
1,5
1,0
5,0
2,5
change in %
0,5
change in %
0,0
-0,5
-1,0
-1,5
0,0
-2,5
G6
G24
75
G6
G24
G50
G100
-2,0
-50
-5,0
-50
0
-25
25
50
100
125
0
-25
25
50
75
100
125
temperature deg C
temperature deg C
Figure 20: Typical output as function of temperature for all gains
Figure 19: Typical output as function of temperature for gains 6 and 24
300A, G24, AV1, OSF 2.048, OSR 128
20
15
10
5
2500
2000
1500
1000
500
AC input frequency 100
Hz
0
0
-500
-1000
-1500
-2000
-2500
-5
-10
-15
-20
0
2,5
5
7,5
10
0
10
20
30
40
50
time in sec
measurement no.
Figure 21: Noise at 125 Hz sampling rate, gain 24
Figure 22: Real time AC measurement at 100 Hz
temperature dependence of reference voltage
0,4
0,2
0,0
original
-0,2
-0,4
-40
-20
0
20
40
60
80
100
120
temperature in °C
Figure 23: temperature dependence of internal reference
voltage (not trimmed)
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AS8501 - Preliminary Data Sheet
austriamicrosystems
11 Package Dimensions
Thermal Resistance junction / ambient.: 66 K/W (typ.) in still air
12 Revision History
Revision
Date
Feb.10,2006
March 23, 2006
Description
1.0
1.1
Initial Revision
RthJA
13 Ordering Information
Delivery in Tape and Reel (1 reel = 1500 devices)
Order AS8501 T&R
Delivery in Tubes (1 Tube = 46 devices)
Order AS8501 TUB
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AS8501 - Preliminary Data Sheet
austriamicrosystems
14 Contact
14.1
Headquarters
austriamicrosystems AG
A 8141 Schloss Premstätten, Austria
Phone: +43 3136 500 0
Fax:
+43 3136 525 01
industry.medical@austriamicrosystems.com
www.austriamicrosystems.com
14.2
Sales Offices
austriamicrosystems Germany GmbH
austriamicrosystems USA, Inc.
8601 Six Forks Road
Suite 400
Tegernseer Landstrasse 85
D-81539 München, Germany
Phone:
Fax:
+49 89 69 36 43 0
Raleigh, NC 27615, USA
+49 89 69 36 43 66
Phone:
Fax:
+1 919 676 5292
+1 509 696 2713
austriamicrosystems Italy S.r.l.
Via A. Volta, 18
austriamicrosystems USA, Inc.
4030 Moorpark Ave
Suite 116
I-20094 Corsico (MI), Italy
Phone:
Fax:
+39 02 4586 4364
+39 02 4585 773
San Jose, CA 95117, USA
Phone:
Fax:
+1 408 345 1790
+1 509 696 2713
austriamicrosystems France S.A.R.L.
124, Avenue de Paris
F-94300 Vincennes, France
austriamicrosystems AG
Phone:
Fax:
+33 1 43 74 00 90
+33 1 43 74 20 98
Suite 811, Tsimshatsui Centre
East Wing, 66 Mody Road
Tsim Sha Tsui East, Kowloon, Hong Kong
austriamicrosystems Switzerland AG
Rietstrasse 4
Phone:
Fax:
+852 2268 6899
+852 2268 6799
CH 8640 Rapperswil, Switzerland
Phone:
Fax:
+41 55 220 9008
+41 55 220 9001
austriamicrosystems AG
AIOS Gotanda Annex 5th Fl., 1-7-11,
Higashi-Gotanda, Shinagawa-ku
Tokyo 141-0022, Japan
austriamicrosystems UK, Ltd.
88, Barkham Ride,
Phone:
Fax:
+81 3 5792 4975
+81 3 5792 4976
Finchampstead, Wokingham
Berkshire RG40 4ET, United Kingdom
Phone:
Fax:
+44 118 973 1797
+44 118 973 5117
austriamicrosystems AG
#805, Dong Kyung Bldg.,
824-19, Yeok Sam Dong,
Kang Nam Gu, Seoul
Korea 135-080
austriamicrosystems AG
Klaavuntie 9 G 55
FI 00910 Helsinki, Finland
Phone:
Fax:
+82 2 557 8776
Phone:
Fax:
+358 9 72688 170
+358 9 72688 171
+82 2 569 9823
austriamicrosystems AG
austriamicrosystems AG
Bivägen 3B
Singapore Representative Office
83 Clemenceau Avenue, #02-01 UE Square
239920, Singapore
S 19163 Sollentuna, Sweden
Phone:
+46 8 6231 710
Phone:
Fax:
+65 68 30 83 05
+65 62 34 31 20
Revision 1.1, 04-April-06
www.austriamicrosystems.com
Page 39 of 40
AS8501 - Preliminary Data Sheet
austriamicrosystems
Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent identification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express,
statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the
right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current
information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability
applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application.
The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any
damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind,
in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of
austriamicrosystems AG rendering of technical or other services.
Copyright
Devices sold by austriamicrosystems are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems makes no warranty, express,
statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems reserves the right
to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems for current
information. This product is intended for use in normal commercial applications.
Copyright © 2004 austriamicrosystems. Trademarks registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior
written consent of the copyright owner. To the best of its knowledge, austriamicrosystems asserts that the information contained in this publication is accurate and correct. However,
austriamicrosystems shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of
business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation
or liability to recipient or any third party shall arise or flow out of austriamicrosystems rendering of technical or other services.
Revision 1.1, 04-April-06
www.austriamicrosystems.com
Page 40 of 40
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