AS8506_技术文档

AS8506

Battery Cell Monitor and Balancer IC

The AS8506 is a battery management IC dedicated to support

cell voltage measurement, monitoring, cell balancing and

temperature measurement functions in Li-Ion battery stacks for

electric/hybrid electric vehicles or in other

General Description

industrial/consumer/PV battery applications.

There are two device versions available:

• The AS8506 is AEC - Q100 automotive qualified.

• The AS8506C is for industrial and other applications.

Ambient temperature range for both products is from -40°C to

+85°C.

It features cell voltage diagnosis with externally adjustable

upper and lower cell voltage limits, fast cell voltage capture on

request through 12-bit SAR ADC, passive cell balancing by

simultaneous comparison of actual cell voltages with a

reference cell voltage and temperature measurement on two

external NTC sensors through 12-bit ADC.

Cells that are above reference will sequentially be discharged

through integrated switches and one external resistor.

There is also an active balancing option through factory setting

to sequentially charge cells which are below reference from an

external DC-DC Flyback converter and an integrated low side

driver.

The device can be used flexibly for battery stacks up to 7 cells

with a minimum stack voltage of 6V and a maximum stack

voltage of 32V.

It can be chained to support battery packs of virtually any

number of cells in synchronized mode through chained clock

and trigger signal.

The status of the battery stack is communicated to outside

world through OR’d voltage_ok signal and balance ready signal.

For further understanding in regards to the contents of the

datasheet, please refer to the Reference Guide located at the end

of the document.

ams Datasheet, Confidential:2013-Sep [1-00]

AS8506 – 1

G e n e r a l D e s c r i p t i o n

Key Benefits & Features

The benefits and features of AS8506, Battery Cell Monitor and

Balancer IC are listed below:

Figure 1:

Added Value of using AS8506

Benefits

Features

Reduce filter / synchronization effort. Acquired data

have same time stamp to inherently generate

Simultaneous cell voltage capture for safe operating

accurate comparison results independent from load area (SOA) monitoring and balancing.

transients.

Strongly reduces data communication and data

Autonomous balancing and SOA monitoring.

processing and thereby improves EMC robustness.

To compensate accumulative charge differences

only. This mitigates cases of occasional wrong

Autonomous passive balancing in the 100 mA range

balance decisions due to flat OCV characteristic or

mismatch in cell temperature

Intrinsic inter module balancing through charge

redistribution, efficiency improvement in case of

leakage path due to defect induced leakage in

particular cells.

Option for active charge balancing with very few

external components.

For OCV capture, cell impedance calculation,

diagnosis

Absolute cell voltage read out, read out of two

temperature sensors.

40-pin MLF (6x6) package, very low number of external

components.

Small form factor, low BOM

Applications

The applications of AS8506 include:

• The AS8506 is ideal for simultaneous cell monitoring and

cell balancing in stacked energy storage systems. Current

levels in the 100 mA range enables to compensate

accumulative SOC mismatch over the entire cell pack.

• Typical applications are

- Li-Ion batteries up to 200 cells for electric vehicles,

- Energy storage systems to buffer energy from PV

panels or for emergency power supplies,

- Battery management for e-scooters and e-bikes,

- Li-Ion or ultra capacitor based board net battery

management systems in the 12V/48V domain, for

handheld applications like power tools, laptops and

in general all Li-Ion battery powered systems.

AS8506 – 2

ams Datasheet, Confidential:2013-Sep [1-00]

General Description

Block Diagram

The functional blocks of this device for reference are

shown below:

Figure 2:

AS8506 Block Diagram

VCELL7

Level Shifters for Stack Communication / Status Signals

5V

Cnt7H

Cnt7L

EXT_RES_CTL

Stack signals

Balance and VREF_H

Switches Level Shifters

LDO

V5V

Pre-regulator

VCELL6

High

REF_T

Cnt6H

Cnt6L

Precision

Reference

CELL_THU

CELL_THL

VREF_IN

Reference &

Threshold

AS8506

VCELL7

Generation Circuit

VCELL5

Cnt5H

Over-temperature

Monitor

C_out7

comp7

Temperature

Sensor /

Switch

Capacitor

Circuit

Cnt5L

TEMP_IN1

TEMP_IN2

VCELL6

VCELL5

VCELL4

C_out6

comp6

Cnt4H

Cnt4L

VCELL[7:1]

C_out5

C_out4

C_out3

Zero Cross

Detection Circuit

comp5

comp4

comp3

VCELL3

Cnt3H

Stack

signals

VCELL4

VCELL3

Cnt3L

VCELL2

Cnt2H

CLK_IN

TRIG_IN

CS

FSM,

Digital Registers,

OTP Logic

VCELL2

VCELL1

Cnt2L

C_out2

C_out1

comp2

comp1

VCELL1

Cnt1H

SCLK

SDO

Cnt1L

SDI

C-GND

ams Datasheet, Confidential:2013-Sep [1-00]

AS8506 – 3

P i n A s s i g n m e n t

Pin Assignment

Figure 3:

Pin Diagram of AS8506

1

2

30

29

28

27

26

25

24

23

22

21

TSECH

V5V

TSECL

VCELL7

VCELL6

VCELL5

VCELL4

VCELL3

VCELL2

VCELL1

C-GND

REF_T

TEMP_IN1

TEMP_IN2

CELL_THL

CELL_THU

CS

3

AS8506

MLF 6x6

4

5

6

7

GND

(Exposed pad)

8

SCLK

9

SDI

10

SDO

AS8506 – 4

ams Datasheet, Confidential:2013-Sep [1-00]

Pin Assignment

Figure 4:

Pin Description

Pin Number

Pin Name

TSECH

Pin Type

Description

Flyback converter transformer secondary high side

Flyback converter transformer secondary low side

Battery cell 7 high level pin

1

2

3

4

5

6

7

8

9

TSECL

VCELL7

VCELL6

VCELL5

VCELL4

VCELL3

VCELL2

VCELL1

Battery cell 6 high level pin

Analog input /

output

Battery cell 5 high level pin

Battery cell 4 high level pin

Battery cell 3 high level pin

Battery cell 2 high level pin

Battery cell 1 high level pin

Power supply

input

10

11

12

C-GND

NC

Battery cell 1 low level pin

Not connected

Analog input /

output

Cell voltage reference value (cell target voltage of

battery)

VREF_IN

Power supply

input

13

14

GND

Ground to the IC

This pin triggers the cell balancing in the device.

Short pulse is for receiving status and continuous

‘High’ for cell balancing. It also acts as a data line

during 3-wire communication.

TRIG_IN

Digital input

Clock input pin in the Slave device. This pin also acts

as a clock during 3-wire communication. Scan clock

in scan mode.

15

16

CLK_IN

This pin alerts when the cell voltage or the

device/cell temperature is not within limits. During

3-wire communication, the CRC error is indicated on

this pin. The internal device cell voltage or

temperature status is ORed with CVT_NOK_IN on

this pin.

CVT_NOK_OUT

Digital output

The ‘device internal balance done’ and ‘balance done

from above device’ are ANDed on this pin. This pin in

Master device indicates the complete system

balance done. During address allocation process,

this pin will be ‘High’ if BD_IN is ‘High’.

17

18

BD_OUT

FD_OUT

Flyback converter gate/opto coupler drive (pad is

push-pull type) can drive up to 12mA.

ams Datasheet, Confidential:2013-Sep [1-00]

AS8506 – 5

P i n A s s i g n m e n t

Pin Number

Pin Name

Pin Type

Description

The wake pulse on this pin brings the IC into

NORMAL mode. This pin has a pull-up resistor to the

internal regulator. Should be driven with an open

drain or external NMOS.

Digital input

with pull-up

19

WAKE_IN

Analog input /

output

20

NC_T

Not connected. Only used in Test mode.

21

22

23

SDO

SDI

Digital output

SPI data out

SPI data in

SPI clock

Digital input

SCLK

Digital input

with pull-up

24

CS

SPI chip select

25

26

CELL_THU

CELL_THL

Cell voltage upper threshold

Cell voltage lower threshold

Temperature input2 to the IC (NTC input; if NTC is not

connected, then should be connected to GND with

1K resistor).

27

TEMP_IN2

Analog input /

output

Temperature input1 to the IC (NTC input; if NTC is not

connected, then should be connected to GND with

1K resistor).

28

29

TEMP_IN1

REF_T

Supply to temperature sensor (Reference voltage to

DAC and ADC).

30

31

V5V

LDO 5V output.

Power supply

input

V5V_IN

Supply to the bottom IC from the cascaded top IC.

Digital output

open drain

Open drain o/p on the VSUP+5V domain. WAKE_IN

information will be transmitted to top device.

32

33

WAKE_OUT

FD_IN

Flyback converter gate drive input in daisy chain

connection. (If FD_IN is ‘high’ then FD_OUT will be

PWM o/p in balance mode).

Digital input

In cell stack system, the device gets balance done

status of above device. During address allocation

process if this pin is ‘High’, then the device address is

decremented by ‘1’.

34

35

BD_IN

Digital input

with pull-down

Indicates cell voltage or temperature status of above

device.

CVT_NOK_IN

AS8506 – 6

ams Datasheet, Confidential:2013-Sep [1-00]

Pin Assignment

Pin Number

Pin Name

Pin Type

Description

This pin propagates the clock to next device in the

stack system. In case of Master device internal RC

clock is transmitted on this pin to Slave device.

36

CLK_OUT

Digital output

This pin transmits the data fromTRIG_IN for balance

and measurement phase. This pin is also used for

propagating the data information to next device in

stack system in SPI3.

37

38

39

TRIG_OUT

VSUP

Power supply

input

Supply to the IC.

This pin informs the device whether it should act as

the Master or Slave. If this pin is connected to GND,

then device will act as Master. If this pin is connected

to VSUP then device will act as Slave.

MS_SL

Digital input

High sides PMOS switch for external resistive divider.

Input to VREF_IN can be taken from external

resistive divider in one of the options.

Analog input /

output

40

VREF_H

ams Datasheet, Confidential:2013-Sep [1-00]

AS8506 – 7

A b s o l u t e M a x i m u m R a t i n g s

Stresses beyond those listed under “Absolute Maximum

Absolute Maximum Ratings

Ratings” may cause permanent damage to the device. These are

stress ratings only. Functional operation of the device at these

or any other conditions beyond those indicated under

“Operating Conditions” on page 10 is not implied. Exposure to

absolute maximum rating conditions for extended periods may

affect device reliability.

Figure 5:

Absolute Maximum Ratings

Symbol

Parameter

Min

Typ

Max

Units

Comments

Electrical Parameters

Voltage at positive

supply pin

V

-0.3

42

0

V

VSUP pin

VSUP

Voltage at negative

supply pin

GND, C-GND; Reference

potential

V

-0.3

GND

Voltage at high side

supply

MS_SL,VREF_H, TSECH

and TSECL

V

VSUP + 0.3

V5V_IN

TRIG_OUT, CLK_OUT,

CVT_NOK_IN, FD_IN,

BD_IN, WAKE_OUT

VSUP +

V5V_IN

High side supply

from top device

VSUP -

0.3

VSUP + 5.5

7

V

Voltage at on LDO

o/p pins

V

-0.3

V5V pin

V5V

All pins expect VSUP,

VCELL1, VCELL2, VCELL3,

VCELL4, VCELL5, VCELL6,

VCELL7, MS_SL, WAKE_IN

V

Voltage on 5V pins

V5V+0.3

V

ESD

Voltage on pins

VCELL1, VCELL2,

VCELL3, VCELL4,

VCELL5, VCELL6,

VCELL7

VCELL1

to

VCELL7

-0.3

7

V

Applied cell voltages

AEC - Q100-004

I

Latch-up Immunity

-100

+100

mA

SCR

AS8506 – 8

ams Datasheet, Confidential:2013-Sep [1-00]

Absolute M aximum R atings

Symbol

Parameter

Min

Typ

Max

Units

Comments

Electrostatic Discharge

VSUP, VREF_IN, SDI, SDO,

CS, SCLK, CELL_THU,

CELL_THL, TEMP_IN1,

TEMP_IN2, REF_T, V5V,

V5V_IN, MS_SL, VREF_H,

NC_T

2

Electrostatic

discharge voltage

AEC - Q100-002

GND, C-GND, CELL1 –

CELL7 (Cell-voltage pins,),

TSECH, TSECL, TRIG_IN,

TRIG_OUT, CLK_IN,

CLK_OUT, CVT_NOK_IN,

CVT_NOK_OUT,

ESD

kV

(1)

HBM standard

4

WAKE_IN, WAKE_OUT,

FD_IN, FD_OUT, BD_IN

and BD_OUT

Continuous Power Dissipation

Maximum power

dissipation

P

1

W

tot

Temperature Ranges and Storage Conditions

T

Storage temperature

-55

150

ºC

stg

Thermal resistance

package

R

30

3

ºC/W

thj_36

Norm: IPC/JEDEC

Package body

temperature

T

260

ºC

BODY

(2)

J-STD-020

Moisture Sensitive

Level

MSL

Note(s) and/or Footnote(s):

1. Human body model: R = 1.5kΩ; C = 100pF.

2. The reflow peak soldering temperature (body temperature) is specified according IPC/JEDEC J-STD-020 “Moisture/Reflow Sensitivity

Classification for Non-hermetic Solid State Surface Mount Devices”.

ams Datasheet, Confidential:2013-Sep [1-00]

AS8506 – 9

Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s

All defined tolerances for external components in this

specification need to be assured over the whole operation

conditions range and also over lifetime.

Typical Operating

Characteristics

Figure 6:

Operating Conditions

Symbol

Parameter

Min

Typ

Max

Unit

Note

Positive supply

voltage

VSUP

6

32

V

Normal operating condition

Negative supply

voltage

With reference to all the

voltages

VSS

-0.3

-40

2

0

85

6

V

Maximum junction

T

Ambient temperature

ºC

AMB

temperature (T ) 115ºC

J

Supply current,

NORMAL mode

3

mA

VSUP=32V, in NORMAL mode

I

SUPP, nom

Supply current,

NORMAL mode, With

External Components

VSUP=32V, in the balancing

phase with stack connection

(50% PWM duty cycle)

15

10

20

17

40

35

mA

μA

Supply current, SLEEP

mode

I

SUPP, sleep

AS8506 – 10

ams Datasheet, Confidential:2013-Sep [1-00]

Elec trical Charac teristics

Electrical Characteristics

Device Level Specifications

-40°C < Tj < 115°C.

Figure 7:

Device Level Specifications

Symbol

Vcell_in

Parameter

Min Typ

Max

4.5

Unit

Note

Cell Input voltage

measurement

1.8

ADC/DAC

ADC/DAC Reference

7

15

mV

0.1% error because of

the DAC/Guaranteed by

design

DAC_error

Com_off

Error of the DAC

2

1

Error because of the

comparator resolution

mV

Guaranteed by design

Typical value is from the

lab evaluation data.

Maximum value is from

the test data.

Sign_path_accuracy

Signal path accuracy

Initialization time

5

15

50

After Initialization, the

system will go to sleep

mode and waits for

wake signal.

T

ms

INITIALIZATION

After wake signal,

device enters into wait

mode and stays for two

sec for TRIG_IN signal, if

no TRIG_IN event

occurs, device goes to

sleep mode.

Wake up time from the

Wake signal to system

wait mode

T

75

WAKE-UP

Cell voltage and

Temperature

measurement time

Tmeas

16

ms

At10KHz clock time

Tspi3_read5k

Tspi3_read20k

Tspi3_read40k

13.6

3.4

At 5KHz clock time

At 20KHz clock time

At 40KHz clock time

SPI3 read time for

single channel

measurement

1.7

ams Datasheet, Confidential:2013-Sep [1-00]

AS8506 – 11

E l e c t r i c a l C h a ra c t e r i s t i c s

Low Dropout Regulator (5V Output LDO)

-40ºC < T < 115ºC; all voltages are with respect to ground (GND);

J

positive current flows into the pin, NORMAL operating mode, if

not otherwise mentioned. The LDO block is a linear voltage

regulator, which provides a regulated 5V.

Figure 8:

LDO Parameters

Symbol

Parameter

Input supply voltage

Output voltage range

Load Current

Min Typ Max

Unit

V

Note

V

6

12

32

5.25

50

SUP

V5V

4.75

5.0

V

I

mA

LOAD

Output short circuit

current

ICC_SH

85

60

35

250

mA

NORMAL mode

f=1kHz / No production

test

PSRR

dB

f=1MHz / No production

test

CL1

ESR1

CL2

2.2

1

10

220

1

μF

Ω

LDO output Capacitor 1

LDO output Capacitor 2

Electrolytic

Ceramic

100

0.02

nF

Ω

ESR2

Note(s) and/or Footnote(s):

1. In NORMAL mode, maximum load current will be 50mA. After internal thermal shutdown, current limit is 20mA.

2. The LDO is disabled in SLEEP mode.

AS8506 – 12

ams Datasheet, Confidential:2013-Sep [1-00]

Elec trical Charac teristics

High-precision Bandgap Reference

-40ºC < T < 115ºC; all voltages are with respect to ground

J

(GND).

Figure 9:

Bandgap Reference Parameters

Symbol

Parameter

Min Typ Max

Unit

Note

Reference output after

trim

BG_Out

1.2

1.235

2.5

1.27

4

V

After temperature trim

Reference variation with

respect to Temperature

BG_out_T

mV

After trim on the absolute

No production test

var

PSRR1K

PSRRDC

PSRR at 1KHz

PSRR at DC

20

80

dB

Note: This bandgap output is the reference for the V5V (LDO) regulator.

Digital to Analog Converter

-40ºC < T < 115ºC; all voltages are with respect to ground

J

(GND).

Figure 10:

Digital to Analog Converter

Symbol

Parameter

Min

4.75

Typ Max

Unit

V

Note

V

Input supply voltage

Input reference voltage

Resolution

5

5.25

LDO output as supply

After absolute trim

Guaranteed by design

SUP_DAC

V

4.485

4.5

12

10

50

4

4.515

V

INREF

D

bits

KHz

μs

IN

F

Update rate

Settling time

INL

DAC

SETT_DAC

T

No production test

DAC

LSB

INL

DAC

DNL

0.5

DNL

ams Datasheet, Confidential:2013-Sep [1-00]

AS8506 – 13

E l e c t r i c a l C h a ra c t e r i s t i c s

Analog to Digital Converter

-40ºC < T < 115ºC; all voltages are with respect to ground

J

(GND).

Figure 11:

Analog to Digital Converter

Symbol

Parameter

Min Typ

Max

5.25

Unit

V

Note

LDO output as supply

After absolute trim

V

Input supply voltage

Input reference voltage

Resolution

4.75

5

SUP

V

4.485

4.5

12

4.515

V

INREF

D

bits

OUT

Measurement time per

channel

T

1.4

ms

MEAS_ADC

ADC

INL

4

2

LSB

No production test.

INL

ADC

DNL

Pre-Regulator

This Pre_reg is an internal regulator which provides supply to

digital and a few analog blocks..

-40ºC < T < 115ºC; all voltages are with respect to ground

J

(GND).

Figure 12:

Pre-reg Parameters

Symbol

Parameter

Min Typ Max

Unit

Note

V

Input supply voltage

6

12

32

V

SUP

Prereg_output voltage

range

P5V

3V3

4.3

5.0

5.5

V

3.3V_output voltage

range

2.8

3.3

3.6

AS8506 – 14

ams Datasheet, Confidential:2013-Sep [1-00]

Elec trical Charac teristics

PWM Driver

40ºC < T < 115ºC; all voltages are with respect to ground (GND).

J

Figure 13:

PWM Driver

Symbol

Parameter

Min Typ Max Unit

Note

V5V

Output voltage

Frequency of PWM

4.5

25

22

12

17

27

30

37

42

47

7

5

100

25

15

20

30

35

40

45

50

12

5.5

200

28

18

23

33

38

43

48

53

20

V

KHz

%

F

PWM

%

CMOS load mode,

Optocoupler load mode

F

Duty cycle

Duty

%

F

Duty cycle error

Rise time

%

duty_error

tr

30

50

10

60

80

ns

CMOS load mode,

Optocoupler load mode

Guaranteed by design

pwm

tf

Fall time

pwm

Idrive

Cload

Driver strength

Driver switch load capacitance

12

mA

pF

Optocoupler load mode

opto

100

fd_out

ams Datasheet, Confidential:2013-Sep [1-00]

AS8506 – 15

E l e c t r i c a l C h a ra c t e r i s t i c s

PWM Oscillator

-40ºC < T < 115ºC; all voltages are with respect to ground

J

(GND).

Figure 14:

PWM Oscillator

Symbol

Parameter

Frequency

Accuracy

Min Typ

Max

Unit

kHz

%

Note

• After the frequency

trim.

• Programmable

frequency options for

25KHz, 50KHz and

200KHz are available.

f

90

100

15

110

OSC

f

OSC_ACC

Oscillator for Digital Circuit

-40ºC < T < 115ºC; all voltages are with respect to ground

J

(GND).

Figure 15:

Oscillator for Digital Circuit

Symbol

Parameter

Min Typ Max

Unit

kHz

%

Note

f

Oscillator for Digital circuit

Frequency

Accuracy

9

10

15

11

OSC-DIG

f

OSC_ACC

AS8506 – 16

ams Datasheet, Confidential:2013-Sep [1-00]

Elec trical Charac teristics

External Temperature Thresholds

-40°C < T < 115°C; all voltages are with respect to ground (GND).

J

Figure 16:

External Temperature Thresholds

Symbol

Parameter

Min

3.084

3.148

3.213

3.277

3.341

3.406

3.470

3.534

3.599

3.663

3.727

3.792

3.856

3.920

3.984

4.049

Typ

3.165

3.231

3.297

3.363

3.429

3.495

3.561

3.627

3.693

3.759

3.825

3.891

3.957

4.023

4.089

4.155

Max

3.238

3.306

3.373

3.441

3.508

3.576

3.643

3.711

3.779

3.846

3.914

3.981

4.049

4.116

4.184

4.25

Unit

Note

Code 0000

Code 0001

Code 0010

Code 0011

Code 0100

Code 0101

Code 0110

Code 0111

Code 1000

Code 1001

Code 1010

Code 0011

Code 0100

Code 0101

Code 0110

Code 0111

16 reference

thresholds are with a

step of 66mV.

Ref_ext_warn/sutdown

V

ams Datasheet, Confidential:2013-Sep [1-00]

AS8506 – 17

E l e c t r i c a l C h a ra c t e r i s t i c s

Ron of the Shuttle Switches (Internal Switch for

Charging/Discharging)

-40°C < T < 115°C.

J

Figure 17:

Ron of the Shuttle Switches

Symbol

Parameter

Min Typ Max Unit

Note

The maximum

charging/discharging

current limit through

shuttle switch is 100mA.

Only for Cell1 maximum

charging/discharging

current is limited to 30mA

less than 2V of cell voltage

at 115 junction of cell

voltage.

Ron_shut

Shuttle switch ON resistance

5

20

Ω

Over-Temperature Measurement

Figure 18:

OTM Parameters

Symbol

Parameter

Min Typ Max

Unit

Note

Junction temperature for

Shutdown

T

Shut down temperature

115

100

135

125

115

145

140

130

ºC

jshut

Junction temperature for

Warning

T

Warning temperature

Recovery temperature

ºC

jwarn

Junction temperature for

Recovery

T

jrecv

AS8506 – 18

ams Datasheet, Confidential:2013-Sep [1-00]

Elec trical Charac teristics

Weak Cell Detection (Voltage Comparator)

Figure 19:

Weak Cell Detection

Symbol

Parameter

Min Typ

Max

4.5

Unit

V

Note

V

Supply voltage

-0.3

3.6

CELL

LOW

V

Low voltage detection

-100

100

mV

2

4

6

8

No production test.

Programmable option.

Tl_spike

Minimum input spike filter

μs

Power on Voltage Detection

Figure 20:

Power on Voltage Detection

Symbol

Parameter

Min Typ Max Unit

Note

VSUP Power-on-Reset

threshold ON

VSUP_POR

5.2

4.6

3.8

3.6

4.1

3.8

5.5

4.85

4.45

4.1

5.8

5.1

4.8

4.5

4.7

4.3

V

Rising edge of VSUP

VSUP Power-on-Reset

threshold OFF

VSUP_RESET

V5V_IN_POR

V5V_IN_RESET

V5V_POR

Master reset for device

V5V_IN Power-on-Reset

threshold ON

Voltages are with respect to

VSUP measure as pass fail

test

V5V_IN Power-on-Reset

threshold OFF

V5V Power-on-Reset

threshold ON

4.5

Rising edge of V5V

Falling edge of V5V

V5V Power-on-Reset

threshold OFF

V5V_RESET

4.1

ams Datasheet, Confidential:2013-Sep [1-00]

AS8506 – 19

E l e c t r i c a l C h a ra c t e r i s t i c s

Electrical Characteristics for Digital Inputs and

Outputs

All pull-up, pull-downs have been implemented with active

devices.

Figure 21:

Digital Inputs and Outputs

Port Type Symbol

Parameter

Min

Typ

Max

Unit

Note

CS

Negative-going

threshold

Vt-

1.62

2.27

2.22

3.42

V

V5V=5V

Positive-going

threshold

INPUT

Schmitt

Trigger

Vt+

In CS pad, Pulled up to

V5V. (ISUP_HV)

I

Pull-up current

-100

-30

0.4

μA

lil_cs

SDO

High level

output voltage

BBC4C_HV,

PPTRIM_PDIO

V

2.5

V

OH

Low level

output voltage

V

VSUP ≥ 6V

OL

OUTPUT

Tristate

High level input

voltage

V

0.7*V5V

V

IH

Low level input

voltage

V

0.3*V5V

4

V

IL

Output drive

current

I

mA

O

SCLK, SDI

High level input

voltage

SDI is ICC_HV

(PPRTIM_MODE)

V

0.7*V5V

V

IH

IO Buffer

Low level input

voltage

SCLK is ICC_HV

(PPRTIM_PCLK)

V

0.3*V5V

IL

AS8506 – 20

ams Datasheet, Confidential:2013-Sep [1-00]

Elec trical Charac teristics

Port Type Symbol

Parameter

Min

Typ

Max

Unit

Note

CVT_NOK_OUT, BD_OUT, TRIG_OUT, CLK_OUT

BU2SC_HV for

CVT_NOK_OUT,

BU1C_HV for

BD_OUT, BU4SC_HV

for TRIG_OUT and

CLK_OUT

High level

2.4

V

OH

output voltage

OUTPUT

Buffer

Low level

output voltage

V

0.4

VSUP ≥ 6V

OL

Output drive

current

I

4/2/1

mA

O

FD_OUT

High level input

voltage

BU24SC_HV for

FD_OUT

V

2.4

V

OH

OUTPUT

Buffer

Low level input

voltage

V

0.4

24

VSUP ≥ 6V

OL

Output drive

current

I

mA

O

MS_SL

High level input

voltage

High voltage input

pad

V

VSUP

V

IH

INPUT Buffer

Low level input

voltage

V

0.3*V5V

IL

CLK_IN, TRIG_IN

High level input

voltage

Vt-

1.62

2.22

V

ISC_V5_HV

INPUT

Schmitt

Trigger

Low level input

voltage

Vt+

2.27

0.3*V5V

FD_IN,BD_IN, CVT_NOK_IN

High level input

voltage

V

0.7*V5V

V

ICC_V5_HV

Internal pull

IH

INPUT Buffer

Low level input

voltage

V

3.42

-30

IL

WAKE_IN

Pull up

current

Ipull_up

Pull-up current

-100

μA

Note: Test limits for Iih and Iil are 1.0uA and -1.0uA for input pads.

ams Datasheet, Confidential:2013-Sep [1-00]

AS8506 – 21

D e t a i l e d D e s c r i p t i o n

The device consists of the following blocks:

Detailed Description

• PWM driver

• LDO_5V with 5V / 50mA output

• Temperature monitor block

• High precision bandgap reference

• DAC for the reference voltage generation

• SAR ADC for cell voltage and external temperature

measurement

• Oscillators for PWM drive and for the digital logic

• Pre-Regulator

• SC Comparator

• Weak cell detection logic

• PORs on different supplies

Voltage Regulator (LDO_5V)

Power input to the LDO is VSUP pin. It is switched ON when the

device is in NORMAL mode and switched OFF in SLEEP mode.

The LDO takes the input from Bandgap and scales it up to the

required voltage. It starts charging only after entering NORMAL

mode. This LDO is the supply for DAC, the PWM driver and Cell

voltage comparators.It’s additional features are as follows:

• Stability is better than 2.5% over input range.

• Load current up to 50mA.

High Precision Bandgap (HPBG)

AS8506 has a high precision bandgap to generate accurate

reference. This reference voltage is used to generate reference

for DAC and ADC.

HPBG is trimmed with respect to temperature. Variation of the

bandgap with temperature is 3mV in the temperature range

from -40ºC to 115ºC.

External Temperature Monitor and

Measurement

Two sensor inputs TEMP_IN1 and TEMP_IN2 with a comparator

on each pin, are available. If the temperature sensor connected

to TEMP_IN1 crosses its threshold, then a warning flag is set in

the device (status can be read through SPI) and the device will

continue balancing.

If the temperature sensor connected to TEMP_IN2 crosses its

threshold, then a flag is set in the device and balancing is

stopped; but the device continues to stay in NORMAL mode for

maintaining synchronism. In both the cases, the

microcontroller will be interrupted by a pulse on

CVT_NOK_OUT pin.

AS8506 – 22

ams Datasheet, Confidential:2013-Sep [1-00]

Detailed Descript ion

In case the external temperature sensors are not being used,

then both the inputs must be connected to GND pin through

1k resistor. In the measurement phase, external temperature is

measured through the SAR ADC. Both channels of temperature

will be measured and stored in temp_in1_lsb_reg to

temp_in2_msb_reg.

Internal Temperature Monitor

The internal temperature monitor has two thresholds at T

jwarn

125ºC and T

135ºC. If the internal temperature exceeds

jshut

125ºC, then a warning flag is set in the device (status can be

read through SPI) and the device will continue balancing.

If the internal temperature exceeds 135ºC, then a flag is set in

the device and balancing is stopped; but the device continues

to stay in NORMAL mode for maintaining synchronism. In both

the cases, the microcontroller will be interrupted by a pulse on

CVT_NOK_OUT pin. The balance recovery temperature is 115ºC.

PWM Generator

In the Balance phase of the AS8506, based on the decision made

during the Compare phase, some part of the cell is charged with

the Flyback converter. To drive the external Flyback converter,

AS8506 generates a PWM signal to drive external FET or

Optocoupler or Isolation device.

The frequency and of the PWM generator can be controlled by

timer_cntl_reg register.

PWM frequency is not used for the passive balancing.

RC Oscillator

The AS8506 has a trimable RC oscillator. It is designed to

generate f

clock for the digital circuit and for the clocking

osc-dig

of the IC. Each oscillator will be trimmed with the process to get

the accuracy to f with 5-bit OTP Factory trim code.

osc-accy

DAC for the Reference Generation

AS8506 has a 12-bit DAC to generate the cell reference voltage,

cell threshold low and high voltage. The DAC code is written

into AS8506 with SPI interface from microcontroller. The output

of the DAC is given to one of the inputs of the comparators, to

compare the cell voltages synchronously. Reference for the DAC

is 4.5V, which is internally generated and is available as

reference for temperature inputs on REF_T.

ams Datasheet, Confidential:2013-Sep [1-00]

AS8506 – 23

D e t a i l e d D e s c r i p t i o n

SAR ADC

AS8506 has a 12-bit SAR ADC to measure the cell voltage and

external temperature. The SAR ADC uses the 12-bit DAC to

generate the digital code. The SAR ADC range is 1.8V to 4.5V for

cell voltage measurement and 0.2V to 4.5V for the temperature

measurement.

Cell voltage and temperature is measured in the short trigger

phase. After the trigger goes ‘high’, compare phase starts and

then all the cell voltages and external temperature are

measured and stored in the digital registers.

Pre-Regulator

AS8506 has an internal pre-regulator, which generates supply

voltages for the internal blocks. Pre-Regulator output is used as

a supply for the oscillators. All the digital logic and the FSM will

work on the pre-regulator supply.

In SLEEP mode only the pre-regulator will be working along with

the WAKE_IN detect circuit.

Cell Threshold

AS8506 has the potential to set the two threshold levels to the

cell voltage through pins CELL_THU and CELL_THL. These

values can be set externally, (or) through OTP trim bits, (or) from

the external microcontroller by writing DAC code into the cell

threshold registers in the register space.

Weak Cell Detection

AS8506 has the ability to detect the weak cell. During load

conditions, if the cell reaches voltage of about 0.1V to -0.2V,

then this variation is detected and stored in the zero cross

detection register. This event is indicated to the master device

by a pulse on CVT_NOK_OUT pin in Compare and Balance

phase. The master device indicates the microcontroller by

setting CVT_NOK_OUT ‘high’. In WAIT mode only this will be

stored in the register; there won’t be any CVT_NOK_OUT to μC.

The register is cleared on μC reading.

External Resister Divider Control

AS8506 has the provision to enable the external divider to give

the desired cell voltage to the at VREF_IN pin. External resister

divider can be connected between VREF_H pin to ground.

Calculate the external resister divider values such that the

output of the divider will provide the desired reference value.

When comparison is not happening, this divider can be

disabled using SPI.

AS8506 – 24

ams Datasheet, Confidential:2013-Sep [1-00]

Detailed Descript ion

PORs on Different Supplies

AS8506 has power-on-reset blocks on VSUP, V5Vand V5V_IN

supply pins. The values for POR and Reset thresholds are given

in Figure 20.

Figure 22:

Power-up Sequence of VSUP, V5V and VSUP+5V

VSUP_POR

VSUP_RESET

VSUP

VSUP_POR

V5V_5V_POR

V5V_5V

V5V_5V_RESET

V5V_5v_POR

V5V_POR

V5V_RESET

V5V

V5V_POR

ams Datasheet, Confidential:2013-Sep [1-00]

AS8506 – 25

D e t a i l e d D e s c r i p t i o n

AS8506 System Operation

The AS8506 battery stack system can be set up by configuring

one AS8506 device as ‘Master’ and the rest as ‘Slave’ devices.

The AS8506 Master device is connected to the microcontroller,

and the Slave devices are connected to Master through a

daisy-chain of 3-wire customized SPI protocol. The

microcontroller can communicate to the Slave devices through

the Master. On power-up of the system, the microcontroller

must assign an address to all AS8506 devices including the

Master. The microcontroller can assign the address to AS8506

devices by initiating the address allocation process, by writing

a top most Slave device address into dadd_for_allc_reg register

of Master and then writing ‘07’ data into spi3_cmd_reg. Once

the address allocation process is successful, the microcontroller

can start the cell balancing. If cell balancing or check status

command is not triggered by the microcontroller, after WAIT

mode timeout period all devices enter into SLEEP mode.

The complete system communication procedure is explained

below.

• The microcontroller gives wake pulse on WAKE_IN to

bring the Master and Slaves in NORMAL mode.

• After the wake-up time period, the microcontroller (μC)

sends the reference voltage digital code to the Master

device through a 4-wire SPI.

• After receiving the digital reference code from μC, the

Master device initiates a 3-wire custom SPI operation to

send the digital reference code to the Slave devices.

• The microcontroller waits for the 3-wire SPI operation

time period. After the 3-wire SPI time period, it initiates

the cell balancing through TRIG_IN. The balancing will

continue as long as TRIG_IN is ‘High’.

• The microcontroller can change the reference value at any

time by making TRIG_IN ‘Low’ and initiating a 4-wire SPI

with new value of reference code. From here on, the

procedure is same as from point 3.

• The balance done is indicated on BD_OUT pin.

• The failure in the 3-wire SPI operation is indicated on

CVT_NOK_OUT pin.

AS8506 – 26

ams Datasheet, Confidential:2013-Sep [1-00]

Detailed Descript ion

Figure 23:

Functional Diagram of AS8506

uC reference voltage

calculator found change in

reference (average) voltage

uC reference voltage

calculator found change in

reference (average) voltage

MICRO

PROCESSOR

4-wire SPI

write

Wake

up

pulse

by

Trigger from uC

on TRIG_IN pin

for cell balancing

operation

Trigger from uC

on TRIG_IN pin

for cell balancing

operation

based on current

status of stack

voltage new

Balance

Reference

voltage from uc

through 4 wire

SPI operation

(DAC code)

uC

Reference

voltage from uc

through 4 wire

SPI operation

(DAC code)

MASTER

3-wire

CUSTOM

write

3-wire

CUSTOM

write

4-wire SPI

Read

CELL

Balancing

4-wire SPI

Read

CELL

Balancing

Wake

up

pulse

by

Sleep

mode

MASTER module

initiates a 2 wire

SPI operation to

send the new

Balance

MASTER module

initiates a 2 wire

SPI operation to

send the Balance

Reference voltage

from uc to slave

modules (DAC

code)

cell Balancing to

reference value

set by uC.

cell Balancing to

reference value

set by uC.

uC

Reference

voltage from uc

to slave modules

(DAC code)

3-wire

CUSTOM

Read

3-wire

CUSTOM

Read

SLAVES

CELL

Balancing

CELL

Balancing

Wake

up

pulse

by

Sleep

mode

Normal

mode

uC

ams Datasheet, Confidential:2013-Sep [1-00]

AS8506 – 27

D e t a i l e d D e s c r i p t i o n

Functional State Diagram

Figure 24:

Finite State Machine Mode

Power ON

Initialization Phase

Vsup POR

OSC clock ON

V5V LDO ON

V5V POR

OTP Load

OTP Load done

Sleep Mode

V5V LDO OFF

OSC clock OFF

Pre-reg ON

Wake_pulse

Wake Mode

V5V LDO ON

Timeout

OSC clock ON

&

No trigger

V5V_por

Wait Mode

Wait for µC Trigger

(X mS)

V5V LDO ON

OSC clock ON

No trigger

long_trigger

short_trigger

Normal Mode

Compare phase

cell

balance

phase

and

Compare

phase

ADC Measurement phase

V5V LDO ON

OSC clock ON

V5V LDO ON

OSC clock ON

AS8506 – 28

ams Datasheet, Confidential:2013-Sep [1-00]

Detailed Descript ion

Operating Modes

The AS8506 has two main operating modes NORMAL and SLEEP,

and has two transition modes WAIT and WAKE. The transition

modes are intermediate modes for switching from SLEEP to

NORMAL and vice versa. The detailed operation of each mode

is explained in subsequent sections. The initialization phase is

explained in“Initialization Sequence” on page 36.

NORMAL Mode

The device enters into NORMAL from WAKE when it receives a

short or long trigger. The NORMAL mode is a full functional

mode, where all the power supply and analog blocks are in

ON-state and the digital is fully functional.

The NORMAL mode has two phases of operation:

• Diagnosis phase

• Balance phase

Diagnosis Phase

In Diagnosis phase AS8506 detects the number of cells

connected to the device. The connected cell voltages are then

compared with upper & lower thresholds and target cell voltage

of all cells connected. Upper and lower cell voltage thresholds

as well as target cell voltages are provided from external in

analog or digital format. The Diagnosis phase sequence of

operation is explained below.

• Detects number of cells connected to the device by

comparing each cell terminals to cell detect threshold

voltage.

• Simultaneously compares each connected cell voltage

with set lower operating voltage threshold Vlimit_L. If any

of the cell voltages is less than the set lower operating

threshold, then an indication is given on CVT_NOK_OUT

pin stating that one/more cell voltages are not within the

operating voltage threshold range. Each cell status is

stored in cel_low_thsld_stat_reg register.

• Simultaneously compares each connected cell voltage

with set higher operating voltage threshold Vlimit_H. If

any of the cell voltages is greater than the set higher

operating threshold, then an indication is given on

CVT_NOK_OUT pin stating that one/more cell voltages

are not within the operating voltage threshold range. Each

cell status is stored in cel_high_thsld_stat_reg register.

• Simultaneously compares each connected cell voltage

with reference value. This result is stored in

cel_ref_stat_reg register and used in balance phase. Cell

reference can be provided by microcontroller by writing

into register or by providing input at external pin

VREF_IN.

• Enables the SAR ADC and measures each cell voltage and

two temperature inputs sequentially. The 12 bits cell

voltage and temperature inputs information is stored in

respective registers.

ams Datasheet, Confidential:2013-Sep [1-00]

AS8506 – 29

D e t a i l e d D e s c r i p t i o n

At the end of the Diagnosis phase, if trigger signal is ‘High’ then

it enters into Balance phase. If trigger signal is ‘Low’ it enters

into WAIT mode.

The Diagnosis phase without the cell voltage measurement

with SAR ADC is called Compare phase.

Balance Phase

The Balance phase is basically a charging cycle in case of active

balancing and a discharging cycle in case of passive balancing.

The Balance phase is divided into 7 time slots. The device will

move through all 7 time slots irrespective of number of cells

connected to the device. This is done to keep synchronization

between each module in case of battery stack system. One time

slot is assigned to each cell (sequential order) for charging or

discharging. The period of time slots is programmable (see

“Status Registers” on page 52).

In each time slot, following operations are done.

• Check CVT_NOK flag status. If CVT_NOK flag is set, then

no operation is done till time slot is over. If CVT_NOK flag

is not set, then move to the next step.

• Based on Diagnosis phase results, shuttle switch

corresponding to current time slot cell is switched ON for

charging that cell in case of active balancing, and

discharging in case of passive balancing.

• The PWM generator is enabled and PWM driver start

driving the Flyback converter FET (external component)

in case of active balancing. The PWM frequency and duty

cycles are factory programmable and also register

controllable. In case of stack system, the bottom module

PWM driver is enabled when there is a request of charging

or discharging from top module on FD_OUT pin.

• At the end of the current time slot, stop the PWM

generator and then open the corresponding shuttle

switches. The device moves to the next time slot.

In the Balance phase, at any point, if the trigger input goes ‘Low’,

then the device suspends balancing operation and enters into

WAIT mode.

Sleep Mode

This is the least power consumption mode of AS8506. In this

mode only pre-reg is ON, rest all analog blocks are OFF and

digital clock is disabled. Only a digital wake detection circuit is

active. The device enters into this mode when there is no trigger

from microcontroller for time greater than WAIT mode timeout

period.

Wait Mode

This mode is a transition mode, where the device waits for

command on TRIG_IN pin either from microcontroller, (or) from

below module in case of stack system. The device will be in this

state for T

period. After the timeout, the device

WMODE_TOUT

AS8506 – 30

ams Datasheet, Confidential:2013-Sep [1-00]

Detailed Descript ion

enters into SLEEP mode. In the WAIT period all power blocks are

ON, all analog blocks are ON and digital is also functional. In

this mode, power consumption is lesser than NORMAL mode

because there are no charge balancing activities being carried

out.

Wake Mode

This is also a transition mode, where the device does

initialization after exiting SLEEP mode. In the SLEEP mode if

AS8506 receives a wake pulse of width T

, the device enters

WAKE

into WAKE mode. In the WAKE mode device enables the V5V LDO

and waits for V5V_por_n signal. Once V5V_por_n signal

becomes ‘High’, the device enters into WAIT mode.

An example of Compare and Balance (active balance) phase

sequence with respect to time is given in Figure 25. In this

example it is assumed that only 6 cells are connected to AS8506

and comparators’ outputs at Diagnosis phase is “010010X”;

Where:

‘0’ indicates respective cell voltage is less than target voltage

and needs charging.

‘1’ indicates respective cell voltage is more than target voltage

and needs charging.

‘X’ indicates no cell is connected to respective comparator and

output is neglected.

Figure 25:

Diagnosis and Balance Phase with Time Sequence for AS8506

Charging

PWM

Charging

PWM

Charging

PWM

Charging

PWM

Idle

Time

Idle

Time

Idle

Time

Cell

Connected

Cell

Connected

Cell

Connected

Cell

Connected

Cell

Connected

Cell

Connected

Cell

Not

Vcell1 < Vrdiv Vcell2 > Vrdiv Vcell3 < Vrdiv Vcell4 < Vrdiv

Vcell5 > Vrdiv Vcell6 < Vrdiv

Connected

Need

Charging

Don’t Need

Charging

Need

Charging

Need

Charging

Don’t Need

Charging

Need

Charging

T_{c_slot}

Compare Phase

Balance Phase

Compare Phase

ams Datasheet, Confidential:2013-Sep [1-00]

AS8506 – 31

D e t a i l e d D e s c r i p t i o n

Wake-up Event

The AS8506 device comes out of SLEEP mode by a wake pulse

on the WAKE_IN pin. To avoid false wake by noises on the

WAKE_IN, the wake signal (Low pulse) is taken through a

low-pass filter from WAKE_IN pin. When a pulse of width

T

is given on the WAKE_IN by the microcontroller, the

wake_pulse

device wakes up and enters into WAKE mode. The low-pass filter

discards all signals having width less than T and allows

filter_min

all signals with width greater than T

. The filter is

filter_max

uncertain in T

region. The negative edge which is

uncertain

passing through the filter will wake the device from SLEEP

mode. In chain of AS8506 devices, to propagate the negative

edge the microcontroller has to give minimum low pulse of

width T

. Before entering into SLEEP mode the wake

wake_pulse

pin must be ‘High’.

Figure 26:

WAKE-UP Signaling

WAKE_IN

T_uncertain

T_{filter_max}

T_{wake_pulse}

T_{filter_min}

T_uncertain

wake_in_fltrd

T_{filter_delay}

AS8506 – 32

ams Datasheet, Confidential:2013-Sep [1-00]

Detailed Descript ion

Trigger Event

The AS8506 device enters into NORMAL mode only when a valid

command is present on the TRIG_IN pin. There are two

commands in the device.

• Diagnosis command

• Cell balance command

When a high pulse of width T

as shown in Figure 27, is

diag_cmd

given on TRIG_IN pin, the device performs the following

operations.

• Compares all connected cell voltages with the set lower

operating voltage threshold, and if any of the cell voltage

is less than lower threshold, then sets a corresponding flag

in the cel_low_thsld_stat_reg register. This is indicated by

high pulse on CVT_NOK_OUT pin.

• Compares all connected cell voltages with the set higher

operating voltage threshold, and if any of the cell voltage

is more than higher threshold, then sets a corresponding

flag in the cel_high_thsld_stat_reg register. This is

indicated by high pulse on CVT_NOK_OUT pin.

• Sets a corresponding flag in the temp_stat_reg register if

ambient temperature or internal chip temperature is

higher than respective thresholds. This is indicated by

high pulse on CVT_NOK_OUT pin.

• It will enable SAR ADC and starts measuring each cell

voltage, and then measures temperature channel

measurement. The 12 bits digital value will be stored in

corresponding registers.

Thus, on diagnosis command the device gives the cell operating

voltage, ambient temperature and internal temperature status

with respect to its safe operating range.

When the TRIG_IN pin is ‘High’ for longer than the status

command, the device enters into Balance phase. Depending

upon cell voltage status, the device starts balancing the cell

voltages. The cell voltage balancing is continued till the high

voltage on the TRIG_IN pin. As soon as TRIG_IN goes ‘Low’, the

device stops balancing and enters into WAIT mode. Thus, the

microcontroller has full control over the balancing time and

stop balancing whenever required.

ams Datasheet, Confidential:2013-Sep [1-00]

AS8506 – 33

D e t a i l e d D e s c r i p t i o n

Figure 27:

TRIG_IN Command Signaling

Cell Balance

Command

Diagnosis

Command

TRIG_IN

T_{status_cmd}

T_{bal_cmd}

Device

State

WAIT

MODE

NORMAL MODE

(Diagnosis phase)

WAIT

MODE

NORMAL MODE

(Compare + Balance phase)

WAIT

MODE

AS8506 – 34

ams Datasheet, Confidential:2013-Sep [1-00]

Detailed Descript ion

Balancing Algorithm

Figure 28:

Cell Balancing Algorithm

Trigger

BD_IN

compare all

connected cells with

reference voltage

BD_OUT

identify and store

toggle of connected cell

comparator outputs

All

connected

cell comp

toggle?

generate Internal

Balance done

YES

NO

Active – balancing

Charge cells with comp

o/p = 0.

Passive – balancing

discharge cell with

comp o/p = 1

7 Time slot

Over ?

NO

YES

ams Datasheet, Confidential:2013-Sep [1-00]

AS8506 – 35

D e t a i l e d D e s c r i p t i o n

Initialization Sequence

The power-up initialization sequence diagram for AS8506 is

shown in Figure 29.

• When the power supply is switched ON, initially VSUP POR

output Vsup_por_n is ‘Low’; hence all the digital logic will

be in reset state.

• Once the VSUP crosses the Vsup_por_th, the VSUP POR

output becomes ‘High’ enabling the oscillator and

high-precision bandgap (HPBG) block.

• The digital block is now operational. It will now enable the

V5V LDO and waits for V5V_por_n high signal from the

V5V POR block.

• Once the V5V crosses V5V_por_th, the V5V_por_n will be

‘High’. The OTP auto load command is generated by ‘High’

on otp_por_n signal. Now the device waits for T

auto_load

period for OTP contents to load into digital local registers.

• After the OTP contents are loaded into digital local

registers, the device power-up sequence is completed.

The device enters into SLEEP mode. In SLEEP mode, the

LDO, oscillator and HPBG are disabled.

• The wake-up circuit monitors the WAKE_IN pin for

wake-up pulse. When a wake-up pulse is received, the

oscillator and HPBG block are enabled and device enters

into WAKE mode. In the WAKE mode, the device enables

V5V LDO and waits for V5V_por_n high signal.

• Once the V5V crosses V5V_por_th, the V5V_por_n will be

‘High’ and the device enters into WAIT mode. In WAIT

mode the device waits for trigger pulse on TRIG_IN pin

from microcontroller. In this state, if a short or long pulse

trigger signal is received on TRIG_IN within T

wmode_tout

period, the AS8506 enters into NORMAL mode and

performs required operations based on trigger pulse.

AS8506 – 36

ams Datasheet, Confidential:2013-Sep [1-00]

D e v i c e I n t e r f a c e

A 4-wire SPI is used to communicate with the device. Pins CS,

SCLK, SDI, and SDO are used for SPI interface.

Device Interface

Serial Peripheral Interface

The Serial Peripheral Interface (SPI) provides the

communication link with the microcontroller. The SPI is

configured for half-duplex data transfer. The SPI in AS8506

provides access to the status registers, control registers and test

registers. The SPI is also used to enter into test and OTP modes.

This interface is only Slave interface and only Master can initiate

the SPI operation. The SPI also supports block data transfer

where sequential register data can be accessed with single SPI

command.

The SPI can work on both the clock polarities. The polarity of

the clock is dependent on the value of SCLK at the falling edge

of CS.

At the falling edge of CS,

• If SCLK is “1”, then the SPI is negative edge triggered.

• If the SCLK is “0”, then SPI is positive edge triggered logic.

see Figure 30 for more details.

Figure 30:

SPI Clock Polarity Table

CS

SCLK

Description

↓

Low

Serial data is transferred at rising edge and sampled at falling edge of SCLK.

↓

High

Serial data is transferred at falling edge and sampled at rising edge of SCLK.

AS8506 – 38

ams Datasheet, Confidential:2013-Sep [1-00]

Device I nter face

The SPI protocol frame is divided into two fields.

• The header field

• The data field

The header field is 1 byte long; containing a read/write

command bit, 1 reserved bit, and 6 address bits. The SPI frame

format is shown in Figure 31. In the data phase MSB is sent first

and LSB is sent last.

Figure 31:

SPI Frame Format

Header Field

Data Field

1 byte

Integer Multiple of Bytes

R/W

0

A5 A4 A3 A2 A1 A0

DATA

Reserved

Bit

6 bits

Address

0 – WRITE

1 – READ

SPI Write Operation

The SPI write operation begins with clock polarity selection at

negative edge of CS (see Figure 30). Once the clock polarity is

selected, the SPI write command is given by providing ‘0’ in R/W

bit of the header field in first sampling edge at SDI pin. The next

bit in header field is reserved and set to ‘0’. The 6 bits address

of register to be written is provided at SDI pin in next six

consecutive sampling edges of SCLK. The data to be written is

followed by last bit of header field. With each sampling edge a

bit is sampled starting from MSB to LSB. During complete SPI

write operation the SCSN has to be ‘Low’. The SPI write

operation ends with positive edge of SCSN. The waveform for

SPI write operation with single data byte is shown in Figure 32

and Figure 33.

ams Datasheet, Confidential:2013-Sep [1-00]

AS8506 – 39

D e v i c e I n t e r f a c e

Figure 32:

SPI Write Operation with Negative Clock Polarity and 1 Byte of Data Field

SCSN

SCLK

R0 A5

A4

A3

A2

A1

A0 D7 D6

D5

D4

D3

D2

D1 D0

SDI

SDO

Figure 33:

SPI Write Operation with Positive Clock Polarity and 1 Byte of Data Field

SCSN

SCLK

SDI

R0

A5

A4

A3 A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

SDO

Sampling Edge

High Impedance Sate

In case of SPI block write operation, first data byte is written

into addressed register same as single byte write operation.

After first data byte, Master can send next data byte by keeping

CS ‘Low’ and giving clock on SCLK as per polarity selection. At

the end of every eighth data bit, the byte is written into next

consecutive address location (internally address is incremented

by one location). In this way, Master can continue writing into

consecutive address locations. The waveform is shown in

Figure 34.

AS8506 – 40

ams Datasheet, Confidential:2013-Sep [1-00]

Device I nter face

Figure 34:

SPI Block Write Operation with Negative Clock Polarity

CS

SCLK

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

A

5

A

4

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

A

3

A

2

A

1

A

0

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

SDI

SDO

Data D7-D0 is

moved to Address

A5-A0 +1 here

moved to Address

A5-A0 +2 here

moved to Address

A5-A0 +3 here

moved to Address

A5-A0 here

moved to Address

A5-A0 +4 here

SPI Read Operation

The SPI read operation also begins with clock polarity selection

at negative edge of SCSN (see Figure 30). Once the clock

polarity is selected, the SPI read command is given by providing

‘1’ in R/W bit of the header field in first sampling edge at SDI

pin. The next bit in header fields is reserved and set to ‘0’. The

6 bits address of register to be read is provided at SDI pin in

next six consecutive sampling edges of SCLK. The read data is

followed by last bit of header field on SDO pin. With each

sampling edge a bit can be read on SDO pin starting from MSB

to LSB. In case of multi-data bytes, MSB of next data byte can

be read after the LSB of previous data byte. During complete

SPI read operation the SCSN has to be ‘Low’. The SPI read

operation ends with positive edge of SCSN. The wave form for

SPI read operation with single data byte is shown in Figure 35

and Figure 36.

Figure 35:

SPI Read Operation with Negative Clock Polarity and 1 Byte of Data Field

SCSN

SCLK

R0

A5

A4

A3

A2

A1 A0

SDI

SDO

D7

D6 D5

D4

D3

D2

D1

D0

ams Datasheet, Confidential:2013-Sep [1-00]

AS8506 – 41

D e v i c e I n t e r f a c e

Figure 36:

SPI Read Operation with Positive Clock Polarity and 1 Byte of Data Field

SCSN

SCLK

A5

A4

A3

A2

A1

A0

R0

SDI

SDO

D7

D6

D5

D4

D3

D2

D1

D0

Sampling Edge

High Impedance Sate

AS8506 – 42

ams Datasheet, Confidential:2013-Sep [1-00]

Device I nter face

In case of SPI block read operation, first data byte is read from

addressed register same as single byte read operation. After

first data byte read, Master can read next consecutive addressed

data by keeping CS ‘Low’ and giving clock on SCLK as per clock

polarity selection. At the end of every eighth data bit, the

address pointer is incremented to next consecutive address

location. In this way Master can continue reading from

consecutive register address locations. The waveform is shown

in Figure 37.

Figure 37:

SPI Block Read Operation with Negative Clock Polarity

CS

SCLK

A

4

A

3

A

2

A

1

A

0

A

5

0

1

SDI

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

SDIO

Data D7-D0 at

Address A5-A0

is read here

Address A5-A0 +1

is read here

Address A5-A0 +2

is read here

Address A5-A0 +3

is read here

Address A5-A0 +4

is read here

Address Allocation Process

During the system configuration the microcontroller has to

allocate a unique address to each of the AS8506 devices

including the Master to communicate with SPI3. The

microcontroller before initiating the address allocation process,

it writes top most device address into allcd_dev_add_reg of the

Master through 4-wire SPI. The microcontroller can initiate the

address allocation process by writing ‘100’ command code and

setting D0 to 1 in spi3_cmd_reg register. By sighting ‘1’ at

spi3_cmd_reg [0], the Master initiates a SPI3 address allocation

write with top most device address as data. The address

“000000” is reserved as broadcast address visible to all devices.

The address allocation process is explained for six AS8506

devices (including Master) stack system in Figure 38.

ams Datasheet, Confidential:2013-Sep [1-00]

AS8506 – 43

D e v i c e I n t e r f a c e

Figure 38:

Address Allocation Process

SPI3 address allocation write

operation

Address allocation process

STOP

CLK-IN/OUT

TRIG-IN/OUT

CVT_NOK_IN

C1

C0 TST

Address of

6^thDevice

New

Address = 6

Address = X

CVT_NOK_OUT6

CVT_NOK_IN5

New

Address = 6

Address of

5^thDevice

Address = X

Final Address

6 -1 = 5

CVT_NOK_OUT5

CVT_NOK_IN4

New

Address = 6

Address of

4^thDevice

Address = X

Final Address

6-1=5 5-1=4

CVT_NOK_OUT4

CVT_NOK_IN3

New

Address = 6

Address of

3^rdDevice

Address = X

Final Address

6-1=5 5-1=4 4-1=3

CVT_NOK_OUT3

CVT_NOK_IN2

New

Address = 6

Address of

2^ndDevice

Address = X

Final Address

6-1=5 5-1=4 4-1=3 3-1=2

CVT_NOK_OUT2

CVT_NOK_IN1

Address of

1^stDevice

(Master)

New

Address = 6

Address = X

Final Address

6-1=5 5-1=4 4-1=3 3-1=2

2-1=1

CVT_NOK_OUT1

(Master)

AS8506 – 44

ams Datasheet, Confidential:2013-Sep [1-00]

Device I nter face

In the address allocation process, the

CVT_NOK_IN/CVT_NOK_OUT pins of AS8506 are used. After

the successful SPI3 address allocation write operation, all

AS8506 devices including Master will store the top device

address (sent by Master in SPI3 address allocation write) as its

address. The top device identifies itself as top most device and

registers the address as its final address and at first rising edge

of clock all devices force ‘High’ on its CVT_NOK_OUT pin. The

concept of address allocation is: after the STOP of SPI3, at every

falling edge of the clock each device will sample its

CVT_NOK_IN pin. If CVT_NOK_IN pin is ‘High’, the device will

decrement the assigned address by ‘1’ and continue to force

‘High’ on its CVT_NOK_OUT pin at rising edge of clock. If

CVT_NOK_IN is sampled to be ‘Low’, then the address value at

register will be stored as its final device address and it stops

forcing ‘High’ on its CVT_NOK_OUT pin and makes it ‘Low’ at

next rising edge of clock.

In Figure 38, top most device pins are suffixed with ‘6’ down to

lower most device (Master) pins suffixed with ‘1’ in descending

order. There is no device above topmost device, CVT_NOK_IN6

is always ‘Low’; therefore the address sent by Master is final

address for the top device. For the fifth device the

CVT_NOK_IN5 is ‘Low’ for one clock cycle, the address is

decremented once. For the fourth device CVT_NOK_IN4 is ‘Low’

for two clock cycles, the address is decremented twice before

registering it as final address. This procedure is continued and

finally the Master device CVT_ONK_IN1 is ‘Low’ for 5 clock

cycles, the address is decremented five times and finally

address register will have value of “000001” as its final address.

The microcontroller can identify the end of address allocation

procedure in two ways:

• One way is by probing CVT_NOK_OUT of Master after

initiating address allocation process for a pulse.

• The other method is by polling bit0 of spi3_cmd_reg

register for ‘0’ (Low) and no CRC errors.

During SPI3 address allocation write operation, if a CRC error

occurs in the any of the Slaves, the Master indicates this failure

of SPI3 transaction to all Slaves by driving TST bit ‘High’. All

Slaves should terminate the address allocation process if a

‘High’ TST bit is seen during start address allocation process

SPI3 write operation. The Master will indicate the failure of

address allocation process to μC by asserting a flag in the

spi3_sts_reg register and sending interrupt pulse on its

CVT_NOK_OUT pin.

ams Datasheet, Confidential:2013-Sep [1-00]

AS8506 – 45

D e v i c e I n t e r f a c e

Communication to Slaves

There are two modes of communication between the Master

and Slaves in the AS8506 stack system:

• Broadcast Communication

• Communication with Individual Slave

Broadcast Communication

The Broadcast of communication is used to send the reference,

lower, upper threshold limit codes and timer control register

values for all the slaves.

Reference and thresholds can be set by one of the two methods:

• Through the external pins

• Through the Internal DAC

In case of the stacked system, reference and thresholds can be

set by writing DAC values though broadcast SPI command.

Write the corresponding data in the registers of timer_cntl_reg,

ref_dcod_lsb_reg/ref_dcod_msb_reg,

hlmt_dcod_lsb_reg/hlmt_dcod_msb_reg and

llmt_dcod_lsb_reg/llmt_dcod_msb_reg and command in the

Command Registers spi3_cmd_reg and spop_dadd_bcmd_reg.

Example:

To write DAC code of 0x0666 in the lower threshold register of

all the devices, initiate a broadcast command as given in the

below sequence.

Figure 39:

Threshold Setting through Broadcast Command to Slaves

Command

Register Name

llmt_dcod_lsb_reg

llmt_dcod_msb_reg

spop_dadd_bcmd_reg

spi3_cmd_reg

Address

0x23

Data

0x66

0x06

0x03

0x09

To set low threshold

0x24

Broadcast the cell lower limit DAC code

Broadcast communication command

0x25

0x28

Each broadcast write operation takes 35 clock cycles of the

communication frequency. The default communication

frequency is 5KHz.

Broadcast slave register write is also possible other than above

registers.

If there any specific register of all the slaves to be written with

the same content of Master then this feature is useful.

Write register address in the spop_reg_add_reg.

AS8506 – 46

ams Datasheet, Confidential:2013-Sep [1-00]

Device I nter face

Example:

To set the external temperature thresholds to 4.15V, initiate a

broadcast command as given in the below sequence.

Figure 40:

External Temperature Threshold Setting through Broadcast Command to Slaves

Command

Register Name

tflg_tshld_setg_reg

spop_reg_add_reg

spi3_cmd_reg

Address

0x1D

Data

0xFF

0x1D

0x0B

To set the external temperature threshold

Address of the register to broadcast

Broadcast communication command

0x26

0x28

Communication with Individual Slave

Communication with an individual slave is done as SPI write or

read.

Write operation.

To perform the write operation to one of the slave device,

corresponding data should be written in these registers

spop_dadd_bcmd_reg, spop_reg_add_reg, wrop_data_reg

and spi3_cmd_reg.

Example:

To set the external temperature threshold of the slave device

address 0x06 to 4.15V, initiate a broadcast command as given

in the below sequence.

Figure 41:

Write Operation to the Individual Slave

Command

Slave device address

Register Name

spop_dadd_bcmd_reg

spop_reg_add_reg

wrop_data_reg

Address

0x25

Data

0x06

0x1D

0xFF

0x05

Address of the slave register

To set the external temperature threshold

Slave write command

0x26

0x27

spi3_cmd_reg

0x28

ams Datasheet, Confidential:2013-Sep [1-00]

AS8506 – 47

D e v i c e I n t e r f a c e

Read operation.

To perform the read operation to one of the slave device,

corresponding data should be written in these registers

spop_dadd_bcmd_reg, spop_reg_add_reg and spi3_cmd_reg.

Data from the slave device will be written in the register

rdop_data_reg.

Example:

To read the temperature status register of the slave device

address 0x06, initiate a broadcast command as given in the

below sequence.

Figure 42:

Read Operation to the Individual Slave

Command

Register Name

Address

0x25

Data

0x06

0x05

0x03

Slave device address Slave

Address of the slave register

write command

spop_dadd_bcmd_reg

spop_reg_add_reg

spi3_cmd_reg

0x26

0x28

AS8506 – 48

ams Datasheet, Confidential:2013-Sep [1-00]

Device I nter face

SPI Timing Diagrams

Figure 43:

Timing Diagram for Write Operation

SCS

...

t_CPS

t_CPHD

t_SCLKH

t_SCLKL

t_CSH

SCLK

CLK

polarity

t_DIS

t_DIH

...

SDI

DATAI

SDO

Figure 44:

Timing Diagram for Read Operation

SCS

t_SCLKH

t_SCLKL

SCLK

SDI

DATAI

t_DOD

t_DOHZ

SDO

DATAO (D7)

DATAO (D0)

0

N

ams Datasheet, Confidential:2013-Sep [1-00]

AS8506 – 49

D e v i c e I n t e r f a c e

SPI Protocol

Figure 45:

SPI Timing Parameters

Symbol

Parameter

Min

Typ

Max

Unit

Note

General

BR

Bit rate

1

Mbps

ns

SPI

T

Clock high time

Clock low time

400

SCLKH

T

ns

SCLKL

Write Operation Parameters

Data in setup

time

t

20

ns

DIS

t

Data in hold time

SCSN hold time

20

ns

DIH

T

20

CSH

Read Operation Parameters

t

Data out delay

80

ns

DOD

Data out to high

impedance delay

Time for the SPI to release

the SDO bus

t

80

DOHZ

Timing Parameters for SCLK Polarity Identification

Setup time of SCLK with

respect to SCSN falling

edge.

Clock setup time

(CLK polarity)

t

20

ns

CPS

Hold time of SCLK with

respect to SCSN falling

edge.

Clock hold time

(CLK polarity)

t

CPHD

AS8506 – 50

ams Datasheet, Confidential:2013-Sep [1-00]

Device I nter face

System Timings

Figure 46:

System Timings

Symbol

Parameter

Min

Wake-up Timing

100

Typ

Max

Unit

Note

T

Wake pulse width

μs

wake_pulse

Time between edge on TRIG_IN pin

to trig_in_fltrd signal

T

4

filter_delay

T

WAKE_IN pin filter specification

1

filter

Trigger Timing

T

Status request command pulse

Cell balance command pulse

500

1000

μs

status_cmd

T

7000

bal_cmd

Wait Mode Timing

T

WAIT mode timeout

2000

ms

wmode_tout

ams Datasheet, Confidential:2013-Sep [1-00]

AS8506 – 51

D e v i c e I n t e r f a c e

Register Space Description

The AS8506 register space is divided into control registers and

test registers. All of these registers are accessed through SPI.

Status Registers

Figure 47:

Cell Detection Status Register

SPI

4

SPI

3

POR

Value

Address Register Name

Features and Bit Description

Indicates the detected cells.

0 → Cell 1 is not detected

1 → Cell 1 is detected

D0

0 → Cell 2 is not detected

1 → Cell 2 is detected

D1

0 → Cell 3 is not detected

1 → Cell 3 is detected

D2

0 → Cell 4 is not detected

1→ Cell 4 is detected

0000_0000

POR_V5V

0x00

cel_det_stat_reg

D3

R

0 → Cell 5 is not detected

1 → Cell 5 is detected

D4

0 → Cell 6 is not detected

1 → Cell 6 is detected

D5

0 → Cell 7 is not detected

1 → Cell 7 is detected

D6

D7

Reserved

AS8506 – 52

ams Datasheet, Confidential:2013-Sep [1-00]

Device I nter face

Figure 48:

Diagnostic Status Register

POR

Value

Address Register Name

Features and Bit Description

SPI4 SPI3

Diagnostic register. μC can read this

register if pulse is detected on

CVT_NOK_OUT pin, to diagnose cause

of indication.

1 → Low Threshold limit cross

Indicator

D0

1 → High Threshold limit

cross indicator

D1

1 → Over-temperature

indicator

0000_0000

POR_V5V

D2

0x01

diag_sts_reg

R

1 → Address allocation

procedure fail

D3

D4

D5

1 → SPI3 read operation fail

1 → SPI3 write operation fail

1 → SPI3 Broadcast operation

D6

D7

fail

Reserved

ams Datasheet, Confidential:2013-Sep [1-00]

AS8506 – 53

D e v i c e I n t e r f a c e

Figure 49:

Cell Lower Threshold Status Register

Features and Bit

Description

POR

Value

Address

Register Name

SPI4 SPI3

Indicates if a cell voltage crossed

the lower threshold limit set by μC.

0 → Cell 1 voltage is more

than Low Threshold limit

set

D0

1 → Cell 1 voltage is less

than Low Threshold limit

set

0 → Cell 2 voltage is more

than Low Threshold limit

set

D1

1 → Cell 2 voltage is less

than Low Threshold limit

set

0 → Cell 3 voltage is more

than Low Threshold limit

set

D2

1 → Cell 3 voltage is less

than Low Threshold limit

set

0 → Cell 4 voltage is more

than Low Threshold limit

set

0000_0000

POR_V5V

D3

0x02

cel_low_thsld_stat_reg

R

1 → Cell 4 voltage is less

than Low Threshold limit

set

0 → Cell 5 voltage is more

than Low Threshold limit

set

D4

1 → Cell 5 voltage is less

than Low Threshold limit

set

0 → Cell 6 voltage is more

than Low Threshold limit

set

D5

1 → Cell 6 voltage is less

than Low Threshold limit

set

0 → Cell 7 voltage is more

than Low Threshold limit

set

D6

1 → Cell 7 voltage is less

than Low Threshold limit

set

D7

Reserved

AS8506 – 54

ams Datasheet, Confidential:2013-Sep [1-00]

Device I nter face

Figure 50:

Cell Higher Threshold Status Register

Features and Bit

Description

POR

Value

Address

Register Name

SPI4 SPI3

Indicates if a cell voltage crossed

the lower threshold limit set by μC.

0 → Cell 1 voltage is less

than High Threshold limit

D0

D1

D2

D3

D4

D5

set

1 → Cell 1 voltage is more

than High Threshold limit

0 → Cell 2 voltage is less

than High Threshold limit

set

1 → Cell 2 voltage is more

than High Threshold limit

0 → Cell 3 voltage is less

than High Threshold limit

set

1 → Cell 3 voltage is more

than High Threshold limit

0 → Cell 4 voltage is less

than High Threshold limit

set

1 → Cell 4 voltage is more

than High Threshold limit

0000_0000

POR_V5V

0x03

cel_high_thsld_stat_reg

R

0 → Cell 5 voltage is less

than High Threshold limit

set

1 → Cell 5 voltage is more

than High Threshold limit

0 → Cell 6 voltage is less

than High Threshold limit

set

1 → Cell 6 voltage is more

than High Threshold limit

0 → Cell 7 voltage is less

than High Threshold limit

set

1 → Cell 7 voltage is more

than High Threshold limit

D6

D7

Reserved

ams Datasheet, Confidential:2013-Sep [1-00]

AS8506 – 55

D e v i c e I n t e r f a c e

Figure 51:

Cell Reference Status Register

POR

Value

Address Register Name

Features and Bit Description

SPI4 SPI3

Indicates which cell has reached the

reference value at least once. This

status is cleared when new reference is

selected.

0 → Cell 1 voltage is less than

reference voltage

1 → Cell 1 voltage is more

than reference voltage

D0

0 → Cell 2 voltage is less than

reference voltage

1 → Cell 2 voltage is more

than reference voltage

D1

0 → Cell 3 voltage is less than

reference voltage

1 → Cell 3 voltage is more

than reference voltage

D2

0000_0000

POR_V5V

0x04

cel_ref_stat_reg

0 → Cell 4 voltage is less than

R

reference voltage

D3

1 → Cell 4 voltage is more

than reference voltage

0 → Cell 5 voltage is less than

reference voltage

1 → Cell 5 voltage is more

than reference voltage

D4

0 → Cell 6 voltage is less than

reference voltage

1 → Cell 6 voltage is more

than reference voltage

D5

0 → Cell 7 voltage is less than

reference voltage

1 → Cell 7 voltage is more

than reference voltage

D6

D7

Reserved

AS8506 – 56

ams Datasheet, Confidential:2013-Sep [1-00]

Device I nter face

Figure 52:

Temperature Status Register

POR

Value

Address Register Name

Features and Bit Description

SPI4 SPI3

Indicates the status of temperature

monitors.

0 → Ambient temperature is

less than warning threshold

1 → Ambient temperature is

more than warning threshold

D0

0 → Internal temperature is

less than warning threshold

1 → Internal temperature is

more than warning threshold

D1

0 → Ambient temperature is

0000_0000

POR_V5V

0x05

temp_stat_reg

R

less than maximum

threshold

1 → Ambient temperature is

D2

more than maximum

threshold

0 → Internal temperature is

less than maximum

threshold

1 → Internal temperature is

D3

more than maximum

threshold

D7:D4

Reserved

ams Datasheet, Confidential:2013-Sep [1-00]

AS8506 – 57

D e v i c e I n t e r f a c e

Figure 53:

Zero Cross Status Register

POR

Value

Address Register Name

Features and Bit Description

SPI4 SPI3

Indicates which cell voltage has crossed

zero voltage and reached negative

during sudden loading condition. This

indirectly indicates the increasing status

of cell internal impedance.

0 → Cell 1 voltage is normal

1 → Cell 1 voltage has

crossed zero voltage towards

D0

negative direction

0 → Cell 2 voltage is normal

1 → Cell 2 voltage has

crossed zero voltage towards

D1

negative direction

0 → Cell 3 voltage is normal

1 → Cell 3 voltage has

crossed zero voltage towards

D2

negative direction

0x06

zero_crs_stat_reg

R

0 → Cell 4 voltage is less than

reference voltage

D3

1 → Cell 4 voltage is more

than reference voltage

0 → Cell 5 voltage is normal

1 → Cell 5 voltage has

crossed zero voltage towards

D4

negative direction

0 → Cell 6 voltage is normal

1 → Cell 6 voltage has

crossed zero voltage towards

D5

negative direction

0 → Cell 7 voltage is normal

1 → Cell 7 voltage has

crossed zero voltage towards

D6

negative direction

D7

Reserved

AS8506 – 58

ams Datasheet, Confidential:2013-Sep [1-00]

Device I nter face

Figure 54:

Cell1 Voltage LSB Register

POR

Value

Address Register Name

Features and Bit Description

SPI4 SPI3

Cell1 voltage measured. 8 least

significant bits of 12-bit ADC code of

Cell1

0000_0000

POR_V5V

0x07

cell1_volt_lsb_reg

R

D7:D0 Bit7 to Bit0 of ADC code

Figure 55:

Cell1 Voltage MSB Register

POR

Value

Address

Register Name

Features and Bit Description SPI4 SPI3

Cell1 voltage measured. 4 most

significant bits of 12-bit ADC code of

Cell1

0000_0000

POR_V5V

0x08

cell1_volt_msb_reg

R

D3:D0 Bit11 to Bit8 of ADC code

D7:D4 Reserved

Figure 56:

Cell2 Voltage LSB Register

POR

Value

Address

Register Name

Features and Bit Description

SPI4 SPI3

Cell2 voltage measured. 8 least

significant bits of 12-bit ADC code of

Cell2

0000_0000

POR_V5V

0x09

Cell2_volt_lsb_reg

R

D7:D0 Bit7 to Bit0 of ADC code

ams Datasheet, Confidential:2013-Sep [1-00]

AS8506 – 59

D e v i c e I n t e r f a c e

Figure 57:

Cell2 Voltage MSB Register

POR

Value

Address

Register Name

Features and Bit Description

SPI4 SPI3

Cell2 voltage measured. 4 most

significant bits of 12-bit ADC code of

Cell2

0000_0000

POR_V5V

0x0A

cell2_volt_msb_reg

R

D3:D0 Bit11 to Bit8 of ADC code

D7:D4 Reserved

Figure 58:

Cell3 Voltage LSB Register

POR

Value

Address

Register Name

Features and Bit Description

SPI4 SPI3

Cell3 voltage measured. 8 least

significant bits of 12-bit ADC code of

Cell3

0000_0000

POR_V5V

0x0B

cell3_volt_lsb_reg

R

D7:D0

Bit7 to Bit0 of ADC code

Figure 59:

Cell3 Voltage MSB Register

POR

Value

Address

Register Name

Features and Bit Description

SPI4 SPI3

Cell3 voltage measured. 4 most

significant bits of 12-bit ADC code of

Cell3

0000_0000

POR_V5V

0x0C

cell3_volt_msb_reg

R

D3:D0 Bit11 to Bit8 of ADC code

D7:D4 Reserved

Figure 60:

Cell4 Voltage LSB Register

POR

Value

Address

Register Name

Features and Bit Description

SPI4 SPI3

Cell4 voltage measured. 8 least

significant bits of 12-bit ADC code of

Cell4

0000_0000

POR_V5V

0x0D

cell4_volt_lsb_reg

R

D7:D0

Bit7 to Bit0 of ADC code

AS8506 – 60

ams Datasheet, Confidential:2013-Sep [1-00]

Device I nter face

Figure 61:

Cell4 Voltage MSB Register

POR

Value

Address

Register Name

Features and Bit Description

SPI4

SPI3

Cell4 voltage measured. 4 most

significant bits of 12-bit ADC code of

Cell4

0000_0000

POR_V5V

0x0E

cell4_volt_msb_reg

R

D3:D0 Bit11 to Bit8 of ADC code

D7:D4 Reserved

Figure 62:

Cell5 Voltage LSB Register

POR

Value

Address

Register Name

Features and Bit Description

SPI4 SPI3

Cell5 voltage measured. 8 least

significant bits of 12-bit ADC code of

Cell5

0000_0000

POR_V5V

0x0F

cell5_volt_lsb_reg

R

D7:D0

Bit7 to Bit0 of ADC code

Figure 63:

Cell5 Voltage MSB Register

POR

Value

Address

Register Name

Features and Bit Description

SPI4 SPI3

Cell5 voltage measured. 4 most

significant bits of 12-bit ADC code of

Cell5

0000_0000

POR_V5V

0x10

cell5_volt_msb_reg

R

D3:D0 Bit11 to Bit8 of ADC code

D7:D4 Reserved

Figure 64:

Cell6 Voltage LSB Register

POR

Value

Address

Register Name

Features and Bit Description

SPI4 SPI3

Cell6 voltage measured. 8 least

significant bits of 12-bit ADC code of

Cell6

0000_0000

POR_V5V

0x11

cell6_volt_lsb_reg

R

D7:D0

Bit7 to Bit0 of ADC code

ams Datasheet, Confidential:2013-Sep [1-00]

AS8506 – 61

D e v i c e I n t e r f a c e

Figure 65:

Cell6 Voltage MSB Register

POR

Value

Address

Register Name

Features and Bit Description

SPI4 SPI3

Cell6 voltage measured. 4 most

significant bits of 12-bit ADC code of

Cell6

0000_0000

POR_V5V

0x12

cell6_volt_msb_reg

R

D3:D0 Bit11 to Bit8 of ADC code

D7:D4 Reserved

Figure 66:

Cell7 Voltage LSB Register

POR

Value

Address

Register Name

Features and Bit Description

SPI4 SPI3

Cell7 voltage measured. 8 least

significant bits of 12-bit ADC code of

Cell7

0000_0000

POR_V5V

0x13

cell7_volt_lsb_reg

R

D7:D0

Bit7 to Bit0 of ADC code

Figure 67:

Cell7 Voltage MSB Register

POR

Value

Address

Register Name

Features and Bit Description

SPI4 SPI3

Cell7 voltage measured. 4 most

significant bits of 12-bit ADC code of

Cell7

0000_0000

POR_V5V

0x14

cell7_volt_msb_reg

R

D3:D0 Bit11 to Bit8 of ADC code

D7:D4 Reserved

Figure 68:

Temperature Input1 LSB Register

POR

Value

Address

Register Name

Features and Bit Description

SPI4 SPI3

Temperature sensor input1 measured.

8 least significant bits of 12-bit ADC

code of temperature input1.

0000_0000

POR_V5V

0x15

temp_in1_lsb_reg

R

D7:D0

Bit7 to Bit0 of ADC code

AS8506 – 62

ams Datasheet, Confidential:2013-Sep [1-00]

Device I nter face

Figure 69:

Temperature Input1 MSB Register

POR

Value

Address

Register Name

Features and Bit Description

SPI4 SPI3

Temperature sensor input1

measured. 4 most significant bits of

12-bit ADC code of temperature

input1.

0000_0000

POR_V5V

0x16

temp_in1_msb_reg

R

D3:D0 Bit11 to Bit8 of ADC code

D7:D4 Reserved

Figure 70:

Temperature Input2 LSB Register

POR

Value

Address

Register Name

Features and Bit Description

SPI4 SPI3

Temperature sensor input2 measured.

8 least significant bits of 12-bit ADC

code of temperature input1.

0000_0000

POR_V5V

0x17

temp_in2_lsb_reg

R

D7:D0

Bit7 to Bit0 of ADC code

Figure 71:

Temperature Input2 MSB Register

POR

Value

Address

Register Name

Features and Bit Description

SPI4 SPI3

Temperature sensor input2 measured.

4 most significant bits of 12-bit ADC

code of temperature input2.

0000_0000

POR_V5V

0x18

temp_in2_msb_reg

R

D3:D0 Bit11 to Bit8 of ADC code

D7:D4 Reserved

ams Datasheet, Confidential:2013-Sep [1-00]

AS8506 – 63

D e v i c e I n t e r f a c e

Figure 72:

SPI3 Status Register

POR

Value

Address Register Name

Features and Bit Description

SPI4 SPI3

This register has status of the latest SPI3

operation.

0 → No CRC error.

D0

D1

1 → CRC error for data from

Master to Slave

0 → No CRC error.

1 → CRC error for data from

Slave to Master

0000_0000

POR_V5V

0x19

spi3_sts_reg

R

0 → Start address allocation

process write pass

1 → Start address allocation

process write fail

D2

D7:D3 Reserved

AS8506 – 64

ams Datasheet, Confidential:2013-Sep [1-00]

Device I nter face

Configuration and 3-Wire SPI Interface Related

Registers

Figure 73:

Device Address for Address Allocation Register

POR

Value

Address

Register Name

Features and Bit Description

SPI4 SPI3

The device address for address

allocation. In the address allocation

process the μC writes top device

address in this register. Address

“00000” is reserved as broadcast

address.

0000_0000

POR_VSUP

0x1A

dadd_for_allc_reg

R/W

D5:D0

D7:D6

Device address

Reserved

Figure 74:

Allocated Device Address Register

POR

Value

Address

Register Name

Features and Bit Description SPI4 SPI3

Final device address after address

allocation process is completed

0000_0000

POR_VSUP

0x1B

allcd_dev_add_reg

R

D5:D0

D7:D6

Device address

Reserved

Figure 75:

Device Configuration Setting Register

POR

Value

Address

Register Name

Features and Bit Description

SPI4 SPI3

Selects SPI3 frequency of operation.

00 → 5 KHz

01 → 20 KHz

0000_0000

POR_VSUP

0x1C

dev_cnfg_setg_reg

D1:D0

R/W

-

10 → 40 KHz

11 → Reserved

D7:D2

Reserved

ams Datasheet, Confidential:2013-Sep [1-00]

AS8506 – 65

D e v i c e I n t e r f a c e

Figure 76:

Temperature Threshold Setting Register

Register

Name

POR

Value

Address

Features and Bit Description

SPI4 SPI3

Sets over-temperature warning flag and

shutdown flag threshold.

D3:D0 Over temperature warning flag

threshold selection

Code Value Code Value Code Value

0000 3.165 0110 3.561 1100 3.957

0001 3.231 0111 3.627 1101 4.023

0010 3.297 1000 3.693 1110 4.089

0011 3.363 1001 3.759 1111 4.155

XXXX_

XXXX

POR_

VSUP

0100 3.429 1010 3.825

0101 3.495 1011 3.891

-

tflg_tshld_setg

_reg

0x1D

R/W

D7:D4 Over temperature shutdown flag

threshold selection

Code Value Code Value Code Value

0000 3.165 0110 3.561 1100 3.957

0001 3.231 0111 3.627 1101 4.023

0010 3.297 1000 3.693 1110 4.089

0011 3.363 1001 3.759 1111 4.155

0100 3.429 1010 3.825

0101 3.495 1011 3.891

-

AS8506 – 66

ams Datasheet, Confidential:2013-Sep [1-00]

Device I nter face

Figure 77:

Timer Control Register

POR

Value

Address Register Name

Features and Bit Description

SPI4 SPI3

000 → 25% duty cycle

001 → 15% duty cycle

010 → 20% duty cycle

011 → 30% duty cycle

100 → 35% duty cycle

D2:D0

101 → 40% duty cycle

110 → 45% duty cycle

111 → 50% duty cycle

00 → 1s time slot

01 → 8s time slot

0000_0000

POR_VSUP

D4:D3

0x1E

timer_cntl_reg

R/W

10 → 16s time slot

11 → 32s time slot

00 → 100 KHz

01 → 25 KHz

D6:D5

10 → 50 KHz

11 → 200 KHz

0 → 5 clock cycles for

comparator

1 → 15 clock cycles for

comparator

D7

Figure 78:

Reference DAC Code LSB Register

POR

Value

Address

Register Name

Features and Bit Description

SPI4 SPI3

Least Significant byte of 12-bit DAC

code for setting reference voltage.

0000_0000

POR_VSUP

0x1F

ref_dcod_lsb_reg

R/W

Bit7 to Bit0 of DAC

D7:D0

code

ams Datasheet, Confidential:2013-Sep [1-00]

AS8506 – 67

D e v i c e I n t e r f a c e

Figure 79:

Reference DAC Code MSB Register

POR

Value

Address

Register Name

Features and Bit Description

SPI4 SPI3

Most Significant byte of 12-bit DAC

code for setting reference voltage.

0000_0000

POR_VSUP

0x20

ref_dcod_msb_reg

Bit11 to Bit8 of DAC

R/W

D3:D0

code

D7:D4

Reserved

Figure 80:

Higher Limit DAC Code LSB Register

POR

Value

Address

Register Name

Features and Bit Description SPI4 SPI3

Least Significant byte of 12-bit DAC

code for setting high limit voltage.

0000_0000

POR_VSUP

0x21

hlmt_dcod_lsb_reg

R/W

Bit7 to Bit0 of DAC

code

D7:D0

Figure 81:

Higher Limit DAC Code MSB Register

POR

Value

Address

Register Name

Features and Bit Description SPI4 SPI3

Most Significant byte of 12-bit DAC

code for setting high limit voltage.

0000_0000

POR_VSUP

0x22

hlmt_dcod_msb_reg

Bit11 to Bit8 of DAC

code

R/W

D3:D0

D7:D4

Reserved

Figure 82:

Lower Limit DAC Code LSB Register

POR

Value

Address

Register Name

Features and Bit Description

SPI4 SPI3

Least Significant byte of 12-bit DAC

code for setting low limit voltage.

0000_0000

POR_VSUP

0x23

llmt_dcod_lsb_reg

R/W

Bit7 to Bit0 of DAC

D7:D0

code

AS8506 – 68

ams Datasheet, Confidential:2013-Sep [1-00]

Device I nter face

Figure 83:

Lower Limit DAC Code MSB Register

POR

Value

Address

Register Name

Features and Bit Description SPI4 SPI3

Most Significant byte of 12-bit DAC

code for setting low limit voltage.

0000_0000

POR_VSUP

0x24

llmt_dcod_msb_reg

Bit11 to Bit8 of DAC

code

R/W

D3:D0

D7:D4

Reserved

Figure 84:

Device Address and Broadcast Command SPI Operation Register

POR

Value

Address Register Name

Features and Bit Description

SPI4 SPI3

Device address/ broadcast command

register

If spi3_cmd_reg [D3-D1] =

001/010

Address of Device to be

accessed.

(000000 address is broadcast

address)

If spi3_cmd_reg [D3-D1] =

100

Broadcast communication

commands.

000000 → No operation

000001 → Timer control

register write

D5:D0

spop_dadd_bcmd

0000_0000

POR_V5V

0x25

_reg

000010 → Cell reference DAC

R/W

-

code write

000011 Cell lower limit DAC

code write

000100 → Cell higher limit

DAC code write

If spi3_cmd_reg [D3-D1] =

101

000000 → Data of register

wrop_data_reg is written to

address stored in

spop_reg_add_reg in all

devices.

Reserved

D7:D6 (accessible only in Master

mode)

ams Datasheet, Confidential:2013-Sep [1-00]

AS8506 – 69

D e v i c e I n t e r f a c e

Figure 85:

SPI Operation Register Address Register

POR

Value

Address

Register Name

Features and Bit Description

SPI4 SPI3

Address of register to be accessed

during 3-wire read/write operation in

the device selected in

spop_dadd_bcmd_reg

0000_0000

POR_V5V

0x26

spop_reg_add_reg

Address of Register to

D6:D0

R/W

-

be accessed (R/W)

Reserved

D7:D4

(accessible only in

Master mode)

Figure 86:

SPI Write Operation Data Register

POR

Value

Address

Register Name

Features and Bit Description

SPI4 SPI3

Data to be written in the register

addressed by spop_reg_add_reg of

device selected in

spop_dadd_bcmd_reg during SPI3

write operation.

0000_0000

POR_V5V

0x27

wrop_data_reg

R/W

-

Bit7 to Bit0 of accessed

register

(accessible only in

D7:D0

Master mode)

AS8506 – 70

ams Datasheet, Confidential:2013-Sep [1-00]

Device I nter face

Figure 87:

SPI3 Command Register

POR

Value

Address Register Name

Features and Bit Description

SPI4 SPI3

3-wire SPI command register. Register is

cleared once the SPI3 transaction is

done.

0 → No SPI3 operation

1 → Start SPI3 operation

corresponding to

D0

command code

000 → Reserved

001 → Slave register Read

010 → Slave register Write

011 → Start address

allocation process

0000_0000

POR_V5V

0x28

spi3_cmd_reg

R/W

-

D3:D1

D7:D4

100 → Broadcast

configuration command

101 → Broadcast Slave

register Write

110 → Reserved

111 → Reserved

Reserved

Figure 88:

SPI Read Operation Data Register

POR

Value

Address

Register Name

Features and Bit Description

SPI4 SPI3

Read data from the register

addressed by spop_reg_add_reg of

device selected in

spop_dadd_bcmd_reg during SPI3

read operation.

0000_0000

POR_VSUP

0x29

rdop_data_reg

R/W

Bit7 to Bit0 of accessed

register

(accessible only in

D7:D0

Master mode)

ams Datasheet, Confidential:2013-Sep [1-00]

AS8506 – 71

D e v i c e I n t e r f a c e

Figure 89:

Feature Selection Register 1

POR

Value

Address

Register Name

Features and Bit Description

SPI4 SPI3

Feature selection register1.

1 → Zero cross

D0

detection enable

Zero cross detection

filter setting

00 → 8μs

01 → 6μs

D2:D1

10 → 4μs

11 → 2μs

D3

D4

Reserved

1 → External resistor

divider enable

0000_0000

POR_VSUP

0x2A

feat_sel_reg_1

R/W

0 → Cell reference is

generated from DAC

1 → Cell reference is

supplied externally on

VREF_IN pin

D5

0 → Cell Lower/Higher

limit is generated from

DAC

D6

D7

1 → Cell Lower/Higher

limit is supplied

externally on CELL_THL

and CELL_THU pins

Reserved

AS8506 – 72

ams Datasheet, Confidential:2013-Sep [1-00]

Device I nter face

Figure 90:

Feature Selection Register 2

POR

Value

Address

Register Name

Features and Bit Description

SPI4 SPI3

Feature selection register2.

FD_OUT pad

configuration

10 → Optocoupler

driver

0000_0010

POR_V5V

0x2B

feat_sel_reg_2

D1:D0

D7:D2

R/W

-

11 → Normal Pad

Reserved

Note: Registers from address 0x2C to 0x2F are ‘Reserved’.

OTP Reflection Registers

Figure 91:

OTP Reflection Register 1

POR

Value

Address

Register Name

Features and Bit Description

SPI4 SPI3

OTP bits [0:7]

D7:D0

0000_0000

POR_V5V

0x30

otp_refln_reg_1

R

Chip ID [0:7]

Figure 92:

OTP Reflection Register 2

POR

Value

Address

Register Name

Features and Bit Description

SPI4 SPI3

OTP bits [8:15]

D7:D0

0000_0000

POR_V5V

0x31

otp_refln_reg_2

R

Chip ID [8:15]

ams Datasheet, Confidential:2013-Sep [1-00]

AS8506 – 73

D e v i c e I n t e r f a c e

Figure 93:

OTP Reflection Register 3

POR

Value

Address

Register Name

Features and Bit Description

SPI4 SPI3

OTP bits [16:23]

Chip ID [16:18], OTP bits

[19:23]

0000_0000

POR_V5V

0x32

otp_refln_reg_3

D7:D0

R

Figure 94:

OTP Reflection Register 4

POR

Value

Address

Register Name

Features and Bit Description

SPI4 SPI3

0000_0000

POR_V5V

0x33

otp_refln_reg_4

D7:D0

OTP bits [24:31]

R

Figure 95:

OTP Reflection Register 5

POR

Value

Address

Register Name

Features and Bit Description

SPI4 SPI3

0000_0000

POR_V5V

0x34

otp_refln_reg_5

D7:D0

OTP bits [32:39]

R

Figure 96:

OTP Reflection Register 6

POR

Value

Address

Register Name

Features and Bit Description

SPI4 SPI3

0000_0000

POR_V5V

0x35

otp_refln_reg_6

D7:D0

OTP bits [40:47]

R

AS8506 – 74

ams Datasheet, Confidential:2013-Sep [1-00]

Device I nter face

Figure 97:

OTP Reflection Register 7

POR

Value

Address

Register Name

Features and Bit Description

SPI4 SPI3

0000_0000

POR_V5V

0x36

otp_refln_reg_7

D7:D0

OTP bits [48:55]

R

Figure 98:

OTP Reflection Register 8

POR

Value

Address

Register Name

Features and Bit Description

SPI4 SPI3

0000_0000

POR_V5V

0x37

otp_refln_reg_8

D7:D0

OTP bits [56:63]

R

Note(s) and/or Footnote(s):

1. Registers from address 0x38 to 0x39 are ‘Reserved’.

2. Registers from address 0x3A to 0x4E are OTP and Test registers. These are for factory use.

ams Datasheet, Confidential:2013-Sep [1-00]

AS8506 – 75

A p p l i c a t i o n I n fo r m a t i o n

Application Information

Figure 99:

Application Schematic with Single Device

VSUP

40

39

38

37

36

35

34

33

32

100nF

31

2-5uF

TSECH

TSECL

VREF_H

TSECH

30

29

28

1

2

V5V

VREF_T

TSECL

REF_T

TL1

TL2

NTC

3

4

5

6

7

8

VCELL7

VCELL6

VCELL5

TEMP_IN1

27

26

25

24

TEMP_IN2

CELL_THL

R

1

R

1

THL

TH

U

AS8506

CELL_THU

CS

VCELL4

VCELL3

CS

R2

R3

Optional fixed

reference

SCLK

SCLK 23

VCELL2

SDI

22

21

SDI

VREF_T

9

VCELL1

C-GND

SDO

Note: Max current on REF_T is 900uA

including the Temperature sensors

SDO

10

RF

1

11

12

13

14

15

16

17

18

19

20

CS

VREF_IN

SCLK

SDI

SDO

WAKE

RF

2

Microcontroller

Note: Open drain on

BD

WAKE_IN pin in the µC

or Transistor as shown

above.

CVT_NOK

Passive balancing

TSECL TSECH

CLK

TRIG

R_Load

Supply from Stack

TSECH

100 mA load

TSECL

Optional factory setting for

Active balancing

AS8506 – 76

ams Datasheet, Confidential:2013-Sep [1-00]

Application I nform ation

Passive balance

Passive balance is to dissipate the energy from the cell with the

higher cell voltage to the reference value (average of the stack

e.g. max cell voltage in constant voltage charge phase or mean

cell voltage as genertaed by resitor divider).

Resistor value should be selected based on the cell chemistry

and voltage limits. Maximum current capability of internal

shuttle switch is 100mA. Internal resistance of the shuttle

switch typically is 5Ω..

Active balance

In the active balance device charge the cells which are lower

than the reference voltage. This is a method of charge transfer

from the stack to the cell.

Flyback converter is used for this charge transfer. Active

balancing mode need to be enabled by factory setting. It is not

available for the default ASSP.

Flyback Converter (with external Transformer)

The high-efficiency, high-voltage, DC-DC Flyback converter

delivers current of 100mA to the lithium ion cell when the

secondary side of the Flyback transformer is connected to the

cell terminals. This also gives the isolation between the primary

supply and the load cell. The Flyback converter is designed to

charge the lithium-ion battery cells during the balancing mode

of the IC. It consists of a PWM waveform generator with variable

duty cycle and a driver. This driver can drive an external

MOSFET, (or) the optocoupler, (or) an isolation device based on

the requirement. During the ON-state of the PWM waveform,

the primary side of the Flyback transformer conducts and stores

the energy. In the other phase the stored energy in the

secondary is transferred to the cell which will be connected to

the secondary side of the transformer. The converter always

works in discontinuous current mode (DCM).

The advantages of this type of control system can be

summarized as following:

• High-efficiency even at light load

• Intrinsically stable

• Simplicity

Figure 100:

External Components

Component

Transformer

Optocoupler

Manufacturer Part Number

Manufacturer

WURTH ELECTRONICS

AVAGO TECHNOLOGIES

WE-FLEX 749196111

ACPL-M72T-000E

ams Datasheet, Confidential:2013-Sep [1-00]

AS8506 – 77

A p p l i c a t i o n I n fo r m a t i o n

Figure 101:

Application with Opto-Coupler/ Isolation Device

VSUP2

40

39

38

37

36

35

34

33

32

31

V5V_U

VREF_H

30

29

28

TSECH2

TSECL2

1

TSECH

V5V

7

6

5

2

TSECL

REF_T

100nF

NTC

2-5uF

TU1

3

4

5

VCELL7

TEMP_IN1

VSUP1

AS8506

MLF 6x6

TU2

27

26

25

24

VCELL6

VCELL5

TEMP_IN2

CELL_THL

NTC

TU2

TU1

6

CELL_THU

CS

VCELL4

VCELL3

7

8

GND

(Exposed Pad)

SCLK

SDI

23

22

VCELL2

1

VSUP1

9

VCELL1

C-GND

SDO

10

21

Note: If slave has to drive

FD pin then SDI has to be

connected local ground

11

12

13

14

15

16

17

18

19

20

VSUP1

40

39

38

37

36

35

34

33

32

31

V5V

VREF_H

TSECH

TSECH1

TSECL1

30

29

28

1

2

V5V

100nF

TSECL

REF_T

2-5uF

7

6

5

TL1

TL2

3

VCELL7

TEMP_IN1

AS8506

MLF 6x6

NTC

27

26

25

24

4

5

6

7

VCELL6

VCELL5

TEMP_IN2

CELL_THL

TL2

TL1

CELL_THU

CS

VCELL4

VCELL3

CS

GND

(Exposed Pad)

SCLK

SDI

23

22

8

9

VCELL2

VCELL1

C-GND

SDI

1

SDO

10

21

SDO

11

12

13

14

15

16

17

18

19

20

CS

SCLK

SDI

SDO

WAKE

BD

Micro

controller

CVT_NOK

CLK

TRIG

Optional Factory Setting for Active Balancing

Note: Open drain on WAKE_IN

pin in the µC or Transistor as

shown above.

TSECH1

100 mA load

TSECL1

Supply from Stack

TSECH2

100 mA load

TSECL2

Non-inverting

FD_OUT2

Optocoupler/

isolation device

Converter

for active

balancing

100 V device

Caution: In the application it’s recommended to connect the AS8506 devices stacked first and connect the

battery stack from bottom to top in sequence to avoid any possible damage of the system. While removing

the battery pack its strictly recommended to remove the battery pack from the top. Removing the battery

pack from bottom will damage the system.

AS8506 – 78

ams Datasheet, Confidential:2013-Sep [1-00]

Application I nform ation

Figure 102:

Application Schematic

VSUP2

40

39

38

37

36

35

34

33

32

31

V5V_U

VREF_H

30

29

28

TSECH2

TSECL2

1

2

TSECH

V5V

7

6

5

TSECL

REF_T

100nF

2-5uF

TU1

AS8506

MLF 6x6

3

VSUP1

VCELL7

TEMP_IN1

TU2

NTC

TU2

27

26

25

24

4

5

6

7

VCELL6

VCELL5

NTC

TEMP_IN2

CELL_THL

TU1

CELL_THU

CS

VCELL4

VCELL3

GND

(Exposed Pad)

SCLK

SDI

23

22

8

9

VCELL2

1

V5V_U

VSUP1

VCELL1

C-GND

Note: If slave has to

drive FD pin then SDI

has to be connected

local ground

SDO

10

21

11

12

13

14

15

16

17

18

19

20

VSUP1

40

VREF_H

39

38

37

36

35

34

33

32

31

V5V

TSECH1

TSECL1

30

29

28

1

TSECH

V5V

100nF

2

3

4

5

TSECL

REF_T

2-5uF

7

6

5

TL1

TL2

AS8506

MLF 6x6

VCELL7

TEMP_IN1

NTC

27

26

25

24

VCELL6

VCELL5

TEMP_IN2

CELL_THL

TL2

TL1

6

CELL_THU

CS

VCELL4

VCELL3

CS

7

8

GND

SCLK

SDI

SCLK

SDI

23

22

VCELL2

(Exposed Pad)

9

VCELL1

C-GND

1

SDO

10

21

SDO

11

12

13

14

15

16

17

18

19

20

CS

SCLK

SDI

SDO

WAKE

Micro

Controller

BD

CVT_NOK

CLK

TRIG

Note: Open drain on

Optional Factory Setting for Active Balancing

WAKE_IN pin in the µC or

Transistor as shown

above.

TSECH1

Supply from Stack

100 mA load

TSECL1

TSECH2

100 mA load

TSECL2

100 V device

Converter

for active

balancing

Caution: In the application it’s recommended to connect the AS8506 devices stacked first and connect the

battery stack from bottom to top in sequence to avoid any possible damage of the system. While removing

the battery pack its strictly recommended to remove the battery pack from the top. Removing the battery

pack from bottom will damage the system.

ams Datasheet, Confidential:2013-Sep [1-00]

AS8506 – 79

A p p l i c a t i o n I n fo r m a t i o n

Figure 103:

Application with Opto-Coupler Device Stackable to Higher Numbers

12V / 5V

Stack n+1

Vcc / V Auxiliary

AS8506

Cellx of

stackn

Optocoupler

VCC

RL

Vb

Vo

Stack n

Stack

Ground

AS8506

100KHz

12V / 5V

Vcc / V Auxiliary

Cellx of

stack2

Optocoupler

VCC

RL

Vb

Vo

Stack2

Stack

Ground

AS8506

FDRIVE_OUT

Vcc

Cellx of

stack1

Stack1

AS8506

FDRIVE_OUT(100KHz

Stack

Ground

Caution:: In the application it’s recommended to connect the AS8506 devices stacked first and connect the

battery stack from bottom to top in sequence to avoid any possible damage of the system. While removing the

battery pack its strictly recommended to remove the battery pack from the top. Removing the battery pack

from bottom will damage the system.

AS8506 – 80

ams Datasheet, Confidential:2013-Sep [1-00]

Pack age Drawings & M ark ings

The AS8506 device is available in a 40-pin MLF (6x6) package.

Package Drawings & Markings

Figure 104:

AS8506 Package Drawings and Dimensions

AS8506

YYWWIZZ

(A)

Note: ‘A’ is for active balancing and default is Passive Balancing.

Symbol Min

Nom

0.90

0.02

0.65

0.20 REF

0.40

0.15

0.10

-

0.25

0.15

6.00 BSC

Max

1.00

0.05

1.00

Symbol Min

Nom

0.50 BSC

5.75 BSC

4.50

0.15

0.10

0.05

0.08

0.10

40

Max

A

A1

A2

A3

L

L1

L2

Θ

0.80

0

-

e

D1

E1

D2

E2

4.40

4.60

0.30

0.05

0º

0.50

0.25

0.15

14º

0.30

0.20

aaa

bbb

ccc

ddd

eee

fff

-

b

b1

D

0.20

0.10

E

N

ams Datasheet, Confidential:2013-Sep [1-00]

AS8506 – 81

P a c k a g e D r a w i n g s & M a r k i n g s

Note(s) and/or Footnote(s):

1. Dimensions and toleranceing conform to ASME Y14.5M. - 1994.

2. All dimensions are in millimeters (angles in degrees).

3. Bilateral coplanarity zone applies to the exposed pad as well as the terminal.

4. Radius on terminal is optional.

5. N is the number of terminals.

Figure 105:

AS8506 Packaging Code YYWWXZZ

YY

WW

I

ZZ

Last two digits of the year

Manufacturing week

Plant identifier

Assembly traceability code

AS8506 – 82

ams Datasheet, Confidential:2013-Sep [1-00]

Pack age Drawings & M ark ings

The AS8506C device is available in a 40-pin MLF (6x6) package.

Figure 106:

AS8506C Package Drawings and Dimensions

AS8506C

YYWWIZZ

(A)

Note: ‘A’ is for active balancing and default is Passive Balancing.

Symbol Min

Nom

0.90

0.02

0.65

0.20 REF

0.40

0.15

0.10

-

0.25

0.15

6.00 BSC

Max

1.00

0.05

1.00

Symbol Min

Nom

0.50 BSC

5.75 BSC

4.50

0.15

0.10

0.05

0.08

0.10

40

Max

A

A1

A2

A3

L

L1

L2

Θ

0.80

0

-

e

D1

E1

D2

E2

4.40

4.60

0.30

0.05

0º

0.50

0.25

0.15

14º

0.30

0.20

aaa

bbb

ccc

ddd

eee

fff

-

b

b1

D

0.20

0.10

E

N

ams Datasheet, Confidential:2013-Sep [1-00]

AS8506 – 83

P a c k a g e D r a w i n g s & M a r k i n g s

Note(s) and/or Footnote(s):

1. Dimensions and toleranceing conform to ASME Y14.5M. - 1994.

2. All dimensions are in millimeters (angles in degrees).

3. Bilateral coplanarity zone applies to the exposed pad as well as the terminal.

4. Radius on terminal is optional.

5. N is the number of terminals.

Figure 107:

AS8506C Packaging Code YYWWXZZ

YY

WW

I

ZZ

Last two digits of the year

Manufacturing week

Plant identifier

Assembly traceability code

AS8506 – 84

ams Datasheet, Confidential:2013-Sep [1-00]

RoHS Compliant & ams Green Statement

RoHS: The term RoHS compliant means that ams products fully

comply with current RoHS directives. Our semiconductor

products do not contain any chemicals for all 6 substance

categories, including the requirement that lead not exceed

0.1% by weight in homogeneous materials. Where designed to

be soldered at high temperatures, RoHS compliant products are

suitable for use in specified lead-free processes.

RoHS Compliant & ams Green

Statement

ams Green (RoHS compliant and no Sb/Br): ams Green

defines that in addition to RoHS compliance, our products are

free of Bromine (Br) and Antimony (Sb) based flame retardants

(Br or Sb do not exceed 0.1% by weight in homogeneous

material).

Important Information: The information provided in this

statement represents ams knowledge and belief as of the date

that it is provided. ams bases its knowledge and belief on

information provided by third parties, and makes no

representation or warranty as to the accuracy of such

information. Efforts are underway to better integrate

information from third parties. ams has taken and continues to

take reasonable steps to provide representative and accurate

information but may not have conducted destructive testing or

chemical analysis on incoming materials and chemicals. ams

and ams suppliers consider certain information to be

proprietary, and thus CAS numbers and other limited

information may not be available for release.

ams Datasheet, Confidential:2013-Sep [1-00]

AS8506 – 85

O r d e r i n g & C o n t a c t I n f o r m a t i o n

The devices are available as the standard products shown in

Ordering Information.

Ordering & Contact Information

Figure 108:

Ordering Information

Ordering Code

AS8506-BQFP

Description

Delivery Form

Tape and reel

Package

Reel Size

4000

Monitor and balancer IC

Monitor and Balancer IC

40-pin MLF (6x6)

40-Pin MLF (6x6)

AS8506-BQFM

Tape and Reel

1000

(1)

4000

AS8506C-BQFP

(1)

Monitor and Balancer IC

Tape and Reel

40-Pin MLF (6x6)

1000

AS8506C-BQFM

Note(s) and/or Footnote(s):

1. Non-automotive Version without AECQ 100 Qualification.

Buy our products or get free samples online at:

www.ams.com/ICdirect

Technical Support is available at:

www.ams.com/Technical-Support

For further information and requests, e-mail us at:

ams_sales@ams.com

For sales offices, distributors and representatives, please visit:

www.ams.com/contact

Headquarters

ams AG

Tobelbaderstrasse 30

8141 Unterpremstaetten

Austria, Europe

Tel: +43 (0) 3136 500 0

Website: www.ams.com

AS8506 – 86

ams Datasheet, Confidential:2013-Sep [1-00]

Copyrights & Disclaimer

Copyright ams AG, Tobelbader Strasse 30, 8141

Copyrights & Disclaimer

Unterpremstaetten, Austria-Europe. Trademarks Registered. All

rights reserved. The material herein may not be reproduced,

adapted, merged, translated, stored, or used without the prior

written consent of the copyright owner.

Devices sold by ams AG are covered by the warranty and patent

indemnification provisions appearing in its Term of Sale. ams

AG makes no warranty, express, statutory, implied, or by

description regarding the information set forth herein. ams AG

reserves the right to change specifications and prices at any

time and without notice. Therefore, prior to designing this

product into a system, it is necessary to check with ams AG for

current information. This product is intended for use in

commercial applications. Applications requiring extended

temperature range, unusual environmental requirements, or

high reliability applications, such as military, medical

life-support or life-sustaining equipment are specifically not

recommended without additional processing by ams AG for

each application. This Product is provided by ams “AS IS” and

any express or implied warranties, including, but not limited to

the implied warranties of merchantability and fitness for a

particular purpose are disclaimed.

ams AG shall not be liable to recipient or any third party for any

damages, including but not limited to personal injury, property

damage, loss of profits, loss of use, interruption of business or

indirect, special, incidental or consequential damages, of any

kind, in connection with or arising out of the furnishing,

performance or use of the technical data herein. No obligation

or liability to recipient or any third party shall arise or flow out

of ams AG rendering of technical or other services.

ams Datasheet, Confidential:2013-Sep [1-00]

AS8506 – 87

R e f e re n c e G u i d e

1

2

3

General Description

Key Benefits & Features

Applications

Reference Guide

Block Diagram

4

8

Pin Assignment

Absolute Maximum Ratings

10 Typical Operating Characteristics

11 Electrical Characteristics

11 Device Level Specifications

12 Low Dropout Regulator (5V Output LDO)

13 High-precision Bandgap Reference

13 Digital to Analog Converter

14 Analog to Digital Converter

14 Pre-Regulator

15 PWM Driver

16 PWM Oscillator

16 Oscillator for Digital Circuit

17 External Temperature Thresholds

18 Ron of the Shuttle Switches (Internal Switch for

Charging/Discharging)

18 Over-Temperature Measurement

19 Weak Cell Detection (Voltage Comparator)

19 Power on Voltage Detection

20 Electrical Characteristics for Digital Inputs and Outputs

22 Detailed Description

22 Voltage Regulator (LDO_5V)

22 High Precision Bandgap (HPBG)

22 External Temperature Monitor and Measurement

23 Internal Temperature Monitor

23 PWM Generator

23 RC Oscillator

23 DAC for the Reference Generation

24 SAR ADC

24 Pre-Regulator

24 Cell Threshold

24 Weak Cell Detection

24 External Resister Divider Control

25 PORs on Different Supplies

26 AS8506 System Operation

28 Functional State Diagram

29 Operating Modes

29 NORMAL Mode

29 Diagnosis Phase

30 Balance Phase

30 Sleep Mode

30 Wait Mode

31 Wake Mode

32 Wake-up Event

33 Trigger Event

35 Balancing Algorithm

36 Initialization Sequence

AS8506 – 88

ams Datasheet, Confidential:2013-Sep [1-00]

Reference Guide

38 Device Interface

38 Serial Peripheral Interface

39 SPI Write Operation

41 SPI Read Operation

43 Address Allocation Process

46 Communication to Slaves

46 Broadcast Communication

47 Communication with Individual Slave

47 Write operation.

48 Read operation.

49 SPI Timing Diagrams

50 SPI Protocol

51 System Timings

52 Register Space Description

52 Status Registers

65 Configuration and 3-Wire SPI Interface

Related Registers

73 OTP Reflection Registers

76 Application Information

77 Passive balance

77 Active balance

77 Flyback Converter (with external Transformer)

81 Package Drawings & Markings

85 RoHS Compliant & ams Green Statement

86 Ordering & Contact Information

87 Copyrights & Disclaimer

ams Datasheet, Confidential:2013-Sep [1-00]

AS8506 – 89


型号：	AS8506
厂家：	AMS(艾迈斯)
描述：	Battery Cell Monitor and Balancer IC 电池组电池监视器和平衡IC 电池监视器
文件：	总89页 (文件大小：921K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AS8506 [AMSCO]

相关型号：

AS8506-BQFM

AS8506-BQFP

AS8506C-BQFM

AS8506C-BQFP

AS8510

AS8510-ASSM

AS8510-ASSP

AS8510_10

AS8515

AS8515-ZMFM

AS8515-ZMFP

AS8520