NSD2101-DQFS [AMSCO]
Piezo Motor Driver ASIC for SQL-RV Series Reduced Voltage SQUIGGLE RV and UTAF Motors; 压电电机驱动器ASIC的SQL -RV系列降压SQUIGGLE RV和UTAF汽车
| 型号： | NSD2101-DQFS |
| 厂家： | 
AMS(艾迈斯) |
| 描述： | Piezo Motor Driver ASIC for SQL-RV Series Reduced Voltage SQUIGGLE RV and UTAF Motors |
| 文件： | 总23页 (文件大小：1594K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Datasheet
NSD-2101
Piezo Motor Driver ASIC for SQL-RV Series
Reduced Voltage SQUIGGLE® RV and UTAF™ Motors
1 General Description
In combination with the SQUIGGLE® RV or UTAF, the NSD-2101
provides the industry’s smallest piezo motor drive solution with direct
battery drive; no boost circuit required.
2 Key Features
Industry’s smallest piezo motor drive solution with direct battery
drive
- Wide input supply voltage: 2.3 to 5.5 VDC
- 1.8 x 1.8 mm 16-ball WL-CSP or 4 x 4 mm 16-pin QFN
(minimum order quantities for QFN apply)
The NSD-2101 is a dedicated piezo motor driver ASIC capable of
driving a SQL-RV Series Reduced Voltage SQUIGGLE® RV motor
or UTAF motor from a single 2.3 to 5.5 VDC supply. The motor can
be controlled using a standard I²C interface.
Low power consumption:
- Proprietary design optimizes power usage
- Hard power-down mode for lowest power consumptio
- Idle mode via software for reduced powewhile preserving
frequency calibration
The NSD-2101 uses proprietary control technology to dynamically
adjust motor drive frequency to maintain optimal motor performance
and minimal power consumption over wide temperature ranges and
operating conditions. A built-in oscillator eliminates the need for an
external master clock.
Proprietary frequency tracking controls maxmizes motor
performance over a range of oping ad environmental
condis
uilt-in oscillator; no externl ocor oscillator required
I²C interface for dect serial interface to microprocessor
On-chip registers for sring driver instructions
3 Applications
The D-211 is ideal for SQL-RV-1.8 SQUIGGLE® RV
piezoeleric motor driver and UTAF piezoelectric motor driver.
Figure 1. NSD-2101 Functional Block Diagram
C2
VDD
VDDP
2.3V - 5.5V
+
-
VCC
LDO
Bandp
Startup
C1
Reces
Power Save
XPD
Connection to
SQUIGGLE® RV
Motor
Connection to
UTAF motor
Fruency
Trackig &
Control
P1-1
P1-1
VCO
P1-2
P2-1
P2-2
P1-2
P2-1
PPTRIM
1 x MLA
Squiggle
Motor Driver
DA
SCL
ADR
Control
P2-2
I²C Interface &
Registers
Test
VSS
TM
VSSP
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Revision 0.6
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NSD-2101
Datasheet - Contents
Contents
1 General Description ..................................................................................................................................................................
2 Key Features.............................................................................................................................................................................
3 Applications...............................................................................................................................................................................
4 Pin Assignments .......................................................................................................................................................................
4.1 Pin Descriptions....................................................................................................................................................................................
5 Absolute Maximum Ratings ......................................................................................................................................................
6 Electrical Characteristics...........................................................................................................................................................
6.1 DC/AC Characteristics for Digital Inputs and Outputs........................................................................................................................
7 Detailed Description................................................................................................................................................................
7.1 Output Drivers ..................................................................................................................................................................................
7.2 Power Dissipation Control .................................................................................................................................................................
7.3 Frequency Tracking.........................................................................................................................................................................
7.4 I²C.....................................................................................................................................................................................................
1
1
1
3
3
4
5
6
8
9
9
7.5 Register Map ................................................................................................................................................................................ 10
7.6 Control Register........................................................................................................................................................................... 11
7.7 Period Counter ............................................................................................................................................................................. 11
7.8 Pulse Counter........................................................................................................................................................................ 12
7.9 Pulse Width Control..................................................................................................................................................................... 12
7.10 Phase Shift .................................................................................................................................................................................... 12
7.11 Period Offset........................................................................................................................................................................... 13
7.12 Hybrid Speed Register ........................................................................................................................................................ 13
8 Application Information ..................................................................................................................................................... 14
8.1 Integration with SQL-RV-1.8 SQUGGE Motor............................................................................................................................... 15
8.2 Integration with UTAF Motors.......................................................................................................................................... 17
8.3 Integration with Other Motors ................................................................................................................................................... 17
9 Package Drawings and Markings ...................................................................................................................................... 18
10 Ordering Information........................................................................................................................................................... 21
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Revision 0.6
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NSD-2101
Datasheet - Pin Assignments
4 Pin Assignments
Figure 2. Pin Assignments (Top View)
1
2
3
4
16
15
14
13
A
B
VDD
VSSP
VDDP
P2-2
TM
12
11
10
9
VDDP
VDDP
1
2
3
4
VSS
VCC
SCL
VSSP
ADR
SDA
VDDP
TM
P2-1
P1-2
1-1
XPD
NSD-2101
SDA
SCL
VSSP
VSSP
C
D
XPD
5
6
7
8
1.8 x 1.8 mm 16-ball WL-CSP
4 x 4 mm 16-pin QFN
4.1 Pin Descriptions
Table 1. Pin Descriptions
Pin Name
TM
Pin Number
Pin Type
Digital input
Analog I/
Chacter
Description
Test mode selection input; connected to VSS
Shut down input, low active
I²C data IO
1
2
Input
XPD
SDA
3
Input / Output
Input
Digitainput / Digital
output pen drain
I²C clock
SCL
4
Address input for I²C
Internal LV Power Supply
Signal Ground Analog
Power Supply
ADR
5
al input
Input
VCC
6
Power
GND
VSS
7
VDD
Power
VSSP
VSSP
VDDP
P
2-2
9
Supply pad
Power Ground Drivers
Power Supply Driver
GND
10
11
12
13
14
15
16
Power
Half Bridge Phase2 inverted
Half Bridge Phase2
P2-1
Analog I/O
Output
Half Bridge Phase1 inverted
Half Bridge Phase1
P1-2
P1-1
Note: SDA (Data IO) and SCL (Data clock) constitute an I²C interface. Both have open drain outputs.
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Revision 0.6
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NSD-2101
Datasheet - Absolute Maximum Ratings
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of
the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 5 is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Min
Typ
Max
Units
Comments
Electrical Parameters
VVDD
Voltage at supply pin
-0.3
-0.3
-0.3
-0.3
0
7
7
V
V
VVDDP
VVCC
VVSSP
VVSS
VLV
Voltage at supply pin for drivers
Voltage at low voltage supply pin
Voltage at VSSP
5.0
0.3
0
V
Internal LV supply (VCC)
GND reference for drivers
GND referenpotential
V
Voltage at VSS
V
Voltage at ADR, SDA, SCL, XPD, TM
Input current (latchup immunity)
-0.3
-100
7
V
Iscr
100
mA
NormJESD78
Electrostatic Discharge
NrmML 883 E method 3015.
Human body model: R=1.5k, C=100pF,
measured and qualified only in QFN16
package.
Electrostatic discharge
ESD
±1
kV
Continuous Power Dissipation
Ptot
Total power dissipation
Thermal resistance QFN16 4x4mm
1
W
Rthja
9.7
-40
33
36.3
KW
Multi-Layer JEDEC board
Temperature Ranges and Storage Conditions
Tstrg
Storage temperature
Package body temperature
Humidity non-condnsing
50
260
85
ºC
ºC
%
Norm: IPC/JEDEC J-STD-020.
The reflow peak soldering temperature
(body temperature) specified is in
accordance with IPC/JEDEC J-STD-020
“Moisture/Reflow Sensitivity Classification
for Non-Hermetic Solid State Surface Mount
Devices”.
Tbody
The lead finish for Pb-free leaded packages
is “Matte Tin” (100% Sn).
5
WL-CSP
QFN
1
3
Represents a maximum floor life time of unlimited
Represents a maximum floor life time of 168h
MSL
Moisture Sensitivity Leve
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Revision 0.6
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NSD-2101
Datasheet - Electrical Characteristics
6 Electrical Characteristics
Table 3. Operating Conditions
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Supply voltage
(VDD/VDDP rise time is between 10µs and
10ms. Above 5.0V only half bridge mode
should be used)
VVDD
Voltage at VDD
2.3
5.5
V
Driver supply
(VDD/VDDP rise time is between 10µs and
10ms. Above 5.0V only half bridge mode
should be used)
VVDDP
Voltage at VDDP
2.3
5.5
V
VVCC
VVSSP
VVSS
VLV
Voltage at VCC
Voltage at VSSP
Internal LV supply
GND reference for drivers
GND reference
1.9
-0.1
0
3.0
0.1
0
V
V
Voltage at VSS
V
Voltage at SDA,SCL, XPD, TM
Junction temperature
-0.3
-30
5.5
125
V
Tjunc
ºC
Total power dissipation eeds to less
than 1W to keep junction emperture in
speed range
Ptot
Total power dissipation
1
5
W
XPD=LOmp=27ºC;
No actiy on I²C
IPd
Power-down current consumption
µA
ISb
Stand-by current consumption
Operating current consumption
XPD=HIGH, pulse generation is stoppe
Without output switching cu
3.5
10
mA
mA
INom
PD=IGH, temp=27ºC, O powered
don, no digital activity; mode et by I²C,
frequency trimmng pserved
IIdle
Idle mode current consumption
1.0
mA
6.1 DC/AC Characteristics for Dital Inputs antputs
Table 4. CMOS Input: XPD, ADR, CLK
Symbol
VIH
Parameter
Conditions
Min
1.2
Typ
Max
VDD
0.3
Units
V
High level input voltage
Low level input voltage
Input leakage current
Capacitive Lad
VIL
VSS
-1
V
ILEAK
CIN
+1
µA
pF
15
Table 5. CMOS I²C Interface: SDASCL
Symbol
VIH
arameter
Conditions
Min
1.2
Typ
Max
VDD
0.3
Units
V
High evel input voltage
Lw level input voltage
Input leakage current
VIL
VSS
-1
V
ILEAK
+1
µA
Depending on external pull-up
resistor
High level output voltage
VVDD -0.5
VVDD
VOH
V
L
CL
Low level output voltage
Capacitive load: SDA, SCL
At 3mA output current
VSS+0.4
50
V
pF
k
RPU
External pull-up resistor: SDA, SCL
As defined by I²C spec
1.2
6.0
7.1
Maximum clock frequency to write
data
I²C write frequency
SCL
400
kHz
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Revision 0.6
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NSD-2101
Datasheet - Detailed Description
7 Detailed Description
Figure 1 shows the main building blocks of the system:
Supply input
LDO and bypass capacitors
I²C interface
Registers
Oscillator
Frequency tracking
Full bridge driver
The input voltage is supplied directly to the full bridge driver. With a full bridge drive, each piezo element sees twice the input voltage (2 VDD).
However, the average input voltage to the piezo can be regulated by the ASIC between VDD and 2 x VDD. This average voltage, which an be
set via I²C along with the duty cycle (or pulse width) of the drive signal, determines the speed of the motor. The result being at lower speeds, the
motor consumes less power.
I²C registers also define the initial switching frequency of the motor, which can be adjusted from 50 kHz to 200 kHz baed othe type of motor
being driven. Other registers control motor direction and the number of pulses the motor is active (correlating to ance raveled). The XPD
input enables a stand-by mode.
7.1 Output Drivers
The output drivers operate rail to rail and are capable of driving capacitiad up to 60nF. The copt is based on two full bridges per motor.
The reduced voltage Squiggle motor consists of 2 plates per phase and 2 hases. In power dowmode e output drivers are pulled to ground.
The same applies when the motor is off.
Table 6. Characteristics for Output Drivers
Symbol
ftr
Parameter
Conditios
Min
Typ
Max
Units
CLOAD 50nF,
VD=2.3V
Rise/fall time from 0.23V to 2.07and
vice versa
0.08
0.8
µs
ftf
Load capacitance
CLOAD
Ilim
10
60
nF
Current limit for driver outputs2
1000
1600
mA
Drive frequency range3
fDFR
fDC
tDT
50
1
200
50
9
kHz
%
Switching frequency duty cycle
VCO clock cycles4
Dead time (additiona
2
4
fPS
Phase sh
-160
+90
±3
deg
deg
Phase sht error
fPSE
1. Measured at 10% to 90% ominimum VDD=2.3V. Maximum with 4 clocks dead-time.
2. Current limit is vad fr fl bridge and half bridge configuration. Due to the dynamic behavior of the output driver the maximum current
limit can not be reaced under all conditions. Device can only be used for direct motor drive.
3. For this frequncy range, frequency tracking is implemented.
4. Error of dead tme imaximum +1 VCO clock cycle.
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Revision 0.6
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NSD-2101
Datasheet - Detailed Description
Figure 3. Motor Drive Concept (SQUIGGLE® RV Motor)
Motor Drive Concept
P1-1
VIN
VIN
VIN
0V
VIN
P1-2
0V
P1-1
or
P2-1
P1-2
or
P2-2
Phase Shift
+90 is Forward
-90 is Reverse
P2-1 VIN
0V
P2-2
VIN
Full Bridge Drive
SQUIGGLE® RV Motor
0V
Figure 4. Motor Drive Concept (UTAF Motor)
Motor DrivConcept
P1
VIN
VIN
VIN
0V
VIN
P1-2
0V
P1-1
or
P2-1
P2
or
2-2
Phase Shift
+72 is Forward
-108 is Reverse
P2-1 VIN
0V
P2-2 VIN
Full Bridge Drive
UTAF Motor
0V
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Revision 0.6
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NSD-2101
Datasheet - Detailed Description
The rise and fall time definition is shown in Figure 5. Time between crossing 10% and 90% threshold of minimum VDD is measured, 10% to 90%
for rise time and 90% to 10% for fall time. A full bridge switching cycle will take longer.
Figure 5. Rise / Fall Time Definition
V(half-bridge)
VDD = 2.3V
90%
10%
0V
t
tr
tf
In Figure 6, the effect of current limit in the output drivers is shown. Each half-bridge output can deliver 1000mA.
Figure 6. Output Driver Current Limit
I(half-bridge)
Ilim = 1600mA
typ 1300mA
Ilim = 1000mA
0mA
t
7.2 Power Dissipation Control
Following techniques are implemented to kep system and on-chip powedissipation low.
Selectable half bridge mode depending oput supply voltage
Selective charge control for full bridge mode
Hybrid Control for full bridge mode
Table 7. Power Dissipation Control
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Selectable half-bridge
HBthr
HBthf
Rising Threshold
Wen half-bridge mode is enabled then the output driver
will switch to half-bridge drive depending on input supply
voltage. Typical system power dissipation can be reduced
down to 25% of standard full-bridge drive. When VDD is
higher than 5.0V only half bridge mode should be used to
avoid exceeding max total power dissipation of 1W. A
typical hysteresis of 100mV is implemented to increase
immunity against supply disturbances.
4.3
4.5
4.7
V
Falling Thresold
4.2
30
4.4
4.6
50
75
V
%
%
Selective chare conrol for full-bridge
CCPDS
ower dissipation saving
Hybrid Control for full-bridge
By adding an additional state in the full bridge switching
scheme the power dissipation can be reduced due to the
fact that the effective voltage on the capacitor is reduced.
With this technique the power dissipation can be reduced
by switching periodically from full-bridge to half-bridge
mode. Power saving in comparison to standard full-bridge
drive is mainly depending on duty cycle between half-
bridge and full-bridge. Hybrid Control is also used for
speed control.
PSPDS
Power dissipation saving
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NSD-2101
Datasheet - Detailed Description
7.3 Frequency Tracking
Based on the motor type, an initial drive signal period must be written to the NSD-2101. The period is specified in units of 0.04 µsec (based on
the nominal internal VCO frequency of 25 MHz). In the case of an SQL-RV-1.8 motor, the period may be 148 (94h) to generate a drive frequency
of ~168.9 kHz.
The NSD-2101 is able to then optimize the drive frequency by, on command, sweeping over a range of frequencies, centered at the specified
period, and settling on the frequency at which the best motor performance was detected. Alternatively, the NSD-2101 may be commanded to
incrementally step the frequency in the direction of increasing motor performance (changing the step direction when the performance drops).
In either case, the NSD-2101 adjusts the frequency by adjusting the VCO trimming, rather than the period count. This affords much higher
resolution than is possible by changing the period count.
Whether sweep mode or incremental (see ‘Control Register’ in Table 8 on page 10), the calibration does not start until a pulse count has been
loaded into registers 02h and 03h.
A sweep calibration is typically performed following a power-up. The sweep calibration offers the greatest range of frequencies. Incremntal
calibration offers the best frequency resolution and can be performed periodically as the motor is being used.
7.4 I²C
The I²C interface is used to control the NSD-2101 and set the value of several registers. These registers will define the diretion and duration of
the output driver signals, the duty cycle, phase shift and average voltage to the motor.
Start/Stop Condition: A HIGH to LOW transition on the SDA line while SCis HIGH the start condition for the bs. A LOW to HIGH
transition on the SDA line while SCL is HIGH is the stop condition.
Every byte put on the SDA line must be 8-bits long. Each byte must be d by an acknowledge bit. Data is transferred with the most
significant bit (MSB) first.
Data transfer with acknowledge is obligatory. The acknowledge-related clok pulse is generatd by he master. The receiver must pull down the
SDA line during the acknowledge clock pulse.
The NSD-2101 is a slave device on the bus. There are two differenaccess modes:
- Byte write
- Page write
The device can be addressed using 7-bit addreing. he first 6 bits are fixd. The ast bit can be set via package pin.
Figure 7. 7-Bit Device Address
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Revision 0.6
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NSD-2101
Datasheet - Detailed Description
7.5 Register Map
Table 8 lists out the registers which can be addressed over the I²C interface.
Table 8. I²C Registers
Data Byte
Description
Address
Note
MSB
X
LSB
P2
X
Control Register
Period count
00h
01h
PS[1] PS[0]
CN[1] CN[0] P1
X
X
X
X
X
X
P: Period count MSB;
D: Direction bit;
DS: Dead time selection bits: ‘00’=2,
‘01’=4, ‘10’=6 and ‘11’=8 VCO cocks.
Pulse count (high byte)
02h
P
D
DS[1] DS[0]
X
X
X
Pulse count (low byte)
Pulse width
03h
04h
05h
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Phase shift
CN needbe 0to enable Period
offset. Period fset is not used when
eithr Incrmental or Sweep Frequency
Tracking is active.
IDL: Sets idle mode;
B: Enable half bridge operation if VDD
> HBth;
Period offset
06h
IDL
HB
HYB
DT
X
X
X
HYB: Enable hybrid speed control;
DT: Enable signal for increased dead
time;
Selection bits(DS[1:0]) are only valid
when DT=1;
Selection bits should not be changed
when the output driver is active.
Hybrid Speed register: 0… half bridge;
128…full bridge operation; linear
transition for values in between;
Default: 128. Values from 1 to 127 are
used for linear speed control.
Hybrid speed
07h
10h
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Reserved register used for device test
only, not accessible during normal
operation.
Reserved register
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NSD-2101
Datasheet - Detailed Description
7.6 Control Register
The control register is used to trigger frequency calibration as well as to select and enable the drive phases.
Table 9. Control Register
Control Flag Mask
1000 0000
Abbr
PS[1]
PS[0]
Default
Description
Reserved (leave 0)
0
1
Phase Select for sensing: PS[1] PS[0]:
00=None
01=Phase1
0100 0000
0010 0000
1
10=Phase2
11= Both Phases
Reserved (leave 0)
0001 0000
0000 1000
0
0
Calibrate Now: CN[1] CN[0]:
00=None
01=Incremental
10=Sweep
CN[1]
CN[0]
0000 0100
0
11=reserved
Enable Phase1
Enable Phase2
0000 0010
0000 0001
P1
P2
1
1
7.7 Period Counter
The period counter is used to define the switching frequency of the motor. The pulse period igenered by dividing the internal VCO clock
frequency by the given period counter value. The MSB in the high bte of the pulse counter (p) iused as the MSB for the period counter.
At 25MHz clock a decimal period counter value of 125 ivean output frequency of 200 Hz. period counter value of 126 results in a switching
frequency of 198.41 kHz. This is equal to a maximum fquency step of 1.59 kHz. he frequency resolution gets better for lower switching
frequencies assuming a fixed VCO clock frequenc
Table 10 lists out few examples to define peiod unter and output switchinfrequency relationship. The values are given for 25MHz typical
VCO clock frequency. The switch frequency is n as:
fD = 25MHz / periunter value
(EQ 1)
Table 10. Period Counter Values
Period Counter Value
0 0111 1101
Typ
Unit
kHz
kHz
kHz
kHz
kHz
kHz
kHz
200.00
198.41
172.4
0 0111 1110
0 1001 0001
0 1010 0110
150.60
149.70
50.10
0 1010 011
1 111 011
1 1110100
50.00
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NSD-2101
Datasheet - Detailed Description
7.8 Pulse Counter
The pulse counter sets the number of pulses the motor should be active. When a new value is written to the pulse count register an internal
counter is started to count generated output pulses. Writing all zeros to the pulse counter stops the motor even if the previous set counter value
is not completed, all outputs pulled to ground. The same is valid for power down mode. Bit 6 in the pulse counter (d) is used to set the direction
of motor motion.
Table 11. Pulse Counter Values
Pulse Counter Value
XXXX X000 0000 0000
XXXX X100 0000 0000
XXXX X111 1111 1111
Typ
0
Unit
Conditions
pulses
pulses
pulses
Motor is off, driver outputs are low
1024
2047
Maximum possible number of pulses
7.9 Pulse Width Control
A register is used to define the duty cycle of the driver output signal. The default value for this register set during power up r power down (XPD
= LOW) is equal to 00h. In this case the default duty cycle of 50% is generated. The resulting duty cycle and resolution singsteps is
depending on the master clock frequency and the switching frequency of the driver output. Table 12 provides an example f25MHz master
clock and 200kHz driver frequency. The value of the duty cycle register should not exceed 50.4% of the period cunter lue. Pulse Width
Modulation is used for speed control when motor is operating in half bridge moe.
Table 12. Pulse Width Register Values
Pulse Width Register
0000 0000
Typ
49.6/50.4
0.8
Unit
%
Conditions
default
0000 0001
%
0000 1101
10.4
%
0001 1011
1.6
0011 0101
42.4
%
0011 1110
49.6
%
0011 1111
50.4
%
If operating in half bridge mode, the pulse width can be used tadjuspeed. At 50% the motor will operate at its maximum speed. To reduce the
speed, the pulse width may be reduced. However, elow ~15%, there may not be enough energy in the signal to move the motor.
7.10 Phase Shift
A register is used to define the phase shift betweetwo phases of the driver output signal. The default value for this register set during power
up or power down (XPD = LOW) is equal o 00h. In this case the default phase shift of 90° is generated. The resulting phase shift and resolution
of single steps is depending on the mster lock frequency and the switching frequency of the driver output. Table 13 provides an example for
25MHz master clock and 200kHz driver equency. The value of the phase shift register should not exceed 50.4% of the period counter value.
Negative phase shift values arachieved by changing the direction bit: -160deg = 20deg and inverted direction bit.
Table 13. Phase ShiRegisr Values
Phase Shift Rgister
000 000
Typ
90.5
Unit
deg
deg
deg
deg
deg
deg
Conditions
Default (Normal for both SQL and UTAF)
0000 0001
2.88
0000 1101
37.44
40.32
89.28
92.16
0000 1110
0001 1111
0010 0000
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NSD-2101
Datasheet - Detailed Description
7.11 Period Offset
Period Offset register defines the offset which is added to the period counter to shift the switching frequency. It also provides some additional
control bits.
This offset is only activated when frequency tracking is stopped. An offset has been provided as some types of motors operate better at slightly
below mechanical resonance. Table 14 provides an example for 25MHz master clock and 200kHz nominal driver frequency. Period offset is only
supposed to lower drive frequency.
Table 14. Period Offset Register Values
Period Offset Register
0000 0000
Typ
0
Unit
%
Conditions
Default, no change of drive frequency
0000 0001
-0.8
-1.6
-5.6
0
%
0000 0010
%
0000 0111
%
Maximum period offset
Idle mode enaed
1000 0000
%
0100 0000
0
%
Half bridge mode nabled
Hybrid sd conrol enabled
Increased dead time enabled
0010 0000
0
%
0001 0000
0
%
Idle mode reduces power consumption while preserving the most recency calibration. To rher reduce power, the XPD pin must be
pulled to ground.
7.12 Hybrid Speed Register
The hybrid speed register allows the average voltage as seen by the motor to be set fVDD to 2 x VDD. This provides a power efficient
method of reducing the speed of the motor. The value f the egister can vary fro0 (habrdge) to 128 (full bridge). The average voltage can
be calculated in the following manner.
AVG VDD + (RegisterVae * VDD / 128)
(EQ 2)
Where: VDD is the supply voltage
Table 15. Hybrid Speed Register Values
Hybrid Speed Register
0000 0000
Typ
0
Unit
%
Conditions
VDD (half bridge)
0010 0000
2
%
VDD + 0.25 * VDD
VDD + 0.75 * VDD
VDD + VDD (full bridge)
0110 0000
75
%
1000 0000
100
%
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NSD-2101
Datasheet - Application Information
8 Application Information
The NSD-2101 is designed to drive one SQL-RV-1.8 SQUIGGLE® RV motor or one UTAF motor. Recommended external components are as
follows:
Table 16. External Components
Component
Manufacturer
Part Number
WxLxH [mm]
C1 470nF Cap 4.0V
TAIYO-YUDEN
AMK063BJ474MP-F
(0201)
For UTAF only
C2 4.7µF Cap 6.3V
C2 10µF Cap 6.3V
PANASONIC
PANASONIC
ECJ-0EB0J475M
ECJ-1VB0J106M
(max 35nF) (0402)1
Full load (0603)1
1. A maximum ESR of 100m at motor switching frequency is assumed. The series resistance of the input supply (VDD, VDDP) should
maximum 50m and capable of delivering at least 1W of power. ESR information for C2 is still missing.
New Scale offers a convenient MC-33DB-RV evaluation board which includes the components, along with input and mtor cnnectors, to take
full advantage of the NSD-2101 ASIC.
The XPD input can be used to place the ASIC in stand-by mode for minimal cuent consmption when the motor is not moving. Alternatively, the
designer can implement an external switch to power off the ASIC completely whethe motor is not moving: e SQIGGLE® RV motor holds its
position with the power off.
Figure 8. NSD-2101
SQL-RV or UTF
6
15
14
13
2.3V – 5.5V
C2
TM
VDDP
VDDP
2
12
11
XPD
NSD-2101
SDA
SCL
VSSP
VSSP
+
-
3
4
10
9
5
6
7
8
C1
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NSD-2101
Datasheet - Application Information
8.1 Integration with SQL-RV-1.8 SQUIGGLE Motor
Communicating with the NSD-2101.
The address of the NSD-2101 is 54h (unless the ADR pin is held high in which case the address would be 55h).
I²C supports 8 data bits and 1 acknowledge bit for a total of 9 bits or clock cycles per byte. When attempting to select a device, the first byte
transmitted by the master contains the device address. This address occupies the upper 7 data bits with data bit 0 having a value of zero which
indicates a write operation (theNSD-2101 does not support a read operation).
Therefore when addressing the NSD-2101 the actual value sent by the host during the first 8 SCL (clock) cycles would be A8h (or AAh if ADR pin
high). If the NSD-2101 is powered and connected properly to the SDA/SCL lines then on the 9th clock pulse, the NSD-2101 will hold the data line
low (acknowledge).
The second byte transmitted must be the number of the register to be written. For example, if attempting to send a pulse count, then the regst
value would be 2.
The third and any subsequent bytes are the values to be written to the specified register and, if more than three bytes are being sent, th
following registers in increasing order.
If the following data were sent over the I²C bus:
A80277FF
Then registers 02 and 03 of the NSD-2101 would receive values of 77h and FFh respectively.
Supporting More Than Two NSD-2101s on a Single I²C Bus.
To support more than two NSD-2101 drivers on the same I²C bus, the R pin may be used as a chip select. That is, one driver is held low by
the host and on all others it is held high. The host then sends commande diver with ADR heow. This of course requires that there be a
separate chip select line for each NSD-2101.
How Motion is Generated.
Motion is initiated by directing the NSD-2101 to issue pulses to the motor. In the case e SQL-RV-1.8 motor, to get any motion, the interval
between the start of each pulse (i.e. the period) must be witn some tolerance (±2Hz) of the resonant frequency of the motor (e.g. ~172
kHz).
The closer this period is to the resonant frequecy of he motor, the more speed/psh force is available. Keep in mind that this is a friction drive
which means the amount of motion is depedesupply voltage, applied fquency vs. actual resonant frequency and the load on the motor.
From an idle state, a minimum of 5 to 10 pulses are required to build ugh orbital motion (of the nut about the screw) to advance the screw.
The minimum pulse count varies with load (higher load, more pulses) awhether or not motion is against or with the load (more against, fewer
with).
As shown in Figure 3, the drive signal is composed two waveforms (square waves) and each waveform may be full or half bridge. In the case
of the SQL motor, these waveforms are 90 degrees out f phase (in keeping with the geometry of the nut). The phase that leads determines the
direction of motion (direction is set by the host uinbit from the pulse count register).
By default the pulse width of each waveform is 50the period (i.e. if register 04 is zero; e.g. pulse with would be 2.9 µsec if the period is 5.8
µsec). But you can adjust the pulse widtas onmeans to regulate speed. The shorter the pulse width (below 50% of the period), the less time
the piezo has to change shape and tus thamount of engagement between nut and screw is reduced.
The default phase shift between wvefors is 25% of the period (i.e. if register 05 is zero). This can also be adjusted and would be for other
motor geometries but in the cae of thSQL-RV-1.8; 25% is recommended.
A second means to djust seed is to set the ratio of full bridge pulses to half bridge pulses (Hybrid Speed Control). This effectively sets the
average voltage seen bthe motor. If the supply is 3V then in full bridge the motor “sees” 6V. But if the hybrid speed is 33% then, on an average,
the motor sees 4.
Note: Duto dissipation limitations of the driver chip, the maximum supply voltage for full bridge operation is 4.5V (9V to the piezo). Although
driver supports a supply of up to 5.5V, at any level above 4.5V, the output needs to be half bridge. Within that limitation the hybrid
speed control is more power efficient than the pulse width control method of the regulating speed since the amount of switching into the
capacitive load of the motor is being reduced.
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NSD-2101
Datasheet - Application Information
Directing the NSD-2101.
The basic command that is sent to the NSD-2101 is the pulse count (with direction). When a non-zero value is written to registers 02 and 03 by
the host microprocessor, the NSD-2101 begins generating pulses on the output pins at the interval defined by the period register (01). For each
pulse, the specified pulse count is decremented. Pulse generation continues until the pulse count reaches zero or the host writes a zero to
registers 02 and 03. See Register Map (page 10) and Pulse Counter (page 12).
Since the pulse counter is limited to 2047 (11 bits), the maximum duration of motion is the 2047 x period. If the period were 5.8 µsec (172.4 kHz),
then the duration would be ~11.8 msec. Therefore to produce continuous motion, the pulse count must be reloaded by the host before the
previous pulse count expires (in this case - at least every 11.7 msec - but every 10 msec would provide more margin allowing for variations in
motor frequency and overhead in the host processer handling I²C traffic).
Given the nominal 25MHz power-up frequency of the VCO within the NSD-2101, the motor period is specified in units of 40 nsec. Therefore the
period value necessary to generate a frequency of 172.4 kHz is 145 (or 91 hexadecimal).
As indicated in the previous section, to generate motion, the pulse period must be very near the interval of the mechanical resonant frequency
the motor. However, for a given motor type, manufacturing tolerances, ambient temperature and mounting have an affect on this resont
frequency. To cancel out these affects, the NSD-2101 supports a frequency tuning (or calibration) feature.
Therefore on power-up, it is recommended that after an appropriate default period count for the given motor type is loaded, frequency sweep
calibration is performed followed by an incremental calibration. See Frequency Tracking (page 9). The sweep needs to bperfmed only once
(for a given power cycle); After that, the incremental calibration will keep the motor in tune.
Note: While performing the frequency calibration, the NSD-2101 is adjustinthe triming of its internal VCO to aximize the performance of
the motor (not the period count itself).
Furthermore, it is recommended that frequency calibration be performa direction that is against the load (typically forward). The reason is
that, depending on the mass being moved (i.e. the inertia), there may btter (intermittent contabetween the load and the screw) when
moving with the load. This chatter can affect the calibration.
Starting a frequency sweep calibration (assuming an SQ-RV-8 motor):
Reg
00
Value (hex)
Comment
6B
91
77
FF
Enables sweep calration using both motor phses
172.4 kHz
01
02
Fwd, DT=11*, Upper 3 bits of pulse et
Lower 8 bits of pulse count s
03
Actual data stream: A8006B9177FF (the host shoulwait at least 10 msec after start)
Starting a frequency incremental calibration:
Reg
00
Value (hex)
Commen
67
91
77
F
Enbles ic. calibration using both motor phases
12.4 kHz
01
02
Fwd, DT=11*, Upper 3 bits of pulse count set
Lower 8 bits of pulse count set
03
Actual dstream: A800679177FF (the host should wait at least 10 msec after start)
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NSD-2101
Datasheet - Application Information
Normal operation:
Reg
Value (hex)
Comment
00
63
Using both motor phases, no calibration enabled.
Actual data stream: A80063
Moving Fwd (full count):
Reg
02
Value (hex) Comment
77
FF
Fwd, DT=11*, Upper 3 bits of pulse count set
03
Lower 8 bits of pulse count set
Actual data stream: A80277FF
Moving Rev (full count):
Reg
02
Value (hex) Comment
37
FF
Rev, DT=11*, Upper 3 bits of pulse count set
03
Lower 8 bits of pulse count set
Actual data stream: A80237FF
Stopping the Motor:
Reg
02
Value (hex) Comment
00
00
Direction & T* n't matter. Zero upper coubits
03
Zero lower count bits
Actual data stream: A8020000
Note: *DT (dead time): The time interval between tswitching of the low side and the high side of a full bridge waveform. The best power
efficiency is achieved when using the maxmum ead time (i.e. DT=11). This minimizes the power consumed while having no affect on
speed/push force.
8.2 Integration with UTAF Motor
New Scale Technologies works closely th OEM customers to provide assistance in using the UTAF motor with the NSD-2101. Please contact
New Scale for assistance.
8.3 Integration with Other Motors
The NSD-2101 was desiged for use with New Scale Technologies’ SQUIGGLE and UTAF motors. Support for other piezo motors may be
provided, for a f, to qalified OEMs. Contact austriamicrosystems or New Scale Technologies to discuss your application.
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Revision 0.6
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NSD-2101
Datasheet - Package Drawings and Markings
9 Package Drawings and Markings
The devices are available in a 16-pin QFN (4x4mm) package or 16-ball WL-CSP (1.8x1.8mm) package.
Figure 9. 16-pin QFN (4x4mm) Package Drawings and Dimensions
Symbol
Min
0.80
0
Nom
0.90
Max
1.00
0.05
A
A1
A3
L
0.02
0.20 REF
0.40
0.35
0
0.45
0.15
0.35
L1
b
-
0.25
0.30
D
4.00 BSC
4.00 BSC
0.65 BSC
2.70
E
e
D2
E2
aaa
bbb
ccc
ddd
eee
fff
2.60
2.80
2.80
-
2.60
2.70
-
-
-
-
-
-
0.15
0.10
0.10
0.05
0.08
0.10
N
16
Notes:
1. Dimensions & tolerancing conform to ASME Y14.5M-1994.
. All dimensions are in millimeters, angles are in degrees.
3. Dimension b applies to metalized terminal and is measured between 0.25mm and 0.30mm from terminal tip.
Dimension L1 represents terminal full back from package edge up to 0.15mm is acceptable.
4. Coplanarity applies to the exposed heat slug as well as the terminal.
5. Radius on terminal is optional.
6. N is the total number of terminals.
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NSD-2101
Datasheet - Package Drawings and Markings
Figure 10. 16-ball WL-CSP (1.8x1.8mm) Package Drawings and Dimensions
Figure 11. Recommended PCB Layout (Top View)
C2
VDD
S
P2-2
P2-1
P1-2
P1-1
C1
Denotes via to ground plane
Note: For better thermal resistance, add as many vias to ground plane as possible.
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NSD-2101
Datasheet - Revision History
Revision History
Revision
0.1
Date
Owner
Description
Initial revision
15 Jan, 2010
24 Feb, 2010
Updated Key Features (page 1), Pin Assignments (page 3)
0.2
rweber (NST) /
pmo (AMS)
Corrected WL-CSP diagram (see Figure 2), added “Top View” to figure
title for clarity (see Figure 11)
0.3
16 Jun, 2010
Updated Table 3 with current consumption info, Corrected info in
Figure 4 and Table 10, Added Section 8.1, 8.2 and 8.3.
0.4
0.5
0.6
26 Aug, 2010
01 Jul, 2011
30 Aug, 2011
Updated Ordering Information (page 21)
rph
Updated sections Absolute Maximum Ratings (page 4), Packag
Drawings and Markings (page 18), Ordering Information (page 2).
Note: Typos may not be explicitly mentioned under revision history.
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NSD-2101
Datasheet - Ordering Information
10 Ordering Information
The devices are available as the standard products shown in Table 17.
Table 17. Ordering Information
Ordering Code
NSD2101-DQFS
NSD2101-DWLS
Description
Delivery Form
Tape & Reel
Tape & Reel
Package
QFN-16 (4x4mm)
Ultrasonic piezo motor driver IC, output for one SQL-RV
series reduced voltage SQUIGGLE® RV
WL-CSP-16 (1.8x1.8mm)
Note: All products are RoHS compliant and austriamicrosystems green.
Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect
Technical Support is available at http://www.austriamicrosystems.com/Technical-Support
For further information and requests, please contact us mailto:sales@austriamicrosystems.com
or find your local distributor at http://www.austriamicrosystems.com/distributor
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NSD-2101
Datasheet - Copyrights
Copyrights
Copyright © 1997-2011, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®.
All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of
the copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale.
austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding
the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at
any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for
current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature rang,
unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment ae
specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100
parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location.
The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicosystms AG shall not
be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss profis, loss of use,
interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arisg out of the furnishing,
performance or use of the technical data herein. No obligation or liability to reciient or any third party shall arise olow out of
austriamicrosystems AG rendering of technical or other services.
Contact Information
Headquarters
austriamicrosystems AG
Tobelbaderstrasse 30
A-8141 Unterpremstaetten, Austria
Tel: +43 (0) 3136 500 0
Fax: +43 (0) 3136 525 01
For Sales Offices, Distributors and Representatives, pleae visit:
http://www.austriamicrosystems.com/contact
Contact Information
Nw Scale echologies, Inc.
121 ictor Heights Parkway
Victor, NY 14564
Tel: +1 585 924 4450
Fax: +1 585 924 4468
sales@newscaletech.com
www.newscaletech.com
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Revision 0.6
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相关型号：
NSD2101-DWLS
Piezo Motor Driver ASIC for SQL-RV Series Reduced Voltage SQUIGGLE RV and UTAF Motors
AMSCO
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