AS29LV800T-80TI_技术文档

Advanced Information

October 2000

AS29LV800

®

3V 1M×8/512K×16 CMOS Flash EEPROM

• Low power consumption

Features

- 200 nA typical automatic sleep mode current

• Organization: 1M×8/512K×16

- 200 nA typical standby current

- 10 mA typical read current

• JEDEC standard software, packages and pinouts

- 48-pin TSOP

- 44-pin SO

• Detection of program/erase cycle completion

- DQ7 DATA polling

- DQ6 toggle bit

- DQ2 toggle bit

- RY/BY output

• Erase suspend/resume

• Sector architecture

- One 16K; two 8K; one 32K; and fifteen 64K byte sectors

- One 8K; two 4K; one 16K; and fifteen 32K word sectors

- Boot code sector architecture—T (top) or B (bottom)

- Erase any combination of sectors or full chip

• Single 2.7-3.6V power supply for read/write operations

• Sector protection

• High speed 80/90/120 ns address access time

• Automated on-chip programming algorithm

- Automatically programs/verifies data at specified ad-

dress

- Supports reading data from or programming data to a

sector not being erased

• Automated on-chip erase algorithm

- Automatically preprograms/erases chip or specified

sectors

• Hardware RESET pin

- Resets internal state machine to read mode

• Low V write lock-out below 1.5V

CC

• 10 year data retention at 150C

• 100,000 write/erase cycle endurance

Logic block diagram

Pin arrangement

48-pin TSOP

44-pin SO

Sector protect/

erase voltage

switches

RY/BY

DQ0–DQ15

V

CC

RY/BY

A18

A17

A7

1

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

RESET

WE

V

SS

2

Erase voltage

generator

Input/output

buffers

3

A8

RESET

4

A9

A6

5

A10

Program/erase

control

A5

6

A11

WE

A4

7

A12

BYTE

A3

8

A13

Program voltage

generator

Command

register

A2

9

A14

A1

10

11

12

13

14

15

16

17

18

19

20

21

22

A15

AS29LV800

A0

A16

STB

Chip enable

Output enable

Data latch

CE

BYTE

V_SS

CE

OE

A-1

V_SS

OE

Logic

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

V_CC

DQ0

DQ8

DQ1

DQ9

DQ2

DQ10

DQ3

DQ11

Y decoder

Y gating

STB

V

detector

Timer

CC

X decoder

Cell matrix

A0–A18

Selection guide

29LV800-80 29LV800-90 29LV800-120

Unit

Maximum access time

t

80

30

90

35

120

50

ns

AA

Maximum chip enable access time

Maximum output enable access time

t

CE

OE

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ALLIANCE SEMICONDUCTOR

1

October 2000

AS29LV800

®

Functional description

The AS29LV800 is an 8 megabit, 3.0 volt only Flash memory organized as 1 Megabyte of 8 bits/512Kbytes of 16 bits each.

For flexible erase and program capability, the 8 megabits of data is divided into nineteen sectors: one 16K, two 8K, one 32K,

and fifteen 64k byte sectors; or one 8K, two 4K, one 16K, and fifteen 32K word sectors. The ×8 data appears on DQ0–DQ7;

the ×16 data appears on DQ0–DQ15. The AS29LV800 is offered in JEDEC standard 48-pin TSOP and 44-pin SOP

packages. This device is designed to be programmed and erased in-system with a single 3.0V V supply. The device can

CC

also be reprogrammed in standard EPROM programmers.

The AS29LV800 offers access times of 80/90/120 ns, allowing 0-wait state operation of high speed microprocessors. To

eliminate bus contention the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls.

Word mode (×16 output) is selected by BYTE = high and Byte mode (×8 output) is selected by BYTE = low.

The AS29LV800 is fully compatible with the JEDEC single power supply Flash standard. Write commands to the command

register using standard microprocessor write timings. An internal state-machine uses register contents to control the erase

and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase

operations. Read data from the device in the same manner as other Flash or EPROM devices. Use the program command

sequence to invoke the automated on-chip programming algorithm that automatically times the program pulse widths and

verifies proper cell margin. Use the erase command sequence to invoke the automated on-chip erase algorithm that

preprograms the sector if it is not already programmed before executing the erase operation, times the erase pulse widths,

and verifies proper cell margin.

Boot sector architecture enables the system to boot from either the top (AS29LV800T) or the bottom (AS29LV800B) sector.

Sector erase architecture allows specified sectors of memory to be erased and reprogrammed without altering data in other

sectors. A sector typically erases and verifies within 1.0 seconds. Hardware sector protection disables both program and

erase operations in all or any combination of the nineteen sectors. The device provides true background erase with Erase

Suspend, which puts erase operations on hold to either read data from or program data to a sector that is not being erased.

The chip erase command will automatically erase all unprotected sectors.

A factory shipped AS29LV800 is fully erased (all bits = 1). The programming operation sets bits to 0. Data is programmed

into the array one byte at a time in any sequence and across sector boundaries. A sector must be erased to change bits from 0

to 1. Erase returns all bytes in a sector to the erased state (all bits = 1). Each sector is erased individually with no effect on

other sectors.

The device features single 3.0V power supply operation for read, write, and erase functions. Internally generated and

regulated voltages are provided for the program and erase operations. A low V detector automatically inhibits write

CC

operations during power transtitions. The RY/BY pin, DATA polling of DQ7, or toggle bit (DQ6) may be used to detect end

of program or erase operations. The device automatically resets to the read mode after program/erase operations are

completed. DQ2 indicates which sectors are being erased.

The AS29LV800 resists accidental erasure or spurious programming signals resulting from power transitions. Control

register architecture permits alteration of memory contents only after successful completion of specific command sequences.

During power up, the device is set to read mode with all program/erase commands disabled when V is less than V

CC

LKO

(lockout voltage). The command registers are not affected by noise pulses of less than 5 ns on OE, CE, or WE. To initiate

write commands, CE and WE must be logical zero and OE a logical one.

When the device’s hardware RESET pin is driven low, any program/erase operation in progress is terminated and the internal

state machine is reset to read mode. If the RESET pin is tied to the system reset circuitry and a system reset occurs during an

automated on-chip program/erase algorithm, data in address locations being operated on may become corrupted and requires

rewriting. Resetting the device enables the system’s microprocessor to read boot-up firmware from the Flash memory.

The AS29LV800 uses Fowler-Nordheim tunnelling to electrically erase all bits within a sector simultaneously. Bytes are

programmed one at a time using EPROM programming mechanism of hot electron injection.

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AS29LV800

October 2000

®

Operating modes

Mode

CE

L

OE

L

WE

A0

L

A1

A6

L

A9

RESET DQ

ID read MFR code

ID read device code

Read

H

L

V

H

Code

ID

L

H

L

H

A0

X

A1

X

A6

X

A9

X

D

OUT

Standby

H

L

X

H

X

High Z

Output disable

Write

H

X

L

A0

L

A1

H

A6

L

A9

D

X

IN

Enable sector protect

Sector unprotect

L

V

Pulse/L

V

ID

L

H

Temporary sector

unprotect

X

V

X

ID

†

Verify sector protect

L

X

L

X

H

X

L

X

H

X

L

V

X

H

L

Code

ID

†

Verify sector unprotect

Hardware Reset

H

X

Code

High Z

L = Low (<V_IL) = logic 0; H = High (>V_IH) = logic 1; V_ID= 10.0 ± 1.0V; X = don’t care.

In ×16 mode, BYTE = V_IH. In ×8 mode, BYTE = V_ILwith DQ8-DQ14 in high Z and DQ15 = A-1.

^†Verification of sector protect/unprotect during A9 = V_ID.

Mode definitions

Item

Description

Selected by A9 = V (9.5V–10.5V), CE = OE = A1 = A6 = L, enabling outputs.

ID

ID MFR code,

device code

When A0 is low (V ) the output data = 52h, a unique Mfr. code for Alliance Semiconductor Flash

IL

products. When A0 is high (V ), D

represents the device code for the AS29LV800.

IH

OUT

Selected with CE = OE = L, WE = H. Data is valid in t

time after addresses are stable, t after CE is

CE

ACC

Read mode

Standby

low and t after OE is low.

OE

Selected with CE = H. Part is powered down, and I reduced to <1.0 µA when CE = V ± 0.3V =

CC

RESET. If activated during an automated on-chip algorithm, the device completes the operation before

entering standby.

Output disable Part remains powered up; but outputs disabled with OE pulled high.

Selected with CE = WE = L, OE = H. Accomplish all Flash erasure and programming through the

command register. Contents of command register serve as inputs to the internal state machine. Address

Write

latching occurs on the falling edge of WE or CE, whichever occurs later. Data latching occurs on the rising

edge WE or CE, whichever occurs first. Filters on WE prevent spurious noise events from appearing as

write commands.

Hardware protection circuitry implemented with external programming equipment causes the device to

disable program and erase operations for specified sectors. For in-system sector protection, refer to Sector

protect algorithm on page14.

Enable

sector protect

Disables sector protection for all sectors using external programming equipment. All sectors must be

protected prior to sector unprotection. For in-system sector unprotection, refer to Sector unprotect

algorithm on page 14.

Sector

unprotect

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October 2000

AS29LV800

®

Item

Description

Verifies write protection for sector. Sectors are protected from program/erase operations on commercial

programming equipment. Determine if sector protection exists in a system by writing the ID read

command sequence and reading location XXX02h, where address bits A12–18 select the defined sector

addresses. A logical 1 on DQ0 indicates a protected sector; a logical 0 indicates an unprotected sector.

Verify sector

protect/

unprotect

Temporarily disables sector protection for in-system data changes to protected sectors. Apply +10V to

RESET to activate temporary sector unprotect mode. During temporary sector unprotect mode, program

protected sectors by selecting the appropriate sector address. All protected sectors revert to protected state

on removal of +10V from RESET.

Temporary

sector

unprotect

Resets the interal state machine to read mode. If device is programming or erasing when RESET = L, data

may be corrupted.

RESET

Deep

power down

Hold RESET low to enter deep power down mode (<1 µA). Recovery time to start of first read cycle is

50ns.

Enabled automatically when addresses remain stable for 300ns. Typical current draw is 1 µA. Existing data

is available to the system during this mode. If an address is changed, automatic sleep mode is disabled and

new data is returned within standard access times.

Automatic

sleep mode

Flexible sector architecture

Bottom boot sector architecture (AS29LV800B)

Top boot sector architecture (AS29LV800T)

Size

Sector

0

×8

×16

(Kbytes)

×8

×16

(Kbytes)

64

32

8

00000h–03FFFh 00000h–01FFFh

04000h–05FFFh 02000h–02FFFh

06000h–07FFFh 03000h–03FFFh

08000h–0FFFFh 04000h–07FFFh

10000h–1FFFFh 08000h–0FFFFh

20000h–2FFFFh 10000h–17FFFh

30000h–3FFFFh 18000h–1FFFFh

40000h–4FFFFh 20000h–27FFFh

50000h–5FFFFh 28000h–2FFFFh

60000h–6FFFFh 30000h–37FFFh

70000h–7FFFFh 38000h–3FFFFh

80000h–8FFFFh 40000h–47FFFh

90000h–9FFFFh 48000h–4FFFFh

A0000h–AFFFFh 50000h–57FFFh

B0000h–BFFFFh 58000h–5FFFFh

C0000h–CFFFFh 60000h–67FFFh

D0000h–DFFFFh 68000h–6FFFFh

E0000h–EFFFFh 70000h–77FFFh

F0000h–FFFFFh 78000h–7FFFFh

16

8

00000h–0FFFFh

10000h–1FFFFh

20000h–2FFFFh

30000h–3FFFFh

40000h–4FFFFh

50000h–5FFFFh

60000h–6FFFFh

70000h–7FFFFh

80000h–8FFFFh

90000h–9FFFFh

00000h–07FFFh

08000h–0FFFFh

10000h–17FFFh

18000h–1FFFFh

20000h–27FFFh

28000h–2FFFFh

30000h–37FFFh

38000h–3FFFFh

40000h–47FFFh

48000h–4FFFFh

1

2

8

3

32

64

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A0000h–AFFFFh 50000h–57FFFh

B0000h–BFFFFh 58000h–5FFFFh

C0000h–CFFFFh 60000h–67FFFh

D0000h–DFFFFh 68000h–6FFFFh

E0000h–EFFFFh

F0000h–F7FFFh

70000h–77FFFh

78000h–7BFFFh

F8000h–F9FFFh 7C000h–7CFFFh

FA000h–FBFFFh 7D000h–7DFFFh

FC000h–FFFFFh 7E000h–7FFFFh

8

16

In word mode, there are one 8K word, two 4K word, one 16K word, and fifteen 32K word sectors. Address range is A18–A-1 ifBYTE = V_IL; address range

is A18–A0 if BYTE = V_IH

.

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AS29LV800

October 2000

®

ID Sector address table

Bottom boot sector address

(AS29LV800B)

Top boot sector address

(AS29LV800T)

Secto

r

A18 A17 A16 A15 A14 A13 A12

A18

0

A17

0

A16 A15 A13 A12

A14

X

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

X

0

1

0

1

0

2

0

1

0

3

1

X

0

4

X

0

1

5

0

1

6

0

1

7

0

1

8

1

0

9

1

0

10

11

12

13

14

15

16

17

18

1

0

1

0

1

0

1

X

READ codes

Mode

A18–A12

A6

L

A1

L

A0

L

Code

52h

MFR code (Alliance Semiconductor)

X

×8 T boot

×8 B boot

×16 T boot

×16 B boot

L

H

DAh

L

5Bh

Device code

L

22DAh

225Bh

L

01h protected

00h unprotected

Sector protection

Sector address

L

H

L

Key: L =Low (<V_IL); H = High (>V_IH); X =Don’t care

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AS29LV800

®

Command format

Required

1st bus cycle

2nd bus cycle

3rd bus cycle

4th bus cycle

5th bus cycle

6th bus cycle

Command

sequence

bus write

cycles

Address

Data

F0h

Address

Data

Address

Data

Address

Data

Address Data Address

Data

Read

Address

Read

Data

Reset/Read

1

3

XXXh

×16

×8

555h

2AAh

555h

Reset/

Read

Data

AAh

55h

F0h

90h

Read Address

AAAh

01h

Device code

22DAh (T)

225Bh (B)

×16

×8

555h

2AAh

555h

02h

Device code

DAh (T)

5Bh (B)

AAAh

×16

×8

555h

2AAh

555h

0052h

52h

00h

MFR code

Autoselect

ID Read

AAAh

3

XXX02h

Sector

protection

0001h = protected

0000h =

unprotected

×16

×8

555h

2AAh

555h

AAh

55h

90h

XXX04h

Sector

protection

0001h=protected

0000h=unprotected

AAAh

×16

×8

555h

AAAh

555

2AAh

555h

2AA

555

555h

AAAh

555

Program

Address

Program

Data

Program

4

3

AAh

55h

A0h

20h

×16

×8

Unlock

bypass

AAA

Unlock bypass

program

Program Program

2

XXX

A0h

90h

address

data

Unlock bypass reset

XXX

555h

XXX

2AAh

555h

2AAh

555h

00h

×16

555h

AAAh

555h

AAAh

555h

AAAh

555h

2AAh

555h

Chip

6

AAh

55h

80h

AAh

55h

10h

30h

Erase

×8

AAAh

555h

AAAh

×16

2AAh

Sector

Address

AAh

Erase

×8

AAAh

XXXh

AAAh

555h

Sector Erase Suspend

Sector Erase Resume

1

B0h

30h

1

2

3

4

5

6

Bus operations defined in "Mode definitions," on page 3.

Reading from and programming to non-erasing sectors allowed in Erase Suspend mode.

Address bits A11-A18 = X = Don’t Care for all address commands except where Program Address and Sector Address are required.

Data bits DQ15-DQ8 are don’t care for unlock and command cycles.

The Unlock Bypass command must be initiated before the Unlock Bypass Program command.

The Unlock Bypass Reset command returns the device to reading array data when it is in the unlock bypass mode.

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AS29LV800

October 2000

®

Command definitions

Item

Description

Initiate read or reset operations by writing the Read/Reset command sequence into the command

register. This allows the microprocessor to retrieve data from the memory. Device remains in read

mode until command register contents are altered.

Reset/Read

Device automatically powers up in read/reset state. This feature allows only reads, therefore

ensuring no spurious memory content alterations during power up.

AS29LV800 provides manufacturer and device codes in two ways. External PROM programmers

typically access the device codes by driving +10V on A9. AS29LV800 also contains an ID Read

command to read the device code with only +3V, since multiplexing +10V on address lines is

generally undesirable.

Initiate device ID read by writing the ID Read command sequence into the command register.

Follow with a read sequence from address XXX00h to return MFR code. Follow ID Read

command sequence with a read sequence from address XXX01h to return device code.

ID Read

To verify write protect status on sectors, read address XXX02h. Sector addresses A18–A12

produce a 1 on DQ0 for protected sector and a 0 for unprotected sector.

Exit from ID read mode with Read/Reset command sequence.

Holding RESET low for 500 ns resets the device, terminating any operation in progress; data

handled in the operation is corrupted. The internal state machine resets 20 µs after RESET is

driven low. RY/BY remains low until internal state machine resets. After RESET is set high, there

is a delay of 50 ns for the device to permit read operations.

Hardware Reset

Programming the AS29LV800 is a four bus cycle operation performed on a byte-by-byte or

word-by-word basis. Two unlock write cycles precede the Program Setup command and program

data write cycle. Upon execution of the program command, no additional CPU controls or

timings are necessary. Addresses are latched on the falling edge of CE or WE, whichever is last;

data is latched on the rising edge of CE or WE, whichever is first. The AS29LV800’s automated

on-chip program algorithm provides adequate internally-generated programming pulses and

verifies the programmed cell margin.

Check programming status by sampling data on theRY/BY pin, or either the DATA polling

(DQ7) or toggle bit (DQ6) at the program address location. The programming operation is

complete if DQ7 returns equivalent data, if DQ6 = no toggle, or if RY/BY pin = high.

Byte/word

Programming

The AS29LV800 ignores commands written during programming. A hardware reset occurring

during programming may corrupt the data at the programmed location.

AS29LV800 allows programming in any sequence, across any sector boundary. Changing data

from 0 to 1 requires an erase operation. Attempting to program data 0 to 1 results in either DQ5 =

1 (exceeded programming time limits); reading this data after a read/reset operation returns a 0.

When programming time limit is exceeded, DQ5 reads high, and DQ6 continues to toggle. In this

state, a Reset command returns the device to read mode.

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AS29LV800

®

Item

Description

The unlock bypass feature increases the speed at which the system programs bytes or words to

the device because it bypasses the first two unlock cycles of the standard program command

sequence.

To initiate the unlock bypass command sequence, two unlock cycles must be written, then

followed by a third cycle which has the unlock bypass command, 20h.

The device then begins the unlock bypass mode. In order to program in this mode, a two cycle

unlock bypass program sequence is required. The first cycle has the unlock bypass program

command, A0h. It is followed by a second cycle which has the program address and data. To

program additional data, the same sequence must be followed.

Unlock Bypass

Command Sequence

The unlock bypass mode has two valid commands, the Unlock Bypass Program command and

the Unlock Bypass Reset command. The only way the system can exit the unlock bypass mode is

by issuing the unlock bypass reset command sequence. This sequence involves two cycles. The

first cycle contains the data, 90h. The second cycle contains the data 00h. Addresses are don’t

care for both cycles. The device then returns to reading array data.

Chip erase requires six bus cycles: two unlock write cycles; a setup command, two additional

unlock write cycles; and finally the Chip Erase command.

Chip erase does not require logical 0s to be written prior to erasure. When the automated on-chip

erase algorithm is invoked with the Chip Erase command sequence, AS29LV800 automatically

programs and verifies the entire memory array for an all-zero pattern prior to erase. The 29LV800

returns to read mode upon completion of chip erase unless DQ5 is set high as a result of

exceeding time limit.

Chip Erase

Sector erase requires six bus cycles: two unlock write cycles, a setup command, two additional

unlock write cycles, and finally the Sector Erase command. Identify the sector to be erased by

addressing any location in the sector. The address is latched on the falling edge of WE; the

command, 30h is latched on the rising edge of WE. The sector erase operation begins after a

sector erase time-out.

To erase multiple sectors, write the Sector Erase command to each of the addresses of sectors to

erase after following the six bus cycle operation above. Timing between writes of additional

sectors must be less than the erase time-out period, or the AS29LV800 ignores the command and

erasure begins. During the time-out period any falling edge of WE resets the time-out. Any

command (other than Sector Erase or Erase Suspend) during time-out period resets the

AS29LV800 to read mode, and the device ignores the sector erase command string. Erase such

ignored sectors by restarting the Sector Erase command on the ignored sectors.

Sector Erase

The entire array need not be written with 0s prior to erasure. AS29LV800 writes 0s to the entire

sector prior to electrical erase; writing of 0s affects only selected sectors, leaving non-selected

sectors unaffected. AS29LV800 requires no CPU control or timing signals during sector erase

operations.

Automatic sector erase begins after sector erase time-out from the last rising edge of WE from the

sector erase command stream and ends when the DATA polling (DQ7) is logical 1. DATA polling

address must be performed on addresses that fall within the sectors being erased. AS29LV800

returns to read mode after sector erase unless DQ5 is set high by exceeding the time limit.

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AS29LV800

October 2000

®

Item

Description

Erase Suspend allows interruption of sector erase operations to read data from or program data to

a sector not being erased. Erase suspend applies only during sector erase operations, including

the time-out period. Writing an Erase Suspend command during sector erase time-out results in

immediate termination of the time-out period and suspension of erase operation.

AS29LV800 ignores any commands during erase suspend other than Read/Reset, Program or

Erase Resume commands. Writing the Erase Resume Command continues erase operations.

Addresses are Don’t Care when writing Erase Suspend or Erase Resume commands.

AS29LV800 takes 0.2–15 µs to suspend erase operations after receiving Erase Suspend

command. To determine completion of erase suspend, either check DQ6 after selecting an

address of a sector not being erased, or poll RY/BY. Check DQ2 in conjunction with DQ6 to

determine if a sector is being erased. AS29LV800 ignores redundant writes of Erase Suspend.

Erase Suspend

While in erase-suspend mode, AS29LV800 allows reading data (erase-suspend-read mode) from

or programming data (erase-suspend-program mode) to any sector not undergoing sector erase;

these operations are treated as standard read or standard programming mode. AS29LV800

defaults to erase-suspend-read mode while an erase operation has been suspended.

Write the Resume command 30h to continue operation of sector erase. AS29LV800 ignores

redundant writes of the Resume command. AS29LV800 permits multiple suspend/resume

operations during sector erase.

When attempting to write to a protected sector, DATA polling and Toggle Bit 1 (DQ6) are

activated for about <1 µs. When attempting to erase a protected sector, DATA polling and

Toggle Bit 1 (DQ6) are activated for about <5 µs. In both cases, the device returns to read mode

without altering the specified sectors.

Sector Protect

Ready/Busy

RY/BY indicates whether an automated on-chip algorithm is in progress (RY/BY = low) or

completed (RY/BY = high). The device does not accept Program/Erase commands when

RY/BY = low. RY/BY= high when device is in erase suspend mode.RY/BY = high when device

exceeds time limit, indicating that a program or erase operation has failed.RY/BY is an open

drain output, enabling multipleRY/BY pins to be tied in parallel with a pull up resistor to V

.

CC

DID 11-40002-A. 10/19/00

ALLIANCE SEMICONDUCTOR

9

October 2000

AS29LV800

®

Status operations

Only active during automated on-chip algorithms or sector erase time outs. DQ7 reflects

complement of data last written when read during the automated on-chip program algorithm (0

during erase algorithm); reflects true data when read after completion of an automated on-chip

program algorithm (1 after completion of erase agorithm).

DATA polling (DQ7)

Active during automated on-chip algorithms or sector erase time outs. DQ6 toggles when CE or

OE toggles, or an Erase Resume command is invoked. DQ6 is valid after the rising edge of the

fourth pulse of WE during programming; after the rising edge of the sixth WE pulse during chip

erase; after the last rising edge of the sector erase WE pulse for sector erase. For protected

sectors,

Toggle bit 1 (DQ6)

DQ6 toggles for <1 µs during program mode writes, and <5 µs during erase (if all selected sectors

are protected).

Indicates unsuccessful completion of program/erase operation (DQ5 = 1).DATA polling remains

active. If DQ5 = 1 during chip erase, all or some sectors are defective; during byte programming

or sector erase, the sector is defective (in this case, reset the device and execute a program or

erase command sequence to continue working with functional sectors). Attempting to program 0

to 1 will set DQ5 = 1.

Exceeding time limit

(DQ5)

Checks whether sector erase timer window is open. If DQ3 = 1, erase is in progress; no

commands will be accepted. If DQ3 = 0, the device will accept sector erase commands. Check

DQ3 before and after each Sector Erase command to verify that the command was accepted.

Sector erase timer

(DQ3)

During sector erase, DQ2 toggles with OE or CE only during an attempt to read a sector being

erased. During chip erase, DQ2 toggles with OE or CE for all addresses. If DQ5 = 1, DQ2 toggles

only at sector addresses where failure occurred, and will not toggle at other sector addresses. Use

DQ2 in conjunction with DQ6 to determine whether device is in auto erase or erase suspend

mode.

Toggle bit 2 (DQ2)

Write operation status

Status

DQ7

0

DQ6

DQ5

DQ3

N/A

1

DQ2

RY/BY

Auto programming

Toggle

No toggle

Data

0

No toggle

0

1

0

1

Standard mode

†

Program/erase in auto erase

Read erasing sector

0

Toggle

1

0

N/A

Data

N/A

Toggle

Data

Erase suspend mode

Read non-erasing sector

Program in erase suspend

Auto programming (byte)

Program/erase in auto erase

Data

DQ7

0

Data

†

Toggle

0

1

Toggle

No toggle

†

Toggle

Exceeded time limits

Program in erase suspend

DQ7

Toggle

1

N/A

No toggle

1

(non-erase suspended sector)

DQ2 toggles when an erase-suspended sector is read repeatedly.

DQ6 toggles when any address is read repeatedly.

DQ2 = 1 if byte address being programmed is read during erase-suspend program mode.

^†DQ2 toggles when the read address applied points to a sector which is undergoing erase, suspended erase, or a failure to erase.

10

ALLIANCE SEMICONDUCTOR

DID 11-40002-A. 10/19/00

October 2000

AS29LV800

®

Automated on-chip programming algorithm

Automated on-chip erase algorithm

START

Write erase command sequence

(see below)

Write program command sequence

(see below)

DATA polling or toggle bit

successfully completed

DATA polling or toggle bit

successfully completed

Erase complete

Individual sector/multiple sector

Increment

address

erase command sequence

×16 mode (address/data):

Chip erase command sequence

×16 mode (address/data):

Last

NO

address?

555h/AAh

2AAh/55h

555h/80h

555h/AAh

2AAh/55h

555h/10h

555h/AAh

2AAh/55h

YES

Programming completed

555h/80h

Program command sequence

×16 mode (address/data):

555h/AAh

2AAh/55h

Sector address/30h

555h/A0h

Program address/program data

Sector address/30h

optional sector erase commands

†

The system software should check the status of DQ3 prior to and following each

subsequent sector erase command to ensure command completion. The device may

not have accepted the command if DQ3 is high on second status check.

DID 11-40002-A. 10/19/00

ALLIANCE SEMICONDUCTOR

11

AS29LV800

October 2000

®

Programming using unlock bypass command

Unlock bypass command sequence

x16 mode (address/data)

START

555h/AAh

Write unlock

bypass command

(3 cycles)

2AAh/55h

555h/20h

Write unlock

bypass program command

(2 cycles)

Unlock bypass program

command sequence

x16 mode (address/data)

DATA polling or

toggle bit

xxxh/A0h

successfully completed

program address/

program data

Increment

address

Last

NO

address?

Unlock bypass reset

command sequence

x16 mode (address/data)

YES

xxxh/90h

xxxh/00h

Write unlock

bypass reset command

(2 cycles)

Programming completed

12

ALLIANCE SEMICONDUCTOR

DID 11-40002-A. 10/19/00

October 2000

AS29LV800

®

DATA polling algorithm

Toggle bit algorithm

Read byte (DQ0–DQ7)

Address = VA^†

Read byte (DQ0–DQ7)

Address = don’t care

DQ7

DQ6

YES

NO

=

DONE

data

?

toggle

?

NO

YES

DQ5

=

NO

=

1

?

1

?

YES

Read byte (DQ0–DQ7)

Address = VA

Read byte (DQ0–DQ7)

Address = don’t care

DQ7

=

DQ6

†

YES

NO

=

DONE

†

data^‡

toggle

?

†

NO

FAIL

YES

FAIL

†

‡

VA = Byte address for programming. VA = any of the sector

addresses within the sector being erased during Sector Erase. VA

= valid address equals any non-protected sector group address

during Chip Erase.

†

DQ6 rechecked even if DQ5 = 1 because DQ6 may stop toggling

when DQ5 changes to 1.

DQ7 rechecked even if DQ5 = 1 because DQ5 and DQ7 may not

change simultaneously.

DID 11-40002-A. 10/19/00

ALLIANCE SEMICONDUCTOR

13

October 2000

AS29LV800

®

Sector protect algorithm

Sector unprotect algorithm

START

PLSCNT = 1

RESET# = V_ID

Wait 1 µs

PLSCNT = 1

RESET# = V_ID

Wait 1 µs

No

Protect all sectors:

The shaded portion of

the sector protct

No

First Write

Cycle=60h?

Temporary sector

unprotect mode

Temporary sector

unprotect mode

First Write

Cycle=60h?

algorithm must be

initiated for all

unprotected sectors

before calling the

sector unprotect

Yes

Set up sector

address

No

All sectors

protected?

Sector protect:

write 60h to sector

address with

A6=0, A1=1,

A0=0

Yes

Sector unprotect:

write 60h to sector

address with

A6=1, A1=1,

A0=0

Wait 150 µs

Verify sector

protect; write 40h

Wait 15 ms

to sector address

with A6=0,

A1=1, A0=0

Increment

PLSCNT

Set up first

sector address

Verify sector

unprotect; write 40h

to sector address

with A6=1,

Read from sector

address with A6=0,

A1=1, A0=0

Increment

PLSCNT

No

A1=1, A0=0

No

Read from sector

address with A6=1,

A1=1, A0=0

Data=01h?

Yes

PLSCNT=25?

No

Set up next

Yes

sector address

No

Protect

another

Yes

PLSCNT

=1000?

Data=00h?

Yes

sector?

Device failed

No

Remove V_ID

from RESET#

Yes

No

Last sector

verified?

Device failed

Write reset

command

Yes

Remove V_ID

Sector protect

complete

from RESET#

Write reset

command

Sector unprotect

complete

14

ALLIANCE SEMICONDUCTOR

DID 11-40002-A. 10/19/00

AS29LV800

October 2000

®

DC electrical characteristics

Parameter

V

= 2.7–3.6V

Unit

CC

Symbol Test conditions

Min

-

Max

±1

Input load current

I

V

= V to V , V = V

CC MAX

µA

LI

IN

SS

CC

A9 Input load current

= V , A9 = 10V

CC MAX

35

µA

LIT

LO

CC

Output leakage current

= V to V , V = V

CC MAX

-

±1

20

OUT

SS

CC

Active current, read @ 5MHz

Active current, program/erase

CE = V , OE = V

mA

CC1

CC2

IL

IH

CE = V , OE = V

100

IL

IH

CE = V , OE = V

;

*

IL

Automatic sleep mode

I

-

5

µA

CC3

V = 0.3V, V = V - 0.3V

IL

IH

CC

Standby current

I

CE = V - 0.3V, RESET = V - .3V

-

5

µA

V

SB

PD

CC

3

Deep power down current

RESET = 0.3V

-

5

Input low voltage

Input high voltage

Output low voltage

Output high voltage

V

-0.5

0.7×V

-

0.8

IL

V + 0.3

CC

V

IH

CC

I

= 4.0mA, V = V

CC MIN

0.45

OL

OH

LKO

ID

OL

OH

CC

= -2.0 mA, V = V

0.85×V

CC

-

CC

CC MIN

Low V lock out voltage

1.5

9

-

CC

Input HV select voltage

11

* Automatic sleep mode enables the deep power down mode when addresses are stable for 150 ns. Typical sleep mode current is 200 nA.

DID 11-40002-A. 10/19/00

ALLIANCE SEMICONDUCTOR

15

October 2000

AS29LV800

®

AC parameters — read cycle

-80

-90

-120

JEDEC Std

Symbol Symbol

Parameter

Min

Max

-

Min

Max

-

Min

Max

-

Unit

ns

t

Read cycle time

80

-

90

-

120

AVAV

AVQV

ELQV

GLQV

RC

Address to output delay

Chip enable to output

Output enable to output

Output enable setup time

Chip enable to output High Z

Output enable to output High Z

80

30

-

90

35

-

120

50

-

ns

ACC

CE

-

ns

-

ns

OE

0

-

0

-

0

-

ns

OES

DF

t

20

30

ns

EHQZ

GHQZ

-

ns

DF

Output hold time from addresses,

first occurrence of CE or OE

t

0

-

0

-

0

-

ns

AXQX

OH

Output enable hold time: Read

10

t

Output enable hold time:

Toggle and data polling

OEH

t

RESET high to output delay

RESET pin low to read mode

RESET pulse

-

50

10

-

50

10

-

50

10

-

ns

µs

ns

PHQV

RH

READY

RP

500

Read waveform

t_RC

Addresses stable

t_ACC

Addresses

CE

t_DF

t_OES

t_OE

OE

t_OEH

WE

t_OH

t_CE

High Z

Outputs

Output valid

t_RH

RESET

16

ALLIANCE SEMICONDUCTOR

DID 11-40002-A. 10/19/00

AS29LV800

October 2000

®

AC parameters — write cycle

WE controlled

-80

-90

-120

JEDEC

Symbol

Std

Symbol

Parameter

Min

80

0

Max

Min

90

0

Max

Min

120

0

Max

Unit

ns

t

Write cycle time

Address setup time

Address hold time

Data setup time

-

AVAV

WC

AS

AV WL

WLAX

DVWH

WHDX

GHWL

ELWL

45

35

0

45

0

50

0

AH

DS

Data hold time

DH

Read recover time before write

CE setup time

0

GHWL

CS

0

CE hold time

WHEH

WLWH

WHWL

CH

Write pulse width

Write pulse width high

35

30

35

30

50

30

WP

WPH

Write waveform

WE controlled

3rd bus cycle

DATA polling

t

WC

AS

555h

Program address

Addresses

CE

t

AH

t_CH

t_GHWL; t_OES

OE

t_WP

t

WHWH1 or 2

WE

t_CS

t_WPH

t_DH

Program

data

A0h

DQ7

D_OUT

DATA

t_DS

DID 11-40002-A. 10/19/00

ALLIANCE SEMICONDUCTOR

17

October 2000

AS29LV800

®

AC parameters — write cycle 2

CE controlled

-80

-100

-120

JEDEC

Symbol

Std Symbol Parameter

Min

80

0

Max

Min

90

0

Max

Min

120

0

Max

Unit

ns

t

Write cycle time

Address setup time

Address hold time

Data setup time

Data hold time

-

AVAV

AVE L

ELAX

DVEH

EHDX

WC

AS

AH

DS

DH

ns

45

35

0

45

0

50

0

ns

Read recover time before

write

t

0

-

0

-

0

-

ns

GHEL

t

WE setup time

WE hold time

0

-

0

-

0

-

ns

WLEL

EHWH

ELEH

EHEL

WS

WH

CP

CE pulse width

CE pulse width high

35

30

35

30

50

30

CPH

Write waveform 2

CE controlled

DATA polling

Program address

Addresses

WE

555h

t_WC

Program address

t_AH

t_AS

t_GHEL, t_OES

OE

t_CP

t_{WHWH1 or 2}

CE

t_CPH

t_DH

Program

DATA

A0h

t_DS

DQ7

D_OUT

data

18

ALLIANCE SEMICONDUCTOR

DID 11-40002-A. 10/19/00

AS29LV800

October 2000

®

AC parameters — temporary sector unprotect

-80

-90

-120

JEDEC

Symbol

Std Symbol Parameter

Min

500

Max

-

Min

500

Max

-

Min

500

Max

Unit

ns

t

V

rise and fall time

-

VIDR

RSP

ID

RESET setup time for

temporary sector unprotect

4

-

4

-

4

µs

Temporary sector unprotect waveform

10V

RESET

0 or 3V

t_VIDR

0 or 3V

t_VIDR

Program/erase command sequence

CE

WE

t_RSP

RY/BY

AC parameters — RESET

-80

-90

-120

JEDEC

Symbol

Std Symbol Parameter

Min

Max

Min

Max

-

Min

Max

-

Unit

ns

t

500

-

500

RESET pulse

RP

-

50

10

-

50

10

-

50

10

ns

RESET High time before Read

RESET Low to Read mode

RH

µs

READY

RESET waveform

t_RP

RESET

t_READY

RY/BY

t_RH

status

valid data

DQ

Erase waveform

×16 mode

t

AS

2AAh

WC

555h

Addresses

CE

555h

AH

555h

2AAh

Sector address

t

t_GHWL

OE

t_WP

t_CS

t_WC

WE

t_WPH

10h for Chip Erase

30h

t_DH

AAh

55h

80h

AAh

55h

Data

t_DS

DID 11-40002-A. 10/19/00

ALLIANCE SEMICONDUCTOR

19

October 2000

AS29LV800

®

AC Parameters — READY/BUSY

-80

-90

-120

JEDEC

Symbol Std Symbol Parameter

Min Max Min Max Min Max

Unit

µs

ns

-

t

V

setup time

50

0

-

50

0

-

50

0

-

VCS

RB

CC

Recovery time from RY/BY

90

Program/erase valid to RY/BY delay

BUSY

RY/BY waveform

CE

Rising edge of last WE signal

WE

Program/erase

operation

RY/BY

V_CC

tri-stated open-drain

t

BUSY

t

RB

t

VCS

DATA polling waveform

t

CH

CE

t

DF

OE

t

OEH

WE

t

CE

t

OH

High Z

DQ7

Input DQ7

Output DQ7

Output

t

WHWH1 or 2

Toggle bit waveform

CE

t

OEH

WE

OE

DQ6

t

OE

toggle

no toggle

t

DH

20

ALLIANCE SEMICONDUCTOR

DID 11-40002-A. 10/19/00

AS29LV800

October 2000

®

Word/byte configuration

-80

-90

-120

JEDEC

Symbol Std Symbol Parameter

Min Max Min Max Min Max

Unit

ns

-

t

/t

CE to BYTE switching Low or High

BYTE switching Low to output High-Z

BYTE switching High to output Active

-

10

30

-

10

35

-

10

40

-

ELFL ELFH

ns

FLQZ

FHQZ

ns

80

90

120

BYTE read waveform

CE

OE

BYTE

Word

t_ELFL

DQ0-DQ14

Data output

DQ0-DQ7

Data output

DQ0-DQ14

DQ15/A-1

BYTE

to

Byte

DQ15 output

t_FLQZ

Address input

t_ELFH

Byte

to

Word

DQ0-DQ14

Data output

DQ0-DQ7

Data output

DQ0-DQ14

DQ15/A-1

Address input

t_FHQV

DQ15 output

BYTE write waveform

CE

falling edge of last WE signal

WE

BYTE

t_SET

See Erase/Program operations table for t_ASand t_AHspecifications.

(t_AS

)

t_HOLD(t_AH)

Sector protect/unprotect

V_ID

V_IH

RESET#

SA, A6,

A1, A0

Don’t care

Valid*

60h

Don’t care

Valid*

Don’t care

Valid*

Status

Sector protect/unprotect

Verify

40h

60h

DATA

Sector protect: 100 µs

Sector unprotect: 10 ms

1 µs

CE#

WE#

OE#

* For sector protect, A6=0, A1=1, A0=0. For sector unprotect, A6=1, A1=1, A0=0.

DID 11-40002-A. 10/19/00

ALLIANCE SEMICONDUCTOR

21

October 2000

AS29LV800

®

AC test conditions

+3.0V

1N3064

or equivalent

^2.7KΩ

Device under test

^6.2KΩ

C_L*

1N3064

or equivalent

V_SS

Test specifications

Test Condition

80

30

90, 120

Unit

1 TTL gate

100

Output Load

Output Load Capacitance C (including jig capacitance)

pF

ns

V

L

5

Input Rise and Fall Times

Input Pulse Levels

0.0-3.0

1.5

Input timing measurement reference levels

Output timing measurement reference levels

V

1.5

V

Erase and programming performance

Limits

Parameter

Min

Typical

Max

Unit

sec

Sector erase and verify-1 time (excludes 00h programming

prior to erase)

-

1.0

15

Byte

-

10

15

300

360

27

-

µs

Programming time

Word

Chip programming time

7.2

sec

*

Erase/program cycles

100,000

cycles

* Erase/program cycle test is not verified on each shipped unit.

Latchup tolerance

Parameter

Min

-1.0

-0.5

-100

Max

Unit

+12.0

V

Input voltage with respect to V on A9, OE, and RESET pin

SS

V

Input voltage with respect to V on all DQ, address, and control pins

SS

VCC+0.5

+100

Current

mA

Includes all pins except V_CC. Test conditions: V_CC= 3.0V, one pin at a time.

Recommended operating conditions

Parameter

Symbol

Min

+2.7

0

Max

+3.6

0

Unit

V

CC

SS

IH

IL

Supply voltage

V

1.9

V

+ 0.3

V

CC

Input voltage

–0.5

0.8

V

22

ALLIANCE SEMICONDUCTOR

DID 11-40002-A. 10/19/00

AS29LV800

October 2000

®

Absolute maximum ratings

Parameter

Symbol

Min

–0.5

-0.5

–55

–65

-

Max

+ 0.5

Unit

Input voltage (Input or DQ pin)

Input voltage (A9 pin, OE, RESET)

Power supply voltage

V

IN

CC

+12.5

+4.0

+125

+150

150

V

IN

V

CC

OPR

Operating temperature

T

°C

mA

Storage temperature (plastic)

Short circuit output current

T

STG

I

OUT

Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions outside those indicated in the operational sections of this specificati on is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect reliability.

TSOP pin capacitance

Symbol

Parameter

Test setup

Typ

6

Max

7.5

12

Unit

pF

C

Input capacitance

Output capacitance

Control pin capacitance

V

= 0

IN

OUT

= 0

8.5

8

pF

OUT

IN2

10

pF

IN

SO pin capacitance

Symbol

Parameter

Test setup

Typ

6

Max

7.5

12

Unit

pF

C

Input capacitance

Output capacitance

Control pin capacitance

V

= 0

IN

= 0

8.5

8

pF

OUT

IN2

OUT

10

pF

IN

Data retention

Parameter

Temp.(°C)

Min

10

Unit

150°

125°

years

Minimum pattern data retention time

20

DID 11-40002-A. 10/19/00

ALLIANCE SEMICONDUCTOR

23

AS29LV800

October 2000

®

AS29LV800 ordering codes

Package \ Access Time

80 ns (commercial/industrial)

90 ns (commercial/industrial)

120 ns (commercial/industrial)

TSOP, 12×20 mm, 48-pin

Top boot configuration

AS29LV800T-80TC

AS29LV800T-80TI

AS29LV800T-90TC

AS29LV800T-90TI

AS29LV800T-120TC

AS29LV800T-120TI

TSOP, 12×20 mm, 48-pin

Bottom boot configuration

AS29LV800B-80TC

AS29LV800B-80TI

AS29LV800B-90TC

AS29LV800B-90TI

AS29LV800B-120TC

AS29LV800B-120TI

SO, 13.3 mm, 44-pin

Top boot configuration

AS29LV800T-80SC

AS29LV800T-80SI

AS29LV800T-90SC

AS29LV800T-90SI

AS29LV800T-120SC

AS29LV800T-120SI

SO, 13.3 mm, 44-pin

Bottom boot configuration

AS29LV800B-80SC

AS29LV800B-80SI

AS29LV800B-90SC

AS29LV800B-90SI

AS29LV800B-120SC

AS29LV800B-120SI

AS29LV800 part numbering system

AS29LV

800

X

–XXX

X

Options:

B = Burn-in

H = High I (<1mA)

Blank= Standard

3V Flash

EEPROM

prefix

Package:

S = SOJ

Temperature range:

C = Commercial: 0°C to 70°C

Device T= Top boot configuration

number B= Bottom boot configuration access time

Address

SB

T = TSOP I = Industrial: -40°C to 85°C

24

ALLIANCE SEMICONDUCTOR

DID 11-40002-A. 10/19/00

DID 11-40002-A. Copyright ©1998 Alliance Semiconductor. All rights reserved. Alliance Semiconductor corporation reserves the right to make changes in this document at any time to improve design and supply the best product possible. Publication

of information does not constitute commitment to produceor supply the product described. The company cannot assume responsibility for circuits shown or represent that they are free from patent infringement. While the company strives to publish

current, accurate information, we can assume no responsibility or liability for any error or inaccuracies that may appear in this document. Alliance Semiconductor Corporation products are not authorized for use as critical components in life support

devices or systems without the express written consent of the president of Alliance Semiconductor Corporation. The Alliance logo is a registered trademark of Alliance Semiconductor Corporation. All trademarks are property of their respective

holders.


型号：	AS29LV800T-80TI
厂家：	ANADIGICS, INC
描述：	3V 1M】8/512K】16 CMOS Flash EEPROM 3V 1M × 8 / 512K × 16的CMOS闪存EEPROM 闪存可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件：	总24页 (文件大小：394K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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AS2D-2M-10-Z

AS2D-5M-10-Z

AS2D-6M-10-Z

AS2E-2M-10-Z

AS2E-5M-10-Z