APW7063_09 [ANPEC]
Synchronous Buck PWM and Linear Controller; 同步降压PWM和线性控制器
| 型号： | APW7063_09 |
| 厂家： | 
ANPEC ELECTRONICS COROPRATION |
| 描述： | Synchronous Buck PWM and Linear Controller |
| 文件： | 总22页 (文件大小：366K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APW7063
Synchronous Buck PWM and Linear Controller
Features
General Description
The APW7063 integrates PWM and linear controller, as
well as the monitoring and protection functions into a
·
Provide Two Regulated Voltages
- Synchronous Rectified Buck PWM Controller
single package. The synchronous PWM controller which
drives dual N-channel MOSFETs, which provides one
controlled power outputs with under-voltage and over-
current protections. Linear controller drives an external
N-channel MOSFET with under-voltage protection.
APW7063 provides excellent regulation for output load
variation. An internal 0.8V temperature-compensated ref-
erence voltage is designed to meet the various low out-
put voltage applications. APW7063 includes a 250kHz
free-running triangle-wave oscillator that is adjustable
from 70kHz to 800kHz.
- Linear Controller
·
·
Fast Transient Response
- 0~85% DutyRatio
Excellent Output Voltage Regulation
- 0.8V Internal Reference
- ±1% Over Line Voltage and Temperature
Over Current Protection
·
- Sense Low-Side MOSFET’s RDS(ON)
Under Voltage Lockout
·
·
Small Converter Size
A power-on-reset (POR) circuit limits the VCC minimum
opearting supply voltage to assure the controller working
well. Over current protection is achieved by monitoring
the voltage drop across the low side MOSFET, eliminat-
ing the need for a current sensing resistor and short cir-
cuit condition is detected through the FB pin. The over-
current protection triggers the soft-start function until the
fault events be removed, but Under-voltage protection will
shutdown IC directly.
- 250kHz Free-Running Oscillator
- Programmable From 70kHz to 800kHz
14-Lead SOIC Package
·
·
Lead Free and Green Devices Available
(RoHS Compliant)
Applications
Pull the COMP pin below 0.4V will shutdown the controller,
and both gate drive signals will be low.
·
·
·
·
·
Graphic Cards
Memory Power Supplies
DSL or Cable MODEMs
Set Top Boxes
Pin Configuration
Low-Voltage Distributed Power Supplies
RT
SS
1
2
3
4
5
6
7
FBL
14
13
12
11
10
9
DRIVE
VCC
VREG
LGATE
PGND
BOOT
UGATE
FB
COMP
GND
8
PHASE
SOP-14
(Top View)
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
Copyright ã ANPEC Electronics Corp.
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Rev. A.10 - Aug., 2009
APW7063
Ordering and Marking Information
Package Code
APW7063
K : SOP-14
Operating Ambient Temperature Range
C : 0 to 70 oC
Assembly Material
Handling Code
Handling Code
Temperature Range
Package Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
APW7063
XXXXX
XXXXX - Date Code
APW7063 K :
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Absolute Maximum Ratings (Note 1)
Symbol
Parameter
Rating
30
Unit
V
VCC
VCC to GND
LGATE
DRIVE
UGATE
VBOOT
LGATE to GND
DRIVE to GND
UGATE to GND
BOOT to GND
PHASE to GND
30
V
30
V
30
V
30
V
30
V
Operating Junction Temperature
Storage Temperature
0~150
-65 ~ 150
260
oC
oC
oC
TSTG
TSDR
Maximum Lead Soldering Temperature, 10 Seconds
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Thermal Characteristics
Symbol
Parameter
Typical Value
Unit
Junction to Ambient Resistance in Free Air (Note 2)
160
oC/W
qJA
SOP-14
Note 2: qJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
Recommended Operating Conditions
Range
Symbol
Parameter
Unit
Min.
Typ.
12
-
Max.
19
VCC
Supply Voltage
Boot Voltage
8
-
V
V
VBOOT
26
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Rev. A.10 - Aug., 2009
APW7063
Electrical Characteristics
Unless otherswise specified, these specifications apply over VCC = 12V, VBOOT = 12V, RT = OPEN and TA = 0 ~ 70oC. Typlcal values are
at TA = 25oC.
APW7063
Symbol
Parameter
Test Conditions
Unit
Min.
Typ.
Max.
SUPPLY CURRENT
ICC
VCC Nominal Supply
UGATE and LGATE Open
-
3
-
mA
POWER-ON-RESET
Rising VCC Threshold
Falling VCC Threshold
OSCILLATOR
7.0
6.6
7.2
6.8
7.4
7.0
V
V
Free Running Frequency
Total Variation
RT = OPEN, VCC = 12V
6kW < RT to GND < 200kW
RT = OPEN
220
-15
-
250
-
280
+15
-
kHz
%
Ramp Amplitude
1.7
VP-P
REFERENCE
VREF
Reference Voltage
-
0.80
-
-
V
Reference Voltage Tolerance
-1
+1
%
PWM EEEOR AMPLIFIER
DC Gain
-
0
-
75
-
-
dB
%
UGATE Duty Range
FB Input Current
GATE DRIVERS
85
0.1
-
mA
IUGATE
RUGATE
ILGATE
RLGATE
TD
Upper Gate Source
Upper Gate Sink
Lower Gate Source
Lower Gate Sink
Dead Time
VBOOT = 12V, VUGATE = 6V
IUGATE = 0.3A
650
800
4
-
8
-
mA
W
-
VCC = 12V, VLGATE = 6V
ILGATE = 0.3A
550
700
4
mA
W
-
-
8
-
50
nS
LINEAR REGULATOR
Reference Voltage
-
-
0.8
2
-
-
V
%
Regulation
Output Drive Current
VDRIVE = 4V
8
10
12
mA
PROTECTION
FB Under Voltage Level
FBL Under Voltage Level
OCSET Source Current
-
-
-
50
50
-
-
-
%
%
250
mA
VREG
VREG
IOUT
Output Voltage Accuracy
Output Current Capacity
VCC > 12V
VCC = 12V
5.5
-
6
6.5
-
V
20
mA
SOFT-START AND SHUTDOWN
TSS
ISS
Internal Soft-Start Interval
Soft-Start Charge Current
Shutdown Threshold
-
8
-
2
-
12
-
mS
mA
V
CSS = 0mF
10
0.4
50
COMP Falling
Shutdown Hysteresis
-
-
mV
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APW7063
Typical Operating Characteristics
Power Up
Power Down
VCC=VIN1=12V
VIN2=5V, CSS=0.1mF
VCC=VIN1=12V
VIN2=5V, CSS=0.1mF
VCC(10V/div)
SS(5V/div)
VCC(10V/div)
SS(5V/div)
VOUT1(2V/div)
VOUT1(2V/div)
VOUT2(2V/div)
VOUT2(2V/div)
Time (10ms/div)
Time (10ms/div)
Enable (COMP is left open)
Shutdown (COMP is pulled to GND)
VCC=VIN1=12V
VIN2=5V, CSS=0.1mF
VCC=VIN1=12V
VIN2=5V, CSS=0.1mF
VOUT2(2V/div)
VOUT2(2V/div)
VOUT1(2V/div)
VOUT1(2V/div)
COMP(1V/div)
COMP(1V/div)
SS(5V/div)
SS(5V/div)
Time (2ms/div)
Time (10ms/div)
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APW7063
Typical Operating Characteristics (Cont.)
UGATE Falling
UGATERising
VCC=2V, VIN=12V
VCC=2V, VIN=12V
LGATE(10V/div)
LGATE(10V/div)
PHASE(10V/div)
PHASE(10V/div)
UGATE(10V/div)
UGATE(10V/div)
Time (50ns/div)
Time (50ns/div)
Under Voltage Protection (PWM)
Under Voltage Protection (Linear)
VCC=12,VIN=12V
VOUT=3.3V, L=2.2mH
IL(10A/div)
SS(5V/div)
VCC=12V, VIN=5V
VOUT2=2.5V
SS(5V/div)
VOUT2(2V/div)
VOUT1 (2V/div)
UGATE (10V/div)
DRV(5V/div)
Time (5ms/div)
Time (5ms/div)
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APW7063
Typical Operating Characteristics (Cont.)
PWM Load Transient
Linear Load Transient
VCC=12V
VIN=12V
VCC=12V
VOUT=3.3V
COUT=470mFx2
ESR=22.5mW
L=1.5mH
VIN=12V
VOUT=2.5V
COUT=470mF
f=400kHz
VOUT2(100mV/div)
VOUT1(100mV/div)
IOUT2(1A/div)
IOUT1(5A/div)
Time (20ms/div)
Time (10ms/div)
UGATE Sink Current vs. UGATE Voltage
UGATE Source Current vs. UGATE Voltage
1.2
1
1.4
1.2
1
VBOOT=12V
VBOOT=12V
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
0
2
4
6
8
10
12
0
2
4
6
8
10
12
UGATE Voltage (V)
UGATE Voltage (V)
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APW7063
Typical Operating Characteristics (Cont.)
LGATE Source Current vs. LGATE Voltage
LGATE Sink Current vs. LGATE Voltage
1.4
1.2
1
VCC=12V
VCC=12V
1.2
1
0.8
0.8
0.6
0.4
0.2
0.6
0.4
0.2
0
0
0
2
4
6
8
10
12
0
2
4
6
8
10
12
LGATE Voltage (V)
LGATE Voltage (V)
Over Current Protection
VCC=12V,VIN=12V, VOUT=2.5V, ROCSET=1kW
RDS(ON)=16mW, L=2.2mH, IOUT=15A
Switching Frequence vs. RT Resistance
10000
1000
100
10
IL(10A/div)
SS(5V/div)
RT pull up to 12V
RT pull down to GND
UGATE(20V/div)
1
VOUT1(2V/div)
10
100
1000
Time (5ms/div)
Switching Frequency (kHz)
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APW7063
Typical Operating Characteristics (Cont.)
Comp Source Current vs. Comp Voltage
Comp Sink Current vs. Comp Voltage
150
125
100
75
150
125
100
75
VCC=12V
VCC=12V
50
50
25
25
0
0
0
0.5
1
1.5
2
2.5
3
3.5
4
1
1.5
2
2.5
3
3.5
4
Comp Voltage (V)
Comp Voltage (V)
Drive Source Current vs. Drive Voltage
Drive Sink Current vs. Drive Voltage
40
30
20
10
0
10
8
VCC=12V
VCC=12V
6
4
2
0
0
2
4
6
8
10
12
0
2
4
6
8
10
12
Drive Voltage (V)
Drive Voltage (V)
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APW7063
Typical Operating Characteristics (Cont.)
VREG Voltage vs. SupplyVoltage
VREG Voltage vs. Load Current
6
5.5
5
6.5
6.25
6
VCC=12V
4.5
4
5.75
5.5
0
2
4
6
8
10 12 14 16 18
0
5
10
15
20
Supply Voltage (V)
Load Current (mA)
SupplyCurrent vs. Supply Voltage
Reference Voltage vs. Temperature
4
0.8
0.798
0.796
0.794
0.792
0.79
3.5
ICC
3
2.5
2
ICC(SHDN)
1.5
1
0.5
0
-40 -20
0
20 40 60 80 100 120
0
2
4
6
8
10
12
Supply Voltage (V)
Temperature (°C)
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APW7063
Typical Application Circuit
1. Boot-Strap - Use Internal Regulator
12V
C1
1mF
5V
C2
1mF
12V
L1
1mH
VIN
R2
2R2
C3
+
D1
U1
VIN
R1
+
+
C9
470mF
6.3V
25mR
NC
NC
C5
+C6
C4
1N4148
APW7063
470mF
16V
25mR
470mF
470mF
16V
4.7mF
R3
1
2
3
4
5
6
7
14
13
12
11
10
9
8
7
6
5
RT
FBL
DRIVE
VCC
C8
1mF
16V
SS
2
25mR
VREG
FB
25mR
C7
0.1mF
LGATE
Q1
APM3055L
COMP PGND
R4
0R
Q2
APM4220
1
GND
BOOT
3V3
4
4
8
PHASEUGATE
R14
0R
1
2
3
R13
0R
3
C12
0.1mF
2.5V
L2
2.2mH
C11
4.7mF
C10
R5
3.125kF
1%
+
470mF
6.3V
C19
220pF
R6
620R
8
7
6
5
25mR
+
+
C14
R8
C15
4.7mF
D2
SR24
NC
C13
R7
1kF
1%
Q3
2A/40V
1000mF 1000mF
C16
0.01mF
R10
2.32kF
1%
APM4220
6.3V
6.3V
1
2
3
R9
0R
30mR
30mR
C17
56pF
C18
NC
R11
20K
SHDN
R12
1.07kF
1%
2. Boot-Strap - Use External Power
12V
5V
12V
L1
D1
1mH
C1
VIN
R1
2R2
1N4148
1mF
+
C2
U1
C7
+
+C5
+
NC
NC
C3
VINR2
R3
C6
470mF
6.3V
25mR
APW7063
470mF
16V
4.7mF
470mF
470mF
16V
25mR
1
2
3
4
5
6
7
14
13
12
11
10
9
8
7
6
5
C8
1mF
RT
SS
FBL
DRIVE
VCC
16V
25mR
2
3
25mR
C4
0.1mF
VREG
FB
R14
0R
LGATE
Q1
APM3055L
R4
0R
COMP PGND
Q2
1
GND
BOOT
3V3
4
4
APM4220
8
PHASEUGATE
1
2
3
R13
0R
C11
0.1mF
L2
2.5V
2.2mH
R5
3.125kF
1%
+
C9
C10
4.7mF
C19
220pF
470mF
6.3V
R6
820R
8
7
+
+
6
25mR
R7
C12
C13
C14
D2
5
100R
Q3
R9
0R
1000mF 1000mF
4.7mF
6.3V
30mR
SR24
2A/40V
R8
1kF
1%
C15
0.01mF
APM422
6.3V
R10
2.32kF
1%
0
30mR
1
2
3
C16
56pF
C17
0.1mF
R11
20K
SHDN
R12
1.07kF
1%
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APW7063
Block Diagram
VCC
SS
vcc
BOOT
ISS
10mA
5.8V
Power-On
Reset
Gate Control
UGATE
vcc
Soft Start
and
Fault Logic
IOCSET
250mA
GND
PHASE
VCC
O.C.P
Comparator
U.V.P
Comparator
50%VREF
:
2
LGATE
PGND
FBL
50%VREF
VCC
:
2
PWM
Comparator
Error Amp
VCC
DRIVE
VREF
Oscillator
RT
Regulator
VREF
Triangle
Wave
FB
COMP
VREG
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APW7063
Function Pin Description
RT (Pin 1)
VOLTAGE
VSOFT-START
This pin can adjust the switching frequency. Connect a
resistor from RT to VCC for decreasing the switching
frequency. Conversely, connect a resistor from RT to GND
for increasing the switching frequency (See Typical
Characteristics).
VOUT2
VOUT1
SS (Pin 2)
Connect a capacitor from this pin to GND to set the soft-
start interval of the converter. An internal 10mA current
source charges this capacitor to 5.2V. The SS voltage
clamps the reference voltage to the SS voltage, and Fig-
ure1 shows the soft-start interval. At t0, the internal source
current starts to charge the capacitor and the internal 0.8V
reference also starts to rise and follows the SS. Until the
internal reference reaches to 0.8V at t2, the soft-start in-
terval is completed. This method provides a rapid and
controlled output voltage rise. The way of the Soft-Start of
the output2 is the same as the output1, but it starts from
the SS at 2.2V to 3.0V. The APW7063 also provides the
internal Soft-Start which is fixed to 2ms (t0 to t1). If the
external Soft-Start interval is slower than the internal Soft-
FB
FBL
TIME
t0
t1
t2
t3
Figure 1. Soft-Start Interval
VREG (Pin 3)
An internal regulator will supply 6V for boost voltage, a
1mF capacitor to GND is recommended for stability. If the
VREG voltage has variation by other interference, the IC
can not work normally. When the VCC<8V, don’t use the
VREG for BOOST voltage.
Start interval (CSS<0.025mF) or no external capacitor, FB (Pin 4)
the Soft-Start will follow the internal Soft-Start.
FB pin is the inverting input of the error amplifier, and it
C SS
ISS
receives the feedback voltage from an external resistive
divider across the output (VOUT). The output voltage is de-
termined by :
TSoft-Start = t1 - t0 =
´ 0.8V
C SS
t3 = t2 +
´ 0.8V
ISS
ROUT
RGND
æ
è
ö
÷
ø
VOUT = 0.8V´ 1+
ç
Where:
CSS = external Soft-Start capacitor
where ROUT is the resistor connected from VOUT to FB,
ISS = Soft-Start current = 10mA
and RGND is the resistor connected from FB to GND.
CSS ´ 2.2V
ISS
When the FB voltage is under 50% Vref, it will cause the
under voltage protection and shutdown the device. Re-
move the condition and restart the VCC voltage or pull the
COMP from low to high once will enable the device again.
t2 =
COMP (Pin 5)
This pin is the output of the error amplifier. Add an exter-
nal resistor and capacitor network to provide the loop
compensation for the PWM converter (See Applica-
tion Information).
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APW7063
Function Pin Description (Cont.)
COMP (Pin 5) (Cont.)
A 1mF decoupling capacitor to GND is recommended.
Pull this pin below 0.4V will shutdown the controller, forc-
ing the UGATE and LGATE signals to be 0V. A soft-start
cycle will be initiated upon the release of this pin.
DRIVE (Pin 13)
Connect this pin to the gate of an external N-channel
MOSFET transistor. This pin provides the gate voltage for
the linear regulator pass transistor. It also provides a
means of compensating the linear controller for applica-
tions where the user needs to optimize the regulator tran-
sient response.
GND (Pin 6)
Signal ground for the IC.
PHASE (Pin 7)
A resistor (ROCSET) is connected between this pin and the
drain of the low-side MOSFET will determine the over
current limit. An internal 250mA current source will flow
through this resistor, creating a voltage drop. This volt-
age will be compared with the voltage across the low-
side MOSFET. The threshold of the over current limit is
therefore given by :
FBL (Pin 14)
Connect this pin to the output of the linear regulator via a
proper sized resistor divider. The voltage at this pin is
regulated to 0.8V and the output voltage is determined
using the following equation :
ROUT
RGND
æ
è
ö
÷
ø
VOUT = 0.8V ´ 1+
ç
ILIMIT ´ RDS(ON)
ROCSET
=
250uA
where ROUT is the resistor connected from VOUT to FBL,
and RGND is the resistor connected from FBL to GND.
An over current condition will cycle the soft-start function
until the over current condition is removed. Because of
the comparator delay time, the on time of the low-side
MOSFET must be longer than 800ns to have the over
current protection work.
This pin also monitores the under-voltage events. If the
linear regulator is not used, tie the FBL to VREG.
UGATE(Pin 8)
This pin provides gate drive for the high-side MOSFET.
BOOT (Pin 9)
This pin provides the supply voltage to the high side
MOSFET driver. For driving logic levelN-channel MOSEFT,
a bootstrap circuit can be used to create a suitable driver’s
supply.
PGND (Pin 10)
Power ground for the gate diver. Connect the lower
MOSFET source to this pin.
LGATE(Pin 11)
This pin provides the gate drive signal for the low side
MOSFET.
VCC (Pin 12)
This pin provides a supply voltage for the device. When
VCC is above the rising threshold 4.2V, it turns on the
device is turned on. Conversely, when VCC is below the
falling threshold 3.9V, the device is turned off.
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APW7063
Application Information
Component Selection Guidelines
Output Capacitor Selection
ripple current to be approximately 30% of the maximum
output current.
Once the inductance value has been chosen, selecting
an inductor is capable of carrying the required peak cur-
rent without going into saturation. In some types of
inductors, especially core that is make of ferrite, the ripple
current will increase abruptly when it saturates. This will
result in a larger output ripple voltage.
The selection of COUT is determined by the required effec-
tive series resistance (ESR) and voltage rating rather than
the actual capacitance requirement. Therefore, selecting
high performance low ESR capacitors is intended for
switching regulator applications. In some applications,
multiple capacitors have to be paralled to achieve the
desired ESR value. If tantalum capacitors are used, make
sure they are surge tested by the manufactures. If in doubt,
consult the capacitors manufacturer.
Compensation
The output LC filter of a step down converter introduces a
double pole, which contributes with –40dB/decade gain
slope and 180 degrees phase shift in the control loop. A
compensation network between COMP pin and ground
should be added. The simplest loop compensation net-
work is shown in Figure 5.
Input Capacitor Selection
The input capacitor is chosen based on the voltage rating
and the RMS current rating. For reliable operation, select
the capacitor voltage rating to be at least 1.3 times higher
than the maximum input voltage. The maximum RMS
current rating requirement is approximately IOUT/2 where
IOUT is the load current. During power up, the input capaci-
tors have to handle large amount of surge current. If tanta-
lum capacitors are used, make sure they are surge tested
by the manufactures. If in doubt, consult the capacitors
manufacturer.
The output LC filter consists of the output inductor and
output capacitors. The transfer function of the LC filter is
given by:
1+ s´ ESR´ COUT
s2 ´ L´ COUT + s´ ESR´ COUT +1
GAINLC
=
The poles and zero of this transfer function are:
1
FLC
=
For high frequency decoupling, a ceramic capacitor be-
tween 0.1mF to 1mF can connect between VCC and ground
pin.
2´ p ´ L´ COUT
1
FESR
=
2 ´ p ´ ESR ´ COUT
Inductor Selection
The FLC is the double poles of the LC filter, and FESR is
the zero introduced by the ESR of the output capacitor.
The inductance of the inductor is determined by the out-
put voltage requirement. The larger the inductance, the
lower the inductor’s current ripple. This will translate into
lower output ripple voltage. The ripple current and ripple
voltage can be approximated by:
L
Output
PHASE
COUT
VIN - VOUT
Fs x L
VOUT
VIN
IRIPPLE
=
x
ESR
where Fs is the switching frequency of the regulator.
DVOUT = IRIPPLE x ESR
Figure 2. The Output LC Filter
A tradeoff exists between the inductor’s ripple current and
the regulator load transient response time. A smaller in-
ductor will give the regulator a faster load transient re-
sponse at the expense of higher ripple current and vice
versa. The maximum ripple current occurs at the maxi-
mum input voltage. A good starting point is to choose the
Copyright ã ANPEC Electronics Corp.
14
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Rev. A.10 - Aug., 2009
APW7063
Application Information (Cont.)
Compensation (Cont.)
The pole and zero of the compensation network are:
1
FP =
F
LC
C1´ C2
2´ p ´ R3´
-40dB/dec
C1+ C2
1
FZ
=
F
ESR
2´ p ´ R3´ C1
Gain
V
OUT
-20dB/dec
Error
R1
Amplifier
FB
-
COMP
Frequency
Figure 3. The LC Filter Gain & Frequency
R2
+
R3
C1
The PWM modulator is shown in Figure 4. The input is
the output of the error amplifier and the output is the PHASE
node. The transfer function of the PWM modulator is given
by:
VREF
C2
VIN
Figure 5. Compensation Network
GAINPWM =
DVOSC
The closed loop gain of the converter can be written as:
VIN
R2
Driver
GAINLC x GAINPWM x
x GAINAMP
R1+ R2
PWM
Comparator
Figure 6 shows the converter gain and the following guide-
lines will help to design the compensation network.
VOSC
1.Select the desired zero crossover frequency FO:
(1/5 ~ 1/10) x FS >FO>FZ
Output of
PHASE
Error
Amplifier
Use the following equation to calculate R3:
DVOSC
FESR
R1+ R2 FO
R3 =
´
´
´
Driver
2
VIN
R2
gm
FLC
Where:
gm = 900mA/V
Figure 4. The PWM Modulator
The compensation circuit is shown in Figure 5. R3 and
C1 introduce a zero and C2 introduces a pole to reduce
the switching noise. The transfer function of error ampli-
fier is given by:
2.Place the zero FZ before the LC filter double poles
FLC:
FZ = 0.75 x FLC
Calculate the C1 by the equation:
é
ù
1
1
æ
ö
gm ´ R3 +
//
÷
gm´ Zo
GAINAMP =
=
ç
ê
ú
sC1
sC2
ø
è
ë
1
û
C1=
2´ p ´ R1´ 0.75´ FLC
1
æ
ö
s +
ç
÷
R3 ´ C1
3. Set the pole at the half the switching frequency:
FP = 0.5xFS
è
ø
gm ´
=
C1+ C2
R3 ´ C1´ C2
æ
ö
÷
s ´ s +
´ C2
ç
è
ø
Copyright ã ANPEC Electronics Corp.
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Rev. A.10 - Aug., 2009
APW7063
Application Information (Cont.)
Compensation (Cont.)
Linear Regulator Input/Output Capacitor Selection
Calculate the C2 by the equation:
The input capacitor is chosen based on its voltage rating.
Under load transient condition, the input capacitor will
momentarily supply the required transient current. A 1mF
C1
C2 =
p ´ R3 ´ C1 ´ FS - 1
ceramic capacitor will be sufficient in most applications.
The output capacitor for the linear regulator is chosen to
minimize any droop during load transient condition. In
addition, the capacitor is chosen based on its voltage
rating.
FZ=0.75FLC
F
P
=0.5F
S
20 ×log(gm×R3)
Linear Regulator MOSFET Selection
Compensation Gain
The maximum DRIVE voltage is determined by the VCC.
Since this pin drives an external N-channel MOSFET, the
maximum output voltage of the linear regulator is depen-
dent upon the VGS.
Gain
F
LC
FO
VIN
20 ×log
?VOSC
Converter
Gain
F
ESR
VOUT2MAX = VCC- VGS
PWM &
Filter Gain
Another criteria is its efficiency of heat removal. The power
dissipated by the MOSFET is given by:
Frequency
Figure 6. Converter Gain & Frequency
Pdiss = Iout * (VIN - VOUT2
)
where Iout is the maximum load current
Vout2 is the nominal output voltage
MOSFETSelection
The selection of the N-channel power MOSFETs is deter-
mined by the RDS(ON), reverse transfer capacitance (CRSS),
and maximum output current requirement.The losses in
the MOSFETs have two components: conduction loss and
transition loss. For the upper and lower MOSFET, the
losses are approximately given by the following equations:
In some applications, heatsink may be required to help
maintain the junction temperature of the MOSFET below
its maximum rating.
Layout Consideration
In high power switching regulator, a correct layout is im-
portant to ensure proper operation of the regulator. In
general, interconnecting impedances should be mini-
mized by using short and wide printed circuit traces. Sig-
nal and power grounds are to be kept separate and finally
combined using ground plane construction or single point
grounding. Figure 8 illustrates the layout, with bold lines
indicating high current paths. Components along the bold
lines should be placed close together. Below is a check-
list for your layout:
PUPPER = Iou2t (1+ TC)(RDS(ON))D + (0.5)(Iout)(VIN)(tsw)FS
PLOWER = Io2ut (1+ TC)(RDS(ON))(1-D)
where IOUT is the load current
TC is the temperature dependency of RDS(ON)
FS is the switching frequency
tsw is the switching interval
D is the duty cycle
Note that both MOSFETs have conduction losses while
the upper MOSFET include an additional transition loss.
The switching internal, tsw, is the function of the reverse
transfer capacitance CRSS. Figure 7 illustrates the switch-
ing waveform internal of the MOSFET.
· Keep the switching nodes (UGATE, LGATE, and PHASE)
away from sensitive small signal nodes since these
nodes are fast moving signals. Therefore, keep traces
to these nodes as short as possible.
The (1+TC) term factors in the temperature dependency
of the RDS(ON) and can be extracted from the “RDS(ON) vs Tem-
perature” curve of the power MOSFET.
· The ground return of CIN must return to the combine
COUT (-) terminal.
Copyright ã ANPEC Electronics Corp.
16
www.anpec.com.tw
Rev. A.10 - Aug., 2009
APW7063
Application Information (Cont.)
Layout Consideration (Cont.)
· Capacitor CBOOT should be connected as close to
the BOOT and PHASE pins as possible.
VDS
t
Time
sw
Figure 7. Switching waveform across MOSFET
VIN
CIN
APW7063
+
11
PGND
12
LGATE
L
O
A
D
COUT
9
Q1
UGATE
Q2
+
8
PHASE
L1
VOUT
Figure 8. Recommended Layout Diagram
Copyright ã ANPEC Electronics Corp.
17
www.anpec.com.tw
Rev. A.10 - Aug., 2009
APW7063
Package Information
SOP-14
D
SEE VIEW A
°
c
e
b
GAUGE PLANE
SEATING PLANE
L
VIEW A
SOP-14
S
Y
M
B
O
L
MILLIMETERS
INCHES
MIN.
MAX.
1.75
0.25
MIN.
MAX.
A
0.069
0.010
0.004
0.049
0.012
0.007
A1
A2
b
0.10
1.25
0.31
0.17
8.55
5.80
3.80
0.020
0.010
0.51
0.25
8.75
6.20
4.00
c
D
0.337
0.228
0.150
0.344
0.244
0.157
E
E1
e
1.27 BSC
0.050 BSC
0.010
0.016
0.020
0.050
0.25
0.40
0.50
1.27
h
L
°
°
0
0
8
0
8
Note: 1. Follow JEDEC MS-012 AB.
2. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not exceed 6 mil per side.
3. Dimension “E” does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
Copyright ã ANPEC Electronics Corp.
18
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Rev. A.10 - Aug., 2009
APW7063
Carrier Tape & Reel Dimensions
P0
P2
P1
OD0
A
K0
A0
A
OD1
B
B
SECTION A-A
SECTION B-B
d
T1
Application
SOP-14
A
H
T1
16.4+2.00 13.0+0.50
-0.00 -0.20
P2 D0
C
d
D
W
E1
F
7.50±0.10
K0
330.0±2.00
P0
50 MIN.
P1
1.5 MIN.
D1
20.2 MIN. 16.0±0.30 1.75±0.10
T
A0
B0
1.5+0.10
-0.00
0.6+0.00
-0.40
4.0±0.10
8.0±0.10
2.0±0.10
1.5 MIN.
6.40±0.20 9.00±0.20 2.10±0.20
(mm)
Devices Per Unit
Package Type
SOP-14
Unit
Tape & Reel
Quantity
2500
Copyright ã ANPEC Electronics Corp.
19
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Rev. A.10 - Aug., 2009
APW7063
Taping Direction Information
SOP-14
USER DIRECTION OF FEED
Classification Profile
Copyright ã ANPEC Electronics Corp.
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Rev. A.10 - Aug., 2009
APW7063
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
Preheat & Soak
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
Temperature min (Tsmin
)
Temperature max (Tsmax
)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
3 °C/second max.
3°C/second max.
Liquidous temperature (TL)
Time at liquidous (tL)
183 °C
60-150 seconds
217 °C
60-150 seconds
Peak package body Temperature
(Tp)*
See Classification Temp in table 1
20** seconds
See Classification Temp in table 2
30** seconds
Time (tP)** within 5°C of the specified
classification temperature (Tc)
Average ramp-down rate (Tp to Tsmax
)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Volume mm3
350
Package
Thickness
<2.5 mm
³ 2.5 mm
Volume mm3
<350
235 °C
220 °C
220 °C
220 °C
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
Volume mm3
Volume mm3
350-2000
260 °C
Volume mm3
<350
260 °C
260 °C
250 °C
>2000
260 °C
245 °C
245 °C
1.6 mm – 2.5 mm
³ 2.5 mm
250 °C
245 °C
Reliability Test Program
Test item
SOLDERABILITY
HOLT
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
Description
5 Sec, 245°C
1000 Hrs, Bias @ 125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
PCT
TCT
HBM
MM
VMM≧200V
10ms, 1tr≧100mA
Latch-Up
Copyright ã ANPEC Electronics Corp.
21
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Rev. A.10 - Aug., 2009
APW7063
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright ã ANPEC Electronics Corp.
Rev. A.10 - Aug., 2009
22
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