APW7083QBI-TRG [ANPEC]
5A, 26V, 380kHz, Synchronous Step-Down Converter; 5A ， 26V ， 380kHz ，同步降压型转换器
| 型号： | APW7083QBI-TRG |
| 厂家： | 
ANPEC ELECTRONICS COROPRATION |
| 描述： | 5A, 26V, 380kHz, Synchronous Step-Down Converter |
| 文件： | 总22页 (文件大小：428K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APW7083
5A, 26V, 380kHz, Synchronous Step-Down Converter
Features
General Description
·
·
·
Wide Input Voltage from 4.5V to 26V
Output Current Up to 5A
The APW7083 is a 5A, synchronous, step-down converter
with integrated 50mW P-channel power MOSFET and
Adjustable Output Voltage from 0.8V to 90%VIN
- 0.8V Reference Voltage
20mW N-channel power MOSFET. The device, with cur-
rent-mode control scheme, can convert 4.5~26V input volt-
age to the output voltage adjustable from 0.8 to 90% VIN to
provide excellent output voltage regulation.
- ±2.5% System Accuracy
·
Integrated 50mW P-Channel Power MOSFET and
20mW N-Channel Power MOSFET
High Efficiencyup to 95%
The APW7083 regulates the output voltage in an auto-
matic PSM/PWM mode operation, depending on the out-
put current, for high efficiency operation over light to full
load current. The APW7083 is also equipped with power-
on-reset, soft-start, and whole protections (including over-
voltage, under-voltage, over-temperature, and current-
limit) in a single package. In shutdown mode, the supply
current drops below 5mA.
·
·
Current-Mode Operation
- Stable with Ceramic Output Capacitors
- Fast Transient Response
·
·
·
Power-On-Reset Monitoring
Fixed 380kHz Switching Frequencyin PWM Mode
Automatic Pulse-Skipping Mode (PSM)/PWM
Mode Operation
This device, available in 28-pin TQFN5x6 package, pro-
vides a very compact system solution with minimal exter-
nal components and good thermal conductance.
·
·
Built-in Digital Soft-Start
Output Current-Limit Protection with Frequency
Foldback
·
·
·
·
·
·
·
70% Under-Voltage Protection
Over-Temperature Protection
118% Over-Voltage Protection
<5mA Quiescent Current During Shutdown
Thermal-Enhanced TQFN5x6-28 Package
Pb-Free Available as an Option
Lead Free and Green Devices Available
(RoHS Compliant)
Simplified Application Circuit
VIN
4.5V~26V
C1
10mF
C2
1mF
VIN
L1
5A
VOUT
0.8V~90%VIN, 5A
VCC UGND
C3
1mF
LX
U1 ZCS
APW7083
PGND
EN
R5
100kW
C4
22mF
VIN
Applications
R1
COMP
GND
FB
1%
R2
1%
R4
C5
·
·
·
·
·
·
·
LCD Monitor / TV
C6
C7
(Optional)
SetTop Box
Portable DVD
Wireless LAN
ADSL, Switch HUB
Notebook Computer
Step-Down Converters Requiring High Efficiency
and 5A Output Current
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright ã ANPEC Electronics Corp.
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Rev. A.5 - Sep., 2011
APW7083
Ordering and Marking Information
Package Code
QB : TQFN5x6-28
APW7083
Operating Ambient Temperature Range
Assembly Material
Handling Code
I : -40 to 85 oC
Handling Code
TR : Tape & Reel
Assembly Material
Temperature Range
Package Code
G : Halogen and Lead Free Device
APW7083
XXXXX
APW7083 QB :
XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Pin Configuration
FB 1
COMP 2
ZCS 3
22 PGND
21 VIN
20 LX
PGND
LX
PGND 4
PGND 5
PGND 6
PGND 7
LX 8
19 LX
18 LX
17 LX
LX
16 LX
15 LX
TQFN5x6-28
(Top View)
= Thermal Pad (connected to copper plane for better heat dissipation)
Copyright ã ANPEC Electronics Corp.
Rev. A.5 - Sep., 2011
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APW7083
Absolute Maximum Ratings (Note 1)
Symbol
Parameter
Rating
-0.3 ~ 30
-1 ~ VIN +0.3
-5 ~ VIN +6
-0.3 ~ 6.5
VIN+0.3
Unit
VIN
VIN Supply Voltage (VIN to GND)
V
> 100ns
< 100ns
VLX
LX to GND Voltage
ZCS to GND Voltage
V
V
VZCS
V
V
IN > 6.2V
IN £ 6.2V
VCC
VCC Supply Voltage (VCC to GND)
VUGND_GND UGND to GND Voltage
VVIN_UGND VIN to UGND Voltage
EN to GND Voltage
-0.3 ~ VIN+0.3
-0.3 ~ 6.5V
20
V
V
V
FB, COMP to GND Voltage
Maximum Junction Temperature
-0.3 ~ VCC +0.3
150
V
oC
oC
oC
TSTG
TSDR
Storage Temperature
-65 ~ 150
260
Maximum Lead Soldering Temperature, 10 Seconds
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Thermal Characteristics
Symbol
Parameter
Typical Value
Unit
Junction-to-Ambient Resistance in Free Air (Note 2)
75
oC/W
qJA
TQFN5x6-28
Note 2: qJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
Recommended Operating Conditions (Note 3)
Symbol
Parameter
Range
4.5 ~ 26
Unit
V
VIN
VIN Supply Voltage
VCC Supply Voltage
4.0 ~ 5.5
0.8 ~ 90% VIN
0 ~ 5
V
VOUT
IOUT
Converter Output Voltage
Converter Output Current
VCC Input Capacitor
V
A
0.22 ~ 2.2
0.22 ~ 2.2
-40 ~ 85
mF
mF
oC
oC
VIN-to-UGND Input Capacitor
Ambient Temperature
Junction Temperature
TA
TJ
-40 ~ 125
Note 3: Refer to the typical application circuits.
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Rev. A.5 - Sep., 2011
APW7083
Electrical Characteristics
Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=3.3V and TA=-40~85oC, unless
otherwise specified. VCC is regulated by an internal regulator. Typical values are at TA=25oC.
APW7083
Symbol
Parameter
Test Conditions
Unit
Min.
Typ.
Max.
SUPPLY CURRENT
IVIN
IVIN_SD
IVCC
VIN Supply Current
VFB = 0.85V, VEN = 3V, LX = Open
VEN = 0V, VIN = 26V
-
-
-
-
1.0
-
2.0
5
mA
mA
VIN Shutdown Supply Current
VCC Supply Current
VEN = 3V, VCC = 5.0V
0.7
-
-
mA
mA
IVCC_SD
VCC Shutdown Supply Current
VEN = 0V, VCC = 5.0V
1
VCC 4.2V LINEAR REGULATOR
Output Voltage
VIN = 5.2 ~ 26V, IO = 0 ~ 8mA
IO = 0 ~ 8mA
4.0
-60
8
4.2
-40
-
4.5
0
V
Load Regulation
mV
mA
Current-Limit
VCC > POR Threshold
30
VIN-TO-UGND 5.5V LINEAR REGULATOR
Output Voltage (VVIN-UGND
)
VIN = 6.2 ~ 26V, IO = 0 ~ 10mA
IO = 0 ~ 10mA
5.3
-80
10
5.5
-60
-
5.7
0
V
Load Regulation
mV
mA
Current-Limit
VIN = 6.2 ~ 26V
30
POWER-ON-RESET (POR) AND LOCKOUT VOLTAGE THRESHOLDS
VCC POR Voltage Threshold
VCC POR Hysteresis
VCC rising
3.7
-
3.9
0.15
2.5
4.1
-
V
V
V
V
EN Lockout Voltage Threshold
EN Lockout Hysteresis
VEN rising
2.4
-
2.6
-
0.2
VIN-to-UGND Lockout Voltage
Threshold
VVIN-UGND rising
-
-
3.5
0.2
-
-
V
V
VIN-to-UGND Lockout Hysteresis
REFERENCE VOLTAGE
VREF
Reference Voltage
-
0.8
-
-
V
TJ = 25oC, IOUT = 0A, VIN = 12V
-1
+1
TJ = -40 ~ 125oC, IOUT = 0 ~ 3A,
VIN = 4.5 ~ 26V
Output Voltage Accuracy
%
-2.5
-
+2.5
Line Regulation
Load Regulation
VIN = 4.5V to 26V, IOUT = 0A
IOUT < 1A
-
-
-
0.1
-0.3
-
-
-
%
%/A
IOUT = 1 ~ 5A
-0.53
OSCILLATOR AND DUTY
FOSC Oscillator Running Frequency
VIN = 4.5 ~ 26V
VFB = 0V
340
380
80
420
kHz
kHz
%
Foldback Frequency
-
-
-
-
-
-
Maximum Converter’s Duty Cycle
Minimum Pulse Width of LX
93
VIN = 4.5 ~ 26V
200
ns
CURRENT-MODE PWM CONVERTER
Gm
Error Amplifier Transconductance
Error Amplifier DC Gain
-
400
80
-
-
mA/V
COMP = Open
60
dB
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Rev. A.5 - Sep., 2011
APW7083
Electrical Characteristics (Cont.)
Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=3.3V and TA=-40~85oC, unless
otherwise specified. VCC is regulated by an internal regulator. Typical values are at TA=25oC.
APW7083
Symbol
Parameter
Test Conditions
Unit
Min.
Typ.
Max.
CURRENT-MODE PWM CONVERTER (CONT.)
Current-Sense Resistance
-
-
0.12
50
-
W
Between VIN and Exposed Pad,
TJ = 25oC
High-side Switch Resistance
80
mW
Between GND and Exposed Pad,
TJ = 25oC
Low-side Switch Resistance
-
20
30
mW
PROTECTIONS
P-Channel Power MOSFET
Current-Limit
ILIM
Peak Current
VFB falling
6
8
10
A
VUV
FB Under-Voltage Threshold
FB Under-Voltage Hysteresis
FB Under-Voltage Debounce
FB Over-Voltage Threshold
FB Over-Voltage Hysteresis
Over-Temperature Trip Point
Over-Temperature Hysteresis
Dead-Time
66
70
40
2
74
%
mV
ms
-
-
-
-
VOV
TOTP
TD
VFB Rising
114
118
40
150
50
30
122
%
-
-
-
-
-
-
-
-
mV
oC
oC
ns
VLX = -0.7V, VIN = 4.5 ~ 26V
SOFT-START, ENABLE, AND INPUT CURRENTS
tSS
Soft-Start Interval
-
-
8
11
-
-
-
ms
ms
V
Preceding Delay before Soft-Start
EN Logic Low Voltage
EN Logic High Voltage
EN Pin Clamped Voltage
VEN falling, VIN = 4.5 ~ 26V
VEN rising, VIN = 4.5 ~ 26V
IEN = 10mA
-
0.5
-
2.1
12
-
V
-
17
V
P-Channel Power MOSFET Leakage
Current
VEN = 0V, VLX = 0V, VIN = 26V
-
-
4
mA
IFB
IEN
FB Pin Input Current
EN Pin Input Current
VFB = 0.8V
VEN < 3V
-100
-500
-
-
+100
+500
mA
mA
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Rev. A.5 - Sep., 2011
APW7083
Typical Operating Characteristics
Reference Voltage vs.
Oscillator Frequency vs.
Junction Temperature
Junction Temperature
420
410
400
390
380
370
360
350
340
0.816
0.812
0.808
0.804
0.800
0.796
0.792
0.788
0.784
-50 -25
0
25 50 75 100 125 150
-50 -25
0
25 50 75 100 125 150
Junction Temperature, TJ (oC)
Junction Temperature, TJ (oC)
Output Voltage vs. Supply Voltage
Output Voltage vs. Output Current
3.34
3.36
3.35
3.34
3.33
3.32
3.31
3.30
3.29
3.28
3.27
3.26
3.25
3.24
3.33
3.32
3.31
3.30
3.29
3.28
3.27
3.26
IOUT=0.2A
IOUT=1A
IOUT=2A
IOUT=3A
VIN =12V, VOUT =3.3V
5
4
0
1
2
3
4
6
8
10 12 14 16 18 20 22
Supply Voltage, VIN (V)
Output Current, IOUT (A)
Current-Limit Level (Peak Current)
vs. Junction Temperature
VIN Input Current vs. SupplyVoltage
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
9.0
8.5
8.0
7.5
7.0
6.5
6.0
VFB=0.85V
-50 -25
0
25 50 75 100 125 150
0
2
4
6
8
10 12 14 16 18 20 22
VIN Supply Voltage, VIN (V)
Junction Temperature, TJ (oC)
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Rev. A.5 - Sep., 2011
APW7083
Typical Operating Characteristics (Cont.)
Efficiency vs. Output Current
EN Clamp Voltage vs. EN Input Current
100
90
18
16
14
12
10
8
VOUT =5V
80
70
60
TJ=-30 C
VOUT =3.3V
50
40
30
TJ=25C
6
4
TJ=100C
20
10
0
VIN =12V, L1=3.3mH,
C4 =66mF, C1 =10mF
2
0
0.001
0.01
0.1
1
10
1
10
100
1000
10000
Output Current, IOUT (A)
EN Input Current, IEN (mA)
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Rev. A.5 - Sep., 2011
APW7083
Operating Waveforms
Refer to the “Typical Application Circuit”. The test conditions are VIN=12V, VOUT=3.3V, L1=3.3mH, C4=66mF, TA= 25oC
unless otherwise specified.
Load Transient Response
Load Transient Response
IOUT=50mA-5A-50mA,
rise/fall time=10ms
IOUT=1A-5A-1A,
rise/fall time=10ms
1
1
VOUT
VOUT
IL1
IL1
2
2
CH1: VOUT, 200mV/Div, offset=3.3V
CH2: IL1, 2A/Div, DC
CH1: VOUT, 200mV/Div, offset=3.3V
CH2: IL1, 2A/Div, DC
TIME: 100ms/Div
TIME: 100ms/Div
Power On
Power Off
IOUT=5A
IOUT=5A
VIN
VIN
1
1
VOUT
VOUT
2
3
2
3
IL1
IL1
CH1: VIN, 5V/Div, DC
CH2: VOUT, 2V/Div, DC
CH3: IL1, 5A/Div, DC
TIME:5ms/Div
CH1: VIN, 5V/Div, DC
CH2: VOUT, 2V/Div, DC
CH3: IL1, 5A/Div, DC
TIME:5ms/Div
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Rev. A.5 - Sep., 2011
APW7083
Operating Waveforms (Cont.)
Refer to the “Typical Application Circuit”. The test conditions are VIN=12V, VOUT=3.3V, L1=3.3mH, C4=66mF, TA= 25oC
unless otherwise specified.
Enable Through EN Pin
Shutdown Through EN Pin
IOUT=5A
IOUT=5A
VEN
VOUT
IL1
VEN
1
1
VOUT
2
3
2
3
IL1
CH1: VEN, 5V/Div, DC
CH2: VOUT, 2V/Div, DC
CH3: IL1, 5A/Div, DC
TIME:5ms/Div
CH1: VEN, 5V/Div, DC
CH2: VOUT, 2V/Div, DC
CH3: IL1, 5A/Div, DC
TIME:5ms/Div
Over Current
Short Circuit
VOUT is shorted to ground by a wire
0.3Ωload isswitchedintoVOUT
while IOUT=1A
VOUT
1
VOUT
1
IL1
IL1
2
2
CH1: VOUT, 1V/Div, DC
CH2: IL1, 5A/Div, DC
TIME:50ms/Div
CH1: VOUT, 1V/Div, DC
CH2: IL1, 5A/Div, DC
TIME: 50ms/Div
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Rev. A.5 - Sep., 2011
APW7083
Operating Waveforms (Cont.)
Refer to the “Typical Application Circuit”. The test conditions are VIN=12V, VOUT=3.3V, L1=3.3mH, C4=66mF, TA= 25oC
unless otherwise specified.
Switching Waveform
Switching Waveform
IOUT=5A
IOUT=0.5A
VLX
VLX
1
2
1
2
IL1
IL1
CH1: VLX, 5V/Div, DC
CH2: IL1, 2A/Div, DC
TIME: 1ms/Div
CH1: VLX, 5V/Div, DC
CH2: IL1, 2A/Div, DC
TIME: 1ms/Div
Line Transient Response
VIN=12 to 20V, rise/fall
time=10ms, IOUT=1A
VIN
1
2
VOUT
CH1: VIN, 10V/Div, DC
CH2: VOUT, 100mV/Div, offset=3.3V
TIME: 100ms/Div
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Rev. A.5 - Sep., 2011
APW7083
Pin Description
PIN
FUNCTION
NO.
NAME
Feedback Input. The IC senses feedback voltage via FB and regulate the voltage at 0.8V.
Connecting FB with a resistor-divider from the output set the output voltage in the range from
0.8V to 90% VIN.
1
FB
Output of error amplifier. Connect a series RC network from COMP to GND to compensate the
regulation control loop. In some cases, an additional capacitor from COMP to GND is required
for noise decoupling.
2
COMP
3
ZCS
PGND
LX
Zero-Crossing Sense pin. Please externally connect this pin with LX.
4~7, 22
8~20
POWER Ground pins. All these pins must be connected externally to the power ground plane.
Power Switching Output. Connect this pin to the underside Exposed Pad.
Power Input. VIN supplies the power (4.5V to 26V) to the control circuitry, gate driver and
step-down converter switch. Connecting a ceramic bypass capacitor and a suitably large
capacitor between VIN and GND eliminates switching noise and voltage ripple on the input to
the IC.
21, 23, 24
VIN
EN
Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn on the
regulator, drive it low to turn it off. Pull up with 100kW resistor for automatic start-up.
25
26
Gate driver power ground of the P-channel Power MOSFET. A linear regulator regulates a 5.5V
voltage between VIN and UGND to supply power to P-channel MOSFET gate driver. Connect
a ceramic capacitor (1mF typ.) between VIN and UGND for noise decoupling and stability of the
linear regulator.
UGND
Bias input and 4.2V linear regulator’s output. This pin supplies the bias to some control circuits.
The 4.2V linear regulator converts the voltage on VIN to 4.2V to supply the bias when no
external 5V power supply is connected with VCC. Connect a ceramic capacitor (1mF typ.)
between VCC and GND for noise decoupling and stability of the linear regulator.
27
28
VCC
GND
Signal Ground.
Block Diagram
VIN
Current Sense
Amplifier
4.2V Regulator
Current-
Limit
and
VCC
Power-On-Reset
VCC
Zero-Crossing
Comparator
ZCS
POR
UG
OVP
118%VREF
70%VREF
Soft-Start
and
Fault Logic
Gate
Driver
UGND
LX
UVP
Soft-Start
Inhibit
Gate
Control
FB
VCC
Gm
VREF
0.8V
Error
Amplifier
LG
Current
Compartor
Gate
Driver
PGND
COMP
Slope
Compensation
ENOK
2.5V
0.8V
Linear
Regulator
Oscillator
380kHz
Over-
Temperature
Protection
Enable
EN
FB
VIN
GND
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Rev. A.5 - Sep., 2011
APW7083
Typical Application Circuit
4.5~26V Single Power Input Step-down Converter (with Ceramic Input/Output Capacitors)
VIN
4.5~26V
C1
10mF
21, 23, 24
VIN
C2
1mF
27
26
L1
5A
VCC
UGND
C3
1mF
8~20
3
LX
VOUT
0.8V~90%VIN/5A
U1
APW7083
ZCS
C4
22mF
R5
100kW
4~7, 22
25
2
PGND
VIN
EN
R1
1%
1
COMP
FB
R4
3kW
GND
28
R2
1%
C6
22pF
C7
(Optional)
C5
4700pF
Recommended Feedback Compensation Network Components List:
L1
(mH)
C4
(mF)
C4 ESR
(mW)
R1
(kW)
R2
(kW)
R4
(kW)
VIN
(V)
VOUT
(V)
C7
(pF)
C5
(pF)
C6
(pF)
12
12
12
5
3.3
3.3
3.3
66
66
66
3
3
3
63.4
47
12
15
15
68
82
24
20
12
1000
1500
2200
22
22
22
3.3
1.2
7.5
270
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Rev. A.5 - Sep., 2011
APW7083
Function Description
Main Control Loop
good noise decoupling, please place the capacitor physi-
cally close to the IC. The linear regulator is not intended
for powering up any external loads. Do not connect any
external load to VCC. The linear regulator is also equipped
with current-limit protection to protect itself during over-
load or short-circuit conditions on VCC pin.
The APW7083 is a constant frequency current mode
switching regulator. During normal operation, the inter-
nal P-channel power MOSFET is turned on each cycle
when the oscillator sets an internal RS latch and would
be turned off when an internal current comparator (ICMP)
resets the latch. The peak inductor current at which ICMP
resets the RS latch is controlled by the voltage on the
COMP pin, which is the output of the error amplifier
(EAMP). An external resistive divider connected between
VOUT and ground allows the EAMP to receive an output
feedback voltage VFB at FB pin. When the load current
increases, it causes a slight decrease in VFB relative to
the 0.8V reference, which in turn causes the COMP volt-
age to increase until the average inductor current matches
the new load current.
VIN-to-UGND 5.5V Linear Regulator
The built-in 5.5V linear regulator regulates a 5.5V voltage
between VIN and UGND pins to supply bias and gate
charge for the P-channel Power MOSFET gate driver. The
linear regulator is designed to be stable with a low-ESR
ceramic output capacitor of at least 0.22mF. It is also
equipped with current-limit function to protect itself dur-
ing over-load or short-circuit conditions between VIN and
UGND.
The APW7083 shuts off the output of the converters
when the output voltage of the linear regulator is below
3.5V (typical). The IC resumes working by initiating a new
soft-start process when the linear regulator’s output
voltage is above the undervoltage lockout voltage
threshold.
VCC Power-On-Reset (POR) and EN Undervoltage
Lockout
The APW7083 keeps monitoring the voltage on VCC pin
to prevent wrong logic operations which may occur when
VCC voltage is not high enough for the internal control
circuitry to operate. The VCC POR has a rising threshold
of 3.9V (typical) with 0.15V of hysteresis.
Digital Soft-Start
The APW7083 has a built-in digital soft-start to control
the output voltage rise and limit the input current surge
during start-up. During soft-start, an internal ramp, con-
nected to the one of the positive inputs of the error
amplifier, rises up from 0V to 1V to replace the reference
voltage (0.8V) until the ramp voltage reaches the refer-
ence voltage.
An external undervoltage lockout (UVLO) is sensed and
programmed at the EN pin. The EN UVLO has a rising
threshold of 2.5V with 0.2V of hysteresis. The EN UVLO
should be programmed by connecting a resistive divider
from VIN to EN to GND.
After the VCC, EN, and VIN-to-UGNDvoltages exceed their
respective voltage thresholds, the IC starts a start-up pro-
cess and then ramps up the output voltage to the setting
of output voltage. Connecting a RC network from EN to
GND is for setting a turn-on delay that can be used to
sequence the output voltages of multiple devices.
The device is designed with a preceding delay about
10.8ms (typical) before soft-start process.
Enable/Shutdown
Driving EN to ground places the APW7083 in shutdown.
When in shutdown, the internal power MOSFET turns off,
all internal circuitry shuts down and the quiescent supply
current of VIN reduces to <1mA (typical).
VCC 4.2V Linear Regulator
VCC is the output terminal of the internal 4.2V linear regu-
lator which is powered from VIN and provides power to
the APW7083. The linear regulator designed to be stable
with a low-ESR ceramic output capacitor powers the in-
ternal control circuitry, then bypasses VCC to GND with a
ceramic capacitor of at least 0.22mF. In order to provide
Output Under-Voltage Protection
In the process of operation, if a short-circuit occurs, the
output voltage will drop quickly. Before the current-limit
circuit responds, the output voltage will fall out of the re-
Copyright ã ANPEC Electronics Corp.
13
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Rev. A.5 - Sep., 2011
APW7083
Function Description (Cont.)
Output Under-Voltage Protection (Cont.)
FrequencyFoldback
quired regulation range. The under-voltage continually
monitors the FB voltage after soft-start is completed. If a
load step is strong enough to pull the output voltage lower
than the under-voltage threshold, the IC shuts down
converter’s output. The under-voltage threshold is 70%
of the nominal output voltage. The under-voltage com-
parator has a built-in 2ms noise filter to prevent the chips
from wrong UVP shutdown caused by noise. The under-
voltage protection works in a hiccup mode without latched
shutdown. The IC will initiate a new soft-start process at
the end of the proceeding delay.
When the output is shortened to the ground, the frequency
of the oscillator will be reduced to about 80kHz. This lower
frequency allows the inductor current to safely discharge,
thereby preventing current runaway. The oscillator’s fre-
quency will gradually increase to its designed rate when
the feedback voltage on FB approaches 0.8V again.
Over-Temperature Protection (OTP)
The over-temperature circuit limits the junction tempera-
ture of the APW7083. When the junction temperature ex-
ceeds TJ = +150oC, a thermal sensor turns off the power
MOSFET, allowing the devices to cool. The thermal sen-
sor allows the converter to start a start-up process and
regulate the output voltage again after the junction tem-
perature cools by 50oC. The OTP is designed with a 50oC
hysteresis to lower the average TJ during continuous ther-
mal overload conditions, increasing lifetime of the IC.
Over-Voltage Protection
The over-voltage function monitors the output voltage by
FB pin. The FB voltage should increase over 118% of the
reference voltage due to the high-side MOSFET failure,
or for other reasons, the over-voltage protection
comparator, will force the low-side MOSFET gate driver
high. As soon as the output voltage is within regulation,
the OVP comparator is disengaged. The chips will re-
store its normal operation. This OVP scheme only clamps
the voltage overshoot, and does not invert the output volt-
age when otherwise activated with a continuously high
output from low-side MOSFET driver - a common prob-
lem for OVP schemes with a latch.
Current-Limit Protection
TheAPW7083 monitors the output current, flowing through
the P-channel power MOSFET, and limits the current peak
at current-limit level to prevent loads and the IC from dam-
ages during overload or short-circuit conditions.
Copyright ã ANPEC Electronics Corp.
14
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Rev. A.5 - Sep., 2011
APW7083
Application Information
VIN
Power Sequencing
VIN
LX
IQ1
CIN
The APW7083 can operate with single or dual power input
(s). In dual-power application, the voltage (VCC) applied at
VCC pin must be lower than the voltage (VIN) on VIN pin.
The internal parasitic diode from VCC to VIN will conduct
due to the forward-voltage between VCC and VIN.
Therefore, VIN must be provided before VCC.
Q1
Q2
IOUT
IL
VOUT
L
ESR
COUT
ICOUT
Setting Output Voltage
T=1/FOSC
The regulated output voltage is determined by:
R1
VOUT = 0.8×(1+
)
(V)
R2
VLX
DT
I
Suggested R2 is in the range from 1k to 20kW. For por-
table applications, a 10k resistor is suggested for R2. To
prevent stray pickup, please locate resistors R1 and R2
close to APW7083.
IOUT
IL
IOUT
IQ1
Input Capacitor Selection
I
Use small ceramic capacitors for high frequency
decoupling and bulk capacitors to supply the surge cur-
rent needed each time the P-channel power MOSFET (Q1)
turns on. Place the small ceramic capacitors physically
close to the VIN and between the VIN and GND.
ICOUT
VOUT
VOUT
The important parameters for the bulk input capacitor are
the voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and cur-
rent ratings above the maximum input voltage and larg-
est RMS current required by the circuit. The capacitor volt-
age rating should be at least 1.25 times greater than the
maximum input voltage and a voltage rating of 1.5 times
is a conservative guideline. The RMS current (IRMS) of the
bulk input capacitor is calculated as the following equation:
Figure 1. Converter Waveforms
Output Capacitor Selection
An output capacitor is required to filter the output and sup-
ply the load transient current. The filtering requirements
are a function of the switching frequency and the ripple
current (DI). The output ripple is the sum of the voltages,
having phase shift, across the ESR and the ideal output
capacitor. The peak-to-peak voltage of the ESR is calcu-
lated as the following equations:
IRMS =IOUT × D×(1-D)
(A)
VOUT
where D is the duty cycle of the power MOSFET.
D =
........... (1)
V
IN
For a through hole design, several electrolytic capacitors
may be needed. For surface mount designs, solid tanta-
lum capacitors can be used, but caution must be exer-
cised with regard to the capacitor surge current rating.
VOUT ·(1-D)
FOSC ·L
DI =
........... (2)
........... (3)
VESR = DI×ESR
The peak-to-peak voltage of the ideal output capacitor is
calculated as the following equations:
Copyright ã ANPEC Electronics Corp.
15
www.anpec.com.tw
Rev. A.5 - Sep., 2011
APW7083
Application Information (Cont.)
and greater core losses. A reasonable starting point for
setting ripple current is DI £ 0.4 × IOUT(MAX). Remember, the
maximum ripple current occurs at the maximum input
voltage. The minimum inductance of the inductor is cal-
culated by using the following equation:
Output Capacitor Selection (Cont.)
D I
DVCOUT =
(V)
........... (4)
8×FOSC ×COUT
For the applications using bulk capacitors, the DVCOUT is
much smaller than the VESR and can be ignored. Therefore,
the AC peak-to-peak output voltage (DVOUT ) is shown as
below:
VOUT ·(VIN - VOUT)
£ 2
380000 ·L ·VIN
VOUT ·(VIN - VOUT)
DVOUT = D I×ESR
(V)
........... (5)
........... (6)
L ³
(H)
760000 ·VIN
For the applications using ceramic capacitors, the VESR is
much smaller than the DVCOUT and can be ignored.
Therefore, the AC peak-to-peak output voltage (DVOUT ) is
where VIN = VIN(MAX)
Layout Consideration
close to DVCOUT
.
In high power switching regulator, a correct layout is im-
portant to ensure proper operation of the regulator. In
general, interconnecting impedance should be minimized
by using short, wide printed circuit traces. Signal and
power grounds are to be kept separating and finally com-
bined using ground plane construction or single point
grounding. Figure 2 illustrates the layout, with bold lines
indicating high current paths. Components along the bold
lines should be placed close together. The following is a
checklist for your layout:
The load transient requirement is a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of ca-
pacitors and careful layout. High frequency capacitors ini-
tially supply the transient and slow the current load rate
seen by the bulk capacitors. The bulk filter capacitor val-
ues are generally determined by the ESR (Effective Se-
ries Resistance) and voltage rating requirements rather
than actual capacitance requirements.
High frequency decoupling capacitors should be placed
as close to the power pins of the load as physically
possible. Be careful not to add inductance in the circuit
board wiring that could cancel the usefulness of these
low inductance components. An aluminum electrolytic
capacitor’s ESR value is related to the case size with lower
ESR available in larger case sizes. However, the Equiva-
lent Series Inductance (ESL) of these capacitors increases
with case size and can reduce the usefulness of the ca-
pacitor to high slew-rate transient loading.
1. Firstly, to initial the layout by placing the power
components. Orient the power circuitry to achieve a clean
power flow path. If possible, make all the connections on
one side of the PCB with wide, copper filled areas.
2. In Figure 2, the loops with the same color bold lines
conduct high slew rate current. These interconnecting
impedances should be minimized by using wide, short
printed circuit traces.
3. Keep the sensitive small signal nodes (FB, COMP)
away from switching nodes (LX or others) on the PCB.
Therefore, place the feedback divider and the feedback
compensation network close to the IC to avoid switching
noise. Connect the ground of feedback divider directly to
the GND pin of the IC using a dedicated ground trace.
4. The VCC decoupling capacitor should be right next to
the VCC andGND pins. Capacitor C2 should be connected
as close to the VIN and UGND pins as possible.
Inductor Value Calculation
The operating frequency and inductor selection are inter-
related in that higher operating frequencies permit the
use of a smaller inductor for the same amount of inductor
ripple current. However, this is at the expense of efficiency
due to an increase in MOSFET gate charge losses. The
equation (2) shows that the inductance value has a direct
effect on ripple current.
5. Place the decoupling ceramic capacitor C1 near the
VIN as close as possible. The bulk capacitors C8 are also
placed near VIN. Use a wide power ground plane to con-
nect the C1, C8, and C4 to provide a low impedance
Accepting larger values of ripple current allows the use of
low inductances, but results in higher output voltage ripple
Copyright ã ANPEC Electronics Corp.
16
www.anpec.com.tw
Rev. A.5 - Sep., 2011
APW7083
Application Information (Cont.)
Layout Consideration (Cont.)
5mm
0.34mm
path between the components for large and high slew
rate current.
1.85mm
1.38mm
+
21 23
VIN
VIN
-
24
C2
0.225mm
PGND
CIN
26
27
LOUT
UGND
VCC
8~20
3
LX
+
COUT
L
ZCS
o
a
d
C3
LX
APW7083
VOUT
25
2
4~7,22
1
EN
-
PGND
RTOP
COMP
FB
C6
LX
R4
C3
GND
28
CTOP
Feedbac
k Divider
RGND
*Just
Recommend
Figure 2. Current Path Diagram
0.45
0.45
3.57mm
0.265mm
mm mm*
Figure 4. Recommended Minimum Footprint
Power
Ground
VIN
CIN
FB 1
22 PGND
21 VIN
20 LX
19 LX
18 LX
17 LX
COMP 2
ZCS 3
PGND
LX
PGND 4
PGND 5
PGND 6
PGND 7
LX 8
VOUT
COUT
LX
16 LX
15 LX
LOUT
For dissipating heat
Figure 3. Recommended Layout Diagram
Copyright ã ANPEC Electronics Corp.
17
www.anpec.com.tw
Rev. A.5 - Sep., 2011
APW7083
Package Information
TQFN5x6-28
D
A
Pin 1
A1
A3
D1
H
D2
Pin 1 Corner
D3
e
TQFN5x6-28
S
Y
M
B
O
MILLIMETERS
INCHES
MIN.
MAX.
MIN.
MAX.
0.032
0.002
L
A
0.70
0.00
0.80
0.05
0.028
0.000
A1
A3
b
0.20 REF
0.008 REF
0.010
0.232
0.107
0.059
0.071
0.193
0.071
0.139
0.052
0.014
0.240
0.111
0.063
0.075
0.201
0.075
0.143
0.056
0.25
0.35
6.10
2.81
1.60
1.90
5.10
1.90
3.62
1.43
D
5.90
2.71
1.50
1.80
4.90
1.80
3.52
1.33
D1
D2
D3
E
E1
E2
E3
e
0.65 BSC
0.34 REF
0.026 BSC
0.013 REF
0.014
0.008
0.018
L
0.35
0.20
0.45
K
H
Copyright ã ANPEC Electronics Corp.
18
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Rev. A.5 - Sep., 2011
APW7083
Carrier Tape & Reel Dimensions
P0
P2
P1
OD0
A
K0
A0
A
OD1
B
B
SECTION A-A
SECTION B-B
d
T1
Application
TQFN5x6-28
A
H
T1
12.4+2.00 13.0+0.50
-0.00 -0.20
P2 D0
C
d
D
W
E1
F
330.0±2.00 50 MIN.
1.5 MIN.
D1
20.2 MIN. 12.0±0.30 1.75±0.10
5.5±0.10
K0
P0
P1
8.0±0.10
T
A0
B0
1.5+0.10
-0.00
4.0±0.10
2.0±0.10
1.5 MIN.
0.3±0.05
6.5±0.10
5.3±0.10
1.4±0.10
(mm)
Devices Per Unit
Package Type
TQFN5x6-28
Unit
Quantity
2500
Tape & Reel
Copyright ã ANPEC Electronics Corp.
19
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Rev. A.5 - Sep., 2011
APW7083
Taping Direction Information
TQFN5x6-28
USER DIRECTION OF FEED
Classification Profile
Copyright ã ANPEC Electronics Corp.
20
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Rev. A.5 - Sep., 2011
APW7083
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
Preheat & Soak
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
Temperature min (Tsmin
)
Temperature max (Tsmax
)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
3 °C/second max.
3 °C/second max.
Liquidous temperature (TL)
Time at liquidous (tL)
183 °C
60-150 seconds
217 °C
60-150 seconds
Peak package body Temperature
(Tp)*
See Classification Temp in table 1
20** seconds
See Classification Temp in table 2
30** seconds
Time (tP)** within 5°C of the specified
classification temperature (Tc)
Average ramp-down rate (Tp to Tsmax
)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Volume mm3
350
Package
Thickness
<2.5 mm
³ 2.5 mm
Volume mm3
<350
235 °C
220 °C
220 °C
220 °C
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
Volume mm3
Volume mm3
350-2000
260 °C
Volume mm3
<350
260 °C
260 °C
250 °C
>2000
260 °C
245 °C
245 °C
1.6 mm – 2.5 mm
³ 2.5 mm
250 °C
245 °C
Reliability Test Program
Test item
SOLDERABILITY
HOLT
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
Description
5 Sec, 245°C
1000 Hrs, Bias @ Tj=125°C
PCT
TCT
HBM
MM
168 Hrs, 100 RH, 2atm, 121 C
%
°
500 Cycles, -65°C~150°C
VHBM≧2KV
VMM≧200V
10ms, 1tr≧100mA
Latch-Up
Copyright ã ANPEC Electronics Corp.
21
www.anpec.com.tw
Rev. A.5 - Sep., 2011
APW7083
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright ã ANPEC Electronics Corp.
Rev. A.5 - Sep., 2011
22
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