APW8713QBI-TRL [ANPEC]
High Input Voltage 8A PWM Converter With Adj. Soft Start; 高输入电压8A PWM变换器中，ADJ 。软启动
| 型号： | APW8713QBI-TRL |
| 厂家： | 
ANPEC ELECTRONICS COROPRATION |
| 描述： | High Input Voltage 8A PWM Converter With Adj. Soft Start |
| 文件： | 总24页 (文件大小：801K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APW8713
High Input Voltage 8A PWM Converter With Adj. Soft Start
Features
General Description
The APW8713 is a 8A, synchronous, step-down converter
·
Adjustable Output Voltage from +0.8V to +12V
with integrated 30mW N-channel High-Side MOSFET and
9mW Low-Side MOSFET. The APW8713 steps down high
voltage to generate low-voltage chipset or RAM supplies
in notebook computers.
- 0.8V Reference Voltage
- +1% Accuracy over Temperature
Operates from An Input Battery Voltage Range of
+2.7V to +28V
·
The APW8713 provides excellent transient response and
accurate DC voltage output in either PFM or PWM Mode.
In Pulse Frequency Mode (PFM), the APW8713 provides
very high efficiency over light to heavy loads with loading-
modulated switching frequencies. In PWM Mode, the con-
verter works nearly at constant frequency for low-noise
requirements.
·
·
·
·
Power-On-Reset Monitoring on VCC pin
Excellent line and load transient responses
PFM mode for increased light load efficiency
Programmable PWM Frequency from 100kHz to
1000kHz
·
·
Integrated 30mW at VCC=5V N-Channel MOSFET
For High Side
The APW8713 is equipped with accurate current-limit,
output under-voltage, and output over-voltage protections,
perfect for various applications. A Power-On-Reset func-
tion monitors the voltage on VCC to prevent wrong
operation during power-on. The APW8713 has external
adjustable soft-start and built-in an integrated output dis-
charge method for soft stop. A soft-start ramps up the
output voltage with programmable timing to reduce the
start-up current. A soft-stop function actively discharges
the output capacitors.
Integrated9mW atVCC=5VN-ChannelMOSFETFor
Low Side
·
·
·
Integrated Bootstrap Forward P-CH MOSFET
External Adjustable Soft-Start and Soft-Stop
Selectable Forced PWM or automatic PFM/PWM
mode
·
·
·
·
Power Good Monitoring
70% Under-Voltage Protection
125% Over-Voltage Protection
Current-Limit Protection
The APW8713 is available in TQFN4x4-23 (Power PAK).
- Using Sense Low-Side MOSFET’s RDS(ON)
Over-Temperature Protection
TQFN-23 4mmx4mm package
Lead Free and Green Device Available (RoHS
Compliant)
Applications
·
·
·
·
·
·
·
·
·
·
Notebook
Mother Board
Table PC
Hand-Held Portable
AIO PC
Set-top boxes
LCD TV
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright ã ANPEC Electronics Corp.
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Rev. A.3 - Sep., 2013
APW8713
Simplified Application Circuit
VCC
EN
RPOK
VIN
POK
VIN
LX
H / L
PFM
LOUT
VOUT
CSS
SS
COUT
APW8713
Ordering and Marking Information
Package Code
QB: TQFN4x4-23
Operating Ambient Temperature Range
APW8713
Assembly Material
Handling Code
°
I : -40 to 85 C
Handling Code
TR : Tape & Reel
Lead Free Code
Temperature Range
Package Code
L : Lead Free Device G : Halogen and Lead Free Device
APW8713
XXXXX
XXXXX - Date Code
APW8713 QB :
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Pin Configuration
POK 1
EN 2
17 LX
16 LX
PFM 3
AGND 4
FB 5
15 PGND
14 PGND
13 PGND
12 PGND
VIN
LX
TON 6
TQFN 4x4 -23 (TOP VIEW)
= Exposed and Thermal Pad
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APW8713
Absolute Maximum Ratings (Note 1)
Symbol
VVCC
Parameter
VCC Supply Voltage (VCC to AGND)
Rating
-0.3 ~ 7
Unit
V
VIN
VIN Supply Voltage (VIN to AGND)
TON Supply Voltage (TON to AGND)
BOOT Supply Voltage (BOOT to AGND)
BOOT Supply Voltage (BOOT to PHASE)
-0.3 ~ 30
-0.3 ~ 30
-0.3 ~ 37
-0.3 ~ 7
V
VTON
V
VBOOT-GND
VBOOT
VGND
V
V
AGND to PGND
-0.3 ~ +0.3
-0.3 ~ 7
V
All Other Pins (POK, EN, FB, SS and PFM to AGND)
LX Voltage (LX to GND)
V
-5 ~ 32
-0.3 ~ 30
VLX
V
<20ns pulse width
>20ns pulse width
TJ
150
-65 ~ 150
260
oC
oC
oC
Junction Temperature
Storage Temperature
TSTG
TSDR
Maximum Lead Soldering Temperature(10 Seconds)
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recom-
mended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Thermal Characteristics
Symbol
Parameter
Typical Value
Unit
Junction-to-Ambient Resistance in free air (Note 2)
50
oC/W
qJA
Note 2: qJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
Recommended Operating Conditions (Note 3)
Symbol
VVCC
VIN
Parameter
Range
4.5 ~ 5.5
2.7 ~ 28
0.8 ~ 13.2
0 ~ 8
Unit
V
VCC Supply Voltage
Converter Input Voltage
Converter Output Voltage
Converter Output Current
V
VOUT
IOUT
CIN
V
A
PWM1/2 Converter Input Capacitor (MLCC)
VCC Output Capacitor (MLCC)
Ambient Temperature
10 ~
mF
mF
oC
oC
CVCC
TA
1.0 ~
-40 ~ 85
-40 ~ 125
Junction Temperature
TJ
Note 3: Refer to the application circuit for further information.
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APW8713
Electrical Characteristics
Unless otherwise specified, these specifications apply over VIN=12V,VEN=5V and TA= -40 to 85oC. Typical values are at TA=25oC.
APW8713
Symbol
Parameter
Test Condition
Min.
0.8
Typ.
Max.
Unit
VOUT AND VFB VOLTAGE
VOUT
VREF
Output Voltage
Adjustable output range
13.2
V
V
Reference Voltage
Regulation Accuracy
FB Input Bias Current
0.8
-
TA = -40 oC ~ 85 oC
FB=0.75V
-1.0
+1.0
-
%
mA
IFB
0.02
EN go low to output remain below
0.1V
TSTOP
Output Discharge Time
-
5*Tss
-
-
SUPPLY CURRENT
IVCC_NOR
MAL
VCC Quiescent Supply
Current
EN=5V, FB=0.835V, VCC=5V
EN=GND, VCC=5V
-
-
0.7
-
1
mA
mA
IVCC_SHD
VCC Shutdown Current
25
N
ON-TIME TIMER AND INTERNAL SOFT START
TON
FSW
Nominal on time
200
250
300
ns
kHz
ns
VIN=12V, VOUT=1V, RTON=100kW
Frequency adjustable range
Minimum off time
100
1000
TOFF(MIN)
ISS
VFB=0.75V, VPHASE=-0.1V
Vss=0V，Css=0.001uF to 0.1uF
EN High to POK High
-
8
-
250
10
-
12
-
Internal Soft Start Current
Internal Soft Start Time
mA
TSS
330*Css
ms
GATE DRIVER
High Side MOSFET On
Resistance
VIN=12V，VCC=5V
VIN=12V，VCC=5V
-
-
30
9
45
mW
mW
Low Side MOSFET On
Resistance
13.5
BOOTSTRAP SWITCH
VF
IR
Ron
VPVCC – VBOOT-GND, IF = 10mA
-
-
0.5
-
0.7
0.5
V
VBOOT-GND = 30V, VPHASE = 25V,
VPVCC = 5V
Reverse Leakage
mA
VCC POR THRESHOLD
Falling VCC POR Threshold
VLCC_THF
4.25
-
4.35
100
4.45
-
V
Voltage
LDO POR Hysteresis
mV
CONTROL INPUTS
EN High-Level Input Voltage
2.5
-
-
-
0.5
-
V
V
EN Low-Level Input Voltage
EN Leakage
-
EN=0V
-
2.5
-
0.1
-
mA
V
PFM High-Level Input Voltage
PFM Low-Level Input Voltage
PFM Leakage
-
-
0.5
-
V
PFM=0V
-
0.1
mA
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APW8713
Electrical Characteristics
Unless otherwise specified, these specifications apply over VIN=12V,VEN=5V and TA= -40 to 85oC. Typical values are at TA=25oC.
APW8713
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
POWER-OK INDICATOR
POK in from Lower (POK Goes
High)
87
90
93
%
%
VPOK
POK Threshold
POK out from Normal (POK Goes
Low)
120
125
130
IPOK
POK Leakage Current
POK Sink Current
VPOK=5V
-
0.1
7.5
20
-
-
-
-
mA
mA
ms
VPOK=0.5V，
1.25
POK Out Debounce Time2
POK Enable Delay Time
When run away 90%
From EN High to POK High
-
-
Tss
ms
CURRENT SENSE
IOCP OCP Threshold
Valley Current of IL
11
-5
-
-
A
Zero Crossing Comparator
Offset
VGND-LX Voltage, PFM=0V
0
5
mV
PROTECTION
VUV
UVP Threshold
65
70
16
75
%
ms
ms
%
UVP Debounce Interval
UVP Enable Delay
EN high to UVP workable
OVP Occur
Tss
125
3
VOVR
OVP Rising Threshold1
OVP Propagation Delay
120
-
130
-
VFB Rising, Over Voltage=10mV
ms
OTP Rising Threshold (Note
5)
TOTR
-
-
145
45
-
-
oC
oC
OTP Hysteresis (Note 5)
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APW8713
Typical Operating Characteristics
Reference Voltage vs. Junction
Switching Frequency vs. Output
Current
Temperature
0.804
1000
100
10
0.802
0.8
0.798
0.796
0.794
1
Automatic PFM/PWM Mode
Force PWM Mode
0.1
0.001
0.01
0.1
1
10
-50
-25
0
25
50
75
100
Junction Temperature (oC)
Output Current(A)
Output Voltage vs Output Current
Output Voltage vs Input Voltage
1.090
1.085
1.080
1.075
1.070
1.065
1.060
1.055
1.050
1.10
1.09
1.08
Automatic PFM/PWM Mode
Force PWM Mode
1.07
1.06
1.05
PFM Operation
PWM Operation
0
2
4
6
8
10
0
5
10
15
20
25
30
Output Current(A)
Input Voltage(V)
Switching Frequency vs. Input
Voltage
340
330
320
310
300
290
280
0
5
10
15
20
25
30
Input Voltage(V)
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APW8713
Operating Waveforms
Refer to the typical application circuit. TA= 25oC unless otherwise specified.
Enable Without Loading
Enable With Loading
VEN
VEN
1
2
1
2
VLX
VLX
VOUT
VPOK
VOUT
VPOK
3
3
4
4
CSS=10nF
CSS=10nF
CH1: VEN, 5V/Div, DC
CH2: VLX, 10V/Div, DC
CH1: VEN, 5V/Div, DC
CH2: VLX, 10V/Div, DC
CH3: VOUT, 500mV/Div, DC
CH4: VPOK, 5V/Div, DC
TIME:1ms/Div
CH3: VOUT, 500mV/Div, DC
CH4: VPOK, 5V/Div, DC
TIME: 1ms/Div
Soft- Stop Function
Shutdown With Loading
CSS=10nF
VEN
VLX
VEN
VLX
1
1
2
2
VOUT
VOUT
VPOK
VPOK
3
4
3
4
CH1: VEN, 5V/Div, DC
CH2: VLX, 10V/Div, DC
CH3: VOUT, 500mV/Div, DC
CH4: VPOK, 5V/Div, DC
TIME:5ms/Div
CH1: VEN, 5V/Div, DC
CH2: VLX, 10V/Div, DC
CH3: VOUT, 500mV/Div, DC
CH4: VPOK, 5V/Div, DC
TIME:500ms/Div
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APW8713
Operating Waveforms
Refer to the typical application circuit. TA= 25oC unless otherwise specified.
PWM Switching Waveform
PFM Switching Waveform
VOUT
VOUT
1
1
2
VLX
VLX
2
3
IL
IL
3
CH1: VOUT, 50mV/Div, AC
CH2: VLX, 10V/Div, DC
CH3: IL, 2A/Div, DC
CH1: VOUT, 50mV/Div, AC
CH2: VLX, 5V/Div, DC
CH3: IL, 2A/Div, DC
TIME: 2ms/Div
TIME: 1ms/Div
Load Transient 2
Load Transient 1
VOUT
VOUT
1
2
3
1
VLX
VLX
2
3
IL
IL
CH1: VOUT, 100mV/Div, AC
CH2: VLX, 10V/Div, DC
CH3: IL, 5A/Div, DC
CH1: VOUT, 100mV/Div, AC
CH2: VLX, 10V/Div, DC
CH3: IL, 5A/Div, DC
TIME: 20ms/Div
TIME: 20ms/Div
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APW8713
Operating Waveforms
Refer to the typical application circuit. TA= 25oC unless otherwise specified.
Current LImit and UVP Function
Short Circuit Protection
VOUT
VOUT
1
2
1
2
VLX
VLX
IL
IL
3
3
CH1: VOUT, 1V/Div, DC
CH2: VLX, 10V/Div, DC
CH1: VOUT, 1V/Div, DC
CH2: VLX, 10V/Div, DC
CH3: IL, 10A/Div, DC
CH3: IL, 10A/Div, DC
TIME: 500ms/Div
TIME: 20ms/Div
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APW8713
Pin Description
PIN
FUNCTION
NO.
1
NAME
POK
EN
Power-Good Output Pin of PWM. POK is an open-drain output used to indicate the status of the PWM
output voltage. Connect the POK in to +5V through a pull-high resistor.
2
PWM Enable. PWM is enabled when EN=1. When EN=0, PWM is in shutdown.
PFM Selection Input. When the PFM is above high logic level, the Device is in force PWM mode. When the
PFM is below low logic level, the device is in automatic PFM/PWM Mode.
3
PFM
AGND
FB
4
Signal Ground for The IC.
Output Voltage Feedback Pin. This pin is connected to the resistive divider that set the desired output
voltage. The POK, UVP, and OVP circuits detect this signal to report output voltage status.
5
6
7
TON
NC
This Pin is Allowed to Adjust The Switching Frequency. Connect a resistor RTON from TON pin to VIN pin.
No connect.
Battery Voltage Input Pin. VIN powers linear regulators and is also used for the constant on-time PWM
on-time one-shot circuits. Connect VIN to the battery input and bypass with a 1mF capacitor for noise
interference.
8, 9, 22
VIN
LX
Junction Point of The High-Side MOSFET Source, Output Filter Inductor and The Low-Side MOSFET Drain
for PWM. Connect this pin to the Source of the high-side MOSFET. LX serves as the lower supply rail for the
UGATE high-side gate driver. LX is the current-sense input for the PWM.
10, 11,
16~18
12~15,
19
PGND
BOOT
Power Ground of The LGATE Low-Side MOSFET Drivers.
Supply Input for The UGATE Gate Driver and an internal level-shift circuit. Connect to an external capacitor
to create a boosted voltage suitable to drive a logic-level N-channel MOSFET.
20
Supply Voltage Input Pin for Control Circuitry, Connect +5V from the VCC pin to the GND pin. Decoupling at
least 1mF of a MLCC capacitor from the VCC pin to the AGND pin.
21
23
VCC
SS
Soft Start Output. Connect a capacitor to GND to set the soft start interval.
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APW8713
Block Diagram
POK
TON
LX
PFM
GND
125% VREF
Mean Value
Circuit
Delay
Current
Limit
90% VREF
Reference
125% VREF
OV
UV
VIN
Fault
Latch
Logic
VCC
BOOT
70% VREF
Thermal
UG
VLX
Shutdown
FB
Gate
Driver
On-Time
Generator
Error
Comparator
LX
PFM
VCC
LDO
LX
VREF
LG
Soft-Start
Gate
Driver
POR
EN
PGND
VCC
SS
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APW8713
Typical Application Circuit
When Vin=19V, Dual Power Input :
19V
VIN
EN
CIN
10uF /25V X 4
(MLCC)
Mode
Selection
PFM
100K
TON
LX
5V
VCC
VOUT
LOUT
1.0uH
APW8713
1.058V, 8A
CVCC
1uF
CBOOT
0.1uF
RPOK
100k
RTOP
20k
COUT1
150uF
COUT2
22uFx4
BOOT
POK
SS
FB
RGND
62k
PGND
AGND
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Rev. A.3 - Sep., 2013
APW8713
Typical Application Circuit
When Vin=5V, Single Power Input :
5V
VIN
EN
CIN
10uF /12V X 4
(MLCC)
PFM
100K
Mode
Selection
TON
LX
VCC
VOUT
LOUT
1.0uH
1.058V, 8A
CVCC
1uF
CBOOT
0.1uF
APW8713
RPOK
RTOP
20k
100k
COUT1
150uF
COUT2
22uFx4
BOOT
POK
FB
RGND
62k
SS
PGND
AGND
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APW8713
Function Description
Constant-On-Time PWM Controller with Input Feed-
Forward
Where FSW is the nominal switching frequency of the
converter in PWM mode.
The constant on-time control architecture is a pseudo-
fixed frequency with input voltage feed-forward. This ar-
chitecture relies on the output filter capacitor’s effective
series resistance (ESR) to act as a current-sense resistor,
so the output ripple voltage provides the PWM ramp signal.
In PFM operation, the high-side switch on-time controlled
by the on-time generator is determined solely by a one-
shot whose pulse width is inversely proportional to input
voltage and directly proportional to output voltage. In PWM
operation, the high-side switch on-time is determined by
a switching frequency control circuit in the on-time gen-
erator block.
The load current at handoff from PFM to PWM mode is
given by:
1
2
VIN - VOUT
ILOAD (PFM toPWM)
=
´
´ TON-PFM
L
V
IN - VOUT
1
VOUT
=
´
´
2L
FSW
V
IN
Forced-PWM Mode
The Forced-PWM mode disables the zero-crossing
comparator, which truncates the low-side switch on-time
at the inductor current zero crossing. This causes the
low-side gate-drive waveform to become the complement
of the high-side gate-drive waveform. This in turn causes
the inductor current to reverse at light loads while UG
maintains a duty factor of VOUT/VIN. The benefit of Forced-
PWM mode is to keep the switching frequency fairly
constant. The Forced-PWM mode is most useful for re-
ducing audio frequency noise, improving load-transient
response, and providing sink-current capability for dy-
namic output voltage adjustment.
The switching frequency control circuit senses the switch-
ing frequency of the high-side switch and keeps regulat-
ing it at a constant frequency in PWM mode. The design
improves the frequency variation and is more outstand-
ing than a conventional constant on-time controller, which
has large switching frequency variation over input voltage,
output current and temperature. Both in PFM and PWM,
the on-time generator, which senses input voltage on
VIN pin, provides very fast on-time response to input line
transients.
When VPFM is above the PFM high threshold (2.5V,
minimum), the converter is in forced-PWM mode. When
VPFM is below the PFM low threshold (0.5V, maximum),
the chip is in automatic PFM/PWM Mode.
Another one-shot sets a minimum off-time (typical:
250ns). The on-time one-shot is triggered if the error com-
parator is high, the low-side switch current is below the
current-limit threshold, and the minimum off-time one-
shot has timed out.
Power-On-Reset
A Power-On-Reset (POR) function is designed to prevent
wrong logic controls when the VCC voltage is low. The
POR function continually monitors the bias supply volt-
age on the VCC pin if at least one of the enable pins is set
high. When the rising VCC voltage reaches the rising
POR voltage threshold (4.35V, typical), the POR signal
goes high and the chip initiates soft-start operations.
Should this voltage drop lower than 4.25V (typical), the
POR disables the chip.
Over-Current Protection of the PWM Converter
In PFM mode, an automatic switchover to pulse-frequency
modulation (PFM) takes place at light loads. This
switchover is affected by a comparator that truncates the
low-side switch on-time at the inductor current zero
crossing. This mechanism causes the threshold between
PFM and PWM operation to coincide with the boundary
between continuous and discontinuous inductor-current
operation (also known as the critical conduction point).
The on-time of PFM is given by:
En Pin Control
When VEN is above the EN high threshold (2.5V,
minimum), the converter is enabled. When VEN is below
the EN low threshold (0.5V, maximum), the chip is in the
shutdown and only low leakage current is taken from
VCC.
1
VOUT
TON-PFM
=
´
FSW
V
IN
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APW8713
Function Description (Cont.)
Soft-Start
Under-Voltage Protection (UVP)
The APW8713 provides the programmed soft-start func-
tion to limit the inrush current. The soft-start time can be
programmed by the external capacitor between SS and
GND. Typical charge current is 10uA, and the soft-start
time can be calculated by the following formula:
In the process of operation, if a short circuit occurs, the
output voltage will drop quickly. When load current is big-
ger than current limit threshold value, the output voltage
will fall out of the required regulation range. The under-
voltage protection circuit continually monitors the FB volt-
age after soft-start is completed. If a load step is strong
enough to pull the output voltage lower than the under
voltage threshold, the under voltage threshold is 70% of
the nominal output voltage, the internal UVP delay counter
starts to count. After 16ms de-bounce time, the device
turns off both high side and low-side MOSEFET with
latched. Toggling enable pin to low, or recycling VIN, will
clear the latch and bring the chip back to operation.
TSS(ms) = 330´ CSS(nF)
The APW8713 integrates soft-start circuits to ramp up the
output voltage of the converter to the programmed regu-
lation set point at a predictable slew rate. The slew
rate of output voltage is internally controlled to limit the
inrush current through the output capacitors during soft-
start process. When the EN pin is pulled above the rising
EN threshold voltage, the device initiates a soft-start pro-
cess to ramp up the output voltage.
Over-Voltage Protection (OVP)
The over voltage function monitors the output voltage by
FB pin. Should the FB voltage increase over 125% of the
reference voltage due to the high-side MOSFET failure or
for other reasons, the over voltage protection comparator
designed with a 3ms noise filter will force the low-side
MOSFET gate driver fully turn on and latch high. This ac-
tion actively pulls down the output voltage.
During soft-start stage before the PGOOD pin is ready,
the under voltage protection is prohibited. The over volt-
age and current limit protection functions are enabled. If
the output capacitor has residue voltage before startup,
both low-side and high-side MOSFETs are in off-state
until the soft start voltage equal the VFB voltage. This will
ensure the output voltage starts from its existing voltage
level.
This OVP scheme only clamps the voltage overshoot,
and does not invert the output voltage when otherwise
activated with a continuously high output from low-side
MOSFET driver. It’s a common problem for OVP schemes
with a latch. Once an over-voltage fault condition is set, it
can only be reset by toggling EN or VIN power-on-reset
signal.
In the event of under-voltage, over-voltage, over-tempera-
ture or shutdown, the chip enables the soft-stop function.
The soft-stop function discharges the output voltages by
low side turns MOSFET on linearly.
Power Good Indicator
POK is actively held low in shutdown and soft-start status.
In the soft-start process, the POK is an open-drain. When
the soft-start is finished, the POK is released. In normal
operation, the POK window is from 90% to 125% of the
converter reference voltage. When the output voltage has
to stay within this window, POK signal will become high.
When the output voltage outruns 90% or 125% of the
target voltage, POK signal will be pulled low immediately.
In order to prevent false POK drop, capacitors need to
parallel at the output to confine the voltage deviation with
severe load step transient.
Current Limit
The current limit circuit employs a "valley" current-sens-
ing algorithm (See Figure 1). The APW8713 uses the
low-side MOSFET’s RDS(ON) of the synchronous rectifier
as a current-sensing element. If the magnitude of the
current-sense signal at LX pin is above the current-limit
threshold 11A(minimum), the PWM is not allowed to ini-
tiate a new cycle. The actual peak current is greater than
the current-limit threshold by an amount equal to the in-
ductor ripple current. Therefore, the exact current-limit char-
acteristic and maximum load capability are a function of
the sense resistance, inductor value, and input voltage.
Copyright ã ANPEC Electronics Corp.
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Rev. A.3 - Sep., 2013
APW8713
Function Description (Cont.)
Programming the On-Time Control and PWM Switch-
ing Frequency
Current Limit( Cont.)
IPEAK
The APW8713 does not use a clock signal to produce
PWM. The device uses the constant on-time control ar-
chitecture to produce pseudo-fixed frequency with input
voltage feed-forward. The on-time pulse width is propor-
tional to output voltage VOUT and inverse proportional to
input voltage VIN. In PWM, the on-time calculation is writ-
ten as below equation.
IOUT
ΔI
ILIMIT
0
Time
26.3´ 10-12 ´ RTON(W)
TON
=
V (V)
IN
Figure 1. Current Limit algorithm
Where:
RTON is the resistor connected from TON pin to VIN pin.
Furthermore, The approximate PWM switching frequency
is written as:
The PWM controller uses the low-side MOSFETs on-re-
sistance RDS(ON) to monitor the current for protection
against shorted outputs. The MOSFET’s RDS(ON) is varied
by temperature and gate to source voltage, the user
should determine the maximum RDS(ON) in manufacture’s
datasheet.
VOUT
D
V
IN
TON
=
，FSW =
FSW
TON
The PCB layout guidelines should ensure that noise and
DC errors do not corrupt the current-sense signals at LX.
Place the hottest power MOSEFTs as close to the IC as
possible for best thermal coupling. When combined with
the under-voltage protection circuit, this current-limit
method is effective in almost every circumstance.
Where:
FSW is the PWM switching frequency.
Over-Temperature Protection (OTP)
When the junction temperature increases above the ris-
ing threshold temperature TOTR, the IC will enter the over
temperature protection state that suspends the PWM,
which forces the UG and LG gate drivers output low. The
thermal sensor allows the converters to start a start-up
process and regulate the output voltage again after the
junction temperature cools by 45oC. The OTP designed
with a 45oC hysteresis lowers the average TJ during con-
tinuous thermal overload conditions, which increases life-
time of the APW8713.
Copyright ã ANPEC Electronics Corp.
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Rev. A.3 - Sep., 2013
APW8713
Application Information
A good starting point is to choose the ripple current to be
approximately 30% of the maximum output current. Once
the inductance value has been chosen, selecting an in-
ductor that is capable of carrying the required peak cur-
rent without going into saturation.In some types of
inductors, especially core that is made of ferrite, the ripple
current will increase abruptly when it saturates. This re-
sults in a larger output ripple voltage. Besides, the induc-
tor needs to have low DCR to reduce the loss of efficiency.
Output Inductor Selection
The output voltage is adjustable from 0.8V to 12V with a
resistor-divider connected with FB, GND, and converter?¦s
output. Using 1% or better resistors for the resistor-di-
vider is recommended. The output voltage is determined
by:
RTOP
VOUT = 0.8 ´ (1+
)
RGND
Output Capacitor Selection
Where 0.8 is the reference voltage, RTOP is the resistor
connected from converter¡¦s output to FB, and RGND is the
resistor connected from FB to GND. Suggested RGND is in
the range from 1k to 20kW. To prevent stray pickup, locate
resistors RTOP and RGND close to APW8713.
Output voltage ripple and the transient voltage deviation
are factors that have to be taken into consideration when
selecting an output capacitor. Higher capacitor value and
lower ESR reduce the output ripple and the load transient
drop. Therefore, selecting high performance low ESR
capacitors is recommended for switching regulator
applications. In addition to high frequency noise related
to MOSFET turn-on and turnoff, the output voltage ripple
includes the capacitance voltage drop DVCOUT and ESR
voltage drop DVESR caused by the AC peak-to-peak
inductor’s current. These two voltages can be represented
by:
Output Inductor Selection
The duty cycle (D) of a buck converter is the function of the
input voltage and output voltage. Once an output voltage
is fixed, it can be written as:
VOUT
D =
V
IN
IRIPPLE
DCOUT
=
8 ´ COUT ´ FSW
The inductor value (L) determines the inductor ripple
current, IRIPPLE, and affects the load transient response.
Higher inductor value reduces the inductor?¦s ripple cur-
rent and induces lower output ripple voltage. The ripple
current and ripple voltage can be approximated by:
DVESR = IRIPPLE ´ RESR
These two components constitute a large portion of the
total output voltage ripple. In some applications, multiple
capacitors have to be paralleled to achieve the desired
ESR value. If the output of the converter has to support
another load with high pulsating current, more capacitors
are needed in order to reduce the equivalent ESR and
suppress the voltage ripple to a tolerable level. A small
decoupling capacitor (1mF) in parallel for bypassing the
noise is also recommended, and the voltage rating of the
output capacitors are also must be considered.
V
IN - VOUT VOUT
IRIPPLE
=
´
FSW ´ L
V
IN
Where FSW is the switching frequency of the regulator.
Although the inductor value and frequency are increased
and the ripple current and voltage are reduced, a tradeoff
exists between the inductor’s ripple current and the regu-
lator load transient response time.
A smaller inductor will give the regulator a faster load
transient response at the expense of higher ripple current.
Increasing the switching frequency (FSW) also reduces
the ripple current and voltage, but it will increase the
switching loss of the MOSFETs and the power dissipa-
tion of the converter. The maximum ripple current occurs
at the maximum input voltage.
To support a load transient that is faster than the switch-
ing frequency, more capacitors are needed for reducing
the voltage excursion during load step change. Another
aspect of the capacitor selection is that the total AC cur-
rent going through the capacitors has to be less than the
rated RMS current specified on the capacitors in order to
prevent the capacitor from over-heating.
Copyright ã ANPEC Electronics Corp.
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Rev. A.3 - Sep., 2013
APW8713
Application Information (Cont.)
Input Capacitor Selection
Layout Consideration
The input capacitor is chosen based on the voltage rating
and the RMS current rating. For reliable operation, select-
ing the capacitor voltage rating to be at least 1.3 times
higher than the maximum input voltage. The maximum
RMS current rating requirement is approximately IOUT/2,
where IOUT is the load current. During power-up, the input
capacitors have to handle great amount of surge current.
For low-duty notebook applications, ceramic capacitor is
recommended. The capacitors must be connected be-
tween the drain of high-side MOSFET and the source of
low-side MOSFET with very low-impedance PCB layout.
In any high switching frequency converter, a correct lay-
out is important to ensure proper operation of the
regulator. With power devices switching at higher
frequency, the resulting current transient will cause volt-
age spike across the interconnecting impedance and
parasitic circuit elements. As an example, consider the
turn-off transition of the PWM MOSFET. Before turn-off
condition, the MOSFET is carrying the full load current.
During turn-off, current stops flowing in the MOSFET and
is freewheeling by the low side MOSFET and parasitic
diode. Any parasitic inductance of the circuit generates a
large voltage spike during the switching interval. In
general, using short and wide printed circuit traces should
minimize interconnecting impedances and the magni-
tude of voltage spike. Besides, signal and power grounds
are to be kept separate and finally combined using ground
plane construction or single point grounding. The best
tie-point between the signal ground and the power ground
is at the negative side of the output capacitor on each
channel, where there is less noise. Noisy traces beneath
the IC are not recommended. Below is a checklist for
your layout:
Thermal Consideration
Because the APW8802 build-in high-side and low-side
MOSFET, the heat dissipated may exceed the maximum
junction temperature of the part in applications. If the junc-
tion temperature reaches approximately 150oC, both
power switches will be turned off and the LX node will
become high impedance. To avoid the APW8713 from
exceeding the maximum junction temperature, the user
will need to do some thermal analysis. The goal of the
thermal analysis is to determine whether the power dis-
sipated exceeds the maximum junction temperature of
the part. The main power dissipated by the part is
approximated:
- Keep the switching nodes (BOOT and LX) away from
sensitive small signal nodes since these nodes are
fast moving signals. Therefore, keep traces to these
nodes as short as possible and there should be no
other weak signal traces in parallel with theses traces
on any layer.
PUPPER = IO2 UT(1+ TC)(RDS(ON))D + 0.5(IOUT)(V )(tSW )FSW
IN
= IO2 UT(1+ TC)(RDS(ON))(1-D)
- The large layout plane between the drain of the MOSFETs
(VIN and LX nodes) can get better heat sinking.
- The current sense resistor should be close to OCSET
pin to avoid parasitic capacitor effect and noise coupling.
- Decoupling capacitors, the resistor-divider, and boot
capacitor should be close to their pins.
P
LOWER
IOUT is the load current
TC is the temperature dependency of RDS(ON)
FSW is the switching frequency
tSW is the switching interval
- The output bulk capacitors should be close to the loads.
The input capacitor’s ground should be close to the
grounds of the output capacitors.
D is the duty cycle
Note that both internal MOSFETs have conduction losses
while the upper MOSFET include an additional transition
loss. The switching internal, tSW, is the function of the
reverse transfer capacitance CRSS. The (1+TC) term fac-
tors in the temperature dependency of the RDS(ON) and can
be extracted from the "RDS(ON) vs. Temperature" curve
of the power MOSFET. In APW8713 case, the RDS(ON) is
about 30mW from specification table.
- Locate the resistor-divider close to the FB pin to mini-
mize the high impedance trace. In addition, FB pin traces
can’t be close to the switching signal traces (BOOT and
LX).
Copyright ã ANPEC Electronics Corp.
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Rev. A.3 - Sep., 2013
APW8713
Application Information (Cont.)
Recommended Minimum Footprint
TQFN4x4-23
4mm
ThermalVia
diameter
0.3mm X 12
0.45mm *
1.35mm
0.14mm
0.3mm
4mm
0.2mm
0.5mm
0.51mm
0.94mm
0.37mm
0.45mm
* Just Recommend
Copyright ã ANPEC Electronics Corp.
19
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Rev. A.3 - Sep., 2013
APW8713
Package Information
TQFN4x4-23
D
A
Pin 1
A1
A3
NX
Pin 1 Corner
aaa
C
D1
D2
TQFN4x4-23
MILLIMETERS
MIN. MAX.
S
Y
M
B
O
L
INCHES
MIN.
MAX.
0.032
0.002
A
0.70
0.00
0.80
0.05
0.028
0.000
A1
A3
b
0.20 REF
0.008 REF
0.008
0.154
0.102
0.116
0.154
0.049
0.033
0.012
0.161
0.109
0.124
0.161
0.057
0.041
0.20
3.90
2.58
2.95
3.90
1.24
0.85
0.30
4.10
2.78
3.15
4.10
1.44
1.05
D
D1
D2
E
E1
E2
e
0.50 BSC
0.020 BSC
0.35
0.20
0.45
0.014
0.008
0.018
L
K
0.003
aaa
0.08
Copyright ã ANPEC Electronics Corp.
Rev. A.3 - Sep., 2013
20
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APW8713
Carrier Tape & Reel Dimensions
P0
P2
P1
OD0
A
K0
A0
A
OD1
B
B
SECTION A-A
SECTION B-B
d
T1
Application
TQFN4x4
A
H
T1
12.4+2.00 13.0+0.50
-0.00 -0.20
P2 D0
C
d
D
W
E1
F
5.50±0.10
K0
330.0±2.00
50 MIN.
1.5 MIN.
D1
20.2 MIN. 12.0±0.30 1.75±0.10
P0
P1
T
A0
B0
1.5+0.10
-0.00
0.6+0.00
-0.40
4.00±0.10 8.00±0.10 2.00±0.05
1.5 MIN.
4.30±0.20 4.30±0.20 1.00±0.20
(mm)
Devices Per Unit
Package Type
TQFN4x4
Unit
Quantity
3000
Tape & Reel
Copyright ã ANPEC Electronics Corp.
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Rev. A.3 - Sep., 2013
APW8713
Taping Direction Information
TQFN4x4
USER DIRECTION OF FEED
Classification Profile
Copyright ã ANPEC Electronics Corp.
22
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Rev. A.3 - Sep., 2013
APW8713
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
Preheat & Soak
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
Temperature min (Tsmin
)
Temperature max (Tsmax
)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
3 °C/second max.
3°C/second max.
Liquidous temperature (TL)
Time at liquidous (tL)
183 °C
60-150 seconds
217 °C
60-150 seconds
Peak package body Temperature
(Tp)*
See Classification Temp in table 1
20** seconds
See Classification Temp in table 2
30** seconds
Time (tP)** within 5°C of the specified
classification temperature (Tc)
Average ramp-down rate (Tp to Tsmax
)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Volume mm3
350
Package
Thickness
<2.5 mm
³ 2.5 mm
Volume mm3
<350
235 °C
220 °C
220 °C
220 °C
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
Volume mm3
Volume mm3
350-2000
260 °C
Volume mm3
<350
260 °C
260 °C
250 °C
>2000
260 °C
245 °C
245 °C
1.6 mm – 2.5 mm
³ 2.5 mm
250 °C
245 °C
Reliability Test Program
Test item
SOLDERABILITY
HOLT
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
Description
5 Sec, 245°C
1000 Hrs, Bias @ Tj=125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
PCT
TCT
HBM
MM
VMM≧200V
10ms, 1tr≧100mA
Latch-Up
Copyright ã ANPEC Electronics Corp.
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Rev. A.3 - Sep., 2013
APW8713
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright ã ANPEC Electronics Corp.
Rev. A.3 - Sep., 2013
24
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