AOT502 [AOS]
Clamped N-Channel MOSFET; 夹N沟道MOSFET
| 型号： | AOT502 |
| 厂家： | 
ALPHA & OMEGA SEMICONDUCTORS |
| 描述： | Clamped N-Channel MOSFET |
| 文件： | 总7页 (文件大小：321K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AOT502
Clamped N-Channel MOSFET
General Description
Product Summary
VDS
Clamped
60A
AOT502 uses an optimally designed temperature
compensated gate-drain zener clamp. Under overvoltage
conditions, the clamp activates and turns on the MOSFET,
safely dissipating the energy in the MOSFET.
ID (at VGS=10V)
RDS(ON) (at VGS=10V)
< 11.5mΩ
The built in resistor guarantees proper clamp operation
under all circuit conditions, and the MOSFET never goes
into avalanche breakdown. Advanced trench technology
provides excellent low Rdson, gate charge and body diode
characteristics, making this device ideal for motor and
inductive load control applications.
100% UIS Tested
100% Rg Tested
TO220
D
Top View
Bottom View
D
10Ω
G
G
S
D
D
S
S
G
Absolute Maximum Ratings TA=25°C unless otherwise noted
Parameter
Symbol
VDS
Maximum
Clamped
Clamped
60
Units
Drain-Source Voltage
Gate-Source Voltage
V
V
VGS
TC=25°C
Continuous Drain
Current
Pulsed Drain Current C
ID
TC=100°C
41
A
A
IDM
137
TA=25°C
TA=70°C
9
7
Continuous Drain
Current
Avalanche Current C
Avalanche energy L=0.1mH C
IDSM
IAS, AR
I
28.5
41
A
EAS,EAR
mJ
TC=25°C
Power Dissipation B
TC=100°C
79
PD
W
39
TA=25°C
1.9
PDSM
W
Power Dissipation A
TA=70°C
1.2
TJ, TSTG
Junction and Storage Temperature Range
-55 to 175
°C
Thermal Characteristics
Parameter
Maximum Junction-to-Ambient A
Maximum Junction-to-Ambient A D
Maximum Junction-to-Case
Symbol
Typ
13
Max
Units
°C/W
°C/W
°C/W
t
≤ 10s
15.6
65
RθJA
Steady-State
Steady-State
54
RθJC
1.6
1.9
Rev1: May 2009
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Page 1 of 7
AOT502
Electrical Characteristics (TJ=25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max Units
STATIC PARAMETERS
BVDSS(z)
BVCLAMP
IDSS(z)
Drain-Source Breakdown Voltage
Drain-Source Clamping Voltage
Zero Gate Voltage Drain Current
Gate-Source Voltage
ID=10mA, VGS=0V
ID=1A, VGS=0V
33
36
V
44
20
V
VDS=16V, VGS=0V
µA
V
µA
BVGSS
IGSS
VDS=0V, ID=250µA
VDS=0V, VGS=±10V
VDS=VGS, ID=250µA
20
Gate-Body leakage current
Gate Threshold Voltage
10
VGS(th)
ID(ON)
1.6
2.1
2.7
V
A
On state drain current
VGS=10V, VDS=5V
VGS=10V, ID=30A
137
9.3
15.4
55
11.5
18.5
RDS(ON)
Static Drain-Source On-Resistance
mΩ
TJ=125°C
gFS
VSD
IS
Forward Transconductance
Diode Forward Voltage
VDS=5V, ID=30A
S
V
A
IS=1A, VGS=0V
0.73
1
Maximum Body-Diode Continuous Current
75
DYNAMIC PARAMETERS
Ciss
Coss
Crss
Rg
Input Capacitance
960
185
65
1205
266
109
20
1450
345
pF
pF
pF
Ω
VGS=0V, VDS=15V, f=1MHz
Output Capacitance
Reverse Transfer Capacitance
Gate resistance
155
V
GS=0V, VDS=0V, f=1MHz
10
30.0
SWITCHING PARAMETERS
Qg
Qgs
Qgd
tD(on)
tr
Total Gate Charge
Gate Source Charge
Gate Drain Charge
Turn-On DelayTime
Turn-On Rise Time
Turn-Off DelayTime
Turn-Off Fall Time
18.5
2.7
4
23.4
3.4
7
28
4
nC
nC
nC
ns
ns
ns
ns
V
GS=10V, VDS=15V, ID=30A
10
13.5
17.5
63
VGS=10V, VDS=15V, RL=0.5Ω,
RGEN=3Ω
tD(off)
tf
27
trr
IF=30A, dI/dt=750A/µs
IF=30A, dI/dt=750A/µs
14
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
17.5
67
21
80
ns
Qrr
53.5
nC
A. The value of RθJA is measured with the device mounted on 1in 2 FR-4 board with 2oz. Copper, in a still air environment with T A =25°C. The Power
dissipation PDSM is based on R θJA and the maximum allowed junction temperature of 150°C. The value in any given application depends on the
user's specific board design, and the maximum temperature of 175°C may be used if the PCB allows it.
B. The power dissipation PD is based on TJ(MAX)=175°C, using junction-to-case thermal resistance, and is more useful in setting the upper
dissipation limit for cases where additional heatsinking is used.
C. Repetitive rating, pulse width limited by junction temperature T J(MAX)=175°C. Ratings are based on low frequency and duty cycles to keep initial
TJ =25°C.
D. The RθJA is the sum of the thermal impedence from junction to case R θJC and case to ambient.
E. The static characteristics in Figures 1 to 6 are obtained using <300 µs pulses, duty cycle 0.5% max.
F. These curves are based on the junction-to-case thermal impedence which is measured with the device mounted to a large heatsink, assuming a
maximum junction temperature of T J(MAX)=175°C. The SOA curve provides a single pulse rating.
G. These tests are performed with the device mounted on 1 in 2 FR-4 board with 2oz. Copper, in a still air environment with T A=25°C.
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS ARE NOT AUTHORIZED. AOS DOES NOT ASSUME ANY LIABILITY ARISING
OUT OF SUCH APPLICATIONS OR USES OF ITS PRODUCTS. AOS RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN,
FUNCTIONS AND RELIABILITY WITHOUT NOTICE.
Rev1: May 2009
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AOT502
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS
140
120
100
80
80
60
40
20
0
10V
VDS=5V
6V
5V
7V
4.5V
25°C
60
4V
40
125°C
VGS=3.5V
-40°C
4
20
0
2
2.5
3
3.5
VGS(Volts)
4.5
5
0
1
2
3
4
5
V
DS (Volts)
Figure 2: Transfer Characteristics (Note E)
Fig 1: On-Region Characteristics (Note E)
14
12
10
8
2.4
2
VGS=10V
ID=30A
VGS=10V
1.6
1.2
0.8
0.4
6
4
0
5
10
15
20
25
30
-50
0
50
100
150
200
ID (A)
Temperature (°C)
Figure 3: On-Resistance vs. Drain Current and
Gate Voltage (Note E)
Figure 4: On-Resistance vs. Junction Temperature
(Note E)
50
40
30
20
10
0
1.0E+02
1.0E+01
ID=30A
1.0E+00
125°C
1.0E-01
1.0E-02
1.0E-03
1.0E-04
1.0E-05
125°C
25°C
-40°C
25°C
0.0
0.2
0.4
0.6
0.8
1.0
1.2
2
4
6
8
10
VSD (Volts)
VGS (Volts)
Figure 6: Body-Diode Characteristics (Note E)
Figure 5: On-Resistance vs. Gate-Source Voltage
(Note E)
Rev1: May 2009
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Page 3 of 7
AOT502
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS
1800
1600
1400
1200
1000
800
600
400
200
0
10
VDS=15V
ID=30A
8
Ciss
6
4
Crss
Coss
2
0
0
5
10
15
VDS (Volts)
20
25
30
0
5
10
15
20
25
Q
g (nC)
Figure 7: Gate-Charge Characteristics
Figure 8: Capacitance Characteristics
1000
800
600
400
200
0
1000.0
100.0
10.0
1.0
10µs
TJ(Max)=175°C
TC=25°C
RDS(ON)
DC
100µs
1ms
10ms
TJ(Max)=175°C
TC=25°C
0.1
0.0
0.01
0.1
1
10
100
0.0001
0.001
0.01
0.1
1
10
VDS (Volts)
Pulse Width (s)
Figure 10: Single Pulse Power Rating Junction-to-
Case (Note F)
Figure 9: Maximum Forward Biased Safe
Operating Area (Note F)
10
1
D=Ton/T
In descending order
D=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse
TJ,PK=TC+PDM.ZθJC.RθJC
RθJC=1.9°C/W
0.1
PD
0.01
0.001
Ton
Single Pulse
0.0001
T
0.000001
0.00001
0.001
0.01
0.1
1
10
Pulse Width (s)
Figure 11: Normalized Maximum Transient Thermal Impedance (Note F)
Rev1: May 2009
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Page 4 of 7
AOT502
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS
1000
100
10
100
80
60
40
20
0
TA=25°C
TA=100°C
TA=125°C
TA=150°C
0
25
50
75
100
125
150
175
1
10
100
1000
Time in avalanche, tA (us)
TCASE (°C)
Figure 12: Single Pulse Avalanche capability (Note
C)
Figure 13: Power De-rating (Note F)
10000
1000
100
10
80
60
40
20
TA=25°C
1
0
0
0.00001
0.001
0.1
10
1000
25
50
75
100
125
150
175
T
CASE (°C)
Pulse Width (s)
Figure 15: Single Pulse Power Rating Junction-to-
Ambient (Note H)
Figure 14: Current De-rating (Note F)
10
1
D=Ton/T
In descending order
D=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse
TJ,PK=TA+PDM.ZθJA.RθJA
RθJA=65°C/W
0.1
0.01
PD
Single Pulse
Ton
0.001
T
0.0001
0.001
0.01
0.1
1
10
100
1000
Pulse Width (s)
Figure 16: Normalized Maximum Transient Thermal Impedance (Note H)
Rev1: May 2009
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Page 5 of 7
AOT502
TYPICAL PROTECTION CHARACTERISTICS
2.00
Trench BV
1.50
1.00
0.50
0.00
BVCLAMP
D
+
Vz
-
BVDSS(Z)
R
+
-
30
35
40
45
G
VDS (Volts)
Fig 15: BVCLAMP Characteristic
+
VPLATEAU
This device uses built-in Gate to Source and Gate to Drain zener
S
protection. While the Gate-Source zener protects against excessive
VGS conditions, the Gate to Drain protection, clamps the VDS well
below the device breakdown, preventing an avalanche condition
within the MOSFET as a result of voltage over-shoot at the Drain
electrode.
-
It is designed to breakdown well before the device breakdown.
During such an event, current flows through the zener clamp, which
is situated internally between the Gate to Drain. This current flows at
BVDSS(Z), building up the VGS internal to the device. When the current
level through the zener reaches approximately 300mA, the VGS is
approximately equal to VGS(PLATEAU), allowing significant channel
conduction and thus clamping the Drain to Source voltage. The VGS
needed to turn the device on is controlled with an internally lumped
gate resistor R approximately equal to 10Ω.
60.00
50.00
40.00
30.00
20.00
10.00
0.00
BVCLAMP25oC
BVCLAMP 100oC
VGS(PLATEAU)= 10Ω x 300mA =3V
It can also be said that the VDS during clamping is equal to:
BVDSS = BVCLAMP + VGS(PLATEAU)
0.00E+0 2.50E- 5.00E- 7.50E- 1.00E- 1.25E-
05 05 05 04 04
0
Additional power loss associated with the protection circuitry can be
considered negligible when compare to the conduction losses of the
MOSFET itself;
Time in Avalanche (Seconds)
Fig 16: Unclamped Inductive Switching
EX:
PL=30µAmax x 16V=0.48mW (Zener leakage loss)
Fig16: The built-in Gate to Drain clamp prevents the device from going
into Avalanche by setting the clamp voltage well below the actual
breakdown of the device. When the Drain to Gate voltage approaches
the BV clamp, the internal Gate to Source voltage is charged up and
channel conduction occurs, sinking the current safely through the
device. The BVCLAMP is virtually temperature independent, providing
even greater protection during normal operation.
PL(rds)=102A x 6mΩ=300mW (MOSFET loss)
Rev1: May 2009
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Page 6 of 7
AOT502
Gate Charge Test Circuit & Waveform
Vgs
Qg
10V
+
VDC
+
Qgs
Qgd
Vds
VDC
-
-
DUT
Vgs
Ig
Charge
Resistive Switching Test Circuit & Waveforms
RL
Vds
Vds
90%
10%
+
DUT
Vdd
Vgs
VDC
Rg
-
Vgs
Vgs
td(on)
t
r
td(off)
t
f
ton
toff
Unclamped Inductive Switching (UIS) Test Circuit & Waveforms
L
EAR= 1/2 LIA2R
BVDSS
Vds
Id
Vgs
Vds
+
Vgs
Vdd
I AR
VDC
Id
Rg
-
DUT
Vgs
Vgs
Diode Recovery Test Circuit & Waveforms
Qrr = - Idt
Vds +
Vds -
Ig
DUT
Vgs
trr
L
Isd
I F
Isd
Vgs
dI/dt
I RM
+
Vdd
VDC
Vdd
-
Vds
Rev1: May 2009
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Page 7 of 7
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