AOZ1018 [AOS]
EZBuck⑩ 2A Simple Regulator; EZBuck ™ 2A简单的稳压器
| 型号： | AOZ1018 |
| 厂家： | 
ALPHA & OMEGA SEMICONDUCTORS |
| 描述： | EZBuck⑩ 2A Simple Regulator |
| 文件： | 总14页 (文件大小：770K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AOZ1018
EZBuck™ 2A Simple Regulator
General Description
Features
The AOZ1018 is a high efficiency, simple to use, 2A buck
regulator. The AOZ1018 works from a 4.5V to 16V input
voltage range, and provides up to 2A of continuous
output current with an output voltage adjustable down to
0.8V.
● 4.5V to 16V operating input voltage range
● 130 mΩ internal PFET switch for high efficiency:
up to 95%
● Internal soft start
● Output voltage adjustable to 0.8V
● 2A continuous output current
● Fixed 500kHz PWM operation
● Cycle-by-cycle current limit
● Short-circuit protection
The AOZ1018 comes in SO-8 packages and is rated over
a -40°C to +85°C ambient temperature range.
● Thermal shutdown
● Small size SO-8 packages
Applications
● Point of load dc/dc conversion
● PCIe graphics cards
● Set top boxes
● DVD drives and HDD
● LCD panels
● Cable modems
● Telecom/Networking/Datacom equipment
Typical Application
C1
22µF
Cd
1µF
VIN
L1
4.7µH
From µPC
EN
VOUT
+3.3V Output @ 2A
LX
FB
AOZ1018
R1
R2
COMP
C2
47µF
R
C
D1
C
C
AGND
PGND
Figure 1. 3.3V/2A Buck Regulator
Rev. 1.0 November 2006
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Page 1 of 14
AOZ1018
Ordering Information
Part Number
Ambient Temperature Range
Package
Environmental
AOZ1018AI
-40°C to +85°C
SO-8
RoHS
All AOS Products are offered in packaging with Pb-free plating and compliant to RoHS standards. Please visit
wwww.aosmd.com/web/rohs_compliant.jsp for additional information.
Pin Configuration
1
2
3
4
8
7
6
5
NC
VIN
PGND
LX
AGND
FB
EN
COMP
SO-8
(Top View)
Pin Description
Pin Number Pin Name
Pin Function
1
2
3
NC
VIN
Not connected.
Supply voltage input. When VIN rises above the UVLO threshold the device starts up.
AGND
Reference connection for controller section. Also used as thermal connection for controller
section. Electrically needs to be connected to PGND.
4
FB
The FB pin is used to determine the output voltage via a resistor divider between the output and
GND.
5
6
7
8
COMP
EN
External loop compensation pin.
The enable pin is active high. Connect EN pin to VIN if not used. Do not leave the EN pin floating.
PWM output connection to inductor. Thermal connection for output stage.
Power ground. Electrically needs to be connected to AGND.
LX
PGND
Block Diagram
VIN
Internal
+5V
UVLO
& POR
5V LDO
Regulator
OTP
EN
+
ISen
–
Reference
& Bias
Softstart
Q1
ILimit
+
–
+
Level
Shifter
+
FET
Driver
+
–
PWM
Control
Logic
0.8V
PWM
Comp
EAmp
FB
LX
COMP
500kHz
Oscillator
AGND
PGND
Rev. 1.0 November 2006
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Page 2 of 14
AOZ1018
Absolute Maximum Ratings
Exceeding the Absolute Maximum ratings may damage the
device.
Recommend Operating Ratings
The device is not guaranteed to operate beyond the Maximum
Operating Ratings.
Parameter
Rating
Parameter
Rating
Supply Voltage (V )
18V
-0.7V to V +0.3V
Supply Voltage (V )
4.5V to 16V
IN
IN
LX to AGND
Output Voltage Range
0.8V to V
IN
IN
EN to AGND
-0.3V to V +0.3V
Ambient Temperature (T )
-40°C to +85°C
105°C/W
IN
A
FB to AGND
-0.3V to 6V
-0.3V to 6V
Package Thermal Resistance SO-8
)
(1
(Θ
)
JA
COMP to AGND
PGND to AGND
-0.3V to +0.3V
+150°C
Note:
2
1. The value of ΘJA is measured with the device mounted on 1-in
FR-4 board with 2oz. Copper, in a still air environment with T = 25°C.
The value in any given application depends on the user's specific
board design.
Junction Temperature (T )
J
A
Storage Temperature (T )
-65°C to +150°C
S
Electrical Characteristics
)
(2
T = 25°C, V = V = 12V, V = 3.3V unless otherwise specified
OUT
A
IN
EN
Symbol
Parameter
Conditions
Min.
4.5
Typ. Max. Units
V
Supply Voltage
16
V
V
IN
V
Input Under-Voltage Lockout Threshold
V
V
Rising
Falling
4.00
3.70
UVLO
IN
IN
I
Supply Current (Quiescent)
Shutdown Supply Current
Feedback Voltage
I
= 0, VFB = 1.2V, V >1.2V
2
3
3
mA
µA
V
IN
OUT
EN
I
V
= 0V
20
OFF
EN
V
0.782
0.8
0.5
1
0.818
FB
Load Regulation
%
Line Regulation
%
I
Feedback Voltage Input Current
EN Input threshold
200
nA
FB
V
Off Threshold
On Threshold
0.6
EN
V
2.0
V
EN Input Hysteresis
100
mV
HYS
MODULATOR
f
Frequency
350
100
500
600
6
kHz
%
O
D
Maximum Duty Cycle
Minimum Duty Cycle
Error Amplifier Voltage Gain
Error Amplifier Transconductance
MAX
D
%
MIN
500
200
V/ V
µA/ V
PROTECTION
I
Current Limit
2.5
3.6
A
LIM
Over-Temperature Shutdown Limit
TJ Rising
TJ Falling
145
100
°C
ms
t
Soft Start Interval
4
SS
OUTPUT STAGE
High-Side Switch On-Resistance
V
V
= 12V
= 5V
97
166
130
200
IN
IN
mΩ
Note:
2. Specification in BOLD indicate an ambient temperature range of -40°C to +85°C. These specifications are guaranteed by design.
Rev. 1.0 November 2006
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Page 3 of 14
AOZ1018
Typical Performance Characteristics
Circuit of Figure 1. T = 25°C, V = V = 12V, V = 3.3V unless otherwise specified.
OUT
A
IN
EN
Light Load (DCM) Operation
Full Load (CCM) Operation
Vin
Vin
ripple
0.1V/div
ripple
0.1V/div
Vo
Vo
ripple
20mV/div
ripple
20mV/div
IL
IL
1A/div
1A/div
VLX
VLX
10V/div
10V/div
1µs/div
1µs/div
Startup to Full Load
Full Load to Turnoff
Vin
5V/div
Vin
5V/div
Vo
1V/div
Vo
1V/div
Iin
0.5A/div
Iin
0.5A/div
1ms/div
1ms/div
50% to 100% Load Transient
Light Load to Turnoff
Vo
Ripple
50mV/div
Vin
5V/div
Vo
1V/div
Io
1A/div
Iin
0.5A/div
100µs/div
1s/div
Rev. 1.0 November 2006
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Page 4 of 14
AOZ1018
Typical Performance Characteristics (Continued)
Circuit of Figure 1. T = 25°C, V = V = 12V, V = 3.3V unless otherwise specified.
OUT
A
IN
EN
Short Circuit Protection
Short Circuit Recovery
Vo
2V/div
Vo
2V/div
IL
1A/div
IL
1A/div
100µs/div
1ms/div
AOZ1018AI Efficiency
100
95
90
85
80
75
8.0V OUTPUT
5.0V OUTPUT
3.3V OUTPUT
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
Load Current (A)
Note:
3. Thermal de-rating curves for SO-8 package part under typical input and output condition
based on the evaluation board. 25°C ambient temperature and natural convection
(air speed <50LFM) unless otherwise specified.
Derating Curve at 5/6V Input
Derating Curve at 12V Input
2.5
2.5
1.8V, 3.3V, 5V OUTPUT
1.8V, 3.3V, 5V, 8V OUTPUT
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
air speed less than 50lfm
air speed less than 50lfm
25
35
45
55
65
75
85
25
35
45
55
65
75
85
Ambient Temperature (T )
Ambient Temperature (T )
A
A
Rev. 1.0 November 2006
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Page 5 of 14
AOZ1018
Detailed Description
The AOZ1018 is a current-mode step down regulator with
integrated high side PMOS switch. It operates from a
4.5V to 16V input voltage range and supplies up to 2A of
load current. The duty cycle can be adjusted from 6% to
100% allowing a wide range of output voltage. Features
include enable control, Power-On Reset, input under
voltage lockout, fixed internal soft-start and thermal shut
down.
seen in a circuit which is using an NMOS switch. It allows
100% turn-on of the upper switch to achieve linear regu-
lation mode of operation.The minimum voltage drop from
V
to V is the load current times DC resistance of
IN
O
MOSFET plus DC resistance of buck inductor. It can be
calculated by the following equation:
V
= V – I × (R
+ R
)
inductor
OMAX
where;
IN
O
DS(ON)
The AOZ1018 is available in SO-8 package.
V
V
I
is the maximum output voltage,
OMAX
Enable and Soft Start
is the input voltage from 4.5V to 16V,
IN
is the output current from 0A to 2A,
The AOZ1018 has internal soft start feature to limit in-
rush current and ensure the output voltage ramps up
smoothly to regulation voltage. A soft start process
begins when the input voltage rises to 4.0V and voltage
on EN pin is HIGH. In soft start process, the output volt-
age is ramped to regulation voltage in typically 4ms. The
4ms soft start time is set internally.
O
R
is the on resistance of internal MOSFET, the value is
DS(ON)
between 97mΩ and 200mΩ depending on input voltage and
junction temperature, and
R
is the inductor DC resistance.
inductor
Switching Frequency
The AOZ1018 switching frequency is fixed and set by an
internal oscillator. The practical switching frequency
could range from 350kHz to 600kHz due to device
variation.
The EN pin of the AOZ1018 is active high. Connect the
EN pin to VIN if enable function is not used. Pull it to
ground will disable the AOZ1018. Do not leave it open.
The voltage on EN pin must be above 2.0 V to enable the
AOZ1018. When voltage on EN pin falls below 0.6V, the
AOZ1018 is disabled. If an application circuit requires the
AOZ1018 to be disabled, an open drain or open collector
circuit should be used to interface to EN pin.
Output Voltage Programming
Output voltage can be set by feeding back the output to
the FB pin with a resistor divider network. In the applica-
tion circuit shown in Figure 1. The resistor divider net-
Steady-State Operation
work includes R and R . Usually, a design is started by
1
2
picking a fixed R value and calculating the required R
with equation below.
Under steady-state conditions, the converter operates in
fixed frequency and Continuous-Conduction Mode
(CCM).
2
1
R
1
V
= 0.8 × 1 +
-------
O
The AOZ1018 integrates an internal P-MOSFET as the
high-side switch. Inductor current is sensed by amplifying
the voltage drop across the drain to source of the high
side power MOSFET. Output voltage is divided down by
the external voltage divider at the FB pin. The difference
of the FB pin voltage and reference is amplified by the
internal transconductance error amplifier. The error volt-
age, which shows on the COMP pin, is compared against
the current signal, which is sum of inductor current signal
and ramp compensation signal, at PWM comparator
input. If the current signal is less than the error voltage,
the internal high-side switch is on. The inductor current
flows from the input through the inductor to the output.
When the current signal exceeds the error voltage, the
high-side switch is off. The inductor current is freewheel-
ing through the external Schottky diode to output.
R
2
Some standard value of R , R for most commonly used
1
2
output voltage values are listed in Table 1.
Table 1.
V (V)
R1 (kΩ)
R2 (kΩ)
O
0.8
1.2
1.5
1.8
2.5
3.3
5.0
1.0
open
4.99
10
10
11.5
10.2
10
12.7
21.5
31.6
52.3
10
10
The AOZ1018 uses a P-Channel MOSFET as the high
side switch. It saves the bootstrap capacitor normally
Rev. 1.0 November 2006
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Page 6 of 14
AOZ1018
Combination of R and R should be large enough to
avoid drawing excessive current from the output, which
will cause power loss.
control of soft-start circuit when the junction temperature
decreases to 100°C.
1
2
Application Information
The basic AOZ1018 application circuit is shown in
Figure 1. Component selection is explained below.
Since the switch duty cycle can be as high as 100%, the
maximum output voltage can be set as high as the input
voltage minus the voltage drop on upper PMOS and
inductor.
Input Capacitor
The input capacitor must be connected to the V pin and
IN
Protection Features
The AOZ1018 has multiple protection features to prevent
system circuit damage under abnormal conditions.
PGND pin of the AOZ1018 to maintain steady input volt-
age and filter out the pulsing input current. The voltage
rating of input capacitor must be greater than maximum
input voltage plus ripple voltage.
Over Current Protection (OCP)
The sensed inductor current signal is also used for over
current protection. Since AOZ1018 employs peak current
mode control, the COMP pin voltage is proportional to
the peak inductor current. The COMP pin voltage is lim-
ited to be between 0.4V and 2.5V internally. The peak
inductor current is automatically limited cycle by cycle.
The input ripple voltage can be approximated by equation
below:
I
V
V
O
O
O
∆V
=
× 1 –
×
------------------
----------
----------
IN
V
f × C
V
IN
IN
IN
Since the input current is discontinuous in a buck con-
verter, the current stress on the input capacitor is another
concern when selecting the capacitor. For a buck circuit,
the RMS value of input capacitor current can be calcu-
lated by:
The cycle by cycle current limit threshold is set between
2.54A and 3.65A. When the load current reaches the cur-
rent limit threshold, the cycle by cycle current limit circuit
turns off the high side switch immediately to terminate
the current duty cycle. The inductor current stop rising.
The cycle by cycle current limit protection directly limits
inductor peak current. The average inductor current is
also limited due to the limitation on peak inductor current.
When cycle by cycle current limit circuit is triggered, the
output voltage drops as the duty cycle decreasing.
V
V
O
O
I
= I
×
O
1 –
----------
----------
CINRMS
V
V
IN
IN
if let m equal the conversion ratio:
V
O
The AOZ1018 has internal short circuit protection to
protect itself from catastrophic failure under output short
circuit conditions. The FB pin voltage is proportional to
the output voltage. Whenever FB pin voltage is below
0.2V, the short circuit protection circuit is triggered. As a
result, the converter is shut down and hiccups at a
frequency equals to 1/8 of normal switching frequency.
The converter will start up via a soft start once the short
circuit condition disappears. In short circuit protection
mode, the inductor average current is greatly reduced
because of the low hiccup frequency.
= m
----------
V
IN
The relation between the input capacitor RMS current
and voltage conversion ratio is calculated and shown in
Figure 2 below. It can be seen that when V is half of V ,
O
IN
C
is under the worst current stress. The worst current
IN
stress on C is 0.5 x I .
IN
O
0.5
0.4
0.3
0.2
0.1
0
Power-On Reset (POR)
ICINRMS(m)
IO
A power-on reset circuit monitors the input voltage.When
the input voltage exceeds 4V, the converter starts opera-
tion. When input voltage falls below 3.7V, the converter
will be shut down.
Thermal Protection
0
0.5
m
1
An internal temperature sensor monitors the junction
temperature. It shuts down the internal control circuit and
high side PMOS if the junction temperature exceeds
145°C. The regulator will restart automatically under the
Figure 2. I
vs. Voltage Conversion Ratio
CIN
Rev. 1.0 November 2006
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Page 7 of 14
AOZ1018
For reliable operation and best performance, the input
capacitors must have current rating higher than I
When selecting the inductor, make sure it is able to
handle the peak current without saturation even at the
highest operating temperature.
CINRMS
at worst operating conditions. Ceramic capacitors are
preferred for input capacitors because of their low ESR
and high ripple current rating. Depending on the applica-
tion circuits, other low ESR tantalum or electrolytic
capacitor may also be used. When selecting ceramic
capacitors, X5R or X7R type dielectric ceramic capaci-
tors are preferred for their better temperature and voltage
characteristics. Note that the ripple current rating from
capacitor manufactures are based on certain amount of
life time. Further de-rating may be necessary for practical
design requirement.
The inductor takes the highest current in a buck circuit.
The conduction loss on inductor needs to be checked for
thermal and efficiency requirements.
Surface mount inductors in different shape and styles are
available from Coilcraft, Elytone and Murata. Shielded
inductors are small and radiate less EMI noise. But they
cost more than unshielded inductors. The choice
depends on EMI requirement, price and size.
Table 2 lists some inductors for typical output voltage
design.
Inductor
The inductor is used to supply constant current to output
when it is driven by a switching voltage. For given input
and output voltage, inductance and switching frequency
together decide the inductor ripple current, which is,
Output Capacitor
The output capacitor is selected based on the DC output
voltage rating, output ripple voltage specification and rip-
ple current rating.
V
V
O
O
∆I
=
× 1 –
-----------
----------
L
V
The selected output capacitor must have a higher rated
voltage specification than the maximum desired output
voltage including ripple. De-rating needs to be consid-
ered for long term reliability.
f × L
IN
The peak inductor current is:
∆I
L
I
= I
+
O
Output ripple voltage specification is another important
factor for selecting the output capacitor. In a buck con-
verter circuit, output ripple voltage is determined by
inductor value, switching frequency, output capacitor
value and ESR. It can be calculated by the equation
below:
--------
Lpeak
2
High inductance gives low inductor ripple current but
requires larger size inductor to avoid saturation. Low
ripple current reduces inductor core losses. It also
reduces RMS current through inductor and switches,
which results in less conduction loss.
1
∆V = ∆I × ESR +
CO
--------------------------
O
L
8 × f × C
O
Table 2.Typical Inductors
V
(V)
L1
Manufacture
OUT
5.0
Unshielded, 4.7µH LQH55DN4R7M03
Shielded, 4.7µH LQH66SN4R7M03
Shield, 5.8µH ET553-5R8
MURATA
MURATA
ELYTONE
Coilcraft
MURATA
MURATA
ELYTONE
Coilcraft
Coilcraft
MURATA
MURATA
ELYTONE
Coilcraft
Coilcraft
Un-shielded, 6.7µH DO3316P-682MLD
Unshielded, 4.7µH LQH55DN3R3M03
Shield, 4.7µH LQH66SN3R3M03
Shield, 3.3µH ET553-3R3
3.3
Un-shielded, 4.7µH DO3316P-472MLD
Un-shielded, 4.7µH DO1813P-472HC
Unshielded, 2.2µH LQH55DN1R5M03
Shield, 2.2µH LQH66SN1R5M03
Shield, 2.2µH ET553-2R2
1.8
Un-shielded, 2.2µH DO3316P-222MLD
Un-shielded, 2.2µH DO1813P-222HC
Rev. 1.0 November 2006
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Page 8 of 14
AOZ1018
where C is output capacitor value and ESR is the
Equivalent Series Resistor of output capacitor.
With peak current mode control, the buck power stage
can be simplified to be a one-pole and one-zero system
in frequency domain. The pole is dominant pole and can
be calculated by:
O
CO
When low ESR ceramic capacitor is used as output
capacitor, the impedance of the capacitor at the switching
frequency dominates. Output ripple is mainly caused by
capacitor value and inductor ripple current. The output
ripple voltage calculation can be simplified to:
1
f
=
-----------------------------------
p1
2π × C × R
O
L
The zero is a ESR zero due to output capacitor and its
ESR. It is can be calculated by:
1
∆V = ∆I ×
--------------------------
O
L
8 × f × C
O
1
f
=
-------------------------------------------------
Z 1
If the impedance of ESR at switching frequency domi-
nates, the output ripple voltage is mainly decided by
capacitor ESR and inductor ripple current. The output
ripple voltage calculation can be further simplified to:
2π × C × ESR
O
CO
where;
is the output filter capacitor,
C
O
R is load resistor value, and
L
∆V = ∆I × ESR
CO
O
L
ESR is the equivalent series resistance of output capacitor.
CO
For lower output ripple voltage across the entire operat-
ing temperature range; X5R or X7R dielectric type of
ceramic, or other low ESR tantalum or electrolytic output
capacitor is recommended.
The compensation design is actually to shape the con-
verter close loop transfer function to get desired gain and
phase. Several different types of compensation network
can be used for the AOZ1018. For most cases, a series
capacitor and resistor network connected to the COMP
pin sets the pole-zero and is adequate for a stable high-
bandwidth control loop.
In a buck converter, output capacitor current is continu-
ous. The RMS current of output capacitor is decided by
the peak to peak inductor ripple current. It can be
calculated by:
In the AOZ1018, FB pin and COMP pin are the inverting
input and the output of internal transconductance error
amplifier. A series R and C compensation network
connected to COMP provides one pole and one zero.
The pole is:
∆I
L
I
=
----------
CORMS
12
Usually, the ripple current rating of the output capacitor
is a smaller issue because of the low current stress.
When the buck inductor is selected to be very small and
inductor ripple current is high, output capacitor could be
overstressed.
G
EA
f
=
-------------------------------------------
p2
2π × C × G
C
VEA
where;
is the error amplifier transconductance, which is 200 x 10
-6
G
EA
Schottky Diode Selection
A/V,
G
is the error amplifier voltage gain, which is 500 V/V, and
The external freewheeling diode supplies the current to
the inductor when the high side PMOS switch is off. To
reduce the losses due to the forward voltage drop and
recovery of diode, Schottky diode is recommended to
use. The maximum reverse voltage rating of the chosen
Schottky diode should be greater than the maximum
input voltage, and the current rating should be greater
than the maximum load current.
VEA
C is compensation capacitor.
C
The zero given by the external compensation network,
capacitor C and resistor R , is located at:
C
C
1
f
=
------------------------------------
Z 2
2π × C × R
C
C
To design the compensation circuit, a target crossover
Loop Compensation
frequency f for close loop must be selected.The system
C
The AOZ1018 employs peak current mode control for
easy use and fast transient response. Peak current mode
control eliminates the double pole effect of the output
L&C filter. It greatly simplifies the compensation loop
design.
crossover frequency is where control loop has unity gain.
The crossover frequency is also called the converter
bandwidth. Generally a higher bandwidth means faster
response to load transient. However, the bandwidth
should not be too high because of system stability
Rev. 1.0 November 2006
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Page 9 of 14
AOZ1018
concern. When designing the compensation loop,
converter stability under all line and load condition must
be considered.
flows in the first loop when the high side switch is on.The
second loop starts from inductor, to the output capacitors
and load, to the anode of Schottky diode, to the cathode
of Schottky diode. Current flows in the second loop when
the low side diode is on.
Usually, it is recommended to set the bandwidth to be
less than 1/10 of switching frequency. The AOZ1018
operates at a fixed switching frequency range from
350kHz to 600kHz. It is recommended to choose a
crossover frequency less than 30kHz.
In PCB layout, minimizing the two loops area reduces the
noise of this circuit and improves efficiency. A ground
plane is strongly recommended to connect input capaci-
tor, output capacitor, and PGND pin of the AOZ1018.
f
= 30kHz
C
In the AOZ1018 buck regulator circuit, the major power
dissipating components are the AOZ1018, the Schottky
diode and output inductor. The total power dissipation of
converter circuit can be measured by input power minus
output power.
The strategy for choosing R and C is to set the cross
C
C
over frequency with R and set the compensator zero
C
with C . Using selected crossover frequency, f , to
C
C
calculate R :
C
P
= V × I – V × I
IN IN O O
totalloss
V
2π × C
O
O
R
= f
×
C
×
----------- -----------------------------
× G
C
V
G
EA
The power dissipation in Schottky can be approximated
as:
FB
CS
where;
f is desired crossover frequency,
P
= I × (1 – D) × V
O FWSchottky
diodeloss
C
where;
V
is 0.8V,
FB
-6
V
is the Schottky diode forward voltage drop.
G
is the error amplifier transconductance, which is 200x10
FWSchottky
EA
A/V, and
The power dissipation of inductor can be approximately
calculated by output current and DCR of inductor.
G
is the current sense circuit transconductance, which is
CS
5.64 A/V.
2
P
= I × R
× 1.1
inductor
The compensation capacitor C and resistor R together
inductorloss
O
C
C
make a zero. This zero is put somewhere close to the
dominate pole fp1 but lower than 1/5 of selected cross-
The junction to ambient temperature can be calculated
with power dissipation in the AOZ1018 and thermal
impedance from junction to ambient.
over frequency. C can is selected by:
C
1.5
C
=
------------------------------------
C
T
=
jun-amb
2π × R × f
C
p1
(P
– P
– P
) × Θ
inductorloss JA
totalloss
diodeloss
Equation above can also be simplified to:
The maximum junction temperature of AOZ1018 is
145°C, which limits the maximum load current capability.
Please see the thermal de-rating curves for maximum
load current of the AOZ1018 under different ambient
temperature.
C
× R
L
O
C
=
----------------------
C
R
C
An easy-to-use application software which helps to
design and simulate the compensation loop can be found
at www.aosmd.com.
The thermal performance of the AOZ1018 is strongly
affected by the PCB layout. Extra care should be taken
by users during design process to ensure that the IC
will operate under the recommended environmental
conditions.
Thermal Management and Layout
Consideration
In the AOZ1018 buck regulator circuit, high pulsing cur-
rent flows through two circuit loops. The first loop starts
Several layout tips are listed below for the best electric
and thermal performance. Figure 3 illustrates a PCB
layout example as reference.
from the input capacitors, to the V pin, to the LX pins, to
IN
the filter inductor, to the output capacitor and load, and
then return to the input capacitor through ground. Current
Rev. 1.0 November 2006
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Page 10 of 14
AOZ1018
Figure 3. AOZ1018 PCB Layout
1. Do not use thermal relief connection to the V and
5. Pour copper plane on all unused board area and con-
nect it to stable DC nodes, like V , GND or V
IN
.
OUT
the PGND pin. Pour a maximized copper area to the
IN
PGND pin and the V pin to help thermal dissipation.
IN
6. The LX pin is connected to internal PFET drain.They
are low resistance thermal conduction path and most
noisy switching node. Connected a copper plane to
LX pin to help thermal dissipation. This copper plane
should not be too larger otherwise switching noise
may be coupled to other part of circuit.
2. Input capacitor should be connected to the V pin
IN
and the PGND pin as close as possible.
3. A ground plane is preferred. If a ground plane is not
used, separate PGND from AGND and connect them
only at one point to avoid the PGND pin noise cou-
pling to the AGND pin. In this case, put small decou-
pling capacitor to stabilize the input voltage of IC.
7. Keep sensitive signal trace far away form the LX pin.
4. Make the current trace from LX pin to L to Co to the
PGND as short as possible.
Rev. 1.0 November 2006
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Page 11 of 14
AOZ1018
Package Dimensions
D
e
Gauge Plane
Seating Plane
0.25
8
L
E
E1
h x 45°
1
C
θ
7° (4x)
A2
A
0.1
A1
b
Dimensions in millimeters
Dimensions in inches
Symbols Min. Nom. Max.
Symbols Min.
Nom. Max.
0.053 0.065 0.069
0.004 0.010
0.049 0.059 0.065
2.20
A
A1
A2
b
1.35
0.10
1.25
0.31
0.17
4.80
3.80
1.65
—
1.75
0.25
1.65
0.51
0.25
5.00
4.00
A
A1
A2
b
—
1.50
—
0.012
0.007
—
—
0.020
0.010
c
—
c
5.74
D
E1
e
4.90
3.90
1.27 BSC
6.00
—
D
E1
e
0.189 0.193 0.197
0.150 0.154 0.157
0.050 BSC
1.27
E
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
E
0.228 0.236 0.244
h
h
0.010
0.016
0°
—
—
—
0.020
0.050
8°
L
—
L
0.80
θ
—
θ
Unit: mm
Notes:
1. All dimensions are in millimeters.
2. Dimensions are inclusive of plating
3. Package body sizes exclude mold flash and gate burrs. Mold flash at the non-lead sides should be less than 6 mils.
4. Dimension L is measured in gauge plane.
5. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact.
Rev. 1.0 November 2006
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Page 12 of 14
AOZ1018
Tape and Reel Dimensions
SO-8 Carrier Tape
P1
P2
See Note 3
D1
T
See Note 5
E1
E2
E
See Note 3
B0
K0
D0
P0
A0
Feeding Direction
Unit: mm
Package
A0
B0
K0
D0
D1
E
E1
E2
P0
P1
P2
T
SO-8
(12mm)
6.40
0.10
5.20
0.10
2.10
0.10
1.60
0.10
1.50
0.10
12.00 1.75
0.10 0.10
5.50
0.10
8.00
0.10
4.00
0.10
2.00
0.10
0.25
0.10
SO-8 Reel
W1
S
G
V
N
K
M
R
H
W
Tape Size Reel Size
M
N
W
W1
ø330.00 ø97.00 13.00 17.40
H
K
S
G
R
V
ø13.00
+0.50/-0.20
10.60
2.00
0.50
—
—
—
12mm
ø330
0.50
0.10
0.30
1.00
SO-8 Tape
Leader/Trailer
& Orientation
Trailer Tape
300mm min. or
Components Tape
Orientation in Pocket
Leader Tape
500mm min. or
75 empty pockets
125 empty pockets
Rev. 1.0 November 2006
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Page 13 of 14
AOZ1018
AOZ1018 Package Marking
Z1018AI
FAYWLT
Part Number
Assembly Lot Code
Fab & Assembly Location
Year & Week Code
Rev. 1.0 November 2006
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Page 14 of 14
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