AOZ1022PI [AOS]
EZBuck⢠3A Synchronous Buck Regulator; EZBuckâ ?? ¢ 3A同步降压稳压器
| 型号： | AOZ1022PI |
| 厂家： | 
ALPHA & OMEGA SEMICONDUCTORS |
| 描述： | EZBuck⢠3A Synchronous Buck Regulator |
| 文件： | 总17页 (文件大小：842K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AOZ1022
EZBuck™ 3A Synchronous Buck Regulator
General Description
Features
The AOZ1022 is a synchronous high efficiency, simple
to use, 3A buck regulator. The AOZ1022 works from a
4.5V to 16V input voltage range, and provides up to 3A
of continuous output current with an output voltage
adjustable down to 0.8V.
● 4.5V to 16V operating input voltage range
● Synchronous rectification: 100mΩ internal high-side
switch and 20mΩ Internal low-side switch
● High efficiency: up to 95%
● Internal soft start
The AOZ1022 comes in a DFN 5x4 and an EPAD SO-8
package and is rated over a -40°C to +85°C ambient
temperature range.
● Active high power good state
● Output voltage adjustable to 0.8V
● 3A continuous output current
● Fixed 500kHz PWM operation
● Cycle-by-cycle current limit
● Pre-bias start-up
● Short-circuit protection
● Thermal shutdown
● Small size DFN 5x4 and EPAD SO-8 package
Applications
● Point of load DC-DC conversion
● PCIe graphics cards
● Set top boxes
● DVD drives and HDD
● LCD panels
● Cable modems
● Telecom/networking/datacom equipment
Typical Application
VIN
5V DC
C1
R3
22µF
Ceramic
PGOOD
VIN
L1 4.7µH
EN
COMP
VOUT
LX
AOZ1022
R1
R2
C2, C3
R
C
22µF Ceramic
C
C
FB
AGND
PGND
Figure 1. 3.3V/3A Synchronous Buck Regulator
Rev. 1.6 December 2010
www.aosmd.com
Page 1 of 17
AOZ1022
Ordering Information
Part Number
Ambient Temperature Range
Package
Environmental
AOZ1022DI
AOZ1022
-40°C to +85°C
-40°C to +85°C
DFN 5x4
EPAD S0-8
Green
AOS Green Products use reduced levels of Halogens, and are also RoHS compliant.
Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information.
Pin Configuration
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
PGND
VIN
NC
PGND
VIN
PGOOD
LX
LX
PGOOD
EN
PAD
(LX)
AGND
FB
EN
AGND
FB
GND
COMP
COMP
Exposed Pad SO-8
5x4 DFN-8
(Top View)
(Top View)
Pin Description
Pin Number
Exposed
5x4 DFN-8
Pad SO-8 Pin Name
Pin Function
1
2
1
2
PGND
VIN
Power ground. PGND needs to be electrically connected to AGND.
Supply voltage input. When VIN rises above the UVLO threshold and EN is logic high,
the device starts up.
3
4
5
6
7
8
3
4
AGND
FB
Analog ground. AGND is the reference point for controller section. AGND needs to
be electrically connected to PGND.
Feedback input. The FB pin is used to set the output voltage via a resistor divider
between the output and AGND.
5
COMP
EN
External loop compensation pin. Connect a RC network between COMP and AGND
to compensate the control loop.
6
Enable pin. Pull EN to logic high to enable the device. Pull EN to logic low to disable
the device. if on/off control is not needed, connect it to VIN and do not leave it open.
Pad
7
LX
Switching node. LX is the drain of the internal PFET. LX is used as the thermal pad of
the power stage.
PGOOD Power Good Output. PGOOD is an open-drain output that indicates the status of out-
put voltage. PGOOD is pulled low when output is below 90% of the normal regula-
tion.
8
NC
No Connect. Pin 8 is not internally connected.
Rev. 1.6 December 2010
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Page 2 of 17
AOZ1022
Block Diagram
VIN
Internal
+5V
UVLO
& POR
5V LDO
Regulator
OTP
EN
+
ISen
–
Reference
& Bias
Softstart
Q1
ILimit
+
–
+
Level
Shifter
+
FET
Driver
+
–
PWM
Control
Logic
0.8V
PWM
Comp
EAmp
FB
LX
Q2
COMP
Frequency
Foldback
Comparator
Oscillator
+
–
0.2V
PGOOD
–
+
0.72V
AGND
PGND
Absolute Maximum Ratings
Exceeding the Absolute Maximum Ratings may damage the
device.
Recommended Operating Conditions
The device is not guaranteed to operate beyond the Maximum
Recommended Operating Conditions.
Parameter
Supply Voltage (VIN)
Rating
Parameter
Supply Voltage (VIN)
Rating
18V
4.5V to 18V
0.8V to VIN
LX to AGND
-0.7V to VIN+0.3V
-0.3V to VIN+0.3V
-0.3V to 6V
Output Voltage Range
EN to AGND
Ambient Temperature (TA)
Package Thermal Resistance
-40°C to +85°C
50°C/W
FB to AGND
)
(2
Exposed Pad SO-8 (ΘJA
)
COMP to AGND
PGND to AGND
PGOOD to AGND
Junction Temperature (TJ)
Storage Temperature (TS)
ESD Rating(1)
-0.3V to 6V
Note:
-0.3V to 0.3V
-0.3V to 6V
2. The value of ΘJA is measured with the device mounted on
1-in2 FR-4 board with 2oz. Copper, in a still air environment with
TA = 25°C. The value in any given application depends on the
+150°C
user's specific board design.
-65°C to +150°C
2.0kV
Note:
1. Devices are inherently ESD sensitive, handling precautions are
required. Human body model rating: 1.5kΩ in series with 100pF.
Rev. 1.6 December 2010
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Page 3 of 17
AOZ1022
Electrical Characteristics
TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified.(3)
Symbol
Parameter
Conditions
Min.
4.5
Typ. Max. Units
VIN
Supply Voltage
16
V
VUVLO
Input Under-Voltage Lockout Threshold
VIN Rising
VIN Falling
4.1
3.7
1.6
3
V
IIN
Supply Current (Quiescent)
Shutdown Supply Current
Feedback Voltage
IOUT = 0, VFB = 1.2V, VEN > 1.2V
VEN = 0V
2.5
20
mA
µA
V
IOFF
VFB
TA = 25°C
0.788
0.8
0.5
1
0.812
Load Regulation
%
Line Regulation
%
IFB
ENABLE
VEN
Feedback Voltage Input Current
200
nA
EN Input Threshold
EN Input Hysteresis
Off Threshold
On Threshold
0.6
V
2
VHYS
100
mV
MODULATOR
fO
Frequency
350
100
500
600
6
kHz
%
DMAX
DMIN
GVEA
GEA
Maximum Duty Cycle
Minimum Duty Cycle
%
Error Amplifier Voltage Gain
Error Amplifier Transconductance
500
200
V / V
µA / V
PROTECTION
ILIM Current Limit
4.0
3
5.0
7
A
Over-Temperature Shutdown Limit
TJ Rising
TJ Falling
150
100
5
°C
ms
tSS
POWER GOOD
Soft Start Interval
VOLPG
VPGL
tPG
PGOOD LOW Voltage
IOL = 1mA
0.5
1
V
µA
PGOOD Leakage
PGOOD Threshold Voltage
PGOOD Threshold Voltage Hysteresis
PGOOD Delay Time
87
90
3
92
%VO
%
128
µs
PWM OUTPUT STAGE
High-Side Switch On-Resistance
VIN = 12V
VIN = 5V
VIN = 12V
VIN = 5V
97
166
18
130
200
23
mΩ
mΩ
Low-Side Switch On-Resistance
30
36
Note:
3. Specifications in BOLD indicate an ambient temperature range of -40°C to +85°C. These specifications are guaranteed by design.
Rev. 1.6 December 2010
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Page 4 of 17
AOZ1022
Typical Performance Characteristics
Circuit of Figure 1. TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified.
Light Load Operation
Full Load (CCM) Operation
Vin ripple
0.1V/div
Vin ripple
0.1V/div
Vo ripple
20mV/div
Vo ripple
20mV/div
IL
1A/div
IL
1A/div
VLX
10V/div
VLX
10V/div
1s/div
1s/div
Startup to Full Load
Short Circuit Protection
Vin
LX
10V/div
10V/div
Vo
2V/div
Vo
2V/div
lin
IL
1A/div
2A/div
50µs/div
1ms/div
50% to 100% Load Transient
Short Circuit Recovery
LX
10V/div
Vo Ripple
100mV/div
Vo
2V/div
lo
1A/div
IL
2A/div
1ms/div
100s/div
Rev. 1.6 December 2010
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Page 5 of 17
AOZ1022
Efficiency
AOZ1022 Efficiency
Efficiency (VIN = 12V) vs. Load Current
AOZ1022 Efficiency
Efficiency (VIN = 5V) vs. Load Current
100
95
90
85
80
75
70
100
95
90
85
80
75
70
65
5.0V OUTPUT
3.3V OUTPUT
3.3V OUTPUT
1.8V OUTPUT
1.8V
1.2V OUTPUT
65
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
Load Current (A)
Load Current (A)
Thermal Derating Curves
Derating Curve at 5V/6V Input
Derating Curve at 12 Input
5
4
3
2
1
0
3.3
3.2
3.1
3.0
2.9
2.8
1.2V, 1.8V OUTPUT
3.3V
OUTPUT
1.2V, 1.8V, 3.3V, 5.0V OUTPUT
25
35
45
55
65
75
85
25
35
45
55
65
75
85
Ambient Temperature (TA)
Ambient Temperature (TA)
Rev. 1.6 December 2010
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Page 6 of 17
AOZ1022
against the current signal, which is sum of inductor
Detailed Description
current signal and ramp compensation signal, at the
PWM comparator input. If the current signal is less than
the error voltage, the internal high-side switch is on. The
inductor current flows from the input through the inductor
to the output. When the current signal exceeds the error
voltage, the high-side switch is off. The inductor current
is freewheeling through the internal low-side N-MOSFET
switch to output. The internal adaptive FET driver
guarantees no turn on overlap of both high-side and
low-side switch.
The AOZ1022 is a current-mode step down regulator
with integrated high-side PMOS switch and a low-side
NMOS switch. It operates from a 4.5V to 16V input
voltage range and supplies up to 3A of load current.
The duty cycle can be adjusted from 6% to 100%
allowing a wide range of output voltage. Features include
enable control, Power-On Reset, input under voltage
lockout, output over voltage protection, active high power
good state, fixed internal soft-start and thermal shut
down.
Comparing with regulators using freewheeling Schottky
diodes, the AOZ1022 uses freewheeling NMOSFET to
realize synchronous rectification. It greatly improves the
converter efficiency and reduces power loss in the
low-side switch.
Enable and Soft Start
The AOZ1022 has an internal soft start feature to limit
in-rush current and ensure the output voltage ramps up
smoothly to regulation voltage. A soft start process
begins when the input voltage rises to 4.1V and voltage
on EN pin is HIGH. In the soft start process, the output
voltage is typically ramped to regulation voltage in 4ms.
The 4ms soft start time is set internally.
The AOZ1022 uses a P-Channel MOSFET as the high-
side switch. It saves the bootstrap capacitor normally
seen in a circuit which is using an NMOS switch. It allows
100% turn-on of the high-side switch to achieve linear
regulation mode of operation. The minimum voltage drop
from V to V is the load current x DC resistance of
The EN pin of the AOZ1022 is active HIGH. Connect the
EN pin to V if the enable function is not used.
IN
O
IN
MOSFET + DC resistance of buck inductor. It can be
calculated by the equation below:
Pulling EN to ground will disable the AOZ1022. Do not
leave it open. The voltage on the EN pin must be above
2V to enable the AOZ1022. When voltage on the EN
pin falls below 0.6V, the AOZ1022 is disabled. If an appli-
cation circuit requires the AOZ1022 to be disabled, an
open drain or open collector circuit should be used to
interface to the EN pin.
V
= V – I × R
IN O DS(ON)
O_MAX
where;
VO_MAX is the maximum output voltage,
IN is the input voltage from 4.5V to 16V,
O is the output current from 0A to 3A, and
V
I
Power Good
RDS(ON) is the on resistance of internal MOSFET, the value is
between 97mΩ and 200mΩ depending on input voltage and
junction temperature.
The output of Power-Good is an open drain N-channel
MOSFET which supplies an active high power good
stage. A pull-up resistor (R ) should connect this pin to a
3
DC power trail with maximum voltage of 6V. The
AOZ1022 monitors the FB voltage. When FB voltage is
lower than 90% of the normal voltage, N-channel
MOSFET turns on and the Power-Good pin is pulled low.
This indicates the power is abnormal.
Switching Frequency
The AOZ1022 switching frequency is fixed and set by
an internal oscillator. The practical switching frequency
could range from 350kHz to 600kHz due to device
variation.
Steady-State Operation
Output Voltage Programming
Under steady-state conditions, the converter operates in
fixed frequency and Continuous-Conduction Mode
(CCM).
Output voltage can be set by feeding back the output to
the FB pin by using a resistor divider network. See the
application circuit shown in Figure 1. The resistor divider
The AOZ1022 integrates an internal P-MOSFET as the
high-side switch. Inductor current is sensed by amplifying
the voltage drop across the drain to source of the high
side power MOSFET. Output voltage is divided down by
the external voltage divider at the FB pin. The difference
of the FB pin voltage and reference is amplified by the
internal transconductance error amplifier. The error
voltage, which shows on the COMP pin, is compared
network includes R and R . Usually, a design is started
1 2
by picking a fixed R value and calculating the required
2
R with equation on the next page:
1
R
⎛
⎞
⎟
⎠
1
------
V
= 0.8 × 1 +
⎜
O
R
⎝
2
Rev. 1.6 December 2010
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Page 7 of 17
AOZ1022
Some standard value of R , R and most used output
Thermal Protection
1
2
voltage values are listed in Table 1.
An internal temperature sensor monitors the junction
temperature. It shuts down the internal control circuit and
high side PMOS if the junction temperature exceeds
150°C. The regulator will restart automatically under the
control of soft-start circuit when the junction temperature
decreases to 100°C.
V (V)
R (kΩ)
R (kΩ)
O
1
2
0.8
1.2
1.5
1.8
2.5
3.3
5.0
1.0
4.99
10
open
10
11.5
10.2
10
12.7
21.5
31.1
52.3
Application Information
10
The basic AOZ1022 application circuit is show in
Figure 1. Component selection is explained below.
10
Input Capacitor
The combination of R and R should be large enough to
1
2
avoid drawing excessive current from the output, which
will cause power loss.
The input capacitor must be connected to the V pin and
IN
PGND pin of AOZ1022 to maintain steady input voltage
and filter out the pulsing input current. The voltage rating
of input capacitor must be greater than maximum input
voltage plus ripple voltage.
Since the switch duty cycle can be as high as 100%, the
maximum output voltage can be set as high as the input
voltage minus the voltage drop on upper PMOS and
inductor.
The input ripple voltage can be approximated by equa-
tion below:
Protection Features
I
V
V
O
⎛
⎞
⎟
⎠
O
O
-----------------
--------
--------
The AOZ1022 has multiple protection features to prevent
system circuit damage under abnormal conditions.
ΔV
=
× 1 –
×
⎜
IN
f × C
V
V
⎝
IN
IN
IN
Since the input current is discontinuous in a buck
converter, the current stress on the input capacitor is
another concern when selecting the capacitor. For a
buck circuit, the RMS value of input capacitor current
can be calculated by:
Over Current Protection (OCP)
The sensed inductor current signal is also used for
over current protection. Since the AOZ1022 employs
peak current mode control, the COMP pin voltage is
proportional to the peak inductor current. The COMP pin
voltage is limited to be between 0.4V and 2.5V internally.
The peak inductor current is automatically limited cycle
by cycle.
V
⎛
⎜
⎝
⎞
⎟
⎠
V
O
O
--------
IN
--------
I
= I ×
1 –
CIN_RMS
O
V
V
IN
When the output is shorted to ground under fault
conditions, the inductor current decays very slow during
if we let m equal the conversion ratio:
V
O
a switching cycle because of V = 0V. To prevent cata-
O
--------
= m
strophic failure, a secondary current limit is designed
inside the AOZ1022. The measured inductor current is
compared against a preset voltage which represents the
current limit, between 3.5A and 5.0A. When the output
current is more than current limit, the high side switch will
be turned off. The converter will initiate a soft start once
the over-current condition is resolved.
V
IN
The relation between the input capacitor RMS current
and voltage conversion ratio is calculated and shown in
Figure 2 on the next page. It can be seen that when V is
O
half of V , C is under the worst current stress. The
IN
IN
worst current stress on C is 0.5 x I .
IN
O
For reliable operation and best performance, the input
capacitors must have current rating higher than I
Power-On Reset (POR)
CIN_RMS
A power-on reset circuit monitors the input voltage.
When the input voltage exceeds 4.1V, the converter
starts operation. When input voltage falls below 3.7V,
the converter shuts down.
at worst operating conditions. Ceramic capacitors are
preferred for input capacitors because of their low ESR
and high current rating. Depending on the application
circuits, other low ESR tantalum capacitor may also be
used. When selecting ceramic capacitors, X5R or X7R
type dielectric ceramic capacitors should be used for
their better temperature and voltage characteristics.
Rev. 1.6 December 2010
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Page 8 of 17
AOZ1022
Output Capacitor
0.5
0.4
0.3
0.2
0.1
0
The output capacitor is selected based on the DC output
voltage rating, output ripple voltage specification and
ripple current rating.
ICIN_RMS(m)
IO
The selected output capacitor must have a higher rated
voltage specification than the maximum desired output
voltage including ripple. De-rating needs to be consid-
ered for long term reliability.
Output ripple voltage specification is another important
factor for selecting the output capacitor. In a buck con-
verter circuit, output ripple voltage is determined by
inductor value, switching frequency, output capacitor
value and ESR. It can be calculated by the equation
below:
0
0.5
m
1
Figure 2. ICIN vs. Voltage Conversion Ratio
Note that the ripple current rating from capacitor manu-
factures are based on certain amount of life time.
Further de-rating may be necessary in practical design.
1
⎛
⎞
⎠
-------------------------
ΔV = ΔI × ESR
+
O
L
CO
⎝
8 × f × C
O
Inductor
where,
The inductor is used to supply constant current to output
when it is driven by a switching voltage. For given input
and output voltage, inductance and switching frequency
together decide the inductor ripple current, which is:
CO is output capacitor value, and
ESRCO is the equivalent series resistance of the output
capacitor.
V
When low ESR ceramic capacitor is used as output
capacitor, the impedance of the capacitor at the switching
frequency dominates. Output ripple is mainly caused by
capacitor value and inductor ripple current. The output
ripple voltage calculation can be simplified to:
⎛
⎞
⎟
⎠
V
O
O
----------
--------
ΔI
=
× 1 –
⎜
L
f × L
V
⎝
IN
The peak inductor current is:
ΔI
L
1
⎛
⎝
⎞
⎠
--------
I
= I +
-------------------------
ΔV = ΔI ×
Lpeak
O
O
L
2
8 × f × C
O
High inductance gives low inductor ripple current but
requires larger size inductor to avoid saturation. Low
ripple current reduces inductor core losses. It also
reduces RMS current through inductor and switches,
which results in less conduction loss. Usually, peak to
peak ripple current on inductor is designed to be 20%
to 30% of output current.
If the impedance of ESR at switching frequency
dominates, the output ripple voltage is mainly decided
by capacitor ESR and inductor ripple current. The output
ripple voltage calculation can be further simplified to:
ΔV = ΔI × ESR
CO
O
L
For lower output ripple voltage across the entire operat-
ing temperature range, X5R or X7R dielectric type of
ceramic, or other low ESR tantalum are recommended to
be used as output capacitors.
When selecting the inductor, make sure it is able to
handle the peak current without saturation even at the
highest operating temperature.
The inductor takes the highest current in a buck circuit.
The conduction loss on inductor need to be checked for
thermal and efficiency requirements.
In a buck converter, output capacitor current is continuous.
The RMS current of output capacitor is decided by the
peak to peak inductor ripple current. It can be calculated
by:
Surface mount inductors in different shape and styles are
available from Coilcraft, Elytone and Murata. Shielded
inductors are small and radiate less EMI noise. But they
cost more than unshielded inductors. The choice
depends on EMI requirement, price and size.
ΔI
L
----------
I
=
CO_RMS
12
Usually, the ripple current rating of the output capacitor is
a smaller issue because of the low current stress. When
the buck inductor is selected to be very small and induc-
Rev. 1.6 December 2010
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Page 9 of 17
AOZ1022
tor ripple current is high, the output capacitor could be
overstressed.
The zero given by the external compensation network,
capacitor C and resistor R , is located at:
2
3
1
Loop Compensation
-----------------------------------
=
f
Z2
2π × C × R
C
C
The AOZ1022 employs peak current mode control for
easy use and fast transient response. Peak current mode
control eliminates the double pole effect of the output
L&C filter. It greatly simplifies the compensation loop
design.
To design the compensation circuit, a target crossover
frequency f for close loop must be selected. The system
C
crossover frequency is where control loop has unity gain.
The crossover is the also called the converter bandwidth.
Generally a higher bandwidth means faster response to
load transient. However, the bandwidth should not be too
high because of system stability concern. When design-
ing the compensation loop, converter stability under all
line and load condition must be considered.
With peak current mode control, the buck power stage
can be simplified to be a one-pole and one-zero system
in frequency domain. The pole is the dominant pole can
be calculated by:
1
----------------------------------
f
=
Usually, it is recommended to set the bandwidth to be
equal or less than 1/10 of switching frequency. The
AOZ1022 operates at a frequency range from 350kHz
to 600kHz. It is recommended to choose a crossover
frequency equal or less than 40kHz.
p1
2π × C × R
O
L
The zero is an ESR zero due to output capacitor and its
ESR. It is can be calculated by:
1
------------------------------------------------
f
=
f
= 40kHz
Z1
C
2π × C × ESR
O
CO
The strategy for choosing R and C is to set the
C
C
where;
cross over frequency with R and set the compensator
C
zero with C . Using selected crossover frequency, f ,
CO is the output filter capacitor,
C
C
to calculate R :
3
RL is load resistor value, and
ESRCO is the equivalent series resistance of output capacitor.
V
2π × C
2
O
---------- -----------------------------
R
= f ×
×
C
C
The compensation design is actually to shape the
converter control loop transfer function to get the desired
gain and phase. Several different types of compensation
network can be used for the AOZ1022. In most cases, a
series capacitor and resistor network connected to the
COMP pin sets the pole-zero and is adequate for a stable
high-bandwidth control loop.
V
G
× G
EA CS
FB
where;
where fC is desired crossover frequency. For best performance,
fC is set to be about 1/10 of switching frequency,
VFB is 0.8V,
GEA is the error amplifier transconductance, which is 200 x 10-6
A/V, and
In the AOZ1022, FB pin and COMP pin are the inverting
input and the output of internal error amplifier. A series R
and C compensation network connected to COMP
provides one pole and one zero. The pole is:
GCS is the current sense circuit transconductance, which is 6.86
A/V
The compensation capacitor C and resistor R together
C
C
make a zero. This zero is put somewhere close to the
G
EA
------------------------------------------
dominate pole f but lower than 1/5 of selected
f
=
p1
p2
2π × C × G
crossover frequency. C can is selected by:
C
VEA
2
where;
1.5
----------------------------------
=
C
GEA is the error amplifier transconductance, which is 200 x 10-6
A/V,
C
2π × R × f
C
p1
The above equation can be simplified to:
GVEA is the error amplifier voltage; and
C2 is compensation capacitor in Figure 1.
C × R
O
L
---------------------
C
=
C
R
C
Rev. 1.6 December 2010
www.aosmd.com
Page 10 of 17
AOZ1022
An easy-to-use application software which helps to
design and simulate the compensation loop can be found
at www.aosmd.com.
The maximum junction temperature of AOZ1022 is
150°C, which limits the maximum load current capability.
Please see the thermal de-rating curves for maximum
load current of the AOZ1022 under different ambient
temperature.
Thermal Management and Layout
Consideration
The thermal performance of the AOZ1022 is strongly
affected by the PCB layout. Extra care should be taken
by users during design process to ensure that the IC
will operate under the recommended environmental
conditions.
In the AOZ1022 buck regulator circuit, high pulsing
current flows through two circuit loops. The first loop
starts from the input capacitors, to the V pin, to the LX
IN
pins, to the filter inductor, to the output capacitor and
load, and then return to the input capacitor through
ground. Current flows in the first loop when the high side
switch is on. The second loop starts from inductor, to the
output capacitors and load, to the anode of Schottky
diode, to the cathode of Schottky diode. Current flows in
the second loop when the low side diode is on.
The AOZ1022 comes in an EPAD SO-8 package. Layout
tips are listed below for the best electric and thermal
performance. Figure 3 illustrates a PCB layout example
of the AOZ1022.
1. The LX pins are connected to internal PFET and
NFET drains. They are low resistance thermal
conduction path and the most noisy switching node.
Connected a large copper plane to the LX pin to help
thermal dissipation.
In PCB layout, minimizing the two loops area reduces the
noise of this circuit and improves efficiency. A ground
plane is strongly recommended to connect input capaci-
tor, output capacitor, and PGND pin of the AOZ1022.
2. Do not use thermal relief connection to the V and
IN
In the AOZ1022 buck regulator circuit, the major power
dissipating components are the AOZ1022 and the
output inductor. The total power dissipation of converter
circuit can be measured by input power minus output
power.
the PGND pin. Pour a maximized copper area to the
PGND pin and the V pin to help thermal dissipation.
IN
3. Input capacitor should be connected to the V pin
IN
and the PGND pin as close as possible.
4. A ground plane is preferred. If a ground plane is
not used, separate PGND from AGND and connect
them only at one point to avoid the PGND pin noise
coupling to the AGND pin.
P
= V × I – V × I
IN IN O O
total_loss
The power dissipation of inductor can be approximately
calculated by output current and DCR of inductor.
5. Make the current trace from LX pins to L to Co to the
PGND as short as possible.
2
P
= I × R
× 1.1
inductor
inductor_loss
O
6. Pour copper plane on all unused board area and
The actual junction temperature can be calculated with
power dissipation in the AOZ1022 and thermal
impedance from junction to ambient.
connect it to stable DC nodes, like V , GND or V
.
OUT
IN
7. Keep sensitive signal trace far away form the LX
pins.
T
= (P
–P
) × Θ
inductor_loss
JA
junction
total_loss
Rev. 1.6 December 2010
www.aosmd.com
Page 11 of 17
AOZ1022
Package Dimensions, DFN 5x4
D
Index Area
(D/2 x E/2)
e
D/2
L3*
E2
L
E/2
L1
L2*
E
L2*
Pin #1 IDA
Chamfer 0.30
D3
D2
BOTTOM VIEW
TOP VIEW
A3
A
Seating
Plane
b
FRONT VIEW
Dimensions in millimeters
Dimensions in inches
RECOMMENDED LAND PATTERN
Symbols Min.
Nom. Max.
Symbols Min.
Nom. Max.
A
A3
b
0.70
0.75
0.20 Ref.
0.45
5.00
2.15
1.76
4.00
2.33
0.95 BSC
0.55
0.80
A
A3
b
0.028
0.30
0.008 Ref.
0.032
0.50 Typ.
0.95 Typ.
0.285
0.40
4.90
2.05
1.66
3.90
2.23
0.50
5.10
2.25
1.86
4.10
2.43
0.016 0.018 0.020
0.190 0.200 0.210
0.080 0.085 0.089
0.064 0.070 0.074
0.154 0.157 0.161
0.088 0.092 0.096
0.037 BSC
D
D
D2
D3
E
E2
e
D2
D3
E
E2
e
2.25
0.40
1.86
0.65
1.65
4.20
2.33
L
0.50
—
0.60
—
L
0.020 0.022 0.024
L1
L2
L3
aaa
bbb
ccc
ddd
eee
0.40
L1
L2
L3
aaa
bbb
ccc
ddd
eee
—
0.016
0.011 Ref.
0.033 Ref.
0.006
0.004
0.004
—
0.285 Ref.
0.835 Ref.
0.15
0.10
0.10
0.285
4.51
0.08
0.05
0.003
0.002
Notes:
1. Dimensions and tolerancing conform to ASME Y14.5M-1994.
2. All dimensions are in millimeters.
3. The location of the terminal #1 identifier and terminal numbering convention conforms to JEDEC publication 95 SP-002.
4. Dimension b applies to metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. If the terminal has the
optional radius on the other end of the terminal, the dimension b should not be measured in that radius area.
5. Coplanarity applies to the terminals and all other bottom surface metallization.
6. Drawing shown are for illustration only.
7. The dimensions with * are just for reference
8. Pin #3 and Pin #7 are fused to DAP.
Rev. 1.6 December 2010
www.aosmd.com
Page 12 of 17
AOZ1022
Tape Dimensions, DFN 5x4
T
D1
E1
E2
D0
E
B0
Feeding
Direction
K0
P0
A0
UNIT: mm
Package
A0
B0
K0
D0
D1
E
E1
E2
P0
P1
P2
T
1.50
+0.10 / –0
DFN 5x4
(12 mm)
5.30
0.10
4.30
0.10
1.20
0.10
12.00
0.30
1.75
0.10
5.50
0.10
8.00
0.10
4.00
0.20
2.00
0.10
0.30
0.05
1.50
Min.
Leader/Trailer and Orientation
Trailer Tape
300mm Min.
Components Tape
Orientation in Pocket
Leader Tape
500mm Min.
Rev. 1.6 December 2010
www.aosmd.com
Page 13 of 17
AOZ1022
Reel Dimensions, DFN 5x4
II
I
6.01
M
I
Zoom In
R1
P
B
W1
III
Zoom In
Tape Size
Reel Size
M
W1
B
P
ø330
12.40
2.40
0.3
0.5
3-1.8
12mm
ø330
0.05
+0.3
+2.0
-4.0
-0.0
II
Zoom In
A
N=ø1002
A A
1.8
6.0
6.450.05
6.2
0.00
8.00
-0.05
R1
2.20
2.00
8.90.1
14 REF
5.0
1.8
C
12 REF
11.90
46.00.1
44.50.1
41.5 REF
43.00
3.3
4.0
44.50.1
6.50
6.10
40
10.0
VIEW: C
2.5
1.80
0.80
3.00
A
8.00.1
2.00
6.50
8.00+0.050.00
10.71
6
Rev. 1.6 December 2010
www.aosmd.com
Page 14 of 17
AOZ1022
Package Dimensions, EPAD SO-8
Gauge plane
0.2500
D0
C
L
L1
E1
E
E2
E3
L1'
D1
D
Note 5
θ
7 (4x)
A2
A1
A
e
B
Dimensions in millimeters
Dimensions in inches
Symbols Min. Nom. Max.
Symbols Min. Nom. Max.
A
A1
A2
B
1.40
0.00
1.40
0.31
0.17
4.80
3.20
3.10
5.80
—
1.55
0.05
1.50
0.406
—
1.70
0.10
1.60
0.51
0.25
5.00
3.60
3.50
6.20
—
A
A1
A2
B
0.055 0.061 0.067
0.000 0.002 0.004
0.055 0.059 0.063
0.012 0.016 0.020
RECOMMENDED LAND PATTERN
3.70
C
C
0.007
—
0.010
D
4.96
3.40
3.30
6.00
1.27
3.90
2.41
0.40 REF
0.95
—
D
0.189 0.195 0.197
0.126 0.134 0.142
0.122 0.130 0.138
0.228 0.236 0.244
2.20
D0
D1
E
D0
D1
E
5.74
2.71
e
e
—
0.050
—
E1
E2
E3
L
3.80
2.21
4.00
2.61
E1
E2
E3
L
0.150 0.153 0.157
0.087 0.095 0.103
0.016 REF
2.87
0.40
—
1.27
0.10
8
0.016 0.037 0.050
y
y
—
0
—
3
0.004
8
0.80
UNIT: mm
1.27
θ
0
3
θ
0.635
|
L1–L1'
L1
|
—
0.04
1.04 REF
0.12
|
L1–L1'
L1
|
—
0.002 0.005
0.041 REF
Notes:
1. Package body sizes exclude mold flash and gate burrs.
2. Dimension L is measured in gauge plane.
3. Tolerance 0.10mm unless otherwise specified.
4. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact.
5. Die pad exposure size is according to lead frame design.
6. Followed from JEDEC MS-012
Rev. 1.6 December 2010
www.aosmd.com
Page 15 of 17
AOZ1022
Tape and Reel Dimensions, EPAD SO-8
Carrier Tape
P1
P2
D1
T
E1
E2
E
B0
K0
D0
P0
A0
Feeding Direction
UNIT: mm
Package
SO-8
A0
B0
K0
D0
D1
E
E1
E2
P0
P1
P2
T
6.40
5.20
2.10
1.60
1.50
12.00 1.75
5.50
8.00
4.00
2.00
0.25
(12mm) ±0.10 ±0.10 ±0.10 ±0.10 ±0.10 ±0.10 ±0.10 ±0.10 ±0.10 ±0.10 ±0.10 ±0.10
Reel
W1
S
G
V
N
K
M
R
H
W
UNIT: mm
Tape Size Reel Size
M
N
W
W1
ø330.00 ø97.00 13.00 17.40
±0.50 ±0.10 ±0.30 ±1.00 +0.50/-0.20
H
K
S
G
R
V
12mm
ø330
ø13.00
10.60
2.00
±0.50
—
—
—
Leader/Trailer and Orientation
Trailer Tape
300mm min. or
75 empty pockets
Components Tape
Orientation in Pocket
Leader Tape
500mm min. or
125 empty pockets
Rev. 1.6 December 2010
www.aosmd.com
Page 16 of 17
AOZ1022
Part Marking
Z1022DI
FAYWLT
Part Number Code
Assembly Lot Code
Fab & Assembly Location
Year & Week Code
Z1022
Part Number Code
FAYWLT
Assembly Lot Code
Fab & Assembly Location
Year & Week Code
This data sheet contains preliminary data; supplementary data may be published at a later date.
Alpha & Omega Semiconductor reserves the right to make changes at any time without notice.
LIFE SUPPORT POLICY
ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
2. A critical component in any component of a life
support, device, or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
Rev. 1.6 December 2010
www.aosmd.com
Page 17 of 17
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