AOZ8304 [AOS]
Low Capacitance 3.3V TVS Diode Array;
| 型号： | AOZ8304 |
| 厂家： | 
ALPHA & OMEGA SEMICONDUCTORS |
| 描述： | Low Capacitance 3.3V TVS Diode Array 电视 |
| 文件： | 总8页 (文件大小：935K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AOZ8304
Low Capacitance 3.3V TVS Diode Array
General Description
Features
The AOZ8304 is a transient voltage suppressor array
designed to protect high speed data lines from ESD and
lightning.
● ESD protection for high-speed data lines:
– IEC 61000-4-2, level 4 (ESD) immunity test
– ±24kV (air discharge) and ±24kV (contact discharge)
– IEC 61000-4-4 (EFT) 40A (5/50ns)
This device incorporates eight surge rated, low capaci-
tance steering diodes and a TVS in a single package.
During transient conditions, the steering diodes direct
the transient to either the positive side of the power
supply line or to ground. They may be used to meet the
ESD immunity requirements of IEC 61000-4-2, Level 4
and IEC 61000-4-5. The TVS diodes provide effective
suppression of ESD voltages: ±24kV (air discharge) and
±24kV (contact discharge).
– IEC 61000-4-5 (Lightning) 25
– Human Body Model (HBM) ±30kV
● Small package saves board space
● Low insertion loss
● Protects four I/O li
● Low clamping voltage
● Low operating voltage: 3.3V
● Green product
The AOZ8304 comes in a Halogen Free and RoHS
compliant DFN-10 2.6mm x 2.6mm package and is rated
over a -40°C to +85°C ambient temperature range. The
AOZ8304 is compatible with both lead free and SnPb
assembly techniques. The small size, low capacitance
and high ESD protection makes it ideal for protecting
high speed video and data communication interfaces.
● Pb-free device
Aplicatio
● 10/100/00 Ethernet
● USB 2.0 power and data line protection
● Video graphics cards
● Monitors and flat panel displays
● Digital Video Interface (DVI)
● T1/E1 telecom ports
Typical Application
AOZ8304
TRD0+
TRD0-
TRD1+
TRD1-
abit
Ehernet
Controller
RJ45
Connector
AOZ8304
TRD2+
TRD2-
TRD3+
TRD3-
VCC
75Ω
75Ω 75Ω
75Ω
Figure 1. 10/100/1000 Ethernet Port Connection
Rev. 2.0 November 2010
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Page 1 of 8
AOZ8304
Ordering Information
Part Number
Ambient Temperature Range
-40°C to +85°C
Package
Environmental
AOZ8304DIL
2.6mm x 2.6mm DFN-10
RoHS Compliant
Green Product
AOS Green Products (with “L” suffix) use reduced levels of Halogens, and are also RoHS compliant.
Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information.
Pin Configuration
1
10
9
CH1
NC
NC
Pin Number
1, 3, 7, 9
Description
It/Output lines
2
3
4
5
CH2
NC
2, 4, 6, 8, 10
5
No connectio
VP
8
CH3
NC
GND
7
Center Tab
Ground
CH4
NC
6
VP
DFN-10
(Top View)
Absolute Maximum Ratings
Exceeding the Absolute Maximum ratings may damage the device.
Paramter
Rating
VP – GND
3.3V
25A
Peak Pulse Current (IPP), tP = 8/20µs
Peak Power Dissipation (8 x 20µs@ 25°C)
Storage Temperature (TS)
ESD Rating per IEC61000-4-2, Contact1)
ESD Rating per IEC61000-4-2, Air(
ESD Rating per Human Body Model(2)
350W
-65°C to +150°C
±24kV
±24kV
±30kV
Notes:
1. IEC 60004-2 discharge h CDischarge = 150pF, RDischarge = 330¾.
2. Human Body Discharge peMIL-STD-883, Method 3015 CDischarge = 100pF, RDischarge = 1.5k¾.
Maximum Operating Ratings
Parameter
Rating
-40°C to +85°C
Junction Temperature (TJ)
Rev. 2.0 November 2010
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Page 2 of 8
AOZ8304
Electrical Characteristics
TA = 25°C unless otherwise specified. Specifications in BOLD indicate a temperature range of -40°C to +85°C.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
VRWM
IR
Reverse Working Voltage
Reverse Leakage Current
Between pin 5 and GND(4)
VRWM = 3.3V, between pins 5 and GND
VBR = 1mA
3.3
5
V
µA
V
VBR
Reverse Breakdown Volt-
age
3.5
5.6
VCL
Channel Clamp Voltage
Positive Transients
Negative Transient
IPP = 5A, tp = 100ns, any I/O pin to
Ground(3)(6)(8)
7.00
V
V
-4.00
Channel Clamp Voltage
Positive Transients
Negative Transient
IPP = 10A, tp = 100ns, any I/O pin to
Ground(3)(6)(8)
9.00
V
V
-5.00
Channel Clamp Voltage
Positive Transients
Negative Transient
IPP = 25A, tp = 100ns, any I/O pin to
Ground(3)(6)(8)
14.00
-8.00
V
V
Cj
Junction Capacitance
VR = 0V, f = 1MHz, any I/O pin to Gund(3)(7)
VR = 0V, f = 1MHz, between I/O pins(3)(7)
5
pF
pF
1.25
Notes:
3. These specifications are guaranteed by design.
4. The working peak reverse voltage, VRWM, should be equal to or greatethae DC or cons peak operating voltage level.
5. VBR is measured at the pulse test current IT.
6. Measurements performed with no external capacitor on VP (pin 5 flting).
7. Measurements performed with VP biased to 3.3 Volts.
8. Measurements performed using a 100ns Transmission Line Pse (TLP) system.
Rev. 2.0 November 2010
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Page 3 of 8
AOZ8304
Typical Performance Characteristics
Typical Variation of CIN vs. VR
Clamping Voltage vs. Peak Pulse Current
(tperiod = 100ns, tr = 1ns)
(f = 1MHz, T = 25°C)
1.4
14
12
10
8
1.2
1.0
0.8
0.6
0.4
0.2
0
6
0
1.0
2.0
3.0 3.3
5
10
15
20
25
Input Voltage (V)
Pulse Current, I (A)
PP
Forward Voltage vs. Forward Current
I/O – Gnd Insertion Loss (S21) vs. Frequency
(tperiod = 100ns, tr = 1ns)
(Vp = 3.3V)
5
9
8
7
6
5
4
3
0
-5
-10
-15
-20
-25
-30
1
10
100
1,000
10,000
5
10
15
20
25
Forward Current (A)
Frequency (MHz)
Analog Crosstalk (I/O–I/O) vs. Frequency
0
-10
20
-
-40
-50
-60
-70
-80
1
10
100
1,000
10,000
Frequency (MHz)
Rev. 2.0 November 2010
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Page 4 of 8
AOZ8304
with separate ground and power planes. One effective
method to minimize loop problems is to incorporate a
ground plane in the PCB design. The AOZ8304 low
capacitance TVS is designed to protect four high speed
data transmission lines from transient over-voltages by
clamping them to a fixed reference. The low inductance
and construction minimizes voltage overshoot during
high current surges. When the voltage on the protected
line exceeds the reference voltage the internal steering
diodes are forward biased, conducting the transient
current away from the sensitive circuitry.
Application Information
The AOZ8304 TVS is design to protect four data lines
from fast damaging transient over-voltage by clamping it
to a reference. When the transient on a protected data
line exceed the reference voltage the steering diode is
forward bias thus, conducting the harmful ESD transient
away from the sensitive circuitry under protection.
PCB Layout Guidelines
Printed circuit board layout is the key to achieving the
highest level of surge immunity on power and data lines.
The location of the protection devices on the PCB is the
simplest and most important design rule to follow. The
AOZ8304 devices should be located as close as possible
to the noise source. The placement of the AOZ8304
devices should be used on all data and power lines that
enter or exit the PCB at the I/O connector. In most
systems, surge pulses occur on data and power lines
that enter the PCB through the I/O connector. Placing
the AOZ8304 devices as close as possible to the noise
source ensures that a surge voltage will be clamped
before the pulse can be coupled into adjacent PCB
traces. In addition, the PCB should use the shortest
possible traces. A short trace length equates to low
impedance, which ensures that the surge energy will be
dissipated by the AOZ8304 device. Long signal traces
will act as antennas to receive energy from fields that a
produced by the ESD pulse. By keeping line lengths as
short as possible, the efficiency of the line to act s an
antenna for ESD related fields is reduced. Minimize
interconnecting line lengths by placing devices with the
most interconnect as close together as posible. The
protection circuits should shunt the suge voltage to
either the reference or chassis ground. Shunting the
surge voltage directly to the IC’s signal ground can cause
ground bounce. The clamping performance of TVS
diodes on a single ground Pcan be imoved by
minimizing the impedance with relativey short and wide
ground traces. The PB layout and IC package parasitic
inductances can cause significant vershoot to the TVS’s
clamping voltage. The inductance of the PCB can be
reduced by using short trace lengths and multiple layers
Good circuit board layout is criticafor the suppression
of ESD induced transients. The folowing guidelines are
recommended:
1. Place the TVS near the I/O terminals or connectors
to restrict transieoupling.
2. Fill unused portions of the PB with ground plane.
3. Minimize the path lenth between the TVS and the
protected line.
4. Minimize all coductive loops including power and
ground loops.
5The ESD sient return path to ground should be
kept ahort as possible.
6. Never run critical signals near board edges.
7. Use ground planes whenever possible.
8. Avoid running critical signal traces (clocks, resets,
etc.) near PCB edges.
9. Separate chassis ground traces from components
and signal traces by at least 4mm.
10. Keep the chassis ground trace length-to-width ratio
<5:1 to minimize inductance.
11. Protect all external connections with TVS diodes.
TPBIASx
1μF
56Ω
56Ω
IEEE 1394
Connector
TPAx+
IEEE 1394
PHY
TPAx-
TPBx+
TPBx-
GND
56Ω
56Ω
270p
5.1kΩ
AOZ8304
IEEE1394 Port Connection
Rev. 2.0 November 2010
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Page 5 of 8
AOZ8304
Package Dimensions, DFN 2.6mm x 2.6mm
D1
D
e
b
10
E
E1
L
1
Pin #1 ID
Camfer 0.300 x 45
TOP VIEW
e1
Pin 1 ID
BOTTOM VIEW
Dimensions in millimeters
SymbMin.
Nom. Max.
A
1
b
0.50
0.00
0.22
0.55
0.02
0.25
0.60
0.05
0.28
c
D
D1
E
E1
e
0.152 REF
2.60
A
2.55
2.10
2.55
1.25
2.65
2.150 2.20
2.60
1.26
0.50 BSC
2.00 REF
0.35
2.65
1.27
c
A1
SIDE VIEW
Notes:
e1
L
0.30
0.40
1. mensions and tolerancing conform to ASME Y14.5M-1994.
. All dimensions ae in millimeters.
Rev. 2.0 November 2010
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AOZ8304
Tape and Reel Dimensions, DFN 2.6mm x 2.6mm
Carrier Tape
P1
D0
D1
P2
K0
E1
E2
E
R0.3
Max.
B0
A0
P0
T
R0.3 Typ.
Feeding Direction
UNIT: mm
Package
T
B0
A0
K0
D0
D1
ø1.50 12.0
0.10 +0.1/-0.0 Min. 0.3
E
E1
E2
P0
P1
P2
DFN
2.6x2.6
0.30
0.05
2.80
0.10
2.80
0.10
1.10
ø1.50
1.75
0.10
5.50
0.05
400
0.10
4.00
0.10
2.00
0.05
Reel
B
W1
S
K
60°
120°
N
H
Arbor Hole Detail A
Scale 2:1
2.24
W
2.84
B
Back Vw
Section B-B
Front View
S
UNIT: mm
Tape Size
12mm
Reel Size
M
N
W
W1
H
K
ø180
ø179
1.0
60
0.5
13
0.5
17.0
ø13.0
0.2
10.5
0.25
2.0
0.2
Leader / Trer
& Orientation
Trailer Tape
300mm Min.
Components Tape
Orientation in Pocket
Leader Tape
500mm Min.
Rev. 2.0 November 2010
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Page 7 of 8
AOZ8304
Part Marking
Assembly Location Code
Option Code
PNOA
YWLT
Part Number Code
Underscore Denotes Green Product
Year & Week Code
Assembly Lot Code
This datasheet contans preliminary data; supplementary data may be published at a later date.
Alpha & Omega Semiconductor eserves the right to make changes at any time without notice.
LIFE SUPPORT POLICY
ALPHA & MEGA SEMCONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
As used here:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
2. A critical component in any component of a life
support, device, or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
Rev. 2.0 November 2010
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Page 8 of 8
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