AOZ8882DI-05 [AOS]
Ultra-Low Capacitance TVS Diode Array;
| 型号： | AOZ8882DI-05 |
| 厂家： | 
ALPHA & OMEGA SEMICONDUCTORS |
| 描述： | Ultra-Low Capacitance TVS Diode Array 电视 |
| 文件： | 总8页 (文件大小：297K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AOZ8882
Ultra-Low Capacitance TVS Diode Array
General Description
Features
The AOZ8882 is a transient voltage suppressor array
designed to protect high speed data lines such as HDMI,
MDDI, USB, SATA, and Gigabit Ethernet from damaging
ESD events.
ESD protection for high-speed data lines:
– IEC 61000-4-2, level 4 (ESD) immunity test
– Air discharge: ±15 kV; Contact discharge: ±15 kV
– IEC61000-4-4 (EFT) 40 A (5/50 nS)
– IEC61000-4-5 (Lightning) 2.5 A (8/20 µS)
– Human Body Model (HBM) ±24 kV
Array of surge rated diodes with internal TVS diode
Small package saves board space
Protects two I/O lines
This device incorporates four surge rated, low
capacitance steering diodes and a TVS in a single
package. During transient conditions, the steering diodes
direct the transient to either the positive side of the power
supply line or to ground.
The AOZ8882 provides a typical line to ground
capacitance of 0.3 pF and low insertion loss up to 6 GHz
providing greater signal integrity making it ideally suited
for HDMI 1.3 applications, such as Digital TVs, DVD
players, set-top boxes and USB applications in mobile
computing devices.
Low clamping voltage
Low operating voltage: 5.0 V
Applications
USB, MDDI, SATA ports
Monitors and flat panel displays
Set-top box
The AOZ8882 comes in a RoHS compliant and Halogen
Free 1.2 mm x 1.1 mm x 0.55 mm DFN-6 package and is
rated -40 °C to +125 °C junction temperature range.
Video graphics cards
Digital Video Interface (DVI)
Notebook computers
Typical Application
Vbus
+5V
D+
D+
USB 2.0
USB 2.0
Controller
Port
D-
D-
GND
AOZ8882
Figure 1. USB Port
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AOZ8882
Ordering Information
Part Number
Ambient Temperature Range
-40 °C to +85 °C
Package
Environmental
AOZ8882DI-05
DFN-6
Green Product
RoHS Compliant
AOS Green Products use reduced levels of Halogens, and are also RoHS compliant.
Please visit www.aosmd.com/media/AOSGreenPolicy.pdf for additional information.
Pin Configuration
VN
NC
NC
1
2
3
6
5
4
NC
I/O2
I/O1
DFN-6
(Top Thru View)
Absolute Maximum Ratings
Exceeding the Absolute Maximum ratings may damage the device.
Parameter
Rating
Storage Temperature (TS)
-65 °C to +150 °C
ESD Rating per IEC61000-4-2, contact(1)
ESD Rating per IEC61000-4-2, air(1)
ESD Rating per Human Body Model(2)
±15 kV
±15 kV
±24 kV
Notes:
1. IEC 61000-4-2 discharge with CDischarge = 150 pF, RDischarge = 330 Ω.
2. Human Body Discharge per MIL-STD-883, Method 3015 CDischarge = 100 pF, RDischarge = 1.5 kΩ.
Maximum Operating Ratings
Parameter
Rating
-40 °C to +125 °C
Junction Temperature (TJ)
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AOZ8882
Electrical Characteristics
TA = 25°C unless otherwise specified.
Symbol
Parameter
Conditions
Between I/O and VN(3)
Min.
Typ. Max. Units
VRWM
VBR
IR
Reverse Working Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
5.0
V
V
IT = 100 µA, between I/O and VN(4)
6.0
VRWM = 5 V, between I/O and VN
1
µA
VCL
Channel Clamp Voltage
Positive Transients
Negative Transient
IPP = 1 A, tp = 100 ns, any I/O pin to Ground(5)
6
V
V
-6
Channel Clamp Voltage
Positive Transients
Negative Transient
IPP = 5 A, tp = 100 ns, any I/O pin to Ground(5)
IPP = 12 A, tp = 100 ns, any I/O pin to Ground(5)
VR = 0 V, f = 1 MHz, any I/O pin to Ground
12
V
V
-12
Channel Clamp Voltage
Positive Transients
Negative Transient
18
V
V
-18
Cj
Channel Input Capacitance
0.30
0.45
pF
Notes:
3. The working peak reverse voltage, VRWM, should be equal to or greater than the DC or continuous peak operating voltage level.
4. VBR is measured at the pulse test current IT.
5. Measurements performed using a 100 ns Transmission Line Pulse (TLP) system.
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AOZ8882
Typical Performance Characteristics
Clamping Voltage vs. Peak Pulse Current
(t = 100ns, t = 1ns)
Forward Voltage vs. Forward Peak Pulse Current
(t
period
= 100ns, t = 1ns)
r
period
r
18
16
14
12
10
8
18
16
14
12
10
8
6
6
4
4
2
2
0
0
0
2
4
6
8
10
12
14
0
2
4
6
8
10
12
14
Peak Puse Current, I (A)
Forward Current, I (A)
PP
PP
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AOZ8882
Protecting USB Ports from ESD
Because electrostatic discharge (ESD) is common in
electronic systems, a device that provides protection
from the undesirable effects of ESD must be included in
the system design. Designing ESD protection structures
is becoming more and more challenging with the system
bus and I/O operating more often at high-speed data
rates. An Integrated Circuit (IC) connected to external
ports can be damaged by ESD from the operating
environment. The result of ever-shrinking IC process
technology is the decrease of ESD robustness because
of the smaller geometry of the silicon die.
The very low 0.6 pF (typical) line capacitance of the
AOZ8882 ensures less distortion of the 480 Mbit/s
USB 2.0 signal; the chips also protect against
electrostatic discharge up to the stringent IEC61000-4-2
level 4, 8 kV (Contact Discharge) and 15kV standard
(Air Discharge). They also provide ultra low matching
capacitance to help improve the signal quality of
differential data lines. Monolithic integration provides
high device reliability, and an optimized pin-out allows
EMI-free board layouts. Figure 2 illustrates the flow
through design of the PCB layout with the AOZ8882
package design. The pinout of the AOZ8882 is designed
to simply drop onto the IO lines of a USB 2.0 design
without having to divert the signal lines that may add
more parasitic inductance. Pins 1, 4, and 5 are
connected to the internal TVS devices and ground.
Pins 2, 3 and 6 are no connects. The no connects are
in place so the package can be securely soldered onto
the PCB surface.
Since USB is a hot insertion and removal system, the
USB components are subjected to ESD and cable
discharge event more frequently. Traditional methods of
ESD protection include metal oxide varistors (MOVs),
and regular CMOS or bipolar clamping diodes. At higher
data rates the parasitic characteristics of those devices
can cause distortion, deterioration and data loss of the
signal integrity. AOZ8882 offers ESD protection for
high-speed data rates and for diode array chips for ease
of design.
D+
D-
D+
D-
NC
VN
Figure 2. Flow-through Layout
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AOZ8882
USB 2.0 PCB Layout Guidelines
Printed circuit board layout is the key to achieving the
highest level of surge immunity on power and data lines.
The location of the protection devices on the PCB is the
simplest and most important design rule to follow. The
AOZ8882 devices should be located as close as possible
to the noise source. The placement of the AOZ8882
devices should be used on all data and power lines that
enter or exit the PCB at the I/O connector. In most
systems, surge pulses occur on data and power lines that
enter the PCB through the I/O connector. Placing the
AOZ8882 devices as close as possible to the noise
source ensures that a surge voltage will be clamped
before the pulse can be coupled into adjacent PCB
traces. In addition, the PCB should use the shortest
possible traces. A short trace length equates to low
impedance, which ensures that the surge energy will be
dissipated by the AOZ8882 device. Long signal traces
will act as antennas to receive energy from fields that are
produced by the ESD pulse. By keeping line lengths as
short as possible, the efficiency of the line to act as an
antenna for ESD related fields is reduced. Minimize
interconnecting line lengths by placing devices with the
most interconnect as close together as possible. The
protection circuits should shunt the surge voltage to
either the reference or chassis ground. Shunting the
surge voltage directly to the IC’s signal ground can cause
ground bounce. The clamping performance of TVS
diodes on a single ground PCB can be improved by
minimizing the impedance with relatively short and wide
ground traces. The PCB layout and IC package parasitic
inductances can cause significant overshoot to the TVS’s
clamping voltage. The inductance of the PCB can be
reduced by using short trace lengths and multiple layers
with separate ground and power planes. One effective
method to minimize loop problems is to incorporate a
ground plane in the PCB design.
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AOZ8882
Package Dimensions, DFN-6, 1.2 mm x 1.1 mm x 0.55 mm
D
A
E
c
A1
Pin 1 Dot
by Marking
SIDE VIEW
TOP VIEW
b (6x)
e
1
L (5x)
L1
BOTTOM VIEW
RECOMMENDED LAND PATTERN
Dimensions in millimeters
Dimensions in inches
0.20 (6x)
0.45 (6x)
Symbols Min.
Nom. Max.
Symbols Min.
Nom. Max.
A
A1
b
c
D
E
e
L
L1
0.50
0.00
0.15
0.55
—
0.20
0.60
0.05
0.25
A
A1
b
c
D
E
e
L
L1
0.020 0.022 0.024
0.000
—
0.002
1.15
0.006 0.008 0.010
0.006 Ref.
0.045 0.047 0.049
0.041 0.043 0.045
0.016 BSC
0.70
0.25
0.152 Ref.
1.20
1.10
0.40 BSC
0.40
1.15
1.05
1.25
1.15
0.30
0.50
0.012 0.016 0.020
0.015 0.019 0.023
0.40
1.00
0.375 0.475 0.575
UNIT: mm
Note:
1. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact.
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AOZ8882
Part Marking
AOZ8882DI
(1.2 x 1.1 DFN)
CB3
Product Number Code
Assembly Lot Code
Week Code
LEGAL DISCLAIMER
Alpha and Omega Semiconductor makes no representations or warranties with respect to the accuracy or
completeness of the information provided herein and takes no liabilities for the consequences of use of such
information or any product described herein. Alpha and Omega Semiconductor reserves the right to make changes
to such information at any time without further notice. This document does not constitute the grant of any intellectual
property rights or representation of non-infringement of any third party’s intellectual property rights.
LIFE SUPPORT POLICY
ALPHA AND OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
2. A critical component in any component of a life
support, device, or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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