MC54HC164J [ARTSCHIP]
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS;
| 型号： | MC54HC164J |
| 厂家： | 
Artschip |
| 描述： | 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS 逻辑集成电路 触发器 |
| 文件： | 总13页 (文件大小：744K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74HC164
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
MC54HC164…J OR W PACKAGE
z Wide Operating Voltage Range of 2 V to 6V
z Outputs Can Drive Up To 10 LSTTL Loads
MC74HC164…AD,N,NS, OR PW PACKAGE
(TOP VIEW)
z Low Power Consumption, 80-μA Max I
CC
z Typical t
=20 ns
pd
z ±4-mA Output Drive at 5V
z Low Input Current of 1μA Max
z AND-Gated (Enable/Disable) Serial Inputs
z Fully Buffered Clock and Serial Inputs
z Direct Clear
MC54HC164…FK PACKAGE
(TOP VIEW)
Description/ordering information
These 8-bit shift registers feature AND-gated serial inputs
and an asynchronous clear (CLR) input. The gated serial (A
and B) input permit complete control over incoming data; a
low at either input inhibits entry of the new data and resets
the first flip-flop to the low level at the next clock (CLK) pulse.
A high-level input enables the other input, which then
determines the state of the first flip-flop. Data at the serial
inputs can be changed while CLK is high or low, provided the
minimum setup time requirements are met. Clocking occurs
on the low-to-high-level transition of CLK.
NC-No Internal connection
ORDERING INFORMATION
ORDERABLE
PARTNUMBER
MC74HC164 AN
MC74HC164N
TOP-SIDE
MARKING
PACKAGE†
T
A
PDIP –AN
PDIP –N
Tube of 25
MC74HC164 AN
MC74HC164N
Tube of 25
Tube of 50
Reel of 2500
Reel of 250
Reel of 2000
Tube of 90
Reel of 2000
Reel of 250
Tube of 25
Tube of 150
Tube of 55
MC74HC164AD
MC74HC164AD
MC74HC164DT
MC74HC164NSR
MC74HC164PW
MC74HC164PWR
MC74HC164PWT
MC54HC164J
SOIC - D
HC164
HC164
HC164
-40℃ to 85℃
SOP –NS
TSSOP – PW
CDIP – J
CFP – W
LCCC - FK
MCJ54HC164J
MCJ54HC164W
MCJ54HC164FK
-55℃ to 125℃
MC54HC164W
MC54HC164FK
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MC74HC164
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
FUNCTION TABLE
OUTPUTS
INPUTS
CLK
A
X
X
H
L
B
X
X
H
X
L
Q
Q
… Q
H
A
B
L
X
L
↑
L
L
L
H
H
H
H
Q
H
L
Q
BO
Q
HO
AO
Q
Q
An
An
An
Gn
Gn
Gn
↑
Q
Q
Q
Q
↑
X
L
Q
, Q ,Q = the level of Q , Q , or Q , respectively,
B0 H0 A B H
A0
before the indicated steady-state input conditions were
established
Q , QGn = the level of Q or Q before the most recent
An
A
G
↑ transition of CLK: indicates a 1-bit shift
logic diagram (positive logic)
Pin numbers shown are for the AD,J,N,NS, PW, and W packages.
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2
MC74HC164
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
Typical clear, shift, and clear sequence
absolute maximum ratings over operating free-air temperature range (unless otherwise noted) †
Supply voltage range, V …………………………………………………………………………-0.5 V to 7 V
CC
Input clamp current, I (V < 0 or V >V ) (see Note 1)……………………………………………±20mA
IK
I
I
CC
Output clamp current, I (V < 0 or V >V ) (see Note 1)……………………………………… ±20mA
oK
o
o
CC
Continuous output current, I (V = 0 to V ) ……………………………………………………….±25mA
o
o
CC
Continuous current through V
or GND……………………………………………………………..±50mA
CC
Package thermal impedance,
(see Note 2): AD package………………………………………..86℃/W
N package………………………………………..80℃/W
NS package……………………………………...76℃/W
PW package………………………………….…113℃/W
JA
Storage temperature range, T stg …………………………………………………-65℃ to 150℃
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are
stress ratings only, functional operation of the device at these or any other conditions beyond those indicated under
“recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7
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MC74HC164
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
Recommended operating conditions (see Note 3)
MC54HC164
MC74HC164
UNIT
V
MIN
2
NOM
5
MAX
MIN
2
NOM
5
MAX
6
V
V
Supply voltage
6
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
=2V
1.5
3.15
4.2
1.5
3.15
4.2
High-level input voltage
V
V
=4.5V
=6V
IH
=2V
0.5
1.35
1.8
0.5
1.35
1.8
V
IL
Low-level input voltage
=4.5V
=6V
V
V
Input voltage
0
0
V
CC
V
CC
0
0
V
V
V
V
I
CC
CC
Output voltage
O
V
CC
V
CC
V
CC
=2V
1000
500
400
125
1000
500
400
85
△t /△v†
Input transition rise/fall time
ns
=4.5V
=6V
T
Operating free-air temperature
-55
-40
℃
A
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI
CC
application report. Implications of Slow or Floating CMOS Inputs, literature number SCBAOO4.
† If this device is used in the threshold region (from V max = 0.5V to V min =1.5V), there is a potential to go into the wrong
IL
IH
state from induced grounding, causing double clocking. Operating with the inputs at t =1000ns and V
= 2V does not
t
CC
damage the device; however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
Electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
T =25℃
MC54HC164
MAX
1.9
MC74HC164
A
PARAMETER
TEST CONDITIONS
VCC
UNIT
MIN
TYP MAX MIN
MIN
1.9
MAX
2V
4.5V
6V
1.9 1.998
I
= -20μA
4.4 4.499
5.9 5.999
4.4
4.4
OH
V
OH
V = V or V
I L
V
5.9
5.9
I
IH
I
I
= -4mA
4.5V
6V
3.98
5.48
4.3
5.8
3.7
3.84
5.34
OH
OH
= -5.2mA
5.2
2V
0.002
0.001
0.001
0.17
0.1
0.1
0.1
0.1
0.1
I
= 20μA
4.5V
6V
0.1
OL
V
OL
V = V or V
I L
V
0.1
0.1
0.1
I
IH
I
I
= 4mA
4.5V
6V
0.26
0.26
0.4
0.33
0.33
±1000
80
OL
= 5.2mA
0.15
0.4
OH
I
I
V = V or 0
6V
±0.1 ±100
±1000
160
nA
μA
pF
I
I
CC
V = V or 0,
I =0
O
6V
8
CC
I
CC
C
2V to 6V
3
10
10
10
i
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MC74HC164
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
Timing requirements over recommended operating free-air temperature range (unless otherwise noted)
T =25℃
MC54HC164AN
MC74HC164AN
A
V
UNIT
CC
MIN
MAX
MIN
MAX
4.2
21
MIN
MAX
5
2V
6
31
36
f
t
Clock frequency
Pulse duration
MHz
4.5V
6V
25
clock
25
28
2V
100
20
17
80
16
14
100
20
17
100
20
17
5
150
30
25
120
24
20
150
30
25
150
30
25
5
125
25
21
100
20
18
125
25
21
125
25
21
5
low
CLK high or low
Data
4.5V
6V
ns
W
2V
4.5V
6V
2V
4.5V
6V
t
t
Setup time before CLK↑
ns
ns
su
2V
inactive
4.5V
6V
2V
Hold time, data after CLK↑
4.5V
6V
5
5
5
h
5
5
5
Switching characteristics over recommended operating free-air temperature range, CL = 50pF (unless otherwise noted)
(see Figure1)
FROM
(INPUT)
TO
(OUTPUT)
T =25℃
MC54HC164AN
MC74HC164AN
A
PARAMETER
V
UNIT
CC
MIN
6
TYP MAX
MIN
4.2
21
MAX MIN
MAX
2V
10
54
62
5
f
MHz
4.5V
6V
31
36
25
28
255
51
46
220
44
38
95
19
16
max
25
2V
140
28
24
115
23
20
38
8
205
41
295
59
t
Any Q
Any Q
4.5V
6V
PHL
35
51
Ns
ns
2V
175
35
265
53
t
CLK
4.5V
6V
pd
30
45
2V
75
110
22
t
t
4.5V
6V
15
6
13
19
Operating characteristics, T = 25℃
A
PARAMETER
Power dissipation capacitance
TESTCONDITIONS
TYP
UNIT
pF
C
No load
135
pd
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MC74HC164
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
PARAMETER MEASUREMENT INFORMATION
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relation ships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR≤1MHz, ZO =50Ω, tr = 6ns, tf =6ns.
C. For clock inputs, f max is measured when the input duty cycle is 50%.
D. The outputs are measured one at a time with one input transition per measurement.
E. t PLH and t PHL are the same as t pd
.
Figure 1. Load Circuit and Voltage Waveforms
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MC74HC164
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
J (R –GDIP –T **)
CERAMIC DUAL IN-LINE PACKAGE
14 LEADS SHOWN
4040083/F 03/03
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package is hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cop for terminal identification only on press ceramic glass frit seal only.
E. Falls within MIL STD 1835 GDIP1-T14, GDIP1-T16, GDIP1-T18 and GDIP1-T20.
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MC74HC164
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
MECHANICAL DATA
W(R-GDFP-F14)
CERAMIC DUAL FLATPACK
4040180-2/D 07/03
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only.
E. Falls within MIL STD 1835 GDFP1-F14 and JEDEC MO-092AB
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MC74HC164
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
MECHANICAL DATA
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004.
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MC74HC164
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
MECHANICAL DATA
N (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
16 PINS SHOWN
4040049/E 12/2002
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001, except 18 and 20 pin minimum body length (Dim A).
D. The 20 pin end lead shoulder width is a vendor option, either half or full width.
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MC74HC164
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
MECHANICAL DATA
D (R-PDSO-G14)
PLASTIC SMALL-OUTLINE PACKAGE
4040047-3/F 07/2004
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0.15).
D. Falls within JEDEC MS-012 variation AB.
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MC74HC164
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
MECHANICAL DATA
NS(R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14-PINS SHOWN
4040062/C 03/03
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.15.
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MC74HC164
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.15.
D. Falls within JEDEC MO-153.
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