AT24C64CU3-UU-T [ATMEL]
EEPROM, 8KX8, Serial, CMOS, PBGA8, LEAD FREE AND HALOGEN FREE, BGA-8;
| 型号： | AT24C64CU3-UU-T |
| 厂家： | 
ATMEL |
| 描述： | EEPROM, 8KX8, Serial, CMOS, PBGA8, LEAD FREE AND HALOGEN FREE, BGA-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 内存集成电路 |
| 文件： | 总20页 (文件大小：326K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Low-voltage and Standard-voltage Operation
– 1.8 (VCC = 1.8 to 3.6V)
• Internally Organized 8192 x 8
• 2-Wire Serial Interface
• Schmitt Trigger, Filtered Inputs for Noise Suppression
• Bi-directional Data Transfer Protocol
• 1 MHz (3.6V, 2.7V, 2.5V) and 400 KHz (1.8V Compatibility)
• Write Protect Pin for Hardware Data Protection
• 32-Byte Page Write Mode (Partial Page Writes Allowed)
• Self-Timed Write Cycle (5 ms max)
2-Wire
Serial EEPROM
64K (8192 x 8)
• High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
• Lead-free/Halogen-free Devices
• 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-lead Ultra Thin Mini-MAP (MLP2x3),
and 8-ball dBGA2 Packages.
• Die Sales: Wafer Form, Waffle Pack, and Bumped Wafers
AT24C64C
Description
The AT24C64C provides 65,536 bits of serial electrically erasable and programmable
read only memory (EEPROM) organized as 8192 words of 8 bits each. The device’s
cascadable feature allows up to 8 devices to share a common 2-wire bus. The device
is optimized for use in many industrial and commercial applications where low power
and low voltage operation are essential. The AT24C64C is available in space saving
8-lead PDIP, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-lead Ultra Thin Mini-MAP
(MLP2x3) 8-ball dBGA2 packages and is accessed via a 2-wire serial interface. In
addition, the entire family is available in 1.8V (1.8 to 3.6V) versions.
Advance
Information
8-lead Ultra Thin Mini-MAP (MLP 2x3)
Pin Configurations
Pin Name
A0 - A2
SDA
Function
A0
8
7
6
5
1
2
3
4
VCC
WP
A1
Address Inputs
Serial Data
A2
SCL
SDA
GND
SCL
Serial Clock Input
Write Protect
8-ball dBGA2
2-Wire, 32K
Bottom View
WP
Serial E2PROM
8-lead SOIC
A0
8
7
6
5
1
2
3
4
VCC
WP
A0
1
2
3
4
8
7
6
5
VCC
A1
A1
A2
WP
A2
SCL
SDA
SCL
SDA
GND
GND
Bottom View
8-lead TSSOP
8-lead PDIP
A0
A1
1
2
3
4
8
7
6
5
VCC
WP
A0
A1
1
2
3
4
8
7
6
5
VCC
WP
A2
SCL
SDA
A2
SCL
SDA
GND
GND
5174A–SEEPR–7/06
1
AT24C64C
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Operating Temperature...................................... -55 to +125°C
Storage Temperature......................................... -65 to +150°C
Voltage on Any Pin
with Respect to Ground....................................... -1.0 to +5.0V
Maximum Operating Voltage ............................................ 4.3V
DC Output Current........................................................ 5.0 mA
Block Diagram
2
5174A–SEEPR–7/06
AT24C64C
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open
collector devices.
DEVICE/ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs
that are hard wired or left not connected for hardware compatibility with other AT24CXX
devices. When the pins are hardwired, as many as eight 64K devices may be addressed
on a single bus system (device addressing is discussed in detail under the Device
Addressing section). If the pins are left floating, the A2, A1 and A0 pins will be internally
pulled down to GND if the capacitive coupling to the circuit board VCC plane is <3pF.
If coupling is >3pF, Atmel recommends connecting the address pins to GND.
WRITE PROTECT (WP): The write protect input, when connected to GND, allows nor-
mal write operations. When WP is connected high to VCC, all write operations to the
memory are inhibited. If the pin is left floating, the WP pin will be internally pulled down
to GND if the capacitive coupling to the circuit board VCC plane is <3pF. If coupling is
>3pF, Atmel recommends connecting the pin to GND.
Memory Organization AT24C64C, 64K SERIAL EEPROM: The 64K is internally organized as 256 pages of
32 bytes each. Random word addressing requires a 13 bit data word address.
3
5174A–SEEPR–7/06
AT24C64C
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V
Symbol
CI/O
Test Condition
Max
8
Units
pF
Conditions
VI/O = 0V
VIN = 0V
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, SCL)
CIN
6
pF
Note:
1. This parameter is characterized and is not 100% tested.
DC Characteristics
Applicable over recommended operating range from: TAI = -40 to +85°C, VCC = +1.8 to +3.6V (unless otherwise noted)
Symbol
VCC1
ICC1
Parameter
Test Condition
Min
Typ
Max
3.6
2.0
3.0
1.0
3.0
Units
V
Supply Voltage
Supply Current
Supply Current
1.8
VCC = 3.6V
VCC = 3.6V
VCC = 1.8V
VCC = 3.6V
READ at 400 kHz
WRITE at 400 kHz
1.0
2.0
mA
mA
µA
ICC2
Standby Current
(1.8V option)
ISB1
VIN = VCC or VSS
Input Leakage
Current
ILI
VIN = VCC or VSS
0.10
0.05
3.0
3.0
µA
µA
Output Leakage
Current
ILO
VOUT = VCC or VSS
VIL
Input Low Level(1)
Input High Level(1)
Output Low Level
Output Low Level
−0.6
VCC x 0.3
VCC + 0.5
0.4
V
V
V
V
VIH
VCC x 0.7
VOL2
VOL1
VCC = 3.0V
VCC = 1.8V
IOL = 2.1 mA
IOL = 0.15 mA
0.2
Note:
1. VIL min and VIH max are reference only and are not tested.
4
5174A–SEEPR–7/06
AT24C64C
AC Characteristics
Applicable over recommended operating range from TAI = -40°C to +85°C, VCC = +1.8V to +3.6V, CL = 1 TTL Gate and
100 pF (unless otherwise noted)
1.8-volt
2.5-volt
3.6-volt
Symbol
fSCL
Parameter
Min
Max
Min
Max
Min
Max
1000
Units
kHz
µs
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Clock Low to Data Out Valid
400
1000
tLOW
1.3
0.6
0.4
0.4
0.4
0.4
tHIGH
tAA
µs
0.05
0.9
0.05
0.55
0.05
µs
Time the bus must be free before a new
transmission can start(1)
tBUF
1.3
0.5
0.5
µs
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tR
Start Hold Time
0.6
0.6
0
0.25
0.25
0
0.25
0.25
0
µs
µs
µs
ns
µs
ns
µs
ns
ms
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Inputs Rise Time(1)
Inputs Fall Time(1)
Stop Set-up Time
Data Out Hold Time
Write Cycle Time
100
100
100
0.3
0.3
tF
300
100
tSU.STO
tDH
0.6
50
0.25
50
0.25
50
tWR
5
5
Write
Cycles
Endurance(1) 25°C, Page Mode, 3.3V
1,000,000
Notes: 1. This parameter is characterized and is not 100% tested.
2. AC measurement conditions:
RL (connects to VCC): 1.3 kΩ (2.5V, 3.6V), 10 kΩ (1.8V)
Input pulse voltages: 0.3 VCC to 0.7 VCC
Input rise and fall times: ≤ 50 ns
Input and output timing reference voltages: 0.5 VCC
5
5174A–SEEPR–7/06
AT24C64C
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-
nal device. Data on the SDA pin may change only during SCL low time periods (refer to
Data Validity timing diagram). Data changes during SCL high periods will indicate a start
or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition
which must precede any other command (refer to Start and Stop Definition timing
diagram).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command will place the EEPROM in a standby power
mode (refer to Start and Stop Definition timing diagram).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to
acknowledge that it has received each word.
STANDBY MODE: The AT24C64C features a low power standby mode which is
enabled: a) upon power-up and b) after the receipt of the Stop bit and the completion of
any internal operations.
SOFTWARE RESET: After an interruption in protocol, power loss or system reset, any
2-wire part can be protocol reset by following these steps:
(a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then
(c) create a start condition as SDA is high.
6
5174A–SEEPR–7/06
AT24C64C
Bus Timing
SCL: Serial Clock, SDA: Serial Data I/O
Write Cycle Timing
SCL: Serial Clock, SDA: Serial Data I/O
SCL
SDA
ACK
8th BIT
WORDn
(1)
t
wr
START
STOP
CONDITION
CONDITION
Note:
1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
7
5174A–SEEPR–7/06
AT24C64C
Data Validity
Start and Stop Definition
Output Acknowledge
8
5174A–SEEPR–7/06
AT24C64C
Device
Addressing
The 64K EEPROM requires an 8-bit device address word following a start condition to enable
the chip for a read or write operation (see Figure 1 on page 11). The device address word con-
sists of a mandatory one, zero sequence for the first four most significant bits as shown. This
is common to all 2-wire EEPROM devices.
The 64K uses the three device address bits A2, A1, A0 to allow as many as eight devices on
the same bus. These bits must compare to their corresponding hardwired input pins. The A2,
A1, and A0 pins use an internal proprietary circuit that biases them to a logic low condition if
the pins are allowed to float.
The eighth bit of the device address is the read/write operation select bit. A read operation is
initiated if this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a zero. If a compare is not
made, the device will return to standby state.
NOISE PROTECTION: Special internal circuitry placed on the SDA and SCL pins prevent
small noise spikes from activating the device. A low-VCC detector resets the device to prevent
data corruption in a noisy environment.
DATA SECURITY: The AT24C64C has a hardware data protection scheme that allows the
user to write protect the entire memory when the WP pin is at VCC
.
Write
Operations
BYTE WRITE: A write operation requires two 8-bit data word addresses following the device
address word and acknowledgment. Upon receipt of this address, the EEPROM will again
respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit
data word, the EEPROM will output a zero and the addressing device, such as a microcontrol-
ler, must terminate the write sequence with a stop condition. At this time the EEPROM enters
an internally-timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during
this write cycle and the EEPROM will not respond until the write is complete (see Figure 2 on
page 11).
PAGE WRITE: The 64K EEPROM is capable of 32-byte page writes.
A page write is initiated the same way as a byte write, but the microcontroller does not send a
stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges
receipt of the first data word, the microcontroller can transmit up to 31 more data words. The
EEPROM will respond with a zero after each data word received. The microcontroller must ter-
minate the page write sequence with a stop condition (see Figure 3 on page 11).
The data word address lower 5 bits are internally incremented following the receipt of each
data word. The higher data word address bits are not incremented, retaining the memory page
row location. When the word address, internally generated, reaches the page boundary, the
following byte is placed at the beginning of the same page. If more than 32 data words are
transmitted to the EEPROM, the data word address will “roll over” and previous data will be
overwritten.
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a
start condition followed by the device address word. The read/write bit is representative of the
operation desired. Only if the internal write cycle has completed will the EEPROM respond
with a zero, allowing the read or write sequence to continue.
9
5174A–SEEPR–7/06
AT24C64C
Read Operations
Read operations are initiated the same way as write operations with the exception that
the read/write select bit in the device address word is set to one. There are three read
operations: current address read, random address read and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the
last address accessed during the last read or write operation, incremented by one. This
address stays valid between operations as long as the chip power is maintained. The
address “roll over” during read is from the last byte of the last memory page, to the first
byte of the first page. The address “roll over” during write is from the last byte of the cur-
rent page to the first byte of the same page.
Once the device address with the read/write select bit set to one is clocked in and
acknowledged by the EEPROM, the current address data word is serially clocked out.
The microcontroller does not respond with an input zero but does generate a following
stop condition (see Figure 4 on page 12).
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the
data word address. Once the device address word and data word address are clocked
in and acknowledged by the EEPROM, the microcontroller must generate another start
condition. The microcontroller now initiates a current address read by sending a device
address with the read/write select bit high. The EEPROM acknowledges the device
address and serially clocks out the data word. The microcontroller does not respond
with a zero but does generate a following stop condition (see Figure 5 on page 12).
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or
a random address read. After the microcontroller receives a data word, it responds with
an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to
increment the data word address and serially clock out sequential data words. When the
memory address limit is reached, the data word address will “roll over” and the sequen-
tial read will continue. The sequential read operation is terminated when the
microcontroller does not respond with a zero but does generate a following stop condi-
tion (see Figure 6 on page 12).
10
5174A–SEEPR–7/06
AT24C64C
Figure 1. Device Address
Figure 2. Byte Write
Figure 3. Page Write
Note:
1. * = DON’T CARE bits
11
5174A–SEEPR–7/06
AT24C64C
Figure 4. Current Address Read
Figure 5. Random Read
Note:
1. * = DON’T CARE bits
Figure 6. Sequential Read
12
5174A–SEEPR–7/06
AT24C64C
AT24C64C Ordering Information
Ordering Code
Package
8P3
Operation Range
AT24C64C-PU (Bulk form only)
AT24C64CN-SH-B(1) (NiPdAu Lead Finish)
AT24C64CN-SH-T(2) (NiPdAu Lead Finish)
AT24C64C-TH-B(1) (NiPdAu Lead Finish)
AT24C64C-TH-T(2) (NiPdAu Lead Finish)
AT24C64CY6-YH-T(2) (NiPdAu Lead Finish)
AT24C64CU3-UU-T(2)
8S1
8S1
Lead-free/Halogen-free
Industrial Temperature
8A2
(-40°C to 85°C)
8A2
8Y6
8U3-1
Industrial Temperature
AT24C64C-W-11(3)
Die Sale
(-40°C to 85°C)
Notes: 1. “-B” denotes Bulk.
2. “-T” denotes tape and reel. SOIC = 4K per reel. TSSOP, Ultra Thin Mini-MAP and dBGA2 = 5K per reel.
3. Available in waffle pack, tape and reel, and wafer form; order as 788 for inkless wafer form. Bumped die available upon
request. Please contact Serial Interface Marketing.
Package Type
8-lead, 2.00mm x 3.00mm Body, 0.50mm Pitch, Ultra Thin Mini-MAP, Dual no Lead Package (DFN), (MLP 2x3)
8-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150” Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8-lead, 4.4 mm Body, Plastic, Thin Shrink Small Outline Package (TSSOP)
8-ball, die Ball Grid Array Package (dBGA2)
8Y6
8P3
8S1
8A2
8U3-1
Options
-1.8
Low Voltage (1.8V to 3.6V)
13
5174A–SEEPR–7/06
AT24C64C
Packaging Information
8Y6 - MLP
A
D2
b
(8X)
Pin 1
Index
Area
Pin 1 ID
L (8X)
D
e (6X)
A2
A1
1.50 REF.
A3
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
MAX
NOM
2.00 BSC
3.00 BSC
1.50
NOTE
SYMBOL
D
E
D2
E2
A
1.40
1.60
1.40
0.60
0.05
0.55
-
-
-
-
A1
A2
A3
L
0.0
-
0.02
-
0.20 REF
0.30
0.20
0.20
0.40
0.30
e
0.50 BSC
0.25
b
2
Notes:
1. This drawing is for general information only. Refer to JEDEC Drawing MO-229, for proper dimensions,
tolerances, datums, etc.
2. Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the
terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area.
8/26/05
DRAWING NO. REV.
TITLE
2325 Orchard Parkway
San Jose, CA 95131
8Y6, 8-lead 2.0 x 3.0 mm Body, 0.50 mm Pitch, Utlra Thin Mini-Map,
Dual No Lead Package (DFN) ,(MLP 2x3)
8Y6
C
R
14
5174A–SEEPR–7/06
AT24C64C
8P3 – PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
MIN
MAX
NOM
NOTE
SYMBOL
D1
A2 A
A
0.210
0.195
0.022
0.070
0.045
0.014
0.400
2
A2
b
0.115
0.014
0.045
0.030
0.008
0.355
0.005
0.300
0.240
0.130
0.018
0.060
0.039
0.010
0.365
5
6
6
b2
b3
c
D
3
3
4
3
b2
L
D1
E
b3
4 PLCS
0.310
0.250
0.325
0.280
b
E1
e
0.100 BSC
0.300 BSC
0.130
Side View
eA
L
4
2
0.115
0.150
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
8P3
B
R
15
5174A–SEEPR–7/06
AT24C64C
8S1 – JEDEC SOIC
C
1
E
E1
L
N
Ø
TOP VIEW
END VIEW
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
MIN
1.35
0.10
MAX
1.75
0.25
NOM
NOTE
SYMBOL
A1
A
–
–
A1
b
C
D
E1
E
e
0.31
0.17
4.80
3.81
5.79
–
0.51
0.25
5.05
3.99
6.20
–
–
D
–
–
SIDE VIEW
1.27 BSC
L
0.40
0˚
–
–
1.27
8˚
θ
Note:
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
3/17/05
TITLE
DRAWING NO.
8S1
REV.
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
C
Small Outline (JEDEC SOIC)
R
16
5174A–SEEPR–7/06
AT24C64C
8A2 – TSSOP
3
2 1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
MAX
NOM
3.00
NOTE
SYMBOL
D
2.90
3.10
2, 5
A
b
E
6.40 BSC
4.40
E1
A
4.30
–
4.50
1.20
1.05
0.30
3, 5
4
–
A2
b
0.80
0.19
1.00
e
A2
–
D
e
0.65 BSC
0.60
L
0.45
0.75
Side View
L1
1.00 REF
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
5/30/02
DRAWING NO.
TITLE
REV.
2325 Orchard Parkway
San Jose, CA 95131
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
B
8A2
R
17
5174A–SEEPR–7/06
AT24C64C
8U3-1 - dBGA2
E
D
1.
b
A1
PIN 1 BALL PAD CORNER
A2
Top View
A
PIN 1 BALL PAD CORNER
Side Vie
w
1
2
3
4
(d1)
d
7
6
5
8
e
COMMON DIMENSIONS
(Unit of Measure - mm)
(e1)
SYMBOL
NOM
MIN
MAX
NOTE
Bottem View
A
0.73
0.09
0.40
0.20
0.79
0.85
0.19
0.50
0.30
8 SOLDER BALLS
A1
A2
b
0.14
0.45
0.25
2
D
1.50 BSC
2.0 BSC
0.50 BSC
0.25 REF
1.00 BSC
0.25 REF
This drawing is for general information only.
Dimension 'b' is measured at maximum solder ball diameter.
1.
2.
E
e
e1
d
d1
18
5174A–SEEPR–7/06
AT24C64C
Revision History
Doc. Rev.
Comments
5174A
Initial document release
19
5174A–SEEPR–7/06
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5174A–SEEPR–7/06
相关型号：
AT24C64D-SSHM-B
EEPROM, 8KX8, Serial, CMOS, PDSO8, 0.150 INCH, GREEN, PLASTIC, MS-012AA, SOIC-8
ATMEL
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