AT25HP512C1-10CI-1.8 [ATMEL]
SPI Serial EEPROMs; SPI串行EEPROM
| 型号： | AT25HP512C1-10CI-1.8 |
| 厂家： | 
ATMEL |
| 描述： | SPI Serial EEPROMs |
| 文件： | 总15页 (文件大小：181K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Serial Peripheral Interface (SPI) Compatible
• Supports SPI Modes 0 (0,0) and 3 (1,1)
• 10 MHz Clock Rate
• 128-Byte Page Mode Only for Write Operations
• Low-Voltage and Standard-Voltage Operation
– 5.0 (VCC = 4.5V to 5.5V)
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 3.6V)
• Block Write Protection
– Protect 1/4, 1/2, or Entire Array
• Write Protect (WP) Pin and Write Disable Instructions for
Both Hardware and Software Data Protection
• High Reliability
SPI Serial
EEPROMs
256K (32,768 x 8)
512K (65,536 x 8)
– Endurance: 100K Write Cycles
– Data Retention: > 40 Years
– ESD Protection: > 3000V
• 8-Pin PDIP, 8-Pin EIAJ SOIC, and 8-Pin Leadless Array Package
Description
The AT25HP256/512 provides 262,144/524,288 bits of serial electrically erasable pro-
grammable read only memory (EEPROM) organized as 32,768/65,536 words of 8-bits
each. The device is optimized for use in many industrial and commercial applications
where high-speed, low-power, and low-voltage operation are essential. The
AT25HP256/512 is available in a space saving 8-pin PDIP (AT25HP256/512), 8-pin
EIAJ SOIC (AT25HP256), and 8-pin Leadless Array (AT25HP256/512) packages. In
AT25HP256
AT25HP512
Preliminary
(continued)
Pin Configurations
Pin Name
Function
CS
Chip Select
SCK
SI
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
SO
GND
VCC
WP
Power Supply
Write Protect
HOLD
Suspends Serial Input
8-Pin PDIP
8-Pin SOIC
8-Pin Leadless Array
VCC
HOLD
SCK
SI
8
7
6
5
1
2
3
4
CS
1
2
8
7
1
2
8
7
VCC
VCC
CS
SO
CS
SO
SO
HOLD
SCK
SI
HOLD
SCK
SI
WP
GND
3
4
6
5
3
4
6
5
WP
WP
GND
GND
Bottom View
Rev. 1113B–07/98
addition, the entire family is available in 5.0V (4.5V to
5.5V), 2.7V (2.7V to 5.5V), and 1.8V (1.8V to 3.6V) ver-
sions.
Absolute Maximum Ratings*
Operating Temperature .................................. -55°C to +125°C
The AT25HP256/512 is enabled through the Chip Select
pin (CS) and accessed via a 3-wire interface consisting of
Serial Data Input (SI), Serial Data Output (SO), and Serial
Clock (SCK). All programming cycles are completely self-
timed, and no separate ERASE cycle is required before
WRITE.
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground .................................... -1.0V to +7.0V
Maximum Operating Voltage........................................... 6.25V
DC Output Current........................................................5.0 mA
BLOCK WRITE protection is enabled by programming the
status register with top ¼, top ½ or entire array of write pro-
tection. Separate program enable and program disable
instructions are provided for additional data protection.
Hardware data protection is provided via the WP pin to pro-
tect against inadvertent write attempts to the status regis-
ter. The HOLD pin may be used to suspend any serial
communication without resetting the serial sequence.
*NOTICE:
Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other condi-
tions beyond those indicated in the operational sec-
tions of this specification is not implied. Exposure to
absolute maximum rating conditions for extended
periods may affect device reliability.
Block Diagram
32,768/65,536x8
AT25HP256/512
2
AT25HP256/512
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted).
Test Conditions
Max
8
Units
pF
Conditions
VOUT = 0V
VIN = 0V
COUT
Output Capacitance (SO)
CIN
Input Capacitance (CS, SCK, SI, WP, HOLD)
6
pF
Note:
1. This parameter is characterized and is not 100% tested.
DC Characteristics
Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V,
TAC = 0°C to +70°C, VCC = +1.8V to +5.5V (unless otherwise noted).
Symbol
VCC1
VCC2
VCC3
ICC1
ICC2
ISB1
Parameter
Test Condition
Min
1.8
2.7
4.5
Typ
Max
Units
Supply Voltage
3.6
5.5
V
V
Supply Voltage
Supply Voltage
5.5
V
Supply Current
Supply Current
Standby Current
Standby Current
Standby Current
Input Leakage
VCC = 5.0V at 5 MHz, SO = Open Read
VCC = 5.0V at 5 MHz, SO = Open Write
VCC = 1.8V, CS = VCC
6.0
4.0
0.1
0.2
2.0
10.0
7.0
mA
mA
µA
µA
µA
µA
µA
V
2.0
ISB2
VCC = 2.7V, CS = VCC
2.0
ISB3
VCC = 5.0V, CS = VCC
5.0
IIL
VIN = 0V to VCC
-3.0
-3.0
3.0
IOL
Output Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
VIN = 0V to VCC, TAC = 0°C to 70°C
3.0
(1)
VIL
-0.6
VCC x 0.3
VCC + 0.5
0.4
(1)
VIH
VCC x 0.7
V
VOL1
VOH1
VOL2
VOH2
I
OL = 3.0 mA
IOH = -1.6 mA
OL = 0.15 mA
IOH = -100 µA
V
4.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 3.6V
VCC - 0.8
VCC - 0.2
V
I
0.2
V
V
Note:
1. VIL and VIH max are reference only and are not tested.
3
AC Characteristics
Applicable over recommended operating range from TA = -40°C to +85°C, VCC = As Specified,
CL = 1 TTL Gate and 30 pF (unless otherwise noted).
Symbol
Parameter
Voltage
Min
Max
Units
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
0
0
0
10
5
TBD
fSCK
SCK Clock Frequency
MHz
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
2
2
TBD
tRI
Input Rise Time
Input Fall Time
SCK High Time
SCK Low Time
CS High Time
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
2
2
TBD
tFI
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
40
80
TBD
tWH
tWL
tCS
tCSS
tCSH
tSU
tH
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
40
80
TBD
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
50
100
TBD
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
50
100
TBD
CS Setup Time
CS Hold Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
50
100
TBD
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
12
20
TBD
Data In Setup Time
Data In Hold Time
Hold Setup Time
Hold Hold Time
Output Valid
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
10
20
TBD
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
25
50
TBD
tHD
tCD
tV
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
25
50
TBD
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
0
0
0
40
80
TBD
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
0
0
0
tHO
Output Hold Time
AT25HP256/512
4
AT25HP256/512
AC Characteristics (Continued)
Applicable over recommended operating range from TA = -40°C to +85°C, VCC = As Specified,
CL = 1 TTL Gate and 30 pF (unless otherwise noted).
Symbol
Parameter
Voltage
Min
Max
Units
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
0
0
0
100
200
TBD
tLZ
Hold to Output Low Z
ns
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
100
200
TBD
tHZ
Hold to Output High Z
Output Disable Time
Write Cycle Time
ns
ns
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
100
100
TBD
tDIS
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
5
10
TBD
tWC
ms
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
Write
Cycles
Endurance(1)
5.0V, 25°C, Page Mode
100K
Note:
1. This parameter is characterized and is not 100% tested.
5
status register. The WP pin function is blocked when the
WPEN bit in the status register is “0”. This will allow the
user to install the AT25HP256/512 in a system with the WP
pin tied to ground and still be able to write to the status reg-
ister. All WP pin functions are enabled when the WPEN bit
is set to “1”.
Serial Interface Description
MASTER: The device that generates the serial clock.
SLAVE: Because the Serial Clock pin (SCK) is always an
input, the AT25HP256/512 always operates as a slave.
TRANSMITTER/RECEIVER: The AT25HP256/512 has
separate pins designated for data transmission (SO) and
reception (SI).
SPI Serial Interface
MSB: The Most Significant Bit (MSB) is the first bit
transmitted and received.
AT25HP256/512
SERIAL OP-CODE: After the device is selected with CS
going low, the first byte will be received. This byte contains
the op-code that defines the operations to be performed.
INVALID OP-CODE: If an invalid op-code is received, no
data will be shifted into the AT25HP256/512, and the serial
output pin (SO) will remain in a high impedance state until
the falling edge of CS is detected again. This will reinitialize
the serial communication.
CHIP SELECT: The AT25HP256/512 is selected when the
CS pin is low. When the device is not selected, data will not
be accepted via the SI pin, and the serial output pin (SO)
will remain in a high impedance state.
HOLD: The HOLD pin is used in conjunction with the CS
pin to select the AT25HP256/512. When the device is
selected and a serial sequence is underway, HOLD can be
used to pause the serial communication with the master
device without resetting the serial sequence. To pause, the
HOLD pin must be brought low while the SCK pin is low. To
resume serial communication, the HOLD pin is brought
high while the SCK pin is low (SCK may still toggle during
HOLD). Inputs to the SI pin will be ignored while the SO pin
is in the high impedance state.
WRITE PROTECT: The write protect pin (WP) will allow
normal read/write operations when held high. When the
WP pin is brought low and WPEN bit is “1”, all write opera-
tions to the status register are inhibited. WP going low
while CS is still low will interrupt a write to the status regis-
ter. If the internal write cycle has already been initiated, WP
going low will have no effect on any write operation to the
AT25HP256/512
6
AT25HP256/512
Functional Description
The AT25HP256/512 is designed to interface directly with
the synchronous serial peripheral interface (SPI) of the
6800 type series of microcontrollers.
Table 3. Read Status Register Bit Definition
Bit
Definition
Bit 0 (RDY)
Bit 0 = 0 (RDY) indicates the device is
READY. Bit 0 = 1 indicates the write cycle is in
progress.
The AT25HP256/512 utilizes an 8-bit instruction register.
The list of instructions and their operation codes are con-
tained in Table 1. All instructions, addresses, and data are
transferred with the MSB first and start with a high-to-low
CS transition.
Bit 1 (WEN)
Bit 1= 0 indicates the device is not WRITE
ENABLED. Bit 1 = 1 indicates the device is
WRITE ENABLED.
Table 1. Instruction Set for the AT25HP256/512
Bit 2 (BP0)
Bit 3 (BP1)
See Table 4.
See Table 4.
Instruction
Name
Instruction
Format
Operation
WREN
WRDI
0000 X110
0000 X100
0000 X101
0000 X001
0000 X011
0000 X010
Set Write Enable Latch
Reset Write Enable Latch
Read Status Register
Write Status Register
Read Data from Memory Array
Write Data to Memory Array
Bits 4-6 are 0s when device is not in an internal write cycle.
Bit 7 (WPEN) See Table 5.
RDSR
WRSR
READ
WRITE
Bits 0-7 are 1s during an internal write cycle.
WRITE STATUS REGISTER (WRSR): The WRSR instruc-
tion allows the user to select one of four levels of protec-
tion. The AT25HP256/512 is divided into four array
segments. Top quarter (1/4), top half (1/2), or all of the
memory segments can be protected. Any of the data within
any selected segment will therefore be READ only. The
block write protection levels and corresponding status reg-
ister control bits are shown in Table 4.
WRITE ENABLE (WREN): The device will power up in the
write disable state when VCC is applied. All programming
instructions must therefore be preceded by a Write Enable
instruction.
The three bits, BP0, BP1, and WPEN are nonvolatile cells
that have the same properties and functions as the regular
memory cells (e.g. WREN, tWC, RDSR).
WRITE DISABLE (WRDI): To protect the device against
inadvertent writes, the Write Disable instruction disables all
programming modes. The WRDI instruction is independent
of the status of the WP pin.
Table 4. Block Write Protect Bits
READ STATUS REGISTER (RDSR): The Read Status
Register instruction provides access to the status register.
The READY/BUSY and Write Enable status of the device
can be determined by the RDSR instruction. Similarly, the
Block Write Protection bits indicate the extent of protection
employed. These bits are set by using the WRSR instruc-
tion.
Status Register Bits Array Addresses Protected
Level
0
BP1
BP0
AT25HP256/512
None
0
0
1
1
0
1
0
1
1(1/4)
2(1/2)
3(All)
6000 - 7FFF/C000 - FFFF
4000 - 7FFF/8000 - FFFF
0000 - 7FFF/0000 - FFFF
Table 2. Status Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The WRSR instruction also allows the user to enable or
disable the write protect (WP) pin through the use of the
Write Protect Enable (WPEN) bit. Hardware write protec-
tion is enabled when the WP pin is low and the WPEN bit is
“1”. Hardware write protection is disabled when either the
WP pin is high or the WPEN bit is “0.” When the device is
hardware write protected, writes to the Status Register,
including the Block Protect bits and the WPEN bit, and the
block-protected sections in the memory array are disabled.
WPEN
X
X
X
BP1
BP0
WEN
RDY
7
Writes are only allowed to sections of the memory which
are not block-protected.
Protection Level. During an internal write cycle, all com-
mands will be ignored except the RDSR instruction.
NOTE: When the WPEN bit is hardware write protected, it
cannot be changed back to “0”, as long as the WP pin is
held low.
A Write Instruction requires the following sequence. After
the CS line is pulled low to select the device, the WRITE
op-code is transmitted via the SI line followed by the byte
address and the data (D7-D0) to be programmed (Refer to
Table 6). Programming will start after the CS pin is brought
high. (The LOW to High transition of the CS pin must occur
during the SCK low time immediately after clocking in the
D0 (LSB) data bit.
Table 5. WPEN Operation
Protected
Blocks
Unprotected
Blocks
Status
Register
WPEN
WP
X
WEN
0
0
1
1
X
X
0
1
0
1
0
1
Protected
Protected
Protected
Protected
Protected
Protected
Protected
Writable
Protected
Writable
Protected
Writable
Protected
Writable
X
The READY/BUSY status of the device can be determined
by initiating a READ STATUS REGISTER (RDSR) Instruc-
tion. If Bit 0 = 1, the WRITE cycle is still in progress. If Bit 0
= 0, the WRITE cycle has ended. Only the READ STATUS
REGISTER instruction is enabled during the WRITE pro-
gramming cycle.
Low
Low
High
High
Protected
Protected
Protected
Writable
The AT25HP256/512 is capable of a 128-byte PAGE
WRITE operation. After each byte of data is received, the
seven low order address bits are internally incremented by
one; the high order bits of the address will remain constant.
If more than 128-bytes of data are transmitted, the address
counter will roll over and the previously written data will be
overwritten. The AT25HP256/512 is automatically returned
to the write disable state at the completion of a WRITE
cycle.
READ
SEQUENCE
(READ): Reading
the
AT25HP256/512 via the SO (Serial Output) pin requires the
following sequence. After the CS line is pulled low to select
a device, the READ op-code is transmitted via the SI line
followed by the byte address to be read (Refer to Table 6).
Upon completion, any data on the SI line will be ignored.
The data (D7-D0) at the specified address is then shifted
out onto the SO line. If only one byte is to be read, the CS
line should be driven high after the data comes out. The
READ sequence can be continued since the byte address
is automatically incremented and data will continue to be
shifted out. When the highest address is reached, the
address counter will roll over to the lowest address allowing
the entire memory to be read in one continuous READ
cycle.
NOTE: If the device is not Write enabled (WREN), the
device will ignore the Write instruction and will return to the
standby state, when CS is brought high. A new CS falling
edge is required to re-initiate the serial communication.
Table 6. Address Key
Address
AN
AT25HP256/512
A14 - A0 / A15 - A0
A15 / none
WRITE SEQUENCE (WRITE): In order to program the
AT25HP256/512, two separate instructions must be exe-
cuted. First, the device must be write enabled via the
Write Enable (WREN) Instruction. Then a Write (WRITE)
Instruction may be executed. Also, the address of the
memory location(s) to be programmed must be outside the
protected address field location selected by the Block Write
Don’t Care Bits
NOTE: 128-byte PAGE WRITE operation only. Content of
the page in the array will not be guaranteed if less than 128
bytes of data is received (byte write is not supported).
AT25HP256/512
8
AT25HP256/512
Timing Diagrams (for SPI Mode 0 (0, 0))
Synchronous Data Timing
t
CS
V
V
IH
CS
IL
t
t
CSH
CSS
V
IH
t
WL
t
WH
SKC
SI
V
IL
t
t
H
SU
V
V
IH
VALID IN
IL
t
t
t
V
HO
DIS
HI-Z
V
OH
HI- Z
SO
V
OL
WREN Timing
CS
SCK
SI
SO
WRDI Timing
CS
SCK
SI
WRDI OP-CODE
HI-Z
SO
9
RDSR Timing
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
SCK
SI
INSTRUCTION
DATA OUT
HIGH IMPEDANCE
7
6
5
4
3
2
1
0
SO
MSB
WRSR Timing
READ Timing
AT25HP256/512
10
AT25HP256/512
WRITE Timing (AT25HP256)
CS
0
1
2
3
4
5
6
7
8
9
10 11 20 21 22 23 24 25 26 27 28 29 30 31
SCK
SI
BYTE ADDRESS
...
1ST BYTE DATA IN
13
INSTRUCTION
1
0
15
14
7
6
5
3
2
2
4
0
3
1
HIGH IMPEDANCE
SO
11
PAGE WRITE Timing (AT25HP512)
CS
0
1
2
3
4
5
6
7
8
9
10 11 20 21 22 23 24 25 26 10431044 1045 1046 1047
SCK
SI
st
th
BYTE ADDRESS 1 BYTE DATA IN
128 BYTE DATA IN
INSTRUCTION
13
12
1
0
15
14
7
6
5
3
2
2
4
0
3
1
HIGH IMPEDANCE
SO
HOLD Timing
CS
tCD
tCD
SCK
HOLD
SO
tHD
tHD
tHZ
tLZ
AT25HP256/512
12
AT25HP256/512
AT25HP256 Ordering Information
tWC (max)
(ms)
ICC (max)
ISB (max)
(µA)
fMAX
(kHz)
(µA)
Ordering Code
Package
Operation Range
AT25HP256-10CC
AT25HP256C1-10CC
AT25HP256-10PC
AT25HP256W-10SC
8C
Commercial
8C1
8P3
8S2
(0°C to 70°C)
8000
8000
4000
4000
TBD
TBD
7.0
7.0
10000
10000
5000
5000
TBD
5
AT25HP256-10CI
AT25HP256C1-10CI
AT25HP256-10PI
AT25HP256W-10SI
8C
Industrial
8C1
8P3
8S2
(-40°C to 85°C)
AT25HP256-10CC-2.7
AT25HP256C1-10CC-2.7
AT25HP256-10PC-2.7
AT25HP256W-10SC-2.7
8C
Commercial
8C1
8P3
8S2
(0°C to 70°C)
3.0
5
AT25HP256-10CI-2.7
AT25HP256C1-10CI-2.7
AT25HP256-10PI-2.7
AT25HP256W-10SI-2.7
8C
Industrial
8C1
8P3
8S2
(-40°C to 85°C)
3.0
AT25HP256-10CC-1.8
AT25HP256C1-10CC-1.8
AT25HP256-10PC-1.8
AT25HP256W-10SC-1.8
8C
Commercial
8C1
8P3
8S2
(0°C to 70°C)
TBD
TBD
TBD
AT25HP256-10CI-1.8
AT25HP256C1-10CI-1.8
AT25HP256-10PI-1.8
AT25HP256W-10SI-1.8
8C
Industrial
8C1
8P3
8S2
(-40°C to 85°C)
TBD
Package Type
8C
8-Lead, 0.230" Wide, Leadless Array Package (LAP)
8-Lead, 0.300" Wide, Leadless Array Package (LAP)
8C1
8P3
8S2
8-Lead, 0.300" Wide, Plastic Dual In-line Package (PDIP)
8-Lead, 0.300" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)
Options
Blank Standard Device (4.5V to 5.5V)
-2.7
-1.8
Low Voltage (2.7V to 5.5V)
Low Voltage (1.8V to 3.6V)
13
AT25HP512 Ordering Information
tWC (max)
(ms)
ICC (max)
ISB (max)
(µA)
fMAX
(kHz)
(µA)
Ordering Code
Package
Operation Range
AT25HP512C1-10CC
AT25HP512-10PC
8C1
8P3
Commercial
8000
8000
4000
4000
TBD
TBD
7.0
7.0
10000
10000
5000
5000
TBD
(0°C to 70°C)
5
5
AT25HP512C1-10CI
AT25HP512-10PI
8C1
8P3
Industrial
(-40°C to 85°C)
AT25HP512C1-10CC-2.7
AT25HP512-10PC-2.7
8C1
8P3
Commercial
3.0
(0°C to 70°C)
AT25HP512C1-10CI-2.7
AT25HP512-10PI-2.7
8C1
8P3
Industrial
3.0
(-40°C to 85°C)
AT25HP512C1-10CC-1.8
AT25HP512-10PC-1.8
8C1
8P3
Commercial
TBD
TBD
(0°C to 70°C)
TBD
AT25HP512C1-10CI-1.8
AT25HP512-10PI-1.8
8C1
8P3
Industrial
TBD
(-40°C to 85°C)
Package Type
8-Lead, 0.300" Wide, Leadless Array Package (LAP)
8-Lead, 0.300" Wide, Plastic Dual In-line Package (PDIP)
Options
8C1
8P3
Blank Standard Device (4.5V to 5.5V)
-2.7
-1.8
Low Voltage (2.7V to 5.5V)
Low Voltage (1.8V to 3.6V)
AT25HP256/512
14
AT25HP256/512
Packaging Information
8C, 8-Lead, 0.230" Wide, Leadless Array Package
(LAP)
8C1, 8-Lead, 0.300" Wide, Leadless Array Package
(LAP)
Dimensions in Inches and (Millimeters)
Dimensions in Inches and (Millimeters)
SIDE
SIDE
TOP VIEW
VIEW
TOP VIEW
VIEW
5.15 (0.203)
4.85 (0.191)
5.15 (0.203)
4.85 (0.191)
8.15 (0.321)
7.85 (0.309)
1.30 (0.051)
1.00 (0.039)
0.42 (0.017)
0.34 (0.013)
6.15 (0.242)
5.85 (0.230)
1.30 (0.051)
1.00 (0.039)
0.42 (0.017)
0.34 (0.013)
BOTTOM VIEW
BOTTOM VIEW
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
0.41 (0.016) TYP
0.41 (0.016) TYP
1.27 (0.050) TYP
1.27 (0.050) TYP
0.64 (0.025) TYP
0.64 (0.025) TYP
8P3, 8-Lead, 0.300" Wide, Plastic Dual In-line
Package (PDIP) Dimensions in Inches and
(Millimeters) JEDEC STANDARD MS-001 BA
8S2, 8-Lead, 0.200" Wide, Plastic Gull Wing Small
Outline (EIAJ SOIC)
Dimensions in Inches and (Millimeters)
.400 (10.16)
.355 (9.02)
.020 (.508)
.012 (.305)
PIN
1
.213 (5.41) .330 (8.38)
.205 (5.21) .300 (7.62)
.280 (7.11)
.240 (6.10)
PIN 1
.037 (.940)
.027 (.690)
.300 (7.62) REF
.210 (5.33) MAX
.050 (1.27) BSC
.100 (2.54) BSC
SEATING
PLANE
.212 (5.38)
.203 (5.16)
.080 (2.03)
.070 (1.78)
.015 (.380) MIN
.150 (3.81)
.115 (2.92)
.022 (.559)
.014 (.356)
.070 (1.78)
.045 (1.14)
.013 (.330)
.004 (.102)
.325 (8.26)
.300 (7.62)
0
8
0
REF
.010 (.254)
.007 (.178)
REF
15
.012 (.305)
.008 (.203)
.035 (.889)
.020 (.508)
.430 (10.9) MAX
15
相关型号：
AT25HP512C1-10CJ-1.8
EEPROM, 64KX8, Serial, CMOS, 0.300 INCH, 8 X 5 MM, 1.04 MM HEIGHT, 1.27 MM PITCH, LAP-8
MICROCHIP
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