AT49BV1604T-90TI_技术文档

Features

• 2.7V to 3.6V Read/Write

• Access Time - 90 ns

• Sector Erase Architecture

– Thirty 32K word (64K byte) Sectors with Individual Write Lockout

– Eight 4K word (8K byte) Sectors with Individual Write Lockout

– Two 16K word (32K byte) Sectors with Individual Write Lockout

• Fast Word Program Time - 20 µs

• Fast Sector Erase Time - 200 ms

• Dual Plane Organization, Permitting Concurrent Read while Program/Erase

– Memory Plane A: Eight 4K Word, Two 16K Word and Six 32K Word Sectors

– Memory Plane B: Twenty-Four 32K Word Sectors

• Erase Suspend Capability

– Supports Reading/Programming Data from Any Sector by Suspending Erase of

Any Different Sector

• Low Power Operation

16-Megabit

(1M x 16/2M x 8)

3-volt Only

– 25 mA Active

– 10 µA Standby

Flash Memory

• Data Polling, Toggle Bit, Ready/Busy for End of Program Detection

• Optional V_PPPin for Fast Programming

• RESET Input for Device Initialization

• Sector Program Unlock Command

• TSOP, CBGA, and µBGA Package Options

• Top or Bottom Boot Block Configuration Available

AT49BV1604

AT49BV1604T

AT49BV1614

AT49BV1614T

Advance

Description

The AT49BV16X4(T) is 2.7 to 3.6 volt 16-megabit Flash memory organized as

1,048,576 words of 16 bits each or 2,097,152 bytes of 8 bits each. The x16 data

appears on I/O0 - I/O15; the x8 data appears on I/O0 - I/O7. The memory is divided

into 40 blocks for erase operations. The device is offered in 48-pin TSOP and 48-ball

µBGA packages. The device has CE, and OE control signals to avoid any bus con-

tention. This device can be read or reprogrammed using a single 2.7V power supply,

Information

AT49BV16X4(T)

making it ideally suited for in-system programming.

(continued)

Pin Configurations

Pin Name

A0 - A19

CE

Function

AT49BV1604

Addresses

Chip Enable

Output Enable

Write Enable

Reset

OE

WE

RESET

RDY/BUSY

READY/BUSY Output

Optional Power Supply for Faster

Program/Erase Operations

V_PP

I/O0 - I/O14

I/O15 (A-1)

Data Inputs/Outputs

I/O15 (Data Input/Output, Word Mode)

A-1 (LSB Address Input, Byte Mode)

BYTE

NC

Selects Byte or Word Mode

No Connect

Rev. 0925B–05/98

V_CCQ

DC

Output Power Supply

Don’t Connect

1

TSOP Top View

Type 1

A15

A14

A13

A12

A11

A10

A9

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

µBGA Top View (Ball Down)

2

VCCQ

GND

I/O15

I/O7

I/O14

I/O6

I/O13

I/O5

I/O12

I/O4

VCC

I/O11

I/O3

I/O10

I/O2

I/O9

I/O1

I/O8

I/O0

OE

3

8

1

2

3

4

5

6

7

4

5

6

7

A

B

C

D

E

F

A8

8

A13

A14

A15

A16

A11

A10

A8

WE

VPP

RST

NC

A18

NC

A19

A17

A6

A7

A5

A4

A2

NC

9

NC

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

WE

RESET

VPP

NC

AT49BV1604(T)

A12

A9

A3

A1

A19

A18

A17

A7

I/O14

I/O5

I/O6

I/O13

I/O11

I/O12

I/O4

I/O2

I/O3

I/O8

I/O9

CE

A0

VCCQ I/O15

I/O0

I/O1

GND

OE

A6

A5

GND

I/O7

VCC I/O10

A4

A3

GND

CE

A2

A1

A0

TSOP Top View

Type 1

A15

1

48

A16

A14

A13

A12

A11

A10

A9

2

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

BYTE

GND

I/O15/A-1

I/O7

CBGA Top View

3

4

5

G

F

E

D

C

B

A

H

6

I/O14

I/O6

7

A8

8

I/O13

I/O5

1

2

3

4

5

6

A19

NC

9

VSS

I/O1

I/O3

I/O4

I/O6

VSS

OE

CE

A0

A1

A5

A2

A6

A4

A3

A7

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

I/O12

I/O4

WE

I/O9

I/O8

I/O0

I/O2

I/O5

I/O7

A17

RESET

VPP

NC

VCC

I/O11

I/O3

AT49BV1614(T)

I/O11 I/O10

VCC I/O12

I/O13 I/O14

NC

A19

A11

A15

A18

NC RDY/BUSY

RDY/BUSY

A18

A17

A7

I/O10

I/O2

NC RESET WE

I/O9

I/O1

A6

I/O8

A10

A14

A8

A9

A5

I/O0

A4

OE

I/O15 BYTE A16

/A-1

A12

A13

A3

GND

CE

A2

A1

A0

The device powers on in the read mode. Command

sequences are used to place the device in other operation

modes such as program and erase. The device has the

capability to protect the data in any sector. Once the data

protection for a given sector is enabled, the data in that

sector cannot be changed using input levels between

contains an Erase Suspend feature. This feature will put

the Erase on hold for any amount of time and let the user

read data from or program data to any of the remaining

sectors within the same memory plane. There is no reason

to suspend the erase operation if the data to be read is in

the other memory plane. The end of a program or an Erase

cycle is detected by the Ready/Busy pin, Data polling, or by

the toggle bit.

ground and V_CC

.

The device is segmented into two memory planes. Reads

from memory plane B may be performed even while pro-

gram or erase functions are being executed in memory

plane A and vice versa. This operation allows improved

system performance by not requiring the system to wait for

a program or erase operation to complete before a read is

performed. To further increase the flexibility of the device, it

A V_PPpin is provided to improve program/erase times at

lower supply voltages. This pin does not need to be uti-

lized. If it is not used the pin should be connected to ground

or V_CC. To take advantage of faster programming, the pin

should supply 5.0 volts during program and erase opera-

tions.

AT49BV16X4(T)

2

AT49BV16X4(T)

A six byte command (bypass unlock) sequence to remove

the requirement of entering the three byte program

sequence is offered to further improve programming time.

After entering the six byte code, only single pulses on the

write control lines are required for writing into the device.

This mode (single pulse byte/word program) is exited by

powering down the device, or by pulsing the RESET pin

low and then bringing it back to V_CC. Erase and Erase Sus-

pend/Resume commands will not work while in this mode;

if entered they will result in data being programmed into the

device. It is not recommended that the six byte code reside

in the software of the final product but only exist in external

programming code.

The BYTE pin controls whether the device data I/O pins

operate in the byte or word configuration. If the BYTE pin is

set at logic “1”, the device is in word configuration, I/O0-

I/O15 are active and controlled by CE and OE.

If the BYTE pin is set at logic “0”, the device is in byte con-

figuration, and only data I/O pins I/O0-I/O7 are active and

controlled by CE and OE. The data I/O pins I/O8-I/O14 are

tri-stated, and the I/O15 pin is used as an input for the LSB

(A-1) address function.

Block Diagram

I/O0 - I/O15/A-1

OUTPUT

BUFFER

INPUT

BUFFER

IDENTIFIER

REGISTER

INPUT

A0 - A19

BUFFER

STATUS

CE

REGISTER

WE

COMMAND

REGISTER

OE

RESET

BYTE

ADDRESS

LATCH

DATA

RDY/BUSY

VPP

COMPARATOR

WRITE STATE

MACHINE

PROGRAM/ERASE

VOLTAGE SWITCH

Y-DECODER

X-DECODER

Y-GATING

VCC

GND

PLANE B

SECTORS

PLANE A SECTORS

Device Operation

READ: The AT49BV16X4(T) is accessed like an EPROM.

When CE and OE are low and WE is high, the data stored

at the memory location determined by the address pins are

asserted on the outputs. The outputs are put in the high

impedance state whenever CE or OE is high. This dual-line

control gives designers flexibility in preventing bus conten-

tion.

sequences are entered into the device. The command

sequences are shown in the Command Definitions table

(I/O8 - I/O15 are don't care inputs for the command codes).

The command sequences are written by applying a low

pulse on the WE or CE input with CE or WE low (respec-

tively) and OE high. The address is latched on the falling

edge of CE or WE, whichever occurs last. The data is

latched by the first rising edge of CE or WE. Standard

microprocessor write timings are used. The address loca-

tions used in the command sequences are not affected by

entering the command sequences.

COMMAND SEQUENCES: When the device is first pow-

ered on it will be reset to the read or standby mode

depending upon the state of the control line inputs. In order

to perform other device functions, a series of command

3

RESET: A RESET input pin is provided to ease some sys-

tem applications. When RESET is at a logic high level, the

device is in its standard operating mode. A low level on the

RESET input halts the present device operation and puts

the outputs of the device in a high impedance state. When

a high level is reasserted on the RESET pin, the device

returns to the Read or Standby mode, depending upon the

state of the control inputs. By applying a 12V ± 0.5V input

signal to the RESET pin any sector can be reprogrammed

even if the sector lockout feature has been enabled (see

Sector Programming Lockout Override section).

the specified t_BPcycle time. The DATA polling feature or

the toggle bit feature may be used to indicate the end of a

program cycle.

SECTOR PROGRAMMING LOCKOUT: Each sector has a

programming lockout feature. This feature prevents pro-

gramming of data in the designated sectors once the fea-

ture has been enabled. These sectors can contain secure

code that is used to bring up the system. Enabling the lock-

out feature will allow the boot code to stay in the device

while data in the rest of the device is updated. This feature

does not have to be activated; any sector’s usage as a

write protected region is optional to the user.

ERASURE: Before a byte/word can be reprogrammed, it

must be erased. The erased state of memory bits is a logi-

cal “1”. The entire device can be erased by using the Chip

Erase command or individual sectors can be erased by

using the Sector Erase commands.

Once the feature is enabled, the data in the protected sec-

tors can no longer be erased or programmed when input

levels of 5.5V or less are used. Data in the remaining sec-

tors can still be changed through the regular programming

method. To activate the lockout feature, a series of six pro-

gram commands to specific addresses with specific data

must be performed. Please refer to the Command Defini-

tions table.

CHIP ERASE: The entire device can be erased at one

time by using the 6-byte chip erase software code. After the

chip erase has been initiated, the device will internally time

the erase operation so that no external clocks are required.

The maximum time to erase the chip is t_EC

.

SECTOR PROGRAMMING LOCKOUT OVERRIDE: The

user can override the sector programming lockout by taking

the RESET pin to 12V ± 0.5V. By doing this protected data

can be altered through a chip erase, sector erase or

byte/word programming. When the RESET pin is brought

back to TTL levels the sector programming lockout feature

is again active.

If the sector lockout has been enabled, the Chip Erase will

not erase the data in the sector that has been locked; it will

erase only the unprotected sectors. After the chip erase,

the device will return to the read or standby mode.

SECTOR ERASE: As an alternative to a full chip erase, the

device is organized into forty sectors (SA0 - SA39) that can

be individually erased. The Sector Erase command is a six

bus cycle operation. The sector address is latched on the

falling WE edge of the sixth cycle while the 30H data input

command is latched on the rising edge of WE. The sector

erase starts after the rising edge of WE of the sixth cycle.

The erase operation is internally controlled; it will automati-

cally time to completion. The maximum time to erase a sec-

tion is t_SEC. When the sector programming lockout feature

is not enabled, the sector will erase (from the same sector

erase command). Once a sector has been protected, data

in the protected sectors cannot be changed unless the

RESET pin is taken to 12V ± 0.5V. An attempt to erase a

sector that has been protected will result in the operation

terminating in 2 µs.

ERASE SUSPEND/ERASE RESUME: The erase suspend

command allows the system to interrupt a sector erase

operation and then program or read data from a different

sector within the same plane. Since this device has a dual

plane architecture, there is no need to use the erase sus-

pend feature while erasing a sector when you want to read

data from a sector in the other plane. After the erase sus-

pend command is given, the device requires a maximum

time of 15 µs to suspend the erase operation. After the

erase operation has been suspended, the plane which con-

tains the suspended sector enters the erase-suspend-read

mode. The system can then read data or program data to

any other sector within the device. An address is not

required during the erase suspend command. During a

sector erase suspend, another sector cannot be erased. To

resume the sector erase operation, the system must write

the erase resume command. The erase resume command

is a one bus cycle command, which does require the plane

address (determined by A18 and A19). The device also

supports an erase suspend during a complete chip erase.

While the chip erase is suspended, the user can read from

any sector within the memory that is protected. The com-

mand sequence for a chip erase suspend and a sector

erase suspend are the same.

BYTE/WORD PROGRAMMING: Once a memory block is

erased, it is programmed (to a logical “0”) on a byte-by-byte

or on a word-by-word basis. Programming is accomplished

via the internal device command register and is a 4-bus

cycle operation. The device will automatically generate the

required internal program pulses.

Any commands written to the chip during the embedded

programming cycle will be ignored. If a hardware reset hap-

pens during programming, the data at the location being

programmed will be corrupted. Please note that a data “0”

cannot be programmed back to a “1”; only erase operations

can convert “0”s to “1”s. Programming is completed after

PRODUCT IDENTIFICATION: The product identification

mode identifies the device and manufacturer as Atmel. It

AT49BV16X4(T)

4

AT49BV16X4(T)

may be accessed by hardware or software operation. The

hardware operation mode can be used by an external pro-

grammer to identify the correct programming algorithm for

the Atmel product.

I/O2 bit toggling. Please see status bit table for more

details.

RDY/BUSY: An open drain READY/BUSY output pin pro-

vides another method of detecting the end of a program or

erase operation. RDY/BUSY is actively pulled low during

the internal program and erase cycles and is released at

the completion of the cycle. The open drain connection

allows for OR-tying of several devices to the same

RDY/BUSY line.

For details, see Operating Modes (for hardware operation)

or Software Product Identification. The manufacturer and

device code is the same for both modes.

DATA POLLING: The AT49BV16X4(T) features DATA

polling to indicate the end of a program cycle. During a pro-

gram cycle an attempted read of the last byte/word loaded

will result in the complement of the loaded data on I/O7.

Once the program cycle has been completed, true data is

valid on all outputs and the next cycle may begin. During a

chip or sector erase operation, an attempt to read the

device will give a “0” on I/O7. Once the program or erase

cycle has completed, true data will be read from the device.

DATA polling may begin at any time during the program

cycle. Please see “Status Bit Table” for more details.

HARDWARE DATA PROTECTION: Hardware features

protect against inadvertent programs to the

AT49BV16X4(T) in the following ways: (a) V_CCsense: if

V_CCis below 1.8V (typical), the program function is inhib-

ited. (b) V_CCpower on delay: once V_CChas reached the

V_CCsense level, the device will automatically time out 10

ms (typical) before programming. (c) Program inhibit: hold-

ing any one of OE low, CE high or WE high inhibits pro-

gram cycles. (d) Noise filter: pulses of less than 15 ns

(typical) on the WE or CE inputs will not initiate a program

cycle.

TOGGLE BIT: In addition to DATA polling the

AT49BV16X4(T) provides another method for determining

the end of a program or erase cycle. During a program or

erase operation, successive attempts to read data from the

same memory plane will result in I/O6 toggling between

one and zero. Once the program cycle has completed, I/O6

will stop toggling and valid data will be read. Examining the

toggle bit may begin at any time during a program cycle.

INPUT LEVELS: While operating with a 2.7V to 3.6V

power supply, the address inputs and control inputs (OE,

CE, and WE) may be driven from 0 to 5.5V without

adversely affecting the operation of the device. The I/O

lines can only be driven from 0 to V_CC+ 0.6V.

OUTPUT LEVELS: Output High Levels (V_OH) are equal to

V_CCQ- 0.2V (not V_CC). For 2.7V - 3.6V output levels, V_CCQ

must be tied to V_CC. For 1.8V - 2.2V output levels, V_CCQ

must be regulated to 2.0V ± 10% while V_CCmust be regu-

lated to 2.7V - 3.0V (for minimum power).

An additional toggle bit is available on I/O2 which can be

used in conjunction with the toggle bit which is available on

I/O6. While a sector is erase suspended, a read or a pro-

gram operation from the suspended sector will result in the

5

Command Definition in (Hex)⁽¹⁾

1st Bus

Cycle

2nd Bus

Cycle

3rd Bus

Cycle

4th Bus

Cycle

5th Bus

Cycle

6th Bus

Cycle

Command

Sequence

Bus

Cycles Addr Data

Addr

Data Addr Data Addr Data

Addr

Data

Addr

Data

Read

1

6

4

6

Addr D_OUT

Chip Erase

5555

AA

2AAA

55

5555

80

A0

80

5555

Addr

5555

AA

D_IN

AA

2AAA

55

5555

10

30

Sector Erase

Byte/Word Program

Bypass Unlock

SA⁽³⁾⁽⁴⁾

2AAA

55

5555

A0

40

Single Pulse

Byte/Word Program

1

Addr

D_IN

Sector Lockout

Erase Suspend

Erase Resume

Product ID Entry

Product ID Exit⁽²⁾

6

1

3

1

5555

xxxx

PA⁽⁵⁾

5555

xxxx

AA

B0

30

2AAA

55

5555

80

5555

AA

SA⁽³⁾⁽⁴⁾

AA

F0

2AAA

55

5555

90

F0

Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex).

The ADDRESS FORMAT in each bus cycle is as follows: A15 - A0 (Hex), A-1, A14 - A19 (Don’t Care).

2. Either one of the Product ID Exit commands can be used.

3. SA = sector address. Any byte/word address within a sector can be used to designate the sector address (see next four

pages for details).

4. When the sector programming lockout feature is not enabled, the sector will erase (from the same sector erase command).

Once the sector has been protected, data in the protected sectors cannot be changed unless the RESET pin is taken to

12V ± 0.5V.

5. PA is the plane address (A19 - A18).

Absolute Maximum Ratings*

*NOTICE:

Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect device

reliability.

Temperature Under Bias................................ -55°C to +125°C

Storage Temperature..................................... -65°C to +150°C

All Input Voltages

(including NC Pins)

with Respect to Ground...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground.............................-0.6V to V_CC+ 0.6V

Voltage on OE

with Respect to Ground...................................-0.6V to +13.5V

AT49BV16X4(T)

6

AT49BV16X4(T)

Memory Plane A - Bottom Boot

x8

x16

Sector

SA0

Size (Bytes/Words)

8K/4K

Address Range (A19 - A-1)

Address Range (A19 - A0)

000000 - 001FFF

002000 - 003FFF

004000 - 005FFF

006000 - 007FFF

008000 - 009FFF

00A000 - 00BFFF

00C000 - 00DFFF

00E000 - 00FFFF

010000 - 017FFF

018000 - 01FFFF

020000 - 02FFFF

030000 - 03FFFF

040000 - 04FFFF

050000 - 05FFFF

060000 - 06FFFF

070000 - 07FFFF

00000 - 00FFF

01000 - 01FFF

02000 - 02FFF

03000 - 03FFF

04000 - 04FFF

05000 - 05FFF

06000 - 06FFF

07000 - 07FFF

08000 - 0BFFF

0C000 - 0FFFF

10000 - 17FFF

18000 - 1FFFF

20000 - 27FFF

28000 - 2FFFF

30000 - 37FFF

38000 - 3FFFF

SA1

8K/4K

SA2

8K/4K

SA3

8K/4K

SA4

8K/4K

SA5

8K/4K

SA6

8K/4K

SA7

8K/4K

SA8

32K/16K

64K/32K

SA9

SA10

SA11

SA12

SA13

SA14

SA15

7

Memory Plane B - Bottom Boot

x8

x16

Sector

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA39

Size (Bytes/Words)

64K/32K

Address Range (A19 - A-1)

Address Range (A19 - A0)

080000 - 08FFFF

090000 - 09FFFF

0A0000 - 0AFFFF

0B0000 - 0BFFFF

0C0000 - 0CFFFF

0D0000 - 0DFFFF

0E0000 - 0EFFFF

0F0000 - 0FFFFF

100000 - 10FFFF

110000 - 11FFFF

120000 - 12FFFF

130000 - 13FFFF

140000 - 14FFFF

150000 - 15FFFF

160000 - 16FFFF

170000 - 17FFFF

180000 - 18FFFF

190000 - 19FFFF

1A0000 - 1AFFFF

1B0000 - 1BFFFF

1C0000 - 1CFFFF

1D0000 - 1DFFFF

1E0000 - 1EFFFF

1F0000 - 1FFFFF

40000 - 47FFF

48000 - 4FFFF

50000 - 57FFF

58000 - 5FFFF

60000 - 67FFF

68000 - 6FFFF

70000 - 77FFF

78000 - 7FFFF

80000 - 87FFF

88000 - 8FFFF

90000 - 97FFF

98000 - 9FFFF

A0000 - A7FFF

A8000 - AFFFF

B0000 - B7FFF

B8000 - BFFFF

C0000 - C7FFF

C8000 - CFFFF

D0000 - D7FFF

D8000 - DFFFF

E0000 - E7FFF

E8000 - EFFFF

F0000 - F7FFF

F8000 - FFFFF

AT49BV16X4(T)

8

AT49BV16X4(T)

Memory Plane B - Top Boot

x8

x16

Sector

SA0

Size (Bytes/Words)

64K/32K

Address Range (A19 - A-1)

Address Range (A19 - A0)

000000 - 00FFFF

010000 - 01FFFF

020000 - 02FFFF

030000 - 03FFFF

040000 - 04FFFF

050000 - 05FFFF

060000 - 06FFFF

070000 - 07FFFF

080000 - 08FFFF

090000 - 09FFFF

0A0000 - 0AFFFF

0B0000 - 0BFFFF

0C0000 - 0CFFFF

0D0000 - 0DFFFF

0E0000 - 0EFFFF

0F0000 - 0FFFFF

100000 - 10FFFF

110000 - 11FFFF

120000 - 12FFFF

130000 - 13FFFF

140000 - 14FFFF

150000 - 15FFFF

160000 - 16FFFF

170000 - 17FFFF

00000 - 07FFF

08000 - 0FFFF

10000 - 17FFF

18000 - 1FFFF

20000 - 27FFF

28000 - 2FFFF

30000 - 37FFF

38000 - 3FFFF

40000 - 47FFF

48000 - 4FFFF

50000 - 57FFF

58000 - 5FFFF

60000 - 67FFF

68000 - 6FFFF

70000 - 77FFF

78000 - 7FFFF

80000 - 87FFF

88000 - 8FFFF

90000 - 97FFF

98000 - 9FFFF

A0000 - A7FFF

A8000 - AFFFF

B0000 - B7FFF

B8000 - BFFFF

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

9

Memory Plane A - Top Boot

x8

x16

Sector

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA39

Size (Bytes/Words)

64K/32K

32K/16K

8K/4K

Address Range (A19 - A-1)

Address Range (A19 - A0)

180000 - 18FFFF

190000 - 19FFFF

1A0000 - 1AFFFF

1B0000 - 1BFFFF

1C0000 - 1CFFFF

1D0000 - 1DFFFF

1E0000 - 1E7FFF

1E8000 - 1EFFFF

1F0000 - 1F1FFF

1F2000 - 1F3FFF

1F4000 - 1F5FFF

1F6000 - 1F7FFF

1F8000 - 1F9FFF

1FA000 - 1FBFFF

1FC000 - 1FDFFF

1FE000 - 1FFFFF

C0000 - C7FFF

C8000 - CFFFF

D0000 - D7FFF

D8000 - DFFFF

E0000 - E7FFF

E8000 - EFFFF

F0000 - F3FFF

F4000 - F7FFF

F8000 - F8FFF

F9000 - F9FFF

FA000 - FAFFF

FB000 - FBFFF

FC000 - FCFFF

FD000 - FDFFF

FE000 - FEFFF

FF000 - FFFFF

8K/4K

AT49BV16X4(T)

10

AT49BV16X4(T)

DC and AC Operating Range

AT49BV16X4-90

AT49BV16X4-12

0°C - 70°C

Com.

Ind.

0°C - 70°C

-40°C - 85°C

2.7V to 3.6V

Operating

Temperature (Case)

-40°C - 85°C

2.7V to 3.6V

V_CCPower Supply

Operating Modes

(6)

Mode

CE

OE

WE

RESET

V_PP

Ai

I/O

D_OUT

Read

V_IL

V_IH

X

Ai

Program/

Erase⁽²⁾

V_IL

V_IH

V_IL

X

V_IH

5V ± 10%

Ai

X

D_IN

Standby/Program

Inhibit

X⁽¹⁾

X

High Z

Program Inhibit

Output Disable

Reset

X

V_IL

V_IH

X

V_IH

X

V_IH

V_IL

X

High Z

X

Product Identification

(3)

A1 - A19 = V_IL, A9 = V_H

A0 = V_IL

Manufacturer Code⁽⁴⁾

Device Code⁽⁴⁾

Hardware

V_IL

V_IH

A1 - A19 = V_IL, A9 = V_H

A0 = V_IH

A0 = V_IL, A1 - A19 = V_IL

A0 = V_IH, A1 - A19 = V_IL

Manufacturer Code⁽⁴⁾

Device Code⁽⁴⁾

Software⁽⁵⁾

V_IH

Notes: 1. X can be V_ILor V_IH.

2. Refer to AC Programming Waveforms.

3. V_H= 12.0V ± 0.5V.

4. Manufacturer Code: 1FH (x8); 161F (x16), Device Code: C0H (x8); 16CO (x16).

5. See details under Software Product Identification Entry/Exit.

6. The use of the V_PPpin is optional.

DC Characteristics

Symbol

Parameter

Condition

Min

Max

10

1

Units

I_LI

Input Load Current

V_IN= 0V to V_CC

µA

mA

V

I_LO

Output Leakage Current

V_CCStandby Current CMOS

V_CCStandby Current TTL

V_CCActive Current

V_I/O= 0V to V_CC

I_SB1

CE = V_CC- 0.3V to V_CC

CE = 2.0V to V_CC

f = 5 MHz; I_OUT= 0 mA

I_SB2

(1)

I_CC

25

50

0.8

I_CCRW

V_IL

V_CCRead While Write Current

Input Low Voltage

V_IH

Input High Voltage

2.0

2.4

V

V_OL

V_OH

Output Low Voltage

I_OL= 2.1 mA

0.45

V

Output High Voltage

I_OH= -400 µA

V

Note:

1. In the erase mode, I_CCis 50 mA.

11

AC Read Characteristics

AT49BV16X4-90

AT49BV16X4-12

Symbol

Parameter

Min

Max

90

Min

Max

120

50

Units

ns

t_ACC

Address to Output Delay

CE to Output Delay

(1)

t_CE

90

ns

(2)

t_OE

OE to Output Delay

0

40

0

ns

(3)(4)

t_DF

CE or OE to Output Float

Output Hold from OE, CE or Address, whichever occurred first

RESET to Output Delay

25

30

ns

t_OH

t_RO

ns

800

ns

AC Read Waveforms^(1)(2)(3)(4)

ADDRESS

ADDRESS VALID

CE

tCE

tOE

OE

tDF

tOH

tACC

tRO

RESET

HIGH Z

OUTPUT

VALID

OUTPUT

Notes: 1. CE may be delayed up to t_ACC- t_CEafter the address transition without impact on t_ACC

2. OE may be delayed up to t_CE- t_OEafter the falling edge of CE without impact on t_CEor by t_ACC- t_OEafter an address change

without impact on t_ACC

.

3. t_DFis specified from OE or CE whichever occurs first (CL = 5 pF).

4. This parameter is characterized and is not 100% tested.

Input Test Waveforms and

Measurement Level

Output Test Load

t_R, t_F< 5 ns

Pin Capacitance

f = 1 MHz, T = 25°C⁽¹⁾

Typ

Max

6

Units

pF

Conditions

V_IN= 0V

C_IN

4

8

C_OUT

Note:

12

pF

V_OUT= 0V

1. This parameter is characterized and is not 100% tested.

AT49BV16X4(T)

12

AT49BV16X4(T)

AC Byte/Word Load Characteristics

Symbol

Parameter

Min

10

Max

Units

ns

t

_AS, t_OES

Address, OE Set-up Time

Address Hold Time

t_AH

t_CS

t_CH

t_WP

t_DS

100

0

ns

Chip Select Set-up Time

Chip Select Hold Time

Write Pulse Width (WE or CE)

Data Set-up Time

ns

0

ns

100

10

ns

t

_DH, t_OEH

Data, OE Hold Time

Write Pulse Width High

ns

t_WPH

50

ns

AC Byte/Word Load Waveforms

WE Controlled

CE Controlled

13

Program Cycle Characteristics

Symbol

Parameter

Min

Typ

Max

Units

µs

t_BP

Byte/Word Programming Time

Address Set-up Time

Address Hold Time

Data Set-up Time

20

50

t_AS

0

ns

t_AH

100

0

ns

t_DS

ns

t_DH

Data Hold Time

ns

t_WP

Write Pulse Width

100

50

ns

t_WPH

t_EC

Write Pulse Width High

Chip Erase Cycle Time

Sector Erase Cycle Time

ns

10

seconds

ms

t_SEC

200

Program Cycle Waveforms

PROGRAM CYCLE

OE

CE

t

WP

BP

WPH

WE

t

AS

AH

DH

5555

2AAA

ADDRESS

A0 -A19

DATA

t

DS

INPUT

DATA

55

A0

AA

Sector or Chip Erase Cycle Waveforms

(1)

OE

CE

t

WP

WPH

WE

A0-A19

DATA

t

DH

AS

AH

5555

Note 2

2AAA

t

EC

DS

55

WORD 1

80

55

WORD 4

Note 3

WORD 5

AA

WORD 0

AA

WORD 3

WORD 2

Notes: 1. OE must be high only when WE and CE are both low.

2. For chip erase, the address should be 5555. For sector erase, the address depends on what sector is to be erased. (See

note 3 under command definitions.)

3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.

AT49BV16X4(T)

14

AT49BV16X4(T)

Data Polling Characteristics⁽¹⁾

Symbol

Parameter

Min

10

Typ

Max

Units

ns

t_DH

Data Hold Time

t_OEH

t_OE

OE Hold Time

10

ns

OE to Output Delay⁽²⁾

Write Recovery Time

ns

t_WR

0

ns

Notes: 1. These parameters are characterized and not 100% tested.

2. See t_OEspec in AC Read Characteristics.

Data Polling Waveforms

Toggle Bit Characteristics⁽¹⁾

Symbol

t_DH

Parameter

Min

10

Typ

Max

Units

ns

Data Hold Time

OE Hold Time

t_OEH

t_OE

t_OEHP

t_WR

10

ns

OE to Output Delay⁽²⁾

ns

OE High Pulse

150

0

ns

Write Recovery Time

ns

Notes: 1. These parameters are characterized and not 100% tested.

2. See t_OEspec in AC Read Characteristics.

Toggle Bit Waveforms^(1)(2)(3)

Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.

The t_OEHPspecification must be met by the toggling input(s).

2. Beginning and ending state of I/O6 will vary.

3. Any address location may be used but the address should not vary.

15

Status Bit Table

Status Bit

I/O 6

I/O 7

I/O 2

Read Address In

While

Plane A

Plane B

Plane A

Plane B

Plane A

Plane B

Programming in Plane A

Programming in Plane B

I/O7

DATA

I/O7

TOGGLE

DATA

1

DATA

1

DATA

TOGGLE

DATA

Erasing in Plane A

Erasing in Plane B

0

DATA

0

TOGGLE

DATA

TOGGLE

DATA

TOGGLE

Erase Suspended & Read

Erasing Sector

1

TOGGLE

DATA

TOGGLE

DATA

Erase Suspended & Read

Non-Erasing Sector

DATA

Erase Suspended &

Program Erasing Sector

1

TOGGLE

DATA

Erase Suspended &

Program Non-Erasing

Sector in Plane A

I/O7

DATA

TOGGLE

DATA

Erase Suspended &

Program Non-Erasing

Sector in Plane B

DATA

I/O7

DATA

TOGGLE

DATA

TOGGLE

AT49BV16X4(T)

16

AT49BV16X4(T)

Ordering Information

I_CC(mA)

t_ACC

(ns)

Active

Standby

Ordering Code

Package

Operation Range

90

25

0.01

AT49BV1604-90TC

AT49BV1604-90UC

48T

48U

Commercial

(0° to 70°C)

AT49BV1614-90CC

AT49BV1614-90TC

48C2

48T

25

0.01

AT49BV1604-90TI

AT49BV1604-90UI

48T

48U

Industrial

(-40° to 85°C)

AT49BV1614-90CI

AT49BV1614-90TI

48C2

48T

120

AT49BV1604-12TC

AT49BV1604-12UC

48T

48U

Commercial

(0° to 70°C)

AT49BV1614-12CC

AT49BV1614-12TC

48C2

48T

AT49BV1604-12TI

AT49BV1604-12UI

48T

48U

Industrial

(-40° to 85°C)

AT49BV1614-12CI

AT49BV1614-12TI

48C2

48T

90

AT49BV1604T-90TC

AT49BV1604T-90UC

48T

48U

Commercial

(0° to 70°C)

AT49BV1614T-90CC

AT49BV1614T-90TC

48C2

48T

AT49BV1604T-90TI

AT49BV1604T-90UI

48T

48U

Industrial

(-40° to 85°C)

AT49BV1614T-90CI

AT49BV1614T-90TI

48C2

48T

120

AT49BV1604T-12TC

AT49BV1604T-12UC

48T

48U

Commercial

(0° to 70°C)

AT49BV1614T-12CC

AT49BV1614T-12TC

48C2

48T

AT49BV1604T-12TI

AT49BV1604T-12UI

48T

48U

Industrial

(-40° to 85°C)

AT49BV1614T-12CI

AT49BV1614T-12TI

48C2

48T

Package Type

48C2

48T

48-Ball, Plastic Chip-Size Ball Grid Array Package (CBGA)

48-Lead, Thin Small Outline Package (TSOP)

48U

48-Ball, Micro Ball Grid Array Package (µBGA)

17

Packaging Information

48C2, 48-Ball, Plastic Chip-size Ball Grid Array

Package (CBGA)

48T, 48-Lead, Plastic Thin Small Outline Package

(TSOP) Dimensions in Millimeters and (Inches)*

JEDEC OUTLINE MO-142 DD

8.2

7.8

4.0

6

5

4

3

2

1

A

B

C

D

E

F

11.2

10.8

5.6

G

H

0.85

0.75

TYP

0.40 DIA TYP

0.35

1.2 MAX

NON-ACCUMULATIVE

*Controlling dimension: millimeters

48U, 48-Ball, Micro Ball Grid Array Package (µBGA)

6.8

6.4

3.75

F

E

D

C

B

A

1

2

3

4

5

6

7

8

8.4

8.0

5.25

0.75 TYP

0.30 DIA TYP

0.15 MIN.

0.70

1.00

0.85

NON-ACCUMULATIVE

AT49BV16X4(T)

18


型号：	AT49BV1604T-90TI
厂家：	ATMEL
描述：	16-Megabit 1M x 16/2M x 8 3-volt Only Flash Memory 16兆位1M ×16 / 2M ×8 3伏只快闪记忆体
文件：	总18页 (文件大小：217K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AT49BV1604T-90TI [ATMEL]

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