AT88SC1616C-PU [ATMEL]
CryptoMemory 16 Kbit; CryptoMemory 16千位
| 型号： | AT88SC1616C-PU |
| 厂家： | 
ATMEL |
| 描述： | CryptoMemory 16 Kbit |
| 文件： | 总20页 (文件大小：405K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• One of a Family of 9 Devices with User Memories from 1 Kbit to 256-Kbit
• 16-Kbit (2-Kbyte) EEPROM User Memory
– Sixteen 128-byte (1-Kbit) Zones
– Self-timed Write Cycle
– Single Byte or 16-byte Page Write Mode
– Programmable Access Rights for Each Zone
• 2-Kbit Configuration Zone
– 37-byte OTP Area for User-defined Codes
– 160-byte Area for User-defined Keys and Passwords
• High Security Features
CryptoMemory
16 Kbit
– 64-bit Mutual Authentication Protocol (Under License of ELVA)
– Encrypted Checksum
– Stream Encryption
– Four Key Sets for Authentication and Encryption
– Eight Sets of Two 24-bit Passwords
– Anti-tearing Function
AT88SC1616C
Summary
– Voltage and Frequency Monitor
• Smart Card Features
– ISO 7816 Class A (5V) or Class B (3V) Operation
– ISO 7816-3 Asynchronous T = 0 Protocol (Gemplus® Patent)
– Multiple Zones, Key Sets and Passwords for Multi-application Use
– Synchronous 2-wire Serial Interface for Faster Device Initialization
– Programmable 8-byte Answer-To-Reset Register
– ISO 7816-2 Compliant Modules
• Embedded Application Features
– Low Voltage Operation: 2.7V to 5.5V
– Secure Nonvolatile Storage for Sensitive System or User Information
– 2-wire Serial Interface
– 1.0 MHz Compatibility for Fast Operation
– Standard 8-lead Plastic Packages
– Same Pinout as 2-wire Serial EEPROMs
• High Reliability
– Endurance: 100,000 Cycles
– Data Retention: 10 years
– ESD Protection: 4,000V min
Table 1. Pin Configuration
Pad
Description
ISO Module Contact
Standard Package Pin
VCC
Supply Voltage
Ground
C1
C5
C3
C7
C2
8
4
GND
SCL/CLK
SDA/IO
RST
Serial Clock Input
Serial Data Input/Output
Reset Input
6
5
NC
Rev. 2030IS–SMIC–04/07
Note: This is a summary document. A complete document is
available under NDA. For more information, please contact your
local Atmel sales office.
Figure 1. Package Options
Smart Card Module
8-lead SOIC, PDIP
VCC = C1
RST = C2
C5 = GND
C6 = NC
NC
NC
1
2
3
4
8
7
6
5
VCC
NC
SCL/CLK = C3
NC = C4
C7 = SDA/IO
C8 = NC
NC
SCL
SDA
GND
Description
The AT88SC1616C member of the CryptoMemory® family is a high-performance secure
memory providing 16 Kbits of user memory with advanced security and cryptographic
features built in. The user memory is divided into 16 128-byte zones, each of which may
be individually set with different security access rights or effectively combined together
to provide space for 1 to 16 data files.
Smart Card Applications The AT88SC1616C provides high security, low cost, and ease of implementation with-
out the need for a microprocessor operating system. The embedded cryptographic
engine provides for dynamic and symmetric mutual authentication between the device
and host, as well as performing stream encryption for all data and passwords
exchanged between the device and host. Up to four unique key sets may be used for
these operations. The AT88SC1616C offers the ability to communicate with virtually any
smart card reader using the asynchronous T = 0 protocol (Gemplus patent) defined in
ISO 7816-3.
Embedded Applications
Through dynamic and symmetric mutual authentication, data encryption, and the use of
encrypted checksums, the AT88SC1616C provides a secure place for storage of sensi-
tive information within a system. With its tamper detection circuits, this information
remains safe even under attack. A 2-wire serial interface running at 1.0 MHz is used for
fast and efficient communications with up to 15 devices that may be individually
addressed. The AT88SC1616C is available in industry standard 8-lead packages with
the same familiar pinout as 2-wire serial EEPROMs.
Figure 2. Block Diagram
Authentication,
Encryption and
Certification Unit
VCC
GND
Random
Generator
Power
Management
Synchronous
Interface
Data Transfer
SCL/CLK
SDA/IO
Password
Verification
Asynchronous
ISO Interface
EEPROM
RST
Reset Block
Answer to Reset
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AT88SC1616C
2030IS–SMIC–04/07
AT88SC1616C
Pin Descriptions
Supply Voltage (VCC
Clock (SCL/CLK)
)
The VCC input is a 2.7V to 5.5V positive voltage supplied by the host.
In the asynchronous T = 0 protocol, the SCL/CLK input is used to provide the device
with a carrier frequency f. The nominal length of one bit emitted on I/O is defined as an
“elementary time unit” (ETU) and is equal to 372/f. When the synchronous protocol is
used, the SCL/CLK input is used to positive edge clock data into the device and nega-
tive edge clock data out of the device.
Reset (RST)
The AT88SC1616C provides an ISO 7816-3 compliant asynchronous answer to reset
sequence. When the reset sequence is activated, the device will output the data pro-
grammed into the 64-bit answer-to-reset register. An internal pull-up on the RST input
pad allows the device to be used in synchronous mode without bonding RST. The
AT88SC1616C does not support the synchronous answer-to-reset sequence.
Serial Data (SDA/IO)
The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and
may be wired with any number of other open drain or open collector devices. An exter-
nal pull-up resistor should be connected between SDA and VCC. The value of this
resistor and the system capacitance loading the SDA bus will determine the rise time of
SDA. This rise time will determine the maximum frequency during read operations. Low
value pull-up resistors will allow higher frequency operations while drawing higher aver-
age power. SDA/IO information applies to both asynchronous and synchronous
protocols.
When the synchronous protocol is used, the SCL/CLK input is used to positive edge
clock data into the device and negative edge clock data out of the device.
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2030IS–SMIC–04/07
Table 2. DC Characteristics
Applicable over recommended operating range from VCC = +2.7 to 5.5V, TAC = -40oC to +85oC (unless otherwise noted)
Symbol
Parameter
Test Condition
Min
2.7
Typ
Max
5.5
Units
VCC
Supply Voltage
V
ICC
ICC
ICC
ICC
ISB
VIL
VIL
VIL
VIH
VIH
VIH
IIL
Supply Current (VCC = 5.5V)
Supply Current (VCC = 5.5V)
Supply Current (VCC = 5.5V)
Supply Current (VCC = 5.5V)
Standby Current (VCC = 5.5V)
SDA/IO Input Low Threshold(1)
SCL/CLK Input Low Threshold(1)
RST Input Low Threshold(1)
SDA/IO Input High Threshold(1)
SCL/CLK Input High Threshold(1)
RST Input High Threshold(1)
SDA/IO Input Low Current
SCL/CLK Input Low Current
RST Input Low Current
Async READ at 3.57MHz
Async WRITE at 3.57MHz
Synch READ at 1MHz
Synch WRITE at 1MHz
VIN = VCC or GND
5
mA
mA
mA
mA
uA
V
5
5
5
100
0
VCC x 0.2
VCC x 0.2
VCC x 0.2
VCC
0
V
0
V
VCC x 0.7
VCC x 0.7
VCC x 0.7
V
VCC
V
VCC
V
0 < VIL < VCC x 0.15
0 < VIL < VCC x 0.15
0 < VIL < VCC x 0.15
VCC x 0.7 < VIH < VCC
VCC x 0.7 < VIH < VCC
VCC x 0.7 < VIH < VCC
20K ohm external pull-up
IOL = 1mA
15
uA
uA
uA
uA
uA
uA
V
IIL
15
IIL
50
IIH
SDA/IO Input High Current
SCL/CLK Input High Current
RST Input High Current
20
IIH
100
IIH
150
VOH
VOL
IOH
SDA/IO Output High Voltage
SDA/IO Output Low Voltage
SDA/IO Output High Current
VCC x 0.7
0
VCC
VCC x 0.15
20
V
VOH
uA
Note:
1. VIL min and VIH max are reference only and are not tested.
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AT88SC1616C
2030IS–SMIC–04/07
AT88SC1616C
Table 3. AC Characteristics
Applicable over recommended operating range from VCC = +2.7 to 5.5V,
TAC = -40oC to +85oC, CL = 30pF (unless otherwise noted)
Symbol
Parameter
Min
Max
Units
fCLK
Async Clock Frequency (VCC Range: +4.5 - 5.5V)
1
1
5
4
MHz
MHz
MHz
%
fCLK
fCLK
Async Clock Frequency (VCC Range: +2.7 - 3.3V)
Synch Clock Frequency
Clock Duty cycle
0
1
40
60
1
tR
tF
Rise Time - I/O, RST
Fall Time - I/O, RST
Rise Time - CLK
uS
1
uS
tR
9% x period
9% x period
35
uS
tF
Fall Time - CLK
uS
tAA
Clock Low to Data Out Valid
Start Hold Time
nS
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tSU.STO
tDH
200
200
10
nS
Start Set-up Time
nS
Data In Hold Time
nS
Data In Set-up Time
Stop Set-up Time
100
200
20
nS
nS
Data Out Hold Time
Write Cycle Time (at 25°C)
Write Cycle Time
nS
tWR
5
7
mS
mS
tWR
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2030IS–SMIC–04/07
Device Operation For CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-
nal device. Data on the SDA pin may change only during SCL low time periods (see
Figure 5 on page 7). Data changes during SCL high periods will indicate a start or stop
condition as defined below.
Synchronous
Protocols
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition
which must precede any other command (see Figure 6 on page 7).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command will place the EEPROM in a standby power
mode (see Figure 6 on page 7).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has
received each word. This happens during the ninth clock cycle.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-
wire part can be reset by following these steps:
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition.
Figure 3. Bus Timing for 2 wire communications
SCL: Serial Clock, SDA: Serial Data I/O
Figure 4. Write Cycle Timing:
SCL: Serial Clock, SDA: Serial Data I/O
SCL
SDA
ACK
8th BIT
WORDn
(1)
tWR
START
STOP
CONDITION
CONDITION
Note:
The write cycle time tWR is the time from a valid stop condition of a write sequence to the
end of the internal clear/write cycle.
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AT88SC1616C
2030IS–SMIC–04/07
AT88SC1616C
Figure 5. Data Validity
Figure 6. Start and Stop Definitions
Figure 7. Output Acknowledge
7
2030IS–SMIC–04/07
Device Architecture
User Zones
The EEPROM user memory is divided into 16 zones of 1024 bits each. Multiple zones
allow for different types of data or files to be stored in different zones. Access to the user
zones is allowed only after security requirements have been met. These security
requirements are defined by the user during the personalization of the device in the con-
figuration memory. If the same security requirements are selected for multiple zones,
then these zones may effectively be accessed as one larger zone.
Figure 8. User Zone
ZONE
$0
$1
$2
$3
$4
$5
$6
$7
$00
-
-
128 Bytes
User 0
$78
$00
-
User 1
-
-
-
-
User 14
$78
$00
-
128 Bytes
User 15
-
$78
Control Logic
Access to the user zones occurs only through the control logic built into the device. This
logic is configurable through access registers, key registers and keys programmed into
the configuration memory during device personalization. Also implemented in the con-
trol logic is a cryptographic engine for performing the various higher-level security
functions of the device.
Configuration Memory
The configuration memory consists of 2048 bits of EEPROM memory used for storing
passwords, keys and codes and for defining security levels to be used for each user
zone. Access rights to the configuration memory are defined in the control logic and may
not be altered by the user.
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AT88SC1616C
2030IS–SMIC–04/07
AT88SC1616C
Figure 9. Configuration Memory
$0
$1
$2
$3
$4
$5
$6
$7
$00
$08
$10
$18
$20
$28
$30
$38
$40
$48
$50
$58
$60
$68
$70
$78
$80
$88
$90
$98
$A0
$A8
$B0
$B8
$C0
$C8
$D0
$D8
$E0
$E8
$F0
$F8
Answer To Reset
Identification
Read Only
Fab Code
MTZ
Card Manufacturer Code
Lot History Code
DCR
AR0
AR4
AR8
AR12
Identification Number Nc
AR2 PR2
AR6 PR6
PR0
PR4
AR1
AR5
PR1
PR5
AR3
AR7
PR3
PR7
PR8
AR9
PR9
AR10
AR14
PR10
PR14
AR11
AR15
PR11
PR15
Access Control
PR12
AR13
PR13
Issuer Code
For Authentication and Encryption use
Cryptography
For Authentication and Encryption use
Secret
PAC
PAC
PAC
PAC
PAC
PAC
PAC
PAC
Write 0
Write 1
Write 2
Write 3
Write 4
Write 5
Write 6
Write 7
PAC
PAC
PAC
PAC
PAC
PAC
PAC
PAC
Read 0
Read 1
Read 2
Read 3
Read 4
Read 5
Read 6
Read 7
Password
Forbidden
Reserved
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2030IS–SMIC–04/07
Security Fuses
There are three fuses on the device that must be blown during the device personaliza-
tion process. Each fuse locks certain portions of the configuration memory as OTP
memory. Fuses are designed for the module manufacturer, card manufacturer and card
issuer and should be blown in sequence, although all programming of the device and
blowing of the fuses may be performed at one final step.
Protocol Selection
The AT88SC1616C supports two different communication protocols.
•
Smart Card Applications: The asynchronous T = 0 protocol defined by ISO 7816-3
is used for compatibility with the industry’s standard smart card readers.
•
Embedded Applications: A 2-wire serial interface is used for fast and efficient
communication with logic or controllers.
The power-up sequence determines which of the two communication protocols will be
used.
Asynchronous
T = 0 Protocol
This power-up sequence complies with ISO 7816-3 for a cold reset in smart card
applications.
•
•
•
•
VCC goes high; RST, I/O-SDA and CLK-SCL are low.
Set I/O-SDA in receive mode.
Provide a clock signal to CLK-SCL.
RST goes high after 400 clock cycles.
The device will respond with a 64-bit ATR code, including historical bytes to indicate the
memory density within the CryptoMemory family. Once the asynchronous mode has
been selected, it is not possible to switch to the synchronous mode without powering off
the device.
Figure 10. Asynchronous T = 0 Protocol (Gemplus Patent)
V
cc
ATR
I/O-SDA
RST
CLK-SCL
Synchronous
2-wire Serial Interface
The synchronous mode is the default after powering up VCC due to an internal pull-up on
RST. For embedded applications using CryptoMemory in standard plastic packages,
this is the only communication protocol.
•
•
Power-up VCC, RST goes high also.
After stable VCC, CLK-SCL and I/O-SDA may be driven.
10
AT88SC1616C
2030IS–SMIC–04/07
AT88SC1616C
Figure 11. Synchronous 2-wire Protocol
V
cc
-SDA
RST
1
2
4
5
3
-SCL
Note:
Five clock pulses must be sent before the first command is issued.
Communication Security Modes
Communications between the device and host operate in three basic modes. Standard
mode is the default mode for the device after power-up. Authentication mode is acti-
vated by a successful authentication sequence. Encryption mode is activated by a
successful encryption activation following a successful authentication.
Table 4. Communication Security Modes(1)
Mode
Configuration Data
User Data
Clear
Passwords
Clear
Data Integrity Check
MDC(1)
Standard
Clear
Clear
Clear
Authentication
Encryption
Clear
Encrypted
Encrypted
MAC(1)
Encrypted
MAC(1)
Note:
1. Configuration data include viewable areas of the Configuration Zone except the passwords:
MDC: Modification Detection Code
MAC: Message Authentication Code.
Security Options
Anti-tearing
In the event of a power loss during a write cycle, the integrity of the device’s stored data
may be recovered. This function is optional: the host may choose to activate the anti-
tearing function, depending on application requirements. When anti-tearing is active,
write commands take longer to execute, since more write cycles are required to com-
plete them, and data are limited to eight bytes.
Data are written first to a buffer zone in EEPROM instead of the intended destination
address, but with the same access conditions. The data are then written in the required
location. If this second write cycle is interrupted due to a power loss, the device will
automatically recover the data from the system buffer zone at the next power-up.
In 2-wire mode, the host is required to perform ACK polling for up to 8 ms after write
commands when anti-tearing is active. At power-up, the host is required to perform ACK
polling, in some cases for up to 2 ms, in the event that the device needs to carry out the
data recovery process.
Write Lock
If a user zone is configured in the write lock mode, the lowest address byte of an 8-byte
page constitutes a write access byte for the bytes of that page.
Example: The write lock byte at $080 controls the bytes from $080 to $087.
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2030IS–SMIC–04/07
Figure 12. Write Lock Example
Address
$080
$0
$1
$2
$3
$4
$5
$6
$7
11011001
xxxx xxxx
locked
xxxx xxxx
locked
xxxx xxxx
xxxx xxxx
xxxx xxxx
locked
xxxx xxxx
xxxx xxxx
The write lock byte may also be locked by writing its least significant (rightmost) bit to
“0”. Moreover, when write lock mode is activated, the write lock byte can only be pro-
grammed – that is, bits written to “0” cannot return to “1”.
In the write lock configuration, only one byte can be written at a time. Even if several
bytes are received, only the first byte will be taken into account by the device.
Password Verification
Passwords may be used to protect read and/or write access of any user zone. When a
valid password is presented, it is memorized and active until power is turned off, unless
a new password is presented or RST becomes active. There are eight password sets
that may be used to protect any user zone. Only one password is active at a time, but
write passwords give read access also.
Authentication Protocol
The access to a user zone may be protected by an authentication protocol. Any one of
four keys may be selected to use with a user zone.
The authentication success is memorized and active as long as the chip is powered,
unless a new authentication is initialized or RST becomes active. If the new authentica-
tion request is not validated, the card loses its previous authentication and it should be
presented again. Only the last request is memorized.
Note:
Password and authentication may be presented at any time and in any order. If the trials
limit has been reached (after four consecutive incorrect attempts), the password verifica-
tion or authentication process will not be taken into account.
12
AT88SC1616C
2030IS–SMIC–04/07
AT88SC1616C
Figure 13. Password and Authentication Operations
VERIFY RPW
DATA
Checksum (CS)
VERIFY CS
CS
VERIFY CS
Write DATA
Checksum
The AT88SC1616C implements a data validity check function in the form of a check-
sum, which may function in standard, authentication or encryption modes.
In the standard mode, the checksum is implemented as a Modification Detection Code
(MDC), in which the host may read an MDC from the device in order to verify that the
data sent was received correctly.
In the authentication and encryption modes, the checksum becomes more powerful
since it provides a bidirectional data integrity check and data origin authentication capa-
bility in the form of a Message Authentication Code (MAC). Only the host/device that
carried out a valid authentication is capable of computing a valid MAC. While operating
in the authentication or encryption modes, the use of a MAC is required. For an ingoing
command, if the device calculates a MAC different from the MAC transmitted by the
host, not only is the command abandoned but the mode is also reset. A new authentica-
tion and/or encryption activation will be required to reactivate the MAC.
Encryption
The data exchanged between the device and the host during read, write and verify
password commands may be encrypted to ensure data confidentiality.
The issuer may choose to require encryption for a user zone by settings made in the
configuration memory. Any one of four keys may be selected for use with a user zone. In
this case, activation of the encryption mode is required in order to read/write data in the
zone and only encrypted data will be transmitted. Even if not required, the host may
elect to activate encryption provided the proper keys are known.
Supervisor Mode
Modify Forbidden
Enabling this feature allows the holder of one specific password to gain full access to all
eight password sets, including the ability to change passwords.
No write access is allowed in a user zone protected with this feature at any time. The
user zone must be written during device personalization prior to blowing the security
fuses.
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2030IS–SMIC–04/07
Program Only
For a user zone protected by this feature, data within the zone may be changed from a
“1” to a “0”, but never from a “0” to a “1”.
Initial Device
Programming
To enable the security features of CryptoMemory, the device must first be personalized
to set up several registers and load in the appropriate passwords and keys. This is
accomplished through programming the configuration memory of CryptoMemory using
simple write and read commands. To gain access to the configuration memory, the
secure code must first be successfully presented. For the AT88SC1616C device, the
secure code is $20 0C E0. After writing and verifying data in the configuration memory,
the security fuses must be blown to lock this information in the device. For additional
information on personalizing CryptoMemory, please see the application notes Program-
ming CryptoMemory for Embedded Applications and Initializing CryptoMemory for
Smart Card Applications (at www.Atmel.com).
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AT88SC1616C
2030IS–SMIC–04/07
AT88SC1616C
Ordering Information
Ordering Code
Package
Voltage Range
Temperature Range
AT88SC1616C-MJ
AT88SC1616C-MP
M2 – J Module
M2 – P Module
2.7V–5.5V
Commercial (0°C–70°C)
AT88SC1616C-PU
AT88SC1616C-SU
8P3
8S1
Lead-free/Halogen-free/Industrial
2.7V–5.5V
2.7V–5.5V
(−40°C–85°C)
AT88SC1616C-WI
7 mil wafer
Industrial (−40°C–85°C)
Package Type(1)
M2 – J Module
M2 – P Module
8P3
Description
M2 ISO 7816 Smart Card Module
M2 ISO 7816 Smart Card Module with Atmel® Logo
8-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)
8S1
8-lead, 0.150” Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
1. Formal drawings may be obtained from an Atmel sales office.
Note:
15
2030IS–SMIC–04/07
Packaging Information
Ordering Code: MP
Ordering Code: MJ
Module Size: M2
Module Size: M2
Dimension*: 12.6 x 11.4 [mm]
Dimension*: 12.6 x 11.4 [mm]
Glob Top: Square - 8.8 x 8.8 [mm]
Thickness: 0.58 [mm]
Glob Top: Round - 8.5 [mm]
Thickness: 0.58 [mm]
Pitch: 14.25 mm
Pitch: 14.25 mm
*Note: The module dimensions listed refer to the dimensions of the exposed metal contact area. The actual dimensions
of the module after excise or punching from the carrier tape are generally 0.4 mm greater in both directions
(i.e., a punched M2 module will yield 13.0 x 11.8 mm).
16
AT88SC1616C
2030IS–SMIC–04/07
AT88SC1616C
Ordering Code: SU
8-lead SOIC
C
1
E
E1
L
N
Ø
TOP VVIIEEWW
END VIEW
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
MIN
1.35
0.10
MAX
1.75
0.25
NOM
NOTE
SYMBOL
A1
A
–
–
A1
b
C
D
E1
E
e
0.31
0.17
4.80
3.81
5.79
–
0.51
0.25
5.05
3.99
6.20
–
–
D
–
–
SIDE VVIIEEWW
1.27 BSC
L
0.40
0°
–
–
1.27
θ
8°
Note:
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
3/17/05
TITLE
DRAWING NO.
8S1
REV.
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
C
Small Outline (JEDEC SOIC)
R
17
2030IS–SMIC–04/07
Ordering Code: PU
8-lead PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
MIN
MAX
NOM
NOTE
SYMBOL
D1
A2 A
A
0.210
0.195
0.022
0.070
0.045
0.014
0.400
2
A2
b
0.115
0.014
0.045
0.030
0.008
0.355
0.005
0.300
0.240
0.130
0.018
0.060
0.039
0.010
0.365
5
6
6
b2
b3
c
D
3
3
4
3
b2
L
D1
E
b3
4 PLCS
0.310
0.250
0.325
0.280
b
E1
e
0.100 BSC
0.300 BSC
0.130
Side View
eA
L
4
2
0.115
0.150
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
8P3
B
R
18
AT88SC1616C
2030IS–SMIC–04/07
AT88SC1616C
Revision History
Doc. Rev.
2030IS
Date
Comments
4/13/07
1/25/07
Final release version
2030IS
Replaced User Zone, Configuration Memory, and Write
Locks Example tables with new information
2030IS
1/2007
Implemented revision history.
Removed Industrial packages 8P3, 8S1, 8Y4.
Removed 8Y4 offering from datasheet.
19
2030IS–SMIC–04/07
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