AT89S8253-24PU_技术文档

Features

• Compatible with MCS^®-51 Products

• 12K Bytes of In-System Programmable (ISP) Flash Program Memory

– SPI Serial Interface for Program Downloading

– Endurance: 10,000 Write/Erase Cycles

• 2K Bytes EEPROM Data Memory

– Endurance: 100,000 Write/Erase Cycles

• 64-byte User Signature Array

• 2.7V to 5.5V Operating Range

8-bit

• Fully Static Operation: 0 Hz to 24 MHz

• Three-level Program Memory Lock

• 256 x 8-bit Internal RAM

Microcontroller

with 12K Bytes

Flash and 2K

Bytes EEPROM

• 32 Programmable I/O Lines

• Three 16-bit Timer/Counters

• Nine Interrupt Sources

• Enhanced UART Serial Port with Framing Error Detection and Automatic

Address Recognition

• Enhanced SPI (Double Write/Read Buffered) Serial Interface

• Low-power Idle and Power-down Modes

• Interrupt Recovery from Power-down Mode

• Programmable Watchdog Timer

AT89S8253

• Dual Data Pointer

• Power-off Flag

• Flexible ISP Programming (Byte and Page Modes)

– Page Mode: 64 Bytes/Page for Code Memory, 32 Bytes/Page for Data Memory

• Four-level Enhanced Interrupt Controller

• Programmable and Fuseable x2 Clock Option

• Internal Power-on Reset

• 42-pin PDIP Package Option for Reduced EMC Emission

• Green (Pb/Halide-free) Packaging Option

1. Description

The AT89S8253 is a low-power, high-performance CMOS 8-bit microcontroller with

12K bytes of In-System Programmable (ISP) Flash program memory and 2K bytes of

EEPROM data memory. The device is manufactured using Atmel’s high-density non-

volatile memory technology and is compatible with the industry-standard MCS-51

instruction set and pinout. The on-chip downloadable Flash allows the program mem-

ory to be reprogrammed in-system through an SPI serial interface or by a

conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU

with downloadable Flash on a monolithic chip, the Atmel AT89S8253 is a powerful

microcontroller which provides a highly-flexible and cost-effective solution to many

embedded control applications.

3286H–MICRO–9/05

The AT89S8253 provides the following standard features: 12K bytes of In-System Programma-

ble Flash, 2K bytes of EEPROM, 256 bytes of RAM, 32 I/O lines, programmable watchdog timer,

two data pointers, three 16-bit timer/counters, a six-vector, four-level interrupt architecture, a full

duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S8253 is designed

with static logic for operation down to zero frequency and supports two software selectable

power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters,

serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM

contents but freezes the oscillator, disabling all other chip functions until the next external inter-

rupt or hardware reset.

The on-board Flash/EEPROM is accessible through the SPI serial interface. Holding RESET

active forces the SPI bus into a serial programming interface and allows the program memory to

be written to or read from, unless one or more lock bits have been activated.

2. Pin Configurations

2.1

40P6 – 40-lead PDIP

(T2) P1.0

(T2 EX) P1.1

P1.2

1

2

3

4

5

6

7

8

9

40 VCC

39 P0.0 (AD0)

38 P0.1 (AD1)

37 P0.2 (AD2)

36 P0.3 (AD3)

35 P0.4 (AD4)

34 P0.5 (AD5)

33 P0.6 (AD6)

32 P0.7 (AD7)

31 EA/VPP

P1.3

(SS) P1.4

(MOSI) P1.5

(MISO) P1.6

(SCK) P1.7

RST

(RXD) P3.0 10

(TXD) P3.1 11

(INT0) P3.2 12

(INT1) P3.3 13

(T0) P3.4 14

(T1) P3.5 15

(WR) P3.6 16

(RD) P3.7 17

XTAL2 18

30 ALE/PROG

29 PSEN

28 P2.7 (A15)

27 P2.6 (A14)

26 P2.5 (A13)

25 P2.4 (A12)

24 P2.3 (A11)

23 P2.2 (A10)

22 P2.1 (A9)

21 P2.0 (A8)

XTAL1 19

GND 20

2.2

44A – 44-lead TQFP

(MOSI) P1.5

1

2

3

4

5

6

7

8

9

33 P0.4 (AD4)

(MISO) P1.6

(SCK) P1.7

RST

32 P0.5 (AD5)

31 P0.6 (AD6)

30 P0.7 (AD7)

29 EA/VPP

(RXD) P3.0

NC

(TXD) P3.1

(INT0) P3.2

(INT1) P3.3

(T0) P3.4 10

(T1) P3.5 11

28 NC

27 ALE/PROG

26 PSEN

25 P2.7 (A15)

24 P2.6 (A14)

23 P2.5 (A13)

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AT89S8253

3286H–MICRO–9/05

AT89S8253

2.3

44J – 44-lead PLCC

7

8

9

(MOSI) P1.5

(MISO) P1.6

(SCK) P1.7

RST

P0.4 (AD4)

P0.5 (AD5)

P0.6 (AD6)

P0.7 (AD7)

EA/VPP

39

38

37

36

35

34

10

11

12

13

14

15

16

17

(RXD) P3.0

NC

(TXD) P3.1

(INT0) P3.2

(INT1) P3.3

(T0) P3.4

(T1) P3.5

33 ALE/PROG

32 PSEN

31

30

29

P2.7 (A15)

P2.6 (A14)

P2.5 (A13)

2.4

42PS6 – PDIP

RST

1

2

3

4

5

6

7

8

9

42 P1.7 (SCK)

41 P1.6 (MISO)

40 P1.5 (MOSI)

39 P1.4 (SS)

38 P1.3

(RXD) P3.0

(TXD) P3.1

(INT0) P3.2

(INT1) P3.3

(T0) P3.4

37 P1.2

(T1) P3.5

36 P1.1 (T2EX)

35 P1.0 (T2)

34 VDD

(WR) P3.6

(RD) P3.7

XTAL2 10

XTAL1 11

33 PWRVDD

32 P0.0 (AD0)

31 P0.1 (AD1)

30 P0.2 (AD2)

29 P0.3 (AD3)

28 P0.4 (AD4)

27 P0.5 (AD5)

26 P0.6 (AD6)

25 P0.7 (AD7)

24 EA/VPP

GND 12

PWRGND 13

(A8) P2.0 14

(A9) P2.1 15

(A10) P2.2 16

(A11) P2.3 17

(A12) P2.4 18

(A13) P2.5 19

(A14) P2.6 20

(A15) P2.7 21

23 ALE/PROG

22 PSEN

3. Pin Description

3.1

VCC

Supply voltage (all packages except 42-PDIP).

3.2

GND

Ground (all packages except 42-PDIP; for 42-PDIP GND connects only the logic core and the

embedded program/data memories).

3.3

3.4

VDD

Supply voltage for the 42-PDIP which connects only the logic core and the embedded pro-

gram/data memories.

PWRVDD

Supply voltage for the 42-PDIP which connects only the I/O Pad Drivers.

The application board must connect both VDD and PWRVDD to the board supply voltage.

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3286H–MICRO–9/05

3.5

3.6

PWRGND

Port 0

Ground for the 42-PDIP which connects only the I/O Pad Drivers. PWRGND and GND are

weakly connected through the common silicon substrate, but not through any metal links. The

application board must connect both GND and PWRGND to the board ground.

Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink six TTL

inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs.

Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses

to external program and data memory. In this mode, P0 has internal pull-ups.

Port 0 also receives the code bytes during Flash programming and outputs the code bytes dur-

ing program verification. External pull-ups are required during program verification.

3.7

Port 1

Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can

sink/source six TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the weak

internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being

pulled low will source current (I_IL,150 µA typical) because of the weak internal pull-ups.

Some Port 1 pins provide additional functions. P1.0 and P1.1 can be configured to be the

timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX),

respectively.

Furthermore, P1.4, P1.5, P1.6, and P1.7 can be configured as the SPI slave port select, data

input/output and shift clock input/output pins as shown in the following table.

Port Pin

P1.0

Alternate Functions

T2 (external count input to Timer/Counter 2), clock-out

T2EX (Timer/Counter 2 capture/reload trigger and direction control)

SS (Slave port select input)

P1.1

P1.4

P1.5

MOSI (Master data output, slave data input pin for SPI channel)

MISO (Master data input, slave data output pin for SPI channel)

SCK (Master clock output, slave clock input pin for SPI channel)

P1.6

P1.7

Port 1 also receives the low-order address bytes during Flash programming and verification.

3.8

Port 2

Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can

sink/source six TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the weak

internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being

pulled low will source current (I_IL,150 µA typical) because of the weak internal pull-ups.

Port 2 emits the high-order address byte during fetches from external program memory and dur-

ing accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this

application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external

data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2

Special Function Register.

Port 2 also receives the high-order address bits and some control signals during Flash

programming and verification.

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AT89S8253

3286H–MICRO–9/05

AT89S8253

3.9

Port 3

Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can

sink/source six TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the weak

internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being

pulled low will source current (I_IL,150 µA typical) because of the weak internal pull-ups.

Port 3 receives some control signals for Flash programming and verification.

Port 3 also serves the functions of various special features of the AT89S8253, as shown in the

following table.

Port Pin

P3.0

P3.1

P3.2

P3.3

P3.4

P3.5

P3.6

P3.7

Alternate Functions

RXD (serial input port)

TXD (serial output port)

INT0 (external interrupt 0)⁽¹⁾

INT1 (external interrupt 1)⁽¹⁾

T0 (timer 0 external input)

T1 (timer 1 external input)

WR (external data memory write strobe)

RD (external data memory read strobe)

Note:

1. All pins in ports 1 and 2 and almost all pins in port 3 (the exceptions are P3.2 INT0 and P3.3

INT1) have their weak internal pull-ups disabled in the Power-down mode. Port pins P3.2

(INT0) and P3.3 (INT1) are active even in Power-down mode (to be able to sense an

interrupt request to exit the Power-down mode) and as such still have their weak internal

pull-ups turned on.

3.10 RST

Reset input. A high on this pin for at least two machine cycles while the oscillator is running

resets the device.

3.11 ALE/PROG

Address Latch Enable. ALE/PROG is an output pulse for latching the low byte of the address (on

its falling edge) during accesses to external memory. This pin is also the program pulse input

(PROG) during Flash programming.

In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be

used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped dur-

ing each access to external data memory.

If desired, ALE operation can be disabled by setting bit 0 of the AUXR SFR at location 8EH. With

the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly

pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execu-

tion mode.

3.12 PSEN

Program Store Enable. PSEN is the read strobe to external program memory (active low).

When the AT89S8253 is executing code from external program memory, PSEN is activated

twice each machine cycle, except that two PSEN activations are skipped during each access to

external data memory.

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3286H–MICRO–9/05

3.13 EA/VPP

External Access Enable. EA must be strapped to GND in order to enable the device to fetch

code from external program memory locations starting at 0000H up to FFFFH. Note, however,

that if lock bit 1 is programmed, EA will be internally latched on reset.

EA should be strapped to V_CCfor internal program executions. This pin also receives the 12-volt

programming enable voltage (V_PP) during Flash programming when 12-volt programming is

selected.

3.14 XTAL1

3.15 XTAL2

Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

Output from the inverting oscillator amplifier.

4. Block Diagram

P0.0

-

P0.7

P2.0 - P2.7

V_CC

PORT

0

DRIVERS

PORT

2

DRIVERS

FLASH

GND

RAM ADDR.

REGISTER

PORT

0

PORT

2

RAM

EEPROM

LATCH

PROGRAM

ADDRESS

REGISTER

B

STACK

POINTER

ACC

REGISTER

BUFFER

TMP2

TMP1

PC

INCREMENTER

ALU

INTERRUPT, SERIAL PORT,

AND TIMER BLOCKS

PROGRAM

COUNTER

PSW

PSEN

ALE/PROG

TIMING

AND

CONTROL

INSTRUCTION

REGISTER

DUAL

DPTR

EA

/

V_PP

RST

WATCH

DOG

PORT

3

PORT

1

SPI

PORT

PROGRAM

LOGIC

LATCH

OSC

PORT

3 DRIVERS

PORT

1 DRIVERS

P3.0

- P3.7

P1.0

- P1.7

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AT89S8253

3286H–MICRO–9/05

AT89S8253

5. Special Function Registers

A map of the on-chip memory area called the Special Function Register (SFR) space is shown in

Table 5-1.

Note that not all of the addresses are occupied, and unoccupied addresses may not be imple-

mented on the chip. Read accesses to these addresses will generally return random data, and

write accesses will have an indeterminate effect.

User software should not write 1s to these unlisted locations, since they may be used in future

products to invoke new features. In that case, the reset or inactive values of the new bits will

always be 0.

Table 5-1.

AT89S8253 SFR Map and Reset Values

0F8H

0FFH

0F7H

0EFH

0E7H

0DFH

0D7H

0CFH

0C7H

0BFH

B

0F0H

0E8H

0E0H

0D8H

0D0H

0C8H

0C0H

0B8H

00000000

ACC

00000000

PSW

00000000

SPCR

00000100

T2CON

00000000

T2MOD

XXXXXX00

RCAP2L

00000000

RCAP2H

00000000

TL2

00000000

TH2

00000000

SADEN

IP

XX000000

00000000

IPH

P3

11111111

0B0H

0A8H

0B7H

0AFH

XX000000

SADDR

IE

SPSR

000XXX00

0X000000

00000000

WDTCON

0000 0000

P2

11111111

WDTRST

(Write Only)

0A0H

98H

90H

88H

80H

0A7H

9FH

97H

8FH

87H

SCON

00000000

SBUF

XXXXXXXX

P1

11111111

EECON

XX000011

AUXR

CLKREG

TCON

00000000

TMOD

00000000

TL0

00000000

TL1

00000000

TH0

00000000

TH1

00000000

XXXXXXX0

P0

11111111

SP

00000111

DP0L

00000000

DP0H

00000000

DP1L

00000000

DP1H

00000000

SPDR

########

PCON

00XX0000

Note:

# means: 0 after cold reset and unchanged after warm reset.

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3286H–MICRO–9/05

5.1

Auxiliary Register

The AUXR Register contains a single active bit called DISALE.

Table 5-2. AUXR – Auxiliary Register

AUXR Address = 8EH

Not Bit Addressable

Reset Value = XXXX XXX0B

–

6

–

5

–

4

–

3

–

2

Intel_Pwd_Exit

1

DISALE

0

Bit

7

Symbol

DISALE

Function

When DISALE = 0, ALE is emitted at a constant rate of 1/6 the oscillator frequency (except during MOVX when 1

ALE pulse is missing). When DISALE = 1, ALE is active only during a MOVX or MOVC instruction.

When set, this bit configures the interrupt driven exit from power-down to resume execution on the rising edge of

the interrupt signal. When this bit is cleared, the execution resumes after a self-timed interval (nominal 2 ms)

referenced from the falling edge of the interrupt signal.

Intel_Pwd_Exit

5.2

Clock Register

The CLKREG register contains a single active bit called X2.

Table 5-3. CLKREG – Clock Register

CLKREG Address = 8FH

Not Bit Addressable

Reset Value = XXXX XXX0B

–

6

–

5

–

4

–

3

–

2

–

1

X2

0

Bit

7

Symbol

Function

When X2 = 0, the oscillator frequency (at XTAL1 pin) is internally divided by 2 before it is used as the device system

frequency.

X2

When X2 = 1, the divider by 2 is no longer used and the XTAL1 frequency becomes the device system frequency. This

enables the user to choose a 6 MHz crystal instead of a 12 MHz crystal, for example, in order to reduce EMI.

5.3

SPI Registers

Control and status bits for the Serial Peripheral Interface are contained in registers SPCR (see

Table 14-1 on page 25) and SPSR (see Table 14-2 on page 26). The SPI data bits are contained

in the SPDR register. In normal SPI mode, writing the SPI data register during serial data trans-

fer sets the Write Collision bit (WCOL) in the SPSR register. In enhanced SPI mode, the SPDR

is also write double-buffered because WCOL works as a Write Buffer Full Flag instead of being a

collision flag. The values in SPDR are not changed by Reset.

5.4

Interrupt Registers

The global interrupt enable bit and the individual interrupt enable bits are in the IE register. In

addition, the individual interrupt enable bit for the SPI is in the SPCR register. Four priorities can

be set for each of the six interrupt sources in the IP and IPH registers.

IPH bits have the same functions as IP bits, except IPH has higher priority than IP. By using IPH

in conjunction with IP, a priority level of 0, 1, 2, or 3 may be set for each interrupt.

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AT89S8253

3286H–MICRO–9/05

AT89S8253

5.5

5.6

Dual Data Pointer Registers

To facilitate accessing both internal EEPROM and external data memory, two banks of 16-bit

Data Pointer Registers are provided: DP0 at SFR address locations 82H - 83H and DP1 at 84H

- 85H. Bit DPS = 0 in SFR EECON selects DP0 and DPS = 1 selects DP1. The user should

ALWAYS initialize the DPS bit to the appropriate value before accessing the respective Data

Pointer Register.

Power Off Flag

The Power Off Flag (POF), located at bit_4 (PCON.4) in the PCON SFR. POF, is set to “1” dur-

ing power up. It can be set and reset under software control and is not affected by RESET.

6. Data Memory – EEPROM and RAM

The AT89S8253 implements 2K bytes of on-chip EEPROM for data storage and 256 bytes of

RAM. The upper 128 bytes of RAM occupy a parallel space to the Special Function Registers.

That means the upper 128 bytes have the same addresses as the SFR space but are physically

separate from SFR space.

When an instruction accesses an internal location above address 7FH, the address mode used

in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR

space. Instructions that use direct addressing access the SFR space.

For example, the following direct addressing instruction accesses the SFR at location 0A0H

(which is P2).

MOV 0A0H, #data

Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the

following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at

address 0A0H, rather than P2 (whose address is 0A0H).

MOV @R0, #data

Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data

RAM are available as stack space.

The on-chip EEPROM data memory is selected by setting the EEMEN bit in the EECON register

at SFR address location 96H. The EEPROM address range is from 000H to 7FFH. MOVX

instructions are used to access the EEPROM. To access off-chip data memory with the MOVX

instructions, the EEMEN bit needs to be set to “0”.

During program execution mode (using the MOVX instruction) there is an auto-erase capability

at the byte level. This means that the user can update or modify a single EEPROM byte location

in real-time without affecting any other bytes.

The EEMWE bit in the EECON register needs to be set to “1” before any byte location in the

EEPROM can be written. User software should reset EEMWE bit to “0” if no further EEPROM

write is required. EEPROM write cycles in the serial programming mode are self-timed and typi-

cally take 4 ms. The progress of EEPROM write can be monitored by reading the RDY/BSY bit

(read-only) in SFR EECON. RDY/BSY = 0 means programming is still in progress and RDY/BSY

= 1 means an EEPROM write cycle is completed and another write cycle can be initiated. Bit

EELD in EECON controls whether the next MOVX instruction will only load the write buffer of the

EEPROM or will actually start the programming cycle. By setting EELD, only load will occur.

Before the last MOVX in a given page of 32 bytes, EELD should be cleared so that after the last

MOVX the entire page will be programmed at the same time. This way, 32 bytes will only require

4 ms of programming time instead of 128 ms required in single byte programming.

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3286H–MICRO–9/05

In addition, during EEPROM programming, an attempted read from the EEPROM will fetch the

byte being written with the MSB complemented. Once the write cycle is completed, true data are

valid at all bit locations.

6.1

Memory Control Register

The EECON register contains control bits for the 2K bytes of on-chip data EEPROM. It also con-

tains the control bit for the dual data pointer.

Table 6-1.

EECON – Data EEPROM Control Register

EECON Address = 96H

Not Bit Addressable

Reset Value = XX00 0011B

Bit

–

7

–

6

EELD

5

EEMWE

4

EEMEN

3

DPS

2

RDY/BSY

1

WRTINH

0

Symbol

Function

EEPROM data memory load enable bit. Used to implement Page Mode Write. A MOVX instruction writing into the data

EEPROM will not initiate the programming cycle if this bit is set, rather it will just load data into the volatile data buffer of

the data EEPROM memory. Before the last MOVX, reset this bit and the data EEPROM will program all the bytes

previously loaded on the same page of the address given by the last MOVX instruction.

EELD

EEPROM data memory write enable bit. Set this bit to 1 before initiating byte write to on-chip EEPROM with the MOVX

instruction. User software should set this bit to 0 after EEPROM write is completed.

EEMWE

EEMEN

DPS

Internal EEPROM access enable. When EEMEN = 1, the MOVX instruction with DPTR will access on-chip EEPROM

instead of external data memory if the address used is less than 2K. When EEMEN = 0 or the address used is ≥ 2K,

MOVX with DPTR accesses external data memory.

Data pointer register select. DPS = 0 selects the first bank of data pointer register, DP0, and DPS = 1 selects the

second bank, DP1.

RDY/BSY (Ready/Busy) flag for the data EEPROM memory. This is a read-only bit which is cleared by hardware during

the programming cycle of the on-chip EEPROM. It is also set by hardware when the programming is completed. Note

that RDY/BSY will be cleared long after the completion of the MOVX instruction which has initiated the programming

cycle.

RDY/BSY

WRTINH

WRTINH (Write Inhibit) is a READ-ONLY bit which is cleared by hardware when V_ccis too low for the programming cycle

of the on-chip EEPROM to be executed. When this bit is cleared, an ongoing programming cycle will be aborted or a

new programming cycle will not start.

Figure 6-1. Data EEPROM Write Sequence

EEMEN

EEMWE

EELD

MOVX DATA

0

1

2

3

30

31

~

4 ms

RDY/BSY

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AT89S8253

7. Power-On Reset

A Power-On Reset (POR) is generated by an on-chip detection circuit. The detection level is

nominally 1.4V. The POR is activated whenever V_CCis below the detection level. The POR cir-

cuit can be used to trigger the start-up reset or to detect a supply voltage failure in devices

without a brown-out detector. The POR circuit ensures that the device is reset from power-on.

When V_CCreaches the Power-on Reset threshold voltage, the POR delay counter determines

how long the device is kept in POR after V_CCrise, nominally 2 ms. The POR signal is activated

again, without any delay, when V_CCfalls below the POR threshold level. A Power-On Reset (i.e.

a cold reset) will set the POF flag in PCON.

Figure 7-1. Power-up and Brown-out Detection Sequence

V_CC

Min V_CCLevel 2.7V

BOD Level 2.3V

POR Level 1.4V

t

POR

t

2.4V

XTAL1

BOD

1.2V

t

Internal

RESET

t_POR

(2 ms)

t

0

7.1

Brown-out Reset

The AT89S8253 has an on-chip Brown-out Detection (BOD) circuit for monitoring the V_CClevel

during operation by comparing it to a fixed trigger level of 2.4V (max). The trigger level for the

BOD is nominally 2.2V. The purpose of the BOD is to ensure that if V_CCfails or dips while exe-

cuting at speed, the system will gracefully enter reset without the possibility of errors induced by

incorrect execution. When V_CCdecreases to a value below the trigger level, the Brown-out Reset

is immediately activated. When V_CCincreases above the trigger level, the BOD delay counter

starts the MCU after the timeout period has expired in approximately 2 ms.

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3286H–MICRO–9/05

8. Programmable Watchdog Timer

The programmable Watchdog Timer (WDT) counts instruction cycles. The prescaler bits, PS0,

PS1 and PS2 in SFR WDTCON are used to set the period of the Watchdog Timer from 16K to

2048K instruction cycles. The available timer periods are shown in Table 8-1. The WDT time-out

period is dependent upon the external clock frequency.

The WDT is disabled by Power-on Reset and during Power-down mode. When WDT times out

without being serviced or disabled, an internal RST pulse is generated to reset the CPU. See

Table 8-1 for the WDT period selections.

Table 8-1.

Watchdog Timer Time-out Period Selection

WDT Prescaler Bits

Period (Nominal for

F_CLK= 12 MHz)

PS2

PS1

0

PS0

0

1

16 ms

32 ms

0

1

0

64 ms

1

128 ms

256 ms

512 ms

1024 ms

2048 ms

0

1

0

1

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AT89S8253

8.1

Watchdog Control Register

The WDTCON register contains control bits for the Watchdog Timer (shown in Table 8-2).

Table 8-2. WDTCON – Watchdog Control Register

WDTCON Address = A7H

Not Bit Addressable

Reset Value = 0000 0000B

PS2

PS1

6

PS0

5

WDIDLE

4

DISRTO

3

HWDT

2

WSWRST

1

WDTEN

0

Bit

7

Symbol

Function

Prescaler bits for the watchdog timer (WDT). When all three bits are cleared to 0, the watchdog timer has a nominal

period of 16K machine cycles, (i.e. 16 ms at a XTAL frequency of 12 MHz in normal mode or 6 MHz in x2 mode). When

all three bits are set to 1, the nominal period is 2048K machine cycles, (i.e. 2048 ms at 12 MHz clock frequency in

normal mode or 6 MHz in x2 mode).

PS2

PS1

PS0

Enable/disable the Watchdog Timer in IDLE mode. When WDIDLE = 0, WDT continues to count in IDLE mode. When

WDIDLE = 1, WDT freezes while the device is in IDLE mode.

WDIDLE

DISRTO

Enable/disable the WDT-driven Reset Out (WDT drives the RST pin). When DISRTO = 0, the RST pin is driven high

after WDT times out and the entire board is reset. When DISRTO = 1, the RST pin remains only as an input and the

WDT resets only the microcontroller internally after WDT times out.

Hardware mode select for the WDT. When HWDT = 0, the WDT can be turned on/off by simply setting or clearing

WDTEN in the same register (this is the software mode for WDT). When HWDT = 1, the WDT has to be set by writing

the sequence 1EH/E1H to the WDTRST register (with address 0A6H) and after being set in this way, WDT cannot be

turned off except by reset, warm or cold (this is the hardware mode for WDT). To prevent the hardware WDT from

resetting the entire device, the same sequence 1EH/E1H must be written to the same WDTRST SFR before the

timeout interval.

HWDT

Watchdog software reset bit. If HWDT = 0 (i.e. WDT is in software controlled mode), when set by software, this bit resets

WDT. After being set by software, WSWRST is reset by hardware during the next machine cycle. If HWDT = 1, this bit

has no effect, and if set by software, it will not be cleared by hardware.

WSWRST

WDTEN

Watchdog software enable bit. When HWDT = 0 (i.e. WDT is in software-controlled mode), this bit enables WDT when

set to 1 and disables WDT when cleared to 0 (it does not reset WDT in this case, but just freezes the existing counter

state). If HWDT = 1, this bit is READ-ONLY and reflects the status of the WDT (whether it is running or not).

Figure 8-1. Software Mode – Watchdog Timer Sequence

WDTEN

HW

WSWRST

SW

Writes

a 1

SW

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3286H–MICRO–9/05

9. Timer 0 and 1

10. Timer 2

Timer 0 and Timer 1 in the AT89S8253 operate the same way as Timer 0 and Timer 1 in the

AT89S51 and AT89S52. For more detailed information on the Timer/Counter operation, please

click on the document link below:

http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF

Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The

type of operation is selected by bit C/T2 in the SFR T2CON (see Table 10-2 on page 15). Timer

2 has three operating modes: capture, auto-reload (up or down counting), and baud rate gener-

ator. The modes are selected by bits in T2CON, as shown in Table 10-2.

Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is

incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the

count rate is 1/12 of the oscillator frequency.

In the Counter function, the register is incremented in response to a 1-to-0 transition at its corre-

sponding external input pin, T2. In this function, the external input is sampled during S5P2 of

every machine cycle. When the samples show a high in one cycle and a low in the next cycle,

the count is incremented. The new count value appears in the register during S3P1 of the cycle

following the one in which the transition was detected. Since two machine cycles (24 oscillator

periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the

oscillator frequency. To ensure that a given level is sampled at least once before it changes, the

level should be held for at least one full machine cycle.

Table 10-1. Timer 2 Operating Modes

RCLK + TCLK

CP/RL2

TR2

1

MODE

0

1

X

0

1

16-bit Auto-reload

16-bit Capture

Baud Rate Generator

(Off)

1

X

1

0

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AT89S8253

Table 10-2. T2CON – Timer/Counter 2 Control Register

T2CON Address = 0C8H

Reset Value = 0000 0000B

Bit Addressable

TF2

7

EXF2

6

RCLK

5

TCLK

4

EXEN2

3

TR2

2

C/T2

1

CP/RL2

0

Bit

Symbol

TF2

Function

Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either

RCLK = 1 or TCLK = 1.

Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1.

When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be

cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).

EXF2

Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial port

Modes 1 and 3. RCLK = 0 causes Timer 1 overflows to be used for the receive clock.

RCLK

TCLK

Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial port

Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.

Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if

Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.

EXEN2

TR2

Start/Stop control for Timer 2. TR2 = 1 starts the timer.

Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge

triggered).

C/T2

Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2 = 0

causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1. When

either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.

CP/RL2

10.1 Timer 2 Registers

Control and status bits are contained in registers T2CON (see Table 10-2) and T2MOD (see

Table 10-3) for Timer 2. The register pair (RCAP2H, RCAP2L) are the Capture/Reload registers

for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode.

10.2 Capture Mode

In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is

a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON. This bit can then be used

to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same operation, but a 1-to-0 transi-

tion at external input T2EX also causes the current value in TH2 and TL2 to be captured into

RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in

T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt. The capture mode is illus-

trated in Figure 10-1.

15

3286H–MICRO–9/05

Figure 10-1. Timer 2 in Capture Mode

÷12

OSC

C/T2 = 0

C/T2 = 1

TH2

TL2

TF2

OVERFLOW

CONTROL

TR2

CAPTURE

T2 PIN

RCAP2H RCAP2L

EXF2

TRANSITION

DETECTOR

TIMER 2

INTERRUPT

T2EX PIN

CONTROL

EXEN2

10.3 Auto-reload (Up or Down Counter)

Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload

mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR

T2MOD (see Table 10-3). Upon reset, the DCEN bit is set to 0 so that timer 2 will default to

count up. When DCEN is set, Timer 2 can count up or down, depending on the value of the

T2EX pin.

Table 10-3. T2MOD – Timer 2 Mode Control Register

T2MOD Address = 0C9H

Reset Value = XXXX XX00B

Not Bit Addressable

–

6

–

5

–

4

–

3

–

2

T2OE

1

DCEN

0

Bit

7

Symbol

–

Function

Not implemented, reserved for future use.

Timer 2 Output Enable bit.

T2OE

DCEN

When set, this bit allows Timer 2 to be configured as an up/down counter.

Figure 10-2 shows Timer 2 automatically counting up when DCEN = 0. In this mode, two options

are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to 0FFFFH and then sets

the TF2 bit upon overflow. The overflow also causes the timer registers to be reloaded with the

16-bit value in RCAP2H and RCAP2L. The values in RCAP2H and RCAP2L are preset by soft-

ware. If EXEN2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0

transition at external input T2EX. This transition also sets the EXF2 bit. Both the TF2 and EXF2

bits can generate an interrupt if enabled.

Setting the DCEN bit enables Timer 2 to count up or down, as shown in Figure 10-3. In this

mode, the T2EX pin controls the direction of the count. A logic 1 at T2EX makes Timer 2 count

up. The timer will overflow at 0FFFFH and set the TF2 bit. This overflow also causes the 16-bit

value in RCAP2H and RCAP2L to be reloaded into the timer registers, TH2 and TL2,

respectively.

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AT89S8253

3286H–MICRO–9/05

AT89S8253

A logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2 and TL2 equal

the values stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes 0FFFFH

to be reloaded into the timer registers.

The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit

of resolution. In this operating mode, EXF2 does not flag an interrupt.

Figure 10-2. Timer 2 in Auto Reload Mode (DCEN = 0)

Figure 10-3. Timer 2 Auto Reload Mode (DCEN = 1 Timer 2 Auto Reload Mode (DCEN = 1)

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3286H–MICRO–9/05

Figure 10-4. Timer 2 in Baud Rate Generator Mode

TIMER 1 OVERFLOW

2

÷

"0"

"1"

NOTE: OSC. FREQ. IS DIVIDED BY 2, NOT 12

SMOD1

RCLK

2

OSC

÷

C/T2 = 0

"1"

TH2

TL2

Rx

CLOCK

CONTROL

TR2

16

÷

C/T2 = 1

"0"

T2 PIN

TCLK

RCAP2H RCAP2L

Tx

CLOCK

TRANSITION

DETECTOR

16

÷

TIMER 2

INTERRUPT

T2EX PIN

EXF2

CONTROL

EXEN2

11. Baud Rate Generator

Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON (Table

10-2). Note that the baud rates for transmit and receive can be different if Timer 2 is used for the

receiver or transmitter and Timer 1 is used for the other function. Setting RCLK and/or TCLK

puts Timer 2 into its baud rate generator mode, as shown in Figure 10-4.

The baud rate generator mode is similar to the auto-reload mode, in that a rollover in TH2

causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and

RCAP2L, which are preset by software.

The baud rates in Modes 1 and 3 are determined by Timer 2’s overflow rate according to the fol-

lowing equation.

Timer 2 Overflow Rate

Modes 1 and 3 Baud Rates = -----------------------------------------------------------

16

The Timer can be configured for either timer or counter operation. In most applications, it is con-

figured for timer operation (CP/T2 = 0). The timer operation is different for Timer 2 when it is

used as a baud rate generator. Normally, as a timer, it increments every machine cycle (at 1/12

the oscillator frequency). As a baud rate generator, however, it increments every state time (at

1/2 the oscillator frequency). The baud rate formula is given below.

Modes 1 and 3

Baud Rate 32 × [65536 – (RCAP2H,RCAP2L)]

Oscillator Frequency

--------------------------------------- = ----------------------------------------------------------------------------------------------

where (RCAP2H, RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16-bit unsigned

integer.

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AT89S8253

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AT89S8253

Timer 2 as a baud rate generator is shown in Figure 10-4. This figure is valid only if RCLK or

TCLK = 1 in T2CON. Note that a rollover in TH2 does not set TF2 and will not generate an inter-

rupt. Note too, that if EXEN2 is set, a 1-to-0 transition in T2EX will set EXF2 but will not cause a

reload from (RCAP2H, RCAP2L) to (TH2, TL2). Thus when Timer 2 is in use as a baud rate gen-

erator, T2EX can be used as an extra external interrupt.

Note that when Timer 2 is running (TR2 = 1) as a timer in the baud rate generator mode, TH2 or

TL2 should not be read from or written to. Under these conditions, the Timer is incremented

every state time, and the results of a read or write may not be accurate. The RCAP2 registers

may be read but should not be written to, because a write might overlap a reload and cause

write and/or reload errors. The timer should be turned off (clear TR2) before accessing the Timer

2 or RCAP2 registers.

12. Programmable Clock Out

A 50% duty cycle clock can be programmed to come out on P1.0, as shown in Figure 12-1. This

pin, besides being a regular I/O pin, has two alternate functions. It can be programmed to input

the external clock for Timer/Counter 2 or to output a 50% duty cycle clock ranging from 61 Hz to

4 MHz (for a 16 MHz operating frequency).

To configure the Timer/Counter 2 as a clock generator, bit C/T2 (T2CON.1) must be cleared and

bit T2OE (T2MOD.1) must be set. Bit TR2 (T2CON.2) starts and stops the timer.

The clock-out frequency depends on the oscillator frequency and the reload value of Timer 2

capture registers (RCAP2H, RCAP2L), as shown in the following equation.

Oscillator Frequency

Clock Out Frequency = ------------------------------------------------------------------------------------------

4 × [65536 – (RCAP2H,RCAP2L)]

In the clock-out mode, Timer 2 rollovers will not generate an interrupt. This behavior is similar to

when Timer 2 is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate gen-

erator and a clock generator simultaneously. Note, however, that the baud-rate and clock-out

frequencies cannot be determined independently from one another since they both use

RCAP2H and RCAP2L.

Figure 12-1. Timer 2 in Clock-out Mode

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3286H–MICRO–9/05

13. UART

The UART in the AT89S8253 operates the same way as the UART in the AT89S51 and

AT89S52. For more detailed information on the UART operation, please click on the document

link below:

http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF

13.1 Enhanced UART

In addition to all of its usual modes, the UART can perform framing error detection by looking for

missing stop bits, and automatic address recognition. The UART also fully supports multiproces-

sor communication as does the standard 80C51 UART.

When used for framing error detect, the UART looks for missing stop bits in the communication.

A missing bit will set the FE bit in the SCON register. The FE bit shares the SCON.7 bit with SM0

and the function of SCON.7 is determined by PCON.6 (SMOD0). If SMOD0 is set then SCON.7

functions as FE. SCON.7 functions as SM0 when SMOD0 is cleared. When used as FE,

SCON.7 can only be cleared by software.

13.1.1

Automatic Address Recognition

Automatic Address Recognition is a feature which allows the UART to recognize certain

addresses in the serial bit stream by using hardware to make the comparisons. This feature

saves a great deal of software overhead by eliminating the need for the software to examine

every serial address which passes by the serial port. This feature is enabled by setting the SM2

bit in SCON. In the 9-bit UART modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will

be automatically set when the received byte contains either the “Given” address or the

“Broadcast” address. The 9-bit mode requires that the 9th information bit is a 1 to indicate that

the received information is an address and not data.

The 8-bit mode is called mode 1. In this mode the RI flag will be set if SM2 is enabled and the

information received has a valid stop bit following the 8 address bits and the information is either

a Given or Broadcast address.

Mode 0 is the Shift Register mode and SM2 is ignored.

Using the Automatic Address Recognition feature allows a master to selectively communicate

with one or more slaves by invoking the given slave address or addresses. All of the slaves may

be contacted by using the Broadcast address. Two special Function Registers are used to

define the slave’s address, SADDR, and the address mask, SADEN. SADEN is used to define

which bits in the SADDR are to be used and which bits are “don’t care”. The SADEN mask can

be logically ANDed with the SADDR to create the “Given” address which the master will use for

addressing each of the slaves. Use of the Given address allows multiple slaves to be recognized

while excluding others. The following examples will help to show the versatility of this scheme:

Slave 0

SADDR = 1100 0000

SADEN = 1111 1101

Given

= 1100 00X0

Slave 1

SADDR = 1100 0000

SADEN = 1111 1110

Given

= 1100 000X

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3286H–MICRO–9/05

AT89S8253

In the previous example SADDR is the same and the SADEN data is used to differentiate

between the two slaves. Slave 0 requires a 0 in bit 0 and it ignores bit 1. Slave 1 requires a 0 in

bit 1 and bit 0 is ignored. A unique address for slave 0 would be 1100 0010 since slave 1

requires a 0 in bit 1. A unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will

exclude slave 0. Both slaves can be selected at the same time by an address which has bit 0 = 0

(for slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed with 1100 0000.

In a more complex system the following could be used to select slaves 1 and 2 while excluding

slave 0:

Slave 0

Slave 1

Slave 2

SADDR = 1100 0000

SADEN = 1111 1001

Given

= 1100 0XX0

SADDR = 1110 0000

SADEN = 1111 1010

Given

= 1110 0X0X

SADDR = 1110 0000

SADEN = 1111 1100

Given

= 1110 00XX

In the previous example the differentiation among the 3 slaves is in the lower 3 address bits.

Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1 requires

that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. Slave 2 requires that bit 2 = 0

and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude Slave 2, use

address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2.

The Broadcast Address for each slave is created by taking the logical OR of SADDR and

SADEN. Zeros in this result are trended as don’t-cares. In most cases, interpreting the don’t-

cares as ones, the broadcast address will be FF hexadecimal.

Upon reset SADDR (SFR address 0A9H) and SADEN (SFR address 0B9H) are loaded with 0s.

This produces a given address of all “don’t cares” as well as a Broadcast address of all “don’t

cares”. This effectively disables the Automatic Addressing mode and allows the microcontroller

to use standard 80C51-type UART drivers which do not make use of this feature.

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3286H–MICRO–9/05

Table 13-1. PCON – Power Control Register

PCON Address = 87H

Reset Value = 00xx 0000B

Bit Addressable

SMOD1

7

SMOD0

6

–

5

POF

4

GF1

3

GF0

2

PD

1

IDL

0

Bit

Symbol

SMOD1

SMOD0

Function

Double Baud Rate bit. Doubles the baud rate of the UART in Modes 1, 2, or 3.

Frame Error Select. When SMOD0 = 1, SCON.7 is SM0. When SMOD0 = 1, SCON.7 is FE. Note that FE will be set after

a frame error regardless of the state of SMOD0.

POF

Power Off Flag. POF is set to “1” during power up (i.e. cold reset). It can be set or reset under software control and is not

affected by RST or BOD (i.e. warm resets).

GF1, GF0

PD

General-purpose Flags

Power-down bit. Setting this bit activates power-down operation.

Idle Mode bit. Setting this bit activates Idle mode operation

IDL

Table 13-2. SCON – Serial Port Control Register

SCON Address = 98H

Reset Value = 0000 0000B

Bit Addressable

SM0/FE

SM1

6

SM2

5

REN

4

TB8

3

RB8

2

T1

1

RI

0

Bit

7

(SMOD0 = 0/1)⁽¹⁾

Symbol

FE

Function

Framing error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid

frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit. FE will be set

regardless of the state of SMOD0.

SM0

Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0)

Serial Port Mode Bit 1

SM0

SM1

Mode

Description

shift register

8-bit UART

9-bit UART

Baud Rate⁽²⁾

f_osc/12

0

1

0

1

0

1

0

1

2

3

SM1

SM2

variable

f_osc/64 or f_osc/32

variable

Enables the Automatic Address Recognition feature in modes 2 or 3. If SM2 = 1 then Rl will not be set unless the received

9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address. In mode 1, if SM2 =

1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a Given or Broadcast Address.

In Mode 0, SM2 should be 0.

REN

TB8

Enables serial reception. Set by software to enable reception. Clear by software to disable reception.

The 9th data bit that will be transmitted in modes 2 and 3. Set or clear by software as desired.

In modes 2 and 3, the 9th data bit that was received. In mode 1, if SM2 = 0, RB8 is the stop bit that was received. In mode

0, RB8 is not used.

RB8

TI

Transmit interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the

other modes, in any serial transmission. Must be cleared by software.

Receive interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit time in the

other modes, in any serial reception (except see SM2). Must be cleared by software.

RI

Notes: 1. SMOD0 is located at PCON.6.

2. f_osc= oscillator frequency.

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3286H–MICRO–9/05

AT89S8253

14. Serial Peripheral Interface

The serial peripheral interface (SPI) allows high-speed synchronous data transfer between the

AT89S8253 and peripheral devices or between multiple AT89S8253 devices. The AT89S8253

SPI features include the following:

• Full-Duplex, 3-Wire Synchronous Data Transfer

• Master or Slave Operation

• Maximum Bit Frequency = f/4 (f/2 if in x2 Clock Mode)

• LSB First or MSB First Data Transfer

• Four Programmable Bit Rates in Master Mode

• End of Transmission Interrupt Flag

• Write Collision Flag Protection

• Double-Buffered Receive

• Double-Buffered Transmit (Enhanced Mode only)

• Wakeup from Idle Mode (Slave Mode only)

The interconnection between master and slave CPUs with SPI is shown in Figure 14-1. The four

pins in the interface are Master-In/Slave-Out (MISO), Master-Out/Slave-In (MOSI), Shift Clock

(SCK), and Slave Select (SS). The SCK pin is the clock output in master mode, but is the clock

input in slave mode. The MSTR bit in SPCR determines the directions of MISO and MOSI. Also

notice that MOSI connects to MOSI and MISO to MISO. In master mode, SS/P1.4 is ignored and

may be used as a general-purpose input or output. In slave mode, SS must be driven low to

select an individual device as a slave. When SS is driven high, the slave’s SPI port is deacti-

vated and the MOSI/P1.5 pin can be used as a general-purpose input.

Figure 14-1. SPI Master-Slave Interconnection

MSB

MASTER

LSB

MSB

SLAVE

LSB

MISO MISO

8-BIT SHIFT REGISTER

MOSI MOSI

SCK

SS

SCK

SS

SPI

CLOCK GENERATOR

V_CC

23

3286H–MICRO–9/05

Figure 14-2. SPI Block Diagram

S

MISO

P1.6

M

OSCILLATOR

MOSI

P1.5

MSB

LSB

S

8-BIT SHIFT REGISTER

READ DATA BUFFER

WRITE DATA BUFFER⁽¹⁾

DIVIDER

÷4÷16÷64÷128

CLOCK

SPI CLOCK (MASTER)

SCK

1.7

CLOCK

LOGIC

S

SELECT

M

SS

P1.4

MSTR

SPE

SPI CONTROL

8

SPI STATUS REGISTER

SPI CONTROL REGISTER

8

SPI INTERRUPT

REQUEST

INTERNAL

DATA BUS

Note:

1. The Write Data Buffer is only used in enhanced SPI mode.

The SPI has two modes of operation: normal (non-buffered write) and enhanced (buffered

write). In normal mode, writing to the SPI data register (SPDR) of the master CPU starts the SPI

clock generator and the data written shifts out of the MOSI pin and into the MOSI pin of the slave

CPU. Transmission may start after an initial delay while the clock generator waits for the next full

bit slot of the specified baud rate. After shifting one byte, the SPI clock generator stops, setting

the end of transmission flag (SPIF) and transferring the received byte to the read buffer (SPDR).

If both the SPI interrupt enable bit (SPIE) and the serial port interrupt enable bit (ES) are set, an

interrupt is requested. Note that SPDR refers to either the write data buffer or the read data

buffer, depending on whether the access is a write or read. In normal mode, because the write

buffer is transparent (and a write access to SPDR will be directed to the shift buffer), any attempt

to write to SPDR while a transmission is in progress will result in a write collision with WCOL set.

However, the transmission will still complete normally, but the new byte will be ignored and a

new write access to SPDR will be necessary.

Enhanced mode is similar to normal mode except that the write buffer holds the next byte to be

transmitted. Writing to SPDR loads the write buffer and sets WCOL to signify that the buffer is

full and any further writes will overwrite the buffer. WCOL is cleared by hardware when the buff-

ered byte is loaded into the shift register and transmission begins. If the master SPI is currently

idle, i.e. if this is the first byte, then after loading SPDR, transmission of the byte starts and

WCOL is cleared immediately. While this byte is transmitting, the next byte may be written to

SPDR. The Load Enable flag (LDEN) in SPSR can be used to determine when transmission has

started. LDEN is asserted during the first four bit slots of a SPI transfer. The master CPU should

first check that LDEN is set and that WCOL is cleared before loading the next byte. In enhanced

mode, if WCOL is set when a transfer completes, i.e. the next byte is available, then the SPI

immediately loads the buffered byte into the shift register, resets WCOL, and continues trans-

mission without stopping and restarting the clock generator. As long as the CPU can keep the

write buffer full in this manner, multiple bytes may be transferred with minimal latency between

bytes.

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AT89S8253

Table 14-1. SPCR – SPI Control Register

SPCR Address = D5H

Reset Value = 0000 0100B

Not Bit Addressable

SPIE

7

SPE

6

DORD

5

MSTR

4

CPOL

3

CPHA

2

SPR1

1

SPR0

0

Bit

Symbol

Function

SPI interrupt enable. This bit, in conjunction with the ES bit in the IE register, enables SPI interrupts: SPIE = 1 and ES = 1

enable SPI interrupts. SPIE = 0 disables SPI interrupts.

SPIE

SPI enable. SPI = 1 enables the SPI channel and connects SS, MOSI, MISO and SCK to pins P1.4, P1.5, P1.6, and P1.7.

SPI = 0 disables the SPI channel.

SPE

DORD

MSTR

Data order. DORD = 1 selects LSB first data transmission. DORD = 0 selects MSB first data transmission.

Master/slave select. MSTR = 1 selects Master SPI mode. MSTR = 0 selects slave SPI mode.

Clock polarity. When CPOL = 1, SCK is high when idle. When CPOL = 0, SCK of the master device is low when not

transmitting. Please refer to figure on SPI clock phase and polarity control.

CPOL

CPHA

Clock phase. The CPHA bit together with the CPOL bit controls the clock and data relationship between master and slave.

Please refer to figure on SPI clock phase and polarity control.

SPI clock rate select. These two bits control the SCK rate of the device configured as master. SPR1 and SPR0 have no

effect on the slave. The relationship between SCK and the oscillator frequency, F_OSC., is as follows:

SPR1 SPR0 SCK

SPR0

SPR1

0

1

0

1

0

1

f/4 (f/2 in x2 mode)

f/16 (f/8 in x2 mode)

f/64 (f/32 in x2 mode)

f/128 (f/64 in x2 mode)

Notes: 1. Set up the clock mode before enabling the SPI: set all bits needed in SPCR except the SPE bit, then set SPE.

2. Enable the master SPI prior to the slave device.

3. Slave echoes master on next Tx if not loaded with new data.

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3286H–MICRO–9/05

Table 14-2. SPSR – SPI Status Register

SPSR Address = AAH

Reset Value = 000X XX00B

Not Bit Addressable

SPIF

7

WCOL

6

LDEN

5

–

4

–

3

–

2

DISSO

1

ENH

0

Bit

Symbol

Function

SPI interrupt flag. When a serial transfer is complete, the SPIF bit is set and an interrupt is generated if SPIE = 1 and ES

= 1. The SPIF bit is cleared by reading the SPI status register followed by reading/writing the SPI data register.

SPIF

When ENH = 0: Write collision flag. The WCOL bit is set if the SPI data register is written during a data transfer. During

data transfer, the result of reading the SPDR register may be incorrect, and writing to it has no effect. The WCOL bit (and

the SPIF bit) are cleared by reading the SPI status register followed by reading/writing the SPI data register.

WCOL

When ENH = 1: WCOL works in Enhanced mode as Tx Buffer Full. Writing during WCOL = 1 in enhanced mode will

overwrite the waiting data already present in the Tx Buffer. In this mode, WCOL is no longer reset by the SPIF reset but

is reset when the write buffer has been unloaded into the serial shift register.

Load enable for the Tx buffer in enhanced SPI mode.

LDEN

DISSO

ENH

When ENH is set, it is safe to load the Tx Buffer while LDEN = 1 and WCOL = 0. LDEN is high during bits 0 - 3 and is low

during bits 4 - 7 of the SPI serial byte transmission time frame.

Disable slave output bit.

When set, this bit causes the MISO pin to be tri-stated so more than one slave device can share the same interface with

a single master. Normally, the first byte in a transmission could be the slave address and only the selected slave should

clear its DISSO bit.

Enhanced SPI mode select bit. When ENH = 0, SPI is in normal mode, i.e. without write double buffering.

When ENH = 1, SPI is in enhanced mode with write double buffering. The Tx buffer shares the same address with the

SPDR register.

Table 14-3. SPDR – SPI Data Register

SPDR Address = 86H

Reset Value = 00H (after cold reset)

unchanged (after warm reset)

Not Bit Addressable

SPD7

7

SPD6

6

SPD5

5

SPD4

4

SPD3

3

SPD2

2

SPD1

1

SPD0

0

Bit

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AT89S8253

Figure 14-3. SPI Shift Register Diagram

7

Serial In

Serial Master

Serial Slave

8

2:1

MUX

2:1

MUX

D

Q

D

Q

Serial Out

LATCH

CLK

LATCH

CLK

8

Parallel Master

(Write Buffer)

Parallel Slave

(Read Buffer)

Transmit

Byte

Receive

Byte

8

D

Q

D

Q

LATCH

CLK

LATCH

CLK

The CPHA (Clock PHAse), CPOL (Clock POLarity), and SPR (Serial Peripheral clock Rate =

baud rate) bits in SPCR control the shape and rate of SCK. The two SPR bits provide four possi-

ble clock rates when the SPI is in master mode. In slave mode, the SPI will operate at the rate of

the incoming SCK as long as it does not exceed the maximum bit rate. There are also four pos-

sible combinations of SCK phase and polarity with respect to the serial data. CPHA and CPOL

determine which format is used for transmission. The SPI data transfer formats are shown in

Figure 14-4 and Figure 14-5. To prevent glitches on SCK from disrupting the interface, CPHA,

CPOL, and SPR should be set up before the interface is enabled, and the master device should

be enabled before the slave device(s).

Table 14-4. SPI Master Characteristics

Symbol

t_CLCL

t_SCK

t_SHSL

t_SLSH

t_SR

Parameter

Min

41.6

Max

Units

ns

Oscillator Period

Serial Clock Cycle Time

Clock High Time

Clock Low Time

4t_CLCL

ns

t_SCK/2 - 25

ns

Rise Time

25

ns

t_SF

Fall Time

ns

t_SIS

Serial Input Setup Time

Serial Input Hold Time

Serial Output Hold Time

Serial Output Valid Time

10

ns

t_SIH

ns

t_SOH

t_SOV

10

35

ns

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Table 14-5. SPI Slave Characteristics

Symbol

t_CLCL

t_SCK

t_SHSL

t_SLSH

t_SR

Parameter

Min

41.6

Max

Units

ns

Oscillator Period

Serial Clock Cycle Time

Clock High Time

4t_CLCL

1.5 t_CLCL- 25

Clock Low Time

Rise Time

25

t_SF

Fall Time

t_SIS

Serial Input Setup Time

Serial Input Hold Time

Serial Output Hold Time

Serial Output Valid Time

Output Enable Time

Output Disable Time

Slave Enable Lead Time

Slave Disable Lag Time

10

t_SIH

t_SOH

t_SOV

t_SOE

t_SOX

t_SSE

t_SSD

10

35

10

25

10

0

Figure 14-4. SPI Master Timing (CPHA = 0)

SS

t

SF

SR

t

SCK

t

SLSH

SHSL

SCK

(CPOL = 0)

SCK

(CPOL = 1)

t

SHSL

SLSH

t

SIH

SIS

MISO

MOSI

t

SOH

SOV

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Figure 14-5. SPI Slave Timing (CPHA = 0)

SS

t

SR

t

SSD

SCK

SSE

SF

t

SHSL

SLSH

SCK

(CPOL = 0)

SCK

(CPOL= 1)

t

SHSL

t

SOH

t

SOX

SOV

SOE

MISO

MOSI

t

SIS

SIH

Figure 14-6. SPI Master Timing (CPHA = 1)

SS

t

SCK

t

SR

SF

t

SLSH

SHSL

SCK

(CPOL = 0)

SCK

(CPOL = 1)

t

SHSL

SLSH

t

SIH

SIS

MISO

MOSI

t

SOV

SOH

Figure 14-7. SPI Slave Timing (CPHA = 1)

SS

t

SCK

SSE

t

SF

SR

SSD

t

SLSH

SHSL

SCK

(CPOL = 0)

SCK

(CPOL = 1)

t

SLSH

SHSL

t

SOX

SOE

SOV

SOH

MISO

MOSI

t

SIS

SIH

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3286H–MICRO–9/05

Figure 14-8. SPI Transfer Format with CPHA = 0

Note:

*Not defined but normally MSB of character just received

Figure 14-9. SPI Transfer Format with CPHA = 1

SCK CYCLE #

1

2

3

4

5

6

7

8

(FOR REFERENCE)

SCK (CPOL = 0)

SCK (CPOL = 1)

MOSI

(FROM MASTER)

MSB

6

5

4

3

2

1

LSB

MISO

(FROM SLAVE)

6

4

2

LSB

*

SS (TO SLAVE)

Note:

*Not defined but normally LSB of previously transmitted character

15. Interrupts

The AT89S8253 has a total of six interrupt vectors: two external interrupts (INT0 and INT1),

three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These interrupts are all

shown in Figure 15-1.

Each of these interrupt sources can be individually enabled or disabled by setting or clearing a

bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all

interrupts at once.

Note that Table 15-1 shows that bit position IE.6 is unimplemented. User software should not

write a 1 to this bit position, since it may be used in future AT89 products.

Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON. Nei-

ther of these flags is cleared by hardware when the service routine is vectored to. In fact, the

service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt,

and that bit will have to be cleared in software.

The serial interrupt is the logical OR of bits RI and TI in register SCON and also bit SPIF in

SPSR (if SPIE in SPCR is set). None of these flags is cleared by hardware when the service rou-

tine is vectored to. The service routine may have to determine whether the UART or SPI

generated the interrupt.

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AT89S8253

The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers

overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag,

TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows.

Interrupt

Source

Vector Address

0000H

System Reset

External Interrupt 0

Timer 0 Overflow

External Interrupt 1

Timer 1 Overflow

Serial Port

RST or POR or BOD

IE0

0003H

TF0

000BH

IE1

0013H

TF1

001BH

RI or TI

0023H

Table 15-1. Interrupt Enable (IE) Register

IE Address = A8H

Reset Value = 0X00 0000B

Bit Addressable

EA

–

ET2

ES

ET1

EX1

ET0

EX0

Enable Bit = 1 enables the interrupt.

Enable Bit = 0 disables the interrupt.

Symbol

Position

Function

Disables all interrupts. If EA = 0, no interrupt is acknowledged. If EA = 1, each interrupt source is individually

enabled or disabled by setting or clearing its enable bit.

EA

IE.7

–

IE.6

IE.5

IE.4

IE.3

IE.2

IE.1

IE.0

Reserved.

ET2

ES

Timer 2 interrupt enable bit.

SPI and UART interrupt enable bit.

Timer 1 interrupt enable bit.

External interrupt 1 enable bit.

Timer 0 interrupt enable bit.

External interrupt 0 enable bit.

ET1

EX1

ET0

EX0

User software should never write 1s to reserved bits, because they may be used in future AT89 products.

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3286H–MICRO–9/05

Table 15-2. IP – Interrupt Priority Register

IP = B8H

Reset Value = XX00 0000B

Bit Addressable

–

7

–

6

PT2

5

PS

4

PT1

3

PX1

2

PT0

1

PX0

0

Bit

Symbol

PT2

Function

Timer 2 Interrupt Priority Low

Serial Port Interrupt Priority Low

Timer 1 Interrupt Priority Low

External Interrupt 1 Priority Low

Timer 0 Interrupt Priority Low

External Interrupt 0 Priority Low

.

PS

PT1

PX1

PT0

PX0

Table 15-3. IPH – Interrupt Priority High Register

IPH = B7H

Reset Value = XX00 0000B

Not Bit Addressable

–

7

–

6

PT2H

5

PSH

4

PT1H

3

PX1H

2

PT0H

1

PX0H

0

Bit

Symbol

PT2H

PSH

Function

Timer 2 Interrupt Priority High

Serial Port Interrupt Priority High

Timer 1 Interrupt Priority High

External Interrupt 1 Priority High

Timer 0 Interrupt Priority High

External Interrupt 0 Priority High

PT1H

PX1H

PT0H

PX0H

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AT89S8253

Figure 15-1. Interrupt Sources

16. Oscillator Characteristics

XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be

configured for use as an on-chip oscillator, as shown in Figure 16-1. Either a quartz crystal or

ceramic resonator may be used. To drive the device from an external clock source, XTAL2

should be left unconnected while XTAL1 is driven, as shown in Figure 16-2.

Figure 16-1. Oscillator Connections

Note:

C1, C2 = 5 pF 5 pF for Crystals

= 5 pF 5 pF for Ceramic Resonators

Figure 16-2. External Clock Drive Configuration

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3286H–MICRO–9/05

17. Idle Mode

In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. This

mode is invoked by software. The content of the on-chip RAM and all the special functions regis-

ters remain unchanged during this mode. The idle mode can be terminated by any enabled

interrupt or by a hardware reset.

Note that when idle mode is terminated by a hardware reset, the device normally resumes pro-

gram execution from where it left off, up to two machine cycles before the internal reset

algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but

access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a

port pin when idle mode is terminated by a reset, the instruction following the one that invokes

idle mode should not write to a port pin or to external memory.

Table 17-1. Status of External Pins During Idle and Power-down Modes

Mode

Program Memory

Internal

ALE

PSEN

PORT0

Data

PORT1

Data

PORT2

Data

PORT3

Data

Idle

1

0

1

0

Idle

External

Float

Data

Address

Data

Power-down

Internal

Data

External

Float

Data

18. Power-down Mode

In the power-down mode, the oscillator is stopped and the instruction that invokes power-down

is the last instruction executed. The on-chip RAM and Special Function Registers retain their

values until the power-down mode is terminated. Exit from power-down can be initiated either by

a hardware reset or by an enabled external interrupt. Reset redefines the SFRs but does not

change the on-chip RAM. The reset should not be activated before V_CCis restored to its normal

operating level and must be held active long enough to allow the oscillator to restart and

stabilize.

To exit power-down via an interrupt, external interrupt pin P3.2 or P3.3 must be kept low for at

least the specified required crystal oscillator start up time. Afterwards, the interrupt service rou-

tine starts at the rising edge of the external interrupt pin if the SFR bit AUXR.1 is set. If AUXR.1

is reset (cleared), execution starts after a self-timed interval of 2 ms (nominal) from the falling

edge of the external interrupt pin.

The user should not attempt to enter (or re-enter) the power-down mode for a minimum of 4 µs

until after one of the following conditions has occurred: Start of code execution (after any type of

reset), or Exit from power-down mode.

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19. Program Memory Lock Bits

The AT89S8253 has three lock bits that can be left unprogrammed (U) or can be programmed

(P) to obtain the additional features listed in Table 19-1.

When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset.

If the device is powered up without a reset, the latch initializes to a random value and holds that

value until reset is activated. The latched value of EA must agree with the current logic level at

that pin in order for the device to function properly.

Once programmed, the lock bits can only be unprogrammed with the Chip Erase operation in

either the parallel or serial modes.

Table 19-1. Lock Bit Protection Modes⁽¹⁾

Program Lock Bits

LB1

LB2

LB3 Protection Type

1

2

U

No internal memory lock feature.

MOVC instructions executed from external program memory are

disabled from fetching code bytes from internal memory. EA is sampled

and latched on reset and further programming of the Flash memory

(parallel or serial mode) is disabled.

P

U

3

4

P

U

P

Same as Mode 2, but parallel or serial verify are also disabled.

Same as Mode 3, but external execution is also disabled.

Note:

1. U = Unprogrammed

P = Programmed

20. Programming the Flash and EEPROM

Atmel’s AT89S8253 Flash microcontroller offers 12K bytes of In-System reprogrammable Flash

code memory and 2K bytes of EEPROM data memory.

The AT89S8253 is normally shipped with the on-chip Flash code and EEPROM data memory

arrays in the erased state (i.e. contents = FFH) and ready to be programmed. This device sup-

ports a parallel programming mode and a serial programming mode. The serial programming

mode provides a convenient way to reprogram the AT89S8253 inside the user’s system. The

parallel programming mode is compatible with conventional third-party Flash or EPROM

programmers.

The code and data memory arrays are mapped via separate address spaces in the parallel and

serial programming modes: 0000H to 2FFFH for code memory and 000H to 7FFH for data

memory.

The code and data memory arrays in the AT89S8253 are programmed byte-by-byte or by page

in either programming mode. To reprogram any non-blank byte in the parallel or serial mode, the

user needs to invoke the Chip Erase operation first to erase both arrays since there is no built-in

auto-erase capability.

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3286H–MICRO–9/05

Parallel Programming Algorithm: To program and verify the AT89S8253 in the parallel pro-

gramming mode, the following sequence is recommended (see Figure 26-1):

1. Power-up sequence:

a. Apply power between V_CCand GND pins.

b. Set RST pin to “H”.

c. Apply a 3 MHz to 24 MHz clock to XTAL1 pin and wait for at least 10 ms.

2. Set PSEN pin to “L”

a. ALE pin to “H”

b. EA pin to “H” and all other pins to “H”.

3. Raise EA/VPP to 12V to enable Flash programming, erase or verification. Enable the

P3.0 pull-up (10 KΩ typical) for RDY/BSY operation.

4. Apply the appropriate combination of “H” or “L” logic levels to pins P3.3, P3.4, P3.5,

P3.6, P3.7 to select one of the programming operations shown in the Flash Program-

ming Modes table.

5. Apply the desired byte address to pins P1.0 to P1.7 and P2.0 to P2.5.

a. Apply data to pins P0.0 to P0.7 for write code operation.

6. Pulse ALE/PROG once to load a byte in the code memory array, the data memory

array, or the lock bits.

7. Repeat steps 5 and 6, changing the address and data for up to 64 bytes in the code

memory page or 32 bytes in the data memory (EEPROM) page. When loading a page

with individual bytes, the interval between consecutive byte loads should be no longer

than 150 µs. Otherwise the device internally times out and assumes that the page load

sequence is completed, rejecting any further loads before the page programming

sequence has finished. This timing restriction also applies to Page Write of the 64-byte

User Row.

8. After the last byte of the current page has been loaded, wait for 5 ms or monitor the

RDY/BUSY pin until it transitions high. The page write cycle is self-timed and typically

takes less than 5 ms.

9. To verify the last byte of the page just programmed, bring pin P3.4 to “L” and read the

programmed data at pins P0.0 to P0.7.

10. Repeat steps 4 through 7 changing the address and data for the entire array or until the

end of the object file is reached.

11. Power-off sequence:

a. Tri-state the address and data inputs.

b. Disable the P3.0 pullup used for RDY/BUSY operation.

c. Set XTAL1 to “L”.

d. Set RST and EA pins to “L”.

e. Turn V_CCpower off.

Data Polling: The AT89S8253 features DATA Polling to indicate the end of any programming

cycle. During a write cycle in the parallel or serial programming mode, an attempted read of the

last loaded byte will result in the complement of the written datum on P0.7 (parallel mode), and

on the MSB of the serial output byte on MISO (serial mode). Once the write cycle has been com-

pleted, true data are valid on all outputs, and the next cycle may begin. DATA Polling may begin

any time after a write cycle has been initiated.

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Ready/Busy: The progress of byte programming in the parallel programming mode can also be

monitored by the RDY/BSY output signal. Pin P3.0 is pulled Low after ALE goes High during

programming to indicate BUSY. P3.0 is pulled High again when programming is done to indicate

READY. P3.0 needs an external pullup (typical 10 KΩ) when functioning as RDY/BSY.

Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed Code or

Data byte can be read back via the address and data lines for verification. The state of the lock

bits can also be verified directly in the parallel and serial programming modes.

Chip Erase: Both Flash and EEPROM arrays are erased electrically at the same time. In the

parallel programming mode, Chip Erase is initiated by using the proper combination of control

signals. The code and data arrays are written with all “1”s during the Chip Erase operation. The

User Row will also be erased if the UsrRowProEn fuse (Fuse3) = 0 (enabled state).

In the serial programming mode, a chip erase operation is initiated by issuing the Chip Erase

instruction. In this mode, Chip Erase is self-timed and also takes about 8 ms.

During Chip Erase, a serial read from any address location will return 00H at the data outputs.

Serial Programming Fuse: A programmable fuse is available to disable Serial Programming if

the user needs maximum system security. The Serial Programming Fuse can be enabled/dis-

abled in both the Parallel/Serial Programming Modes.

The AT89S8253 is shipped with the Serial Programming Mode enabled.

Reading the Signature Bytes: The signature bytes are read by the same procedure as a nor-

mal verification of locations 030H and 031H, except that P3.6 and P3.7 must be pulled to a logic

low. The values returned are as follows:

(030H) = 1EH indicates manufactured by Atmel

(031H) = 73H indicates AT89S8253

21. Programming Interface

Every code byte in the Flash and EEPROM arrays can be written, and the entire array can be

erased, by using the appropriate combination of control signals. The write operation cycle is self-

timed and once initiated, will automatically time itself to completion.

Most worldwide major programming vendors offer support for the Atmel AT89 microcontroller

series. Please contact your local programming vendor for the appropriate software revision.

22. Serial Downloading

Both the code and data memory arrays can be programmed using the serial SPI bus while RST

is pulled to V_CC. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After

RST is set high, the Programming Enable instruction must be executed first before other opera-

tions can be executed.

The Chip Erase operation turns the content of every memory location in both the Code and Data

arrays into FFH.

The code and data memory arrays have separate address spaces:

0000H to 2FFFH for code memory and 000H to 7FFH for data memory.

Either an external system clock is supplied at pin XTAL1 or a crystal needs to be connected

across pins XTAL1 and XTAL2. The maximum serial clock (SCK) frequency should be less than

1/16 of the crystal frequency. With a 24 MHz oscillator clock, the maximum SCK frequency is

1.5 MHz.

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3286H–MICRO–9/05

23. Serial Programming Algorithm

To program and verify the AT89S8253 in the serial programming mode, the following sequence

is recommended:

1. Power-up sequence:

a. Apply power between VCC and GND pins.

b. Set RST pin to “H”.

If a crystal is not connected across pins XTAL1 and XTAL2, apply a 3 MHz to 24 MHz clock to

XTAL1 pin and wait for at least 10 ms with RST pin high and P1.7 (SCK) low.

2. Enable serial programming by sending the Programming Enable serial instruction to pin

MOSI/P1.5. The frequency of the shift clock supplied at pin SCK/P1.7 needs to be less

than the CPU clock at XTAL1 divided by 16.

3. The code or data array is programmed one byte or one page at a time by supplying the

address and data together with the appropriate Write instruction. The write cycle is self-

timed and typically takes less than 4.0 ms at 5V.

4. Any memory location can be verified by using the Read instruction which returns the

content at the selected address at serial output MISO/P1.6.

5. At the end of a programming session, RST can be set low to commence normal

operation.

Power-off sequence (if needed):

1. Set XTAL1 to “L” (if a crystal is not used).

2. Set RST to “L”.

3. Turn V_CCpower off.

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24. Serial Programming Instruction

The Instruction Set for Serial Programming follows a 4-byte protocol and is shown in Table 24-1.

Table 24-1. Serial Programming Instruction Set

Instruction Format

Instruction

Byte 1

Byte 2

Byte 3

Byte 4

Byte n

Operation

1010 1100

0101 0011

xxxx xxxx

Enable Serial Programming while

RST is high

Programming Enable

1010 1100

0100 0000

0010 0000

0101 0000

0011 0000

1100 0000

1010 0000

1101 0000

1011 0000

1010 1100

100x xxxx

xxxx xxxx

Chip Erase both the 12K and 2K

memory arrays

Chip Erase

xx

Write Program Memory

(Byte Mode)

Write data to Program Memory –

Byte Mode

Read Program Memory

(Byte Mode)

Read data from Program Memory –

Byte Mode

00 0000

Write Program Memory

(Page Mode)

Write data to Program Memory –

Page Mode (64 bytes)

Byte 0 ... Byte 63

00 0000

Read Program Memory

(Page Mode)

Read data from Program Memory –

Page Mode (64 bytes)

Byte 0 ... Byte 63

xxxx

0001

x

Write Data Memory

(Byte Mode)

Write data to Data Memory

– Byte Mode

Read Data Memory

(Byte Mode)

Read data from Data Memory – Byte

Mode

0

0000

Write Data Memory

(Page Mode)

Write data to Data Memory – Page

Mode (32 bytes)

Byte 0 ... Byte 31

Read Data Memory

(Page Mode)

Read data from Data Memory

– Page Mode (32 bytes)

xxxx xxxx

Write User Fuses

Write user fuse bits (refer to next

page for the fuse definitions)

0010 0001

xxxx xxxx

xxxx

Read User Fuses

Write Lock Bits

Read back status of user fuse bits

1010 1100

0010 0100

0100 0010

0010 0010

1110

0

xxxx xxxx

xx

xxxx xxxx

Write the lock bits (write a “0” to

lock)

xxxx xxxx

xxxx x

Read back current status of the lock

bits (a programmed lock bit reads

back as a “0”)

Read Lock Bits

Write User Sgn. Byte

Read User Sgn. Byte

xx

0101 0010

0011 0010

0010 1000

xxxx xxxx

xx

Write User Sgn. Page

Read User Sgn. Page

Byte 0 ... Byte 63

Read Signature Byte

Read ATMEL Sgn. Byte

After Reset signal is high, SCK should be low for at least 64 system clocks before it goes high to clock in the enable data

bytes. No pulsing of Reset signal is necessary. SCK should be no faster than 1/16 of the system clock at pin XTAL1.

For Page Read/Write, the data always starts from byte 0 to 31 or 63. After the command byte and upper address byte are

latched, each byte thereafter is treated as data until all 32 or 64 bytes are shifted in/out. Then the next instruction will be

ready to be decoded.

39

3286H–MICRO–9/05

25. Flash and EEPROM Parallel Programming Modes

ALE

Address

P2.5:0,

P1.7:0

Data I/O

P0.7:0

Mode

RST

H

PSEN

EA

P3.3

P3.4

P3.5

P3.6

P3.7

Serial Prog. Modes⁽¹⁾

Chip Erase⁽²⁾

Page Write^(3)(4)(5)

Read

h

L

h

H

1.0 µs

H

12V

H

L

H

L

H

L

H

L

H

X

12K Code

2K Data

H

DI

ADDR

H

DO

ADDR

Page Write^(3)(4)(6)

Read

H

1.0 µs

H

L

DI

ADDR

2K Data

H

L

DO

ADDR

Bit - 1

D0 = 0

D1 = 0

D2 = 0

D0

X

Write Lock Bits⁽²⁾⁽⁴⁾

Read Lock Bits

Bit - 2

H

L

1.0 µs

12V

H

L

H

L

X

Bit - 3

X

Bit - 1

X

Bit - 2

H

D1

X

Bit - 3

D2

X

Page Write^(3)(4)(5)

Read

User Row

Sig. Row

H

L

1.0 µs

12V

H

L

H

L

H

L

DI

0 - 3FH

H

DO

0 - 3FH

Read

DO

0 - 3FH

SerialPrgEn

SerialPrgDis

x2 ClockEn

x2 ClockDis

UsrRowPrgEn

UsrRowPrgDis

External Clock En

Crystal Clock En

SerialPrg (Fuse1)

x2 Clock (Fuse2)

D0 = 0

D0 = 1

D1 = 0

D1 = 1

D2 = 0

D2 = 1

D3 = 0

D3 = 1

D0

X

Fuse1

Fuse2

Write

H

L

1.0 µs

12V

L

H

L

H

Fuse⁽²⁾⁽⁴⁾

Fuse3

Fuse4

D1

UsrRow Prg

(Fuse3)

Read Fuse

H

L

H

12V

H

L

H

D2

X

Clock Select

(Fuse4)

Notes: 1. See detailed timing for Serial Programming Mode.

2. Internally timed for 8.0 ms.

3. Internally timed for 8.0 ms. Programming begins 150 µs (minimum) after the last write pulse.

4. P3.0 is pulled low during programming to indicate RDY/BSY

5. 1 to 64 bytes can be programmed at a time per page.

6. 1 to 32 bytes can be programmed at a time per page.

40

AT89S8253

3286H–MICRO–9/05

AT89S8253

Figure 25-1. Programming the Flash/EEPROM Memory (Parallel Mode)

V_CC

AT89S8253

A0 - A7

V_CC

ADDR.

P1

ADDR.

P1

0000H/37FFH

PGM

DATA

PGM

DATA

P2.0 - P2.5

P0

P2.0 - P2.5

P0

A8 - A13

P3.3

P3.4

P3.5

P3.6

P3.7

P3.3

P3.4

P3.5

P3.6

P3.7

ALE

PROG

ALE

PROG

SEE FLASH

PROGRAMMING

MODES TABLE

SEE FLASH

PROGRAMMING

MODES TABLE

XTAL2

EA

V_PP

EA

V_PP

3-24 MHz

P3.0

RDY/BSY

(USE 10K

PULLUP)

P3.0

RDY/BSY

(USE 10K

PULLUP)

3-12 MHz

EXTERNAL

CLOCK

XTAL1

GND

RST

V_IH

XTAL1

GND

RST

V_IH

PSEN

Oscillator Bypass

Fuse (Fuse4) Off

Oscillator Bypass

Fuse (Fuse4) On

Figure 25-2. Verifying the Flash/EEPROM Memory (Parallel Mode)

V_CC

AT89S8253

A0 - A7

V_CC

ADDR.

P1

ADDR.

P1

PGM DATA

(USE 10K

PULLUPS)

PGM DATA

(USE 10K

PULLUPS)

0000H/37FFH

P0

P2.0 - P2.5

A8 - A13

P3.3

P3.4

P3.3

P3.4

ALE

EA

V_{I H}

ALE

V_{I H}

SEE FLASH

PROGRAMMING

MODES TABLE

SEE FLASH

PROGRAMMING

MODES TABLE

P3.5

P3.6

P3.7

P3.5

P3.6

P3.7

V_PP

XTAL2

EA

3-24 Mhz

3-12 MHz

EXTERNAL

CLOCK

V_{I H}

XTAL1

GND

RST

XTAL1

GND

RST

PSEN

Oscillator Bypass

Fuse (Fuse4) Off

Oscillator Bypass

Fuse (Fuse4) On

41

3286H–MICRO–9/05

Figure 25-3. Flash/EEPROM Serial Downloading

2.7V to 5.5V

AT89S8253

V_CC

INSTRUCTION

INPUT

INSTRUCTION

INPUT

P1.5/MOSI

P1.6/MISO

P1.7/SCK

P1.6/MISO

P1.7/SCK

DATA OUTPUT

CLOCK IN

DATA OUTPUT

CLOCK IN

XTAL2

3-24 MHz

3-12 MHz

EXTERNAL

CLOCK

XTAL1

GND

RST

V_IH

XTAL1

GND

RST

V_IH

Oscillator Bypass

Fuse (Fuse4) Off

Oscillator Bypass

Fuse (Fuse4) On

42

AT89S8253

3286H–MICRO–9/05

AT89S8253

26. Flash Programming and Verification Characteristics – Parallel Mode

T_A= 20°C to 30°C, V_CC= 4.0V to 5.5V

Min

Max

Units

Symbol

V_PP

Parameter

Programming Enable Voltage

Programming Enable Current

Oscillator Frequency

11.5

12.5

1.0

24

V

mA

MHz

µs

ms

µs

ms

µs

I_PP

1/t_CLCL

t_PWRUP

t_RHX

3

10

1

Power On to RST High ⁽¹⁾

RST High to XTAL Start

Oscillator Settling Time

High Voltage Settling Time

Mode Setup to PROG Low

Address Setup to PROG Low

Data Setup to PROG Low

PROG Width

t_OSTL

t_HSTL

t_MSTP

t_ASTP

t_DSTP

t_PGW

t_AHLD

t_DHLD

t_BLT

1

Address Hold after PROG

Data Hold after PROG

Byte Load Period

1

150

256

4.5

t_PHBL

t_WC

t_MHLD

t_VFY

PROG High to BUSY Low

Write Cycle Time⁽²⁾

Mode Hold After BUSY Low

Address to Data Verify Valid

PROG Setup to V_PPHigh

PROG Hold after V_PPLow

PROG Low to XTAL Halt

XTAL Halt to RST Low

RST Low to Power Off

10

1

t_PSTP

t_PHLD

t_PLX

10

1

t_XRL

1

t_PWRDN

1

Notes: 1. Power On occurs once V_CCreaches 2.4V.

2. 9 ms if Chip Erase.

43

3286H–MICRO–9/05

Figure 26-1. Flash/EEPROM Programming and Verification Waveforms – Parallel Mode

44

AT89S8253

3286H–MICRO–9/05

AT89S8253

27. Serial Downloading Waveforms (SPI Mode 1 −−> CPOL = 0, CPHA = 1)

7

4

6

5

3

2

1

0

SERIAL DATA INPUT

MOSI/P1.5

LSB

MSB

SERIAL DATA OUTPUT

MISO/P1.6

LSB

MSB

SCK/P1.7

28. Serial Programming Characteristics

Figure 28-1. Serial Programming Timing

Change

Outputs

Sample

Inputs

t

SLSH

SHSL

SCK

t

OVSL

t

SHOX

MOSI

MISO

t

SHIV

Table 28-1. Serial Programming Characteristics, T_A= -40°C to 85°C, V_CC= 2.7V - 5.5V (Unless Otherwise Noted)

Symbol

1/t_CLCL

t_CLCL

Parameter

Min

3

Typ

Max

24

Units

MHz

ns

Oscillator Frequency

Oscillator Period

41.6

33.3

t_SHSL

SCK Pulse Width High

SCK Pulse Width Low

MOSI Setup to SCK Low

MOSI Hold after SCK Low

SCK High to MISO Valid

Chip Erase Instruction Cycle Time

Serial Page Write Cycle Time

8 t_CLCL

t_CLCL

2 t_CLCL

10

ns

t_SLSH

ns

t_OVSL

t_SHOX

t_SHIV

ns

16

32

9

ns

t_ERASE

t_SWC

ms

4.5

45

3286H–MICRO–9/05

29. Absolute Maximum Ratings*

*NOTICE:

Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect device

reliability.

Operating Temperature.................................. -55°C to +125°C

Storage Temperature..................................... -65°C to +150°C

Voltage on Any Pin

with Respect to Ground.....................................-1.0V to +7.0V

Maximum Operating Voltage ............................................ 6.6V

DC Output Current...................................................... 15.0 mA

30. DC Characteristics

The values shown in this table are valid for T_A= -40°C to 85°C and V_CC= 2.7 to 5.5V, unless otherwise noted

Symbol

V_IL

Parameter

Condition

Min

-0.5V

Max

Input Low-voltage

Input Low-voltage (EA)

Input High-voltage

Output Low-voltage⁽¹⁾

(Except EA)

0.2 V_CC- 0.1V

0.2 V_CC- 0.3V

V_CC+ 0.5V

0.5V

V_IL1

-0.5V

V_IH

(Except XTAL1, RST)

(XTAL1, RST)

0.2 V_CC+ 0.9V

0.7 V_CC

V_IH1

V_OL

I_OL= 10 mA, V_CC= 4.0V, T_A= 85°C

I_OH= -60 µA, T_A= 85°C

I_OH= -25 µA, T_A= 85°C

I_OH= -10 µA, T_A= 85°C

2.4V

0.75 V_CC

0.9 V_CC

2.4V

Output High-voltage

When Weak Pull Ups are Enabled

(Ports 1, 2, 3, ALE, PSEN)

V_OH

I

_OH= -40 mA, T_A= 85°C

Output High-voltage

When Strong Pull Ups are Enabled

(Port 0 in External Bus Mode, P1, 2, 3,

ALE, PSEN)

V_OH1

I_OH= -25 mA, T_A= 85°C

0.75 V_CC

0.9 V_CC

I_OH= -10 mA, T_A= 85°C

I_IL

Logical 0 Input Current (Ports 1, 2, 3)

V_IN= 0.45V, V_CC= 5.5V, T_A= -40°C

-50 µA

Logical 1 to 0 Transition Current (Ports

1, 2, 3)

I_TL

V_IN= 2V, V_CC= 5.5V, T_A= -40°C

0.45V< V_IN< V_CC

-352 µA

I_LI

Input Leakage Current (Port 0, EA)

Reset Pull-down Resistor

Pin Capacitance

10 µA

150 KΩ

10 pF

RRST

C_IO

50 KΩ

Test Freq. = 1 MHz, T_A= 25°C

Active Mode, 12 MHz, V_CC= 5.5V, T_A= -40°C

Idle Mode, 12 MHz, V_CC= 5.5V, T_A= -40°C

V_CC= 5.5V, T_A= -40°C

10 mA

3.5 mA

100 µA

20 µA

Power Supply Current

Power-down Mode⁽²⁾

I_CC

V_CC= 4.0V, T_A= -40°C

Notes: 1. Under steady state (non-transient) conditions, I_OLmust be externally limited as follows:

Maximum I_OLper port pin: 10 mA,

Maximum I_OLper 8-bit port:15 mA,

Maximum total I_OLfor all output pins: 71 mA

If I_OLexceeds the test condition, V_OLmay exceed the related specification. Pins are not guaranteed to sink current greater

than the listed test conditions.

2. Minimum V_CCfor Power-down is 2V.

46

AT89S8253

3286H–MICRO–9/05

AT89S8253

31. AC Characteristics

The values shown in this table are valid for T_A= -40°C to 85°C and V_CC= 2.7 to 5.5V, unless otherwise noted.

Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other

outputs = 80 pF.

31.1 External Program and Data Memory Characteristics

Variable Oscillator

Symbol

1/t_CLCL

t_LHLL

Parameter

Min

0

Max

Units

MHz

ns

Oscillator Frequency

24

ALE Pulse Width

2t_CLCL- 12

t_CLCL- 12

t_CLCL- 16

t_AVLL

Address Valid to ALE Low

Address Hold after ALE Low

ALE Low to Valid Instruction In

ALE Low to PSEN Low

PSEN Pulse Width

t_LLAX

t_LLIV

4t_CLCL- 50

t_LLPL

t_CLCL- 12

t_PLPH

t_PLIV

3t_CLCL- 12

PSEN Low to Valid Instruction In

Input Instruction Hold after PSEN

Input Instruction Float after PSEN

PSEN to Address Valid

Address to Valid Instruction In

PSEN Low to Address Float

RD Pulse Width

3t_CLCL- 50

t_CLCL- 20

t_PXIX

-10

t_PXIZ

t_PXAV

t_AVIV

t_CLCL- 4

5t_CLCL- 50

20

t_PLAZ

t_RLRH

t_WLWH

t_RLDV

t_RHDX

t_RHDZ

t_LLDV

t_AVDV

t_LLWL

t_AVWL

t_QVWX

t_QVWH

t_WHQX

t_RLAZ

t_WHLH

6t_CLCL

WR Pulse Width

RD Low to Valid Data In

Data Hold after RD

5t_CLCL- 50

0

Data Float after RD

2t_CLCL- 20

8t_CLCL- 50

9t_CLCL- 50

3t_CLCL

ALE Low to Valid Data In

Address to Valid Data In

ALE Low to RD or WR Low

Address to RD or WR Low

Data Valid to WR Transition

Data Valid to WR High

Data Hold after WR

3t_CLCL- 24

4t_CLCL- 12

2t_CLCL- 24

8t_CLCL- 24

2t_CLCL- 24

RD Low to Address Float

RD or WR High to ALE High

0

t_CLCL- 10

t_CLCL+ 20

47

3286H–MICRO–9/05

32. External Program Memory Read Cycle

33. External Data Memory Read Cycle

48

AT89S8253

3286H–MICRO–9/05

AT89S8253

34. External Data Memory Write Cycle

35. External Clock Drive Waveforms

36. External Clock Drive

V_CC= 2.7V to 5.5V

Symbol

1/t_CLCL

t_CLCL

Parameter

Oscillator Frequency

Clock Period

High Time

Min

0

Max

Units

MHz

ns

24

41.6

12

t_CHCX

t_CLCX

ns

Low Time

12

ns

t_CLCH

Rise Time

5

ns

t_CHCL

Fall Time

ns

49

3286H–MICRO–9/05

37. Serial Port Timing: Shift Register Mode Test Conditions

The values in this table are valid for V_CC= 2.7V to 5.5V and Load Capacitance = 80 pF.

Variable Oscillator

Min Max

Symbol

t_XLXL

Parameter

Units

µs

Serial Port Clock Cycle Time

12t_CLCL-15

10t_CLCL-15

2t_CLCL-15

t_CLCL

t_QVXH

t_XHQX

t_XHDX

t_XHDV

Output Data Setup to Clock Rising Edge

Output Data Hold after Clock Rising Edge

Input Data Hold after Clock Rising Edge

Input Data Valid to Clock Rising Edge

ns

0

ns

38. Shift Register Mode Timing Waveforms

39. AC Testing Input/Output Waveforms⁽¹⁾

Note:

1. AC Inputs during testing are driven at V_CC- 0.5V for a logic 1 and 0.45V for a logic 0. Timing measurements are made at V_IH

min. for a logic 1 and V_ILmax. for a logic 0.

40. Float Waveforms⁽¹⁾

Note:

1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to

float when a 100 mV change from the loaded V_OH/V_OLlevel occurs.

50

AT89S8253

3286H–MICRO–9/05

AT89S8253

41. I_CCTest Condition, Active Mode, All Other Pins are Disconnected

V_CC

I_CC

V_CC

RST

V_CC

P0

EA

(NC)

XTAL2

CLOCK SIGNAL

XTAL1

V_SS

42. I_CCTest Condition, Idle Mode, All Other Pins are Disconnected

V_CC

I_CC

V_CC

RST

V_CC

P0

EA

(NC)

XTAL2

CLOCK SIGNAL

XTAL1

V_SS

43. Clock Signal Waveform for I_CCTests in Active and Idle Modes,

t

_CLCH= t_CHCL= 5 ns

V_CC- 0.5V

0.7 V_CC

t_CHCX

t_CLCH

0.2 V_CC- 0.1V

t_CHCL

0.45V

t_CHCX

t_CLCL

44. I_CCTest Condition, Power-down Mode, All Other Pins are Disconnected,

V_CC= 2V to 5.5V

V_CC

I_CC

V_CC

RST

V_CC

P0

EA

(NC)

XTAL2

XTAL1

VSS

51

3286H–MICRO–9/05

45. I_CC(Active Mode) Measurements

AT89S8253 I_CCActive @ 25^oC

With Internal Clock Oscillator

x1 Mode

4.00

3.50

3.00

2.50

2.00

1.50

3.0V

4.0V

5.0V

1

2

3

4

5

6

7

8

9

10 11 12

Frequency (MHz)

AT89S8253 I_CCActive @ 90^oC

With Internal Clock Oscillator

x1 Mode

4.00

3.50

3.00

2.50

2.00

1.50

3.0V

4.0V

5.0V

1

2

3

4

5

6

7

8

9

10 11 12

Frequency (MHz)

52

AT89S8253

3286H–MICRO–9/05

AT89S8253

46. I_CC(Idle Mode) Measurements

AT89S8253 I_CCIdle vs. Frequency,

T = 25°C

With Internal Clock Oscillator

x1 Mode

3

2.5

2

Vcc=3V

Vcc=4V

Vcc=5v

1.5

1

0.5

0

5

10

15

20

25

Frequency (MHz)

47. I_CC(Power Down Mode) Measurements

AT89S8253 I_CCin Power-down

2.5

2

0 deg C

1.5

1

25 deg C

90 deg C

0.5

0

1

2

3

4

5

6

7

V_CC(V)

53

3286H–MICRO–9/05

48. Ordering Information

48.1 Standard Package

Speed

(MHz)

Power

Supply

Ordering Code

Package

Operation Range

AT89S8253-24AC

AT89S8253-24JC

AT89S8253-24PC

AT89S8253-24SC

44A

44J

Commercial

2.7V to 5.5V

40P6

42PS6

(0°C to 70°C)

24

AT89S8253-24AI

AT89S8253-24JI

AT89S8253-24PI

AT89S8253-24SI

44A

44J

Industrial

40P6

42PS6

(-40°C to 85°C)

48.2 Green Package Option (Pb/Halide-free)

Speed

(MHz)

Power

Supply

Ordering Code

Package

Operation Range

AT89S8253-24AU

AT89S8253-24JU

AT89S8253-24PU

AT89S8253-24SU

44A

44J

Industrial

24

2.7V to 5.5V

40P6

42PS6

(-40°C to 85°C)

Package Type

44A

44-lead, Thin Plastic Gull Wing Quad Flat Package (TQFP)

44-lead, Plastic J-leaded Chip Carrier (PLCC)

44J

40P6

42PS6

40-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)

42-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)

54

AT89S8253

3286H–MICRO–9/05

AT89S8253

49. Package Information

49.1 44A – TQFP

PIN 1

B

PIN 1 IDENTIFIER

E1

E

e

D1

D

C

0˚~7˚

A2

A

A1

L

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

–

MAX

1.20

NOM

NOTE

SYMBOL

A

–

A1

A2

D

0.05

0.95

11.75

9.90

11.75

9.90

0.30

0.09

0.45

0.15

1.00

12.00

10.00

12.00

10.00

–

1.05

12.25

D1

E

10.10 Note 2

12.25

Notes:

1. This package conforms to JEDEC reference MS-026, Variation ACB.

2. Dimensions D1 and E1 do not include mold protrusion. Allowable

protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum

plastic body size dimensions including mold mismatch.

E1

B

10.10 Note 2

0.45

C

–

0.20

3. Lead coplanarity is 0.10 mm maximum.

L

–

0.75

e

0.80 TYP

10/5/2001

TITLE

DRAWING NO. REV.

2325 Orchard Parkway

San Jose, CA 95131

44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,

0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

44A

B

R

55

3286H–MICRO–9/05

49.2 44J – PLCC

1.14(0.045) X 45˚

PIN NO. 1

1.14(0.045) X 45˚

0.318(0.0125)

0.191(0.0075)

IDENTIFIER

D2/E2

E1

E

B1

B

e

A2

A1

D1

D

A

0.51(0.020)MAX

45˚ MAX (3X)

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

4.191

MAX

4.572

3.048

–

NOM

NOTE

SYMBOL

A

–

A1

A2

D

2.286

–

0.508

–

17.399

16.510

17.399

16.510

–

17.653

D1

E

–

16.662 Note 2

17.653

–

Notes:

1. This package conforms to JEDEC reference MS-018, Variation AC.

2. Dimensions D1 and E1 do not include mold protrusion.

Allowable protrusion is .010"(0.254 mm) per side. Dimension D1

and E1 include mold mismatch and are measured at the extreme

material condition at the upper or lower parting line.

E1

–

16.662 Note 2

16.002

D2/E2 14.986

–

B

0.660

0.330

–

0.813

3. Lead coplanarity is 0.004" (0.102 mm) maximum.

B1

e

0.533

1.270 TYP

10/04/01

DRAWING NO. REV.

TITLE

2325 Orchard Parkway

San Jose, CA 95131

44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)

44J

B

R

56

AT89S8253

3286H–MICRO–9/05

AT89S8253

49.3 40P6 – PDIP

D

1

E1

A

SEATING PLANE

A1

L

B

B1

e

E

COMMON DIMENSIONS

(Unit of Measure = mm)

0º ~ 15º REF

C

MIN

–

MAX

4.826

–

NOM

NOTE

SYMBOL

A

–

eB

A1

D

0.381

52.070

15.240

13.462

0.356

1.041

3.048

0.203

15.494

–

52.578 Note 2

15.875

E

–

E1

B

–

13.970 Note 2

0.559

–

B1

L

–

1.651

Notes:

1. This package conforms to JEDEC reference MS-011, Variation AC.

2. Dimensions D and E1 do not include mold Flash or Protrusion.

Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").

–

3.556

C

–

0.381

eB

e

17.526

2.540 TYP

09/28/01

DRAWING NO. REV.

40P6

TITLE

2325 Orchard Parkway

San Jose, CA 95131

40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual

Inline Package (PDIP)

B

R

57

3286H–MICRO–9/05

49.4 42PS6 – PDIP

D

1

E1

A

SEATING PLANE

A1

L

B

B1

e

E

COMMON DIMENSIONS

(Unit of Measure = mm)

0º ~ 15º REF

C

MIN

–

MAX

4.83

–

NOM

NOTE

SYMBOL

A

–

eB

A1

D

0.51

36.70

15.24

13.46

0.38

0.76

3.05

0.20

–

36.96 Note 2

15.88

E

–

E1

B

–

13.97 Note 2

0.56

–

B1

L

–

1.27

Notes:

1. This package conforms to JEDEC reference MS-011, Variation AC.

2. Dimensions D and E1 do not include mold Flash or Protrusion.

Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").

–

3.43

C

–

0.30

eB

e

18.55

1.78 TYP

11/6/03

DRAWING NO. REV.

42PS6

TITLE

2325 Orchard Parkway

San Jose, CA 95131

42PS6, 42-lead (0.600"/15.24 mm Wide) Plastic Dual

Inline Package (PDIP)

A

R

58

AT89S8253

3286H–MICRO–9/05

Atmel Corporation

Atmel Operations

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 487-2600

Memory

RF/Automotive

Theresienstrasse 2

Postfach 3535

74025 Heilbronn, Germany

Tel: (49) 71-31-67-0

Fax: (49) 71-31-67-2340

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 436-4314

Regional Headquarters

Microcontrollers

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 436-4314

1150 East Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906, USA

Tel: 1(719) 576-3300

Europe

Atmel Sarl

Route des Arsenaux 41

Case Postale 80

CH-1705 Fribourg

Switzerland

Tel: (41) 26-426-5555

Fax: (41) 26-426-5500

Fax: 1(719) 540-1759

Biometrics/Imaging/Hi-Rel MPU/

High Speed Converters/RF Datacom

Avenue de Rochepleine

La Chantrerie

BP 70602

44306 Nantes Cedex 3, France

Tel: (33) 2-40-18-18-18

Fax: (33) 2-40-18-19-60

BP 123

38521 Saint-Egreve Cedex, France

Tel: (33) 4-76-58-30-00

Fax: (33) 4-76-58-34-80

Asia

Room 1219

Chinachem Golden Plaza

77 Mody Road Tsimshatsui

East Kowloon

Hong Kong

Tel: (852) 2721-9778

Fax: (852) 2722-1369

ASIC/ASSP/Smart Cards

Zone Industrielle

13106 Rousset Cedex, France

Tel: (33) 4-42-53-60-00

Fax: (33) 4-42-53-60-01

1150 East Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906, USA

Tel: 1(719) 576-3300

Japan

9F, Tonetsu Shinkawa Bldg.

1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

Tel: (81) 3-3523-3551

Fax: (81) 3-3523-7581

Fax: 1(719) 540-1759

Scottish Enterprise Technology Park

Maxwell Building

East Kilbride G75 0QR, Scotland

Tel: (44) 1355-803-000

Fax: (44) 1355-242-743

Literature Requests

www.atmel.com/literature

Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any

intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-

TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY

WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR

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©

registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.

Printed on recycled paper.

3286H–MICRO–9/05

xM


型号：	AT89S8253-24PU
厂家：	ATMEL
描述：	8-bit Microcontroller with 12K Bytes Flash and 2K Bytes EEPROM 8位微控制器，带有12K字节的Flash和2K字节EEPROM 闪存微控制器和处理器外围集成电路光电二极管异步传输模式 PC ATM 可编程只读存储器电动程控只读存储器
文件：	总59页 (文件大小：963K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AT89S8253-24PU [ATMEL]

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