AT93C46DN-SH-B [ATMEL]
Three-wire Serial EEPROM 1K (128 x 8 or 64 x 16); 三线制串行EEPROM 1K （ 128 ×8或64 ×16 ）
| 型号： | AT93C46DN-SH-B |
| 厂家： | 
ATMEL |
| 描述： | Three-wire Serial EEPROM 1K (128 x 8 or 64 x 16) |
| 文件： | 总21页 (文件大小：507K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Low-voltage and Standard-voltage Operation
– 1.8 (VCC = 1.8V to 5.5V)
• User-selectable Internal Organization
– 1K: 128 x 8 or 64 x 16
• Three-wire Serial Interface
• 2 MHz Clock Rate (5V)
• Self-timed Write Cycle (5 ms max)
• High Reliability
Three-wire
Serial
EEPROM
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
• 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin mini-MAP (MLP 2x3), 8-lead
TSSOP and 8-ball dBGA2 Packages
• Die Sales: Wafer Form, Tape and Reel, and Bumped Wafers
1K (128 x 8 or 64 x 16)
Description
The AT93C46D provides 1024 bits of serial electrically erasable programmable read-
only memory (EEPROM), organized as 64 words of 16 bits each (when the ORG pin is
connected to VCC), and 128 words of 8 bits each (when the ORG pin is tied to
ground). The device is optimized for use in many industrial and commercial applica-
tions where low-power and low-voltage operations are essential. The AT93C46D is
available in space-saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin mini-
MAP (MLP 2x3), 8-lead TSSOP, and 8-lead dBGA2 packages.
AT93C46D
The AT93C46D is enabled through the Chip Select pin (CS) and accessed via a
three-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift
Clock (SK). Upon receiving a Read instruction at DI, the address is decoded and the
data is clocked out serially on the DO pin. The Write cycle is completely self-timed,
and no separate Erase cycle is required before Write. The Write cycle is only enabled
when the part is in the Erase/Write Enable state. When CS is brought high following
the initiation of a Write cycle, the DO pin outputs the Ready/Busy status of the part.
The AT93C46D is available in 1.8 (1.8V to 5.5V) version.
Table 0-1.
Pin Name
CS
Pin Configurations
Function
8-lead SOIC
8-lead dBGA2
8
7
6
5
1
2
3
4
VCC
NC
CS
SK
D1
D0
CS
SK
DI
1
8
7
6
5
VCC
NC
Chip Select
2
3
4
ORG
GND
ORG
GND
SK
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
DO
Bottom View
DI
8-lead PDIP
8-lead Ultra Thin mini-MAP (MLP 2x3)
DO
CS
1
2
3
4
8
7
6
5
VCC
8
7
6
5
1
2
3
4
VCC
NC
CS
SK
DI
GND
VCC
ORG
NC
SK
DI
NC
Power Supply
Internal Organization
No Connect
ORG
GND
ORG
GND
DO
DO
Bottom View
8-lead TSSOP
CS
SK
DI
1
2
3
4
8
VCC
7
6
5
NC
ORG
GND
DO
5193F–SEEPR–1/08
1. Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only, and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
Operating Temperature......................................−55°C to +125°C
Storage Temperature .........................................−65°C to +150°C
Voltage on Any Pin
with Respect to Ground........................................ −1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
Figure 1-1. Block Diagram
Notes: 1. When the ORG pin is connected to VCC, the “x 16” organization is selected. When it is con-
nected to ground, the “x 8” organization is selected. If the ORG pin is left unconnected and the
application does not load the input beyond the capability of the internal 1 Meg ohm pullup, then
the “x 16” organization is selected.
2. For the AT93C46D, if the “x 16” organization is the mode of choice and pin 6 (ORG) is left
unconnected, Atmel® recommends using AT93C46E device. For more details, see the
AT93C46E datasheet.
2
AT93C46D
5193F–SEEPR–1/08
AT93C46D
Table 1-1.
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V (unless otherwise noted)
Pin Capacitance(1)
Symbol
COUT
CIN
Test Conditions
Max
5
Units
pF
Conditions
VOUT = 0V
VIN = 0V
Output Capacitance (DO)
Input Capacitance (CS, SK, DI)
5
pF
Note:
1. This parameter is characterized and is not 100% tested.
Table 1-2.
DC Characteristics
Applicable over recommended operating range from: TAI = −40°C to +85°C, VCC = +1.8V to +5.5V (unless otherwise noted)
Symbol
VCC1
Parameter
Test Condition
Min
1.8
2.7
4.5
Typ
Max
5.5
Unit
V
Supply Voltage
Supply Voltage
Supply Voltage
VCC2
5.5
V
VCC3
5.5
V
READ at 1.0 MHz
WRITE at 1.0 MHz
CS = 0V
0.5
0.5
0.4
6.0
10.0
0.1
0.1
2.0
mA
mA
µA
µA
µA
µA
µA
ICC
Supply Current
VCC = 5.0V
2.0
ISB1
ISB2
ISB3
IIL
Standby Current
Standby Current
Standby Current
Input Leakage
VCC = 1.8V
1.0
VCC = 2.7V
CS = 0V
10.0
15.0
1.0
VCC = 5.0V
CS = 0V
VIN = 0V to VCC
VIN = 0V to VCC
IOL
Output Leakage
1.0
(1)
VIL1
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
−0.6
2.0
0.8
2.7V ≤ VCC ≤ 5.5V
V
V
(1)
VIH1
VCC + 1
VCC x 0.3
VCC + 1
0.4
(1)
VIL2
−0.6
1.8V ≤ VCC ≤ 2.7V
(1)
VIH2
VCC x 0.7
VOL1
VOH1
VOL2
VOH2
IOL = 2.1 mA
IOH = −0.4 mA
OL = 0.15 mA
IOH = −100 µA
V
V
V
V
2.7V ≤ VCC ≤ 5.5V
2.4
I
0.2
1.8V ≤ VCC ≤ 2.7V
VCC – 0.2
Note:
1. VIL min and VIH max are reference only and are not tested.
3
5193F–SEEPR–1/08
Table 1-3.
AC Characteristics
Applicable over recommended operating range from TAI = −40°C to + 85°C, VCC = +2.7V to +5.5V,
CL = 1 TTL Gate and 100 pF (unless otherwise noted)
Symbol
Parameter
Test Condition
Min
Typ
Max
Units
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
0
0
0
2
1
0.25
SK Clock
Frequency
fSK
MHz
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
250
1000
tSKH
tSKL
tCS
SK High Time
SK Low Time
ns
ns
ns
ns
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
250
1000
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
250
1000
Minimum CS
Low Time
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
50
50
200
tCSS
CS Setup Time
Relative to SK
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
100
100
400
tDIS
tCSH
tDIH
DI Setup Time
CS Hold Time
DI Hold Time
Relative to SK
Relative to SK
Relative to SK
ns
ns
ns
0
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
100
100
400
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
250
1000
tPD1
tPD0
tSV
Output Delay to “1”
Output Delay to “0”
CS to Status Valid
AC Test
AC Test
AC Test
ns
ns
ns
ns
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
250
1000
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
250
1000
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
100
150
400
CS to DO in High
Impedance
AC Test
CS = VIL
tDF
1.8V ≤ VCC ≤ 5.5V
0.1
1M
3
5
ms
tWP
Write Cycle Time
5.0V, 25°C
(1)
Endurance
Write Cycles
Note:
1. This parameter is ensured by characterization.
4
AT93C46D
5193F–SEEPR–1/08
AT93C46D
Table 1-4.
Instruction Set for the AT93C46D
Address
Op
Data
Instruction
SB
Code
x 8
x 16
x 8
x 16
Comments
Reads data stored in memory, at
specified address
READ
1
10
A6 – A0
A5 – A0
Write enable must precede all
programming modes
EWEN
1
00
11XXXXX
11XXXX
ERASE
WRITE
1
1
11
01
A6 – A0
A6 – A0
A5 – A0
A5 – A0
Erases memory location An – A0
Writes memory location An – A0
D7 – D0
D7 – D0
D15 – D0
Erases all memory locations. Valid
only at VCC = 4.5V to 5.5V
ERAL
1
00
10XXXXX
10XXXX
Writes all memory locations. Valid
only at VCC = 4.5V to 5.5V
WRAL
EWDS
1
1
00
00
01XXXXX
00XXXXX
01XXXX
00XXXX
D15 – D0
Disables all programming instructions
Note:
The Xs in the address field represent DON’T CARE values and must be clocked.
2. Functional Description
The AT93C46D is accessed via a simple and versatile three-wire serial communication inter-
face. Device operation is controlled by seven instructions issued by the host processor. A valid
instruction starts with a rising edge of CS and consists of a start bit (logic “1”) followed by the
appropriate op code and the desired memory address location.
READ (READ): The Read (READ) instruction contains the address code for the memory loca-
tion to be read. After the instruction and address are decoded, data from the selected memory
location is available at the serial output pin DO. Output data changes are synchronized with the
rising edges of serial clock SK. It should be noted that a dummy bit (logic “0”) precedes the 8- or
16-bit data output string.
ERASE/WRITE ENABLE (EWEN): To assure data integrity, the part automatically goes into the
Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable (EWEN)
instruction must be executed first before any programming instructions can be carried out.
Please note that once in the EWEN state, programming remains enabled until an EWDS instruc-
tion is executed or VCC power is removed from the part.
ERASE (ERASE): The Erase (ERASE) instruction programs all bits in the specified memory
location to the logical “1” state. The self-timed erase cycle starts once the Erase instruction and
address are decoded. The DO pin outputs the Ready/Busy status of the part if CS is brought
high after being kept low for a minimum of 250 ns (tCS). A logic “1” at pin DO indicates that the
selected memory location has been erased and the part is ready for another instruction.
WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be written
into the specified memory location. The self-timed programming cycle tWP starts after the last bit
of data is received at serial data input pin DI. The DO pin outputs the Read/Busy status of the
part if CS is brought high after being kept low for a minimum of 250 ns (tCS). A logic “0” at DO
indicates that programming is still in progress. A logic “1” indicates that the memory location at
the specified address has been written with the data pattern contained in the instruction and the
5
5193F–SEEPR–1/08
part is ready for further instructions. A Ready/Busy status cannot be obtained if the CS is
brought high after the end of the self-timed programming cycle tWP.
ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the memory array
to the logic “1” state and is primarily used for testing purposes. The DO pin outputs the
Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns
(tCS). The ERAL instruction is valid only at VCC = 5.0V ± 10%.
WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations with the
data patterns specified in the instruction. The DO pin outputs the Ready/Busy status of the part if
CS is brought high after being kept low for a minimum of 250 ns (tCS). The WRAL instruction is
valid only at VCC = 5.0V 10%.
ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, the Erase/Write
Disable (EWDS) instruction disables all programming modes and should be executed after all
programming operations. The operation of the Read instruction is independent of both the
EWEN and EWDS instructions and can be executed at any time.
6
AT93C46D
5193F–SEEPR–1/08
AT93C46D
3. Timing Diagrams
Figure 3-1. Synchronous Data Timing
μs
Note:
1. This is the minimum SK period.
Table 3-1.
Organization Key for Timing Diagrams
AT93C46D (1K)
I/O
AN
DN
x 8
A6
x 16
A5
D7
D15
Figure 3-2. READ Timing
tCS
High Impedance
7
5193F–SEEPR–1/08
Figure 3-3. EWEN Timing
tCS
CS
SK
DI
...
1
0
0
1
1
Figure 3-4. EWDS Timing
tCS
CS
SK
DI
...
0
0
0
1
0
Figure 3-5. WRITE Timing
tCS
CS
SK
DI
...
...
AN
DN
1
0
1
A0
D0
HIGH IMPEDANCE
BUSY
READY
DO
tWP
8
AT93C46D
5193F–SEEPR–1/08
AT93C46D
Figure 3-6. WRAL Timing(1)
tCS
CS
SK
DI
1
0
0
0
1
...
DN ... D0
BUSY
HIGH IMPEDANCE
DO
READY
tWP
Note:
1. Valid only at VCC = 4.5V to 5.5V.
Figure 3-7. ERASE Timing
tCS
CS
STANDBY
CHECK
STATUS
SK
DI
A0
1
1
1
AN
...
AN-1 AN-2
tDF
tSV
HIGH IMPEDANCE
HIGH IMPEDANCE
BUSY
DO
READY
tWP
9
5193F–SEEPR–1/08
Figure 3-8. ERAL Timing(1)
tCS
CS
STANDBY
CHECK
STATUS
SK
DI
1
0
0
1
0
tDF
tSV
BUSY
HIGH IMPEDANCE
HIGH IMPEDANCE
DO
READY
tWP
Note:
1. Valid only at VCC = 4.5V to 5.5V.
10
AT93C46D
5193F–SEEPR–1/08
AT93C46D
4. AT93C46D Ordering Information
Ordering Code
Voltage
1.8
Package
8P3
Operation Range
AT93C46D-PU (Bulk form only)
AT93C46DN-SH-B(1) (NiPdAu Lead finish)
AT93C46DN-SH-T(2) (NiPdAu Lead finish)
AT93C46D-TH-B(1) (NiPdAu Lead finish)
AT93C46D-TH-T(2) (NiPdAu Lead finish)
AT93C46DY6-YH-T(2) (NiPdAu Lead finish)
AT93C46DU3-UU-T(2)
1.8
8S1
Lead-free/Halogen-free/
Industrial Temperature
1.8
8S1
1.8
8A2
(−40°C to 85°C)
1.8
8A2
1.8
8Y6
1.8
8U3-1
Industrial
AT93C46D-W-11(3)
1.8
Die Sale
(−40°C to 85°C)
Notes: 1. “-B” denotes bulk
2. “-T” denotes tape and reel. SOIC = 4K per reel. TSSOP, Ultra Thin Mini MAP, and dBGA2 = 5K per reel.
3. Available in tape and reel, and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request.
Please contact Serial Interface Marketing.
Package Type
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
8-ball, Die Ball Grid Array Package (dBGA2)
8P3
8S1
8A2
8U3-1
8Y6
8-lead, 2.00 mm x 3.00 mm Body, 0.50mm Pitch, Ultra-Thin Mini-MAO, Dual No Lead Package. (DFN), (MLP 2x3mm)
Options
−1.8
Low Voltage (1.8V to 5.5V)
11
5193F–SEEPR–1/08
5. Part Marking Scheme
5.1
AT93C46D 8-PDIP
TOP MARK
Seal Year
Y = SEAL YEAR
WW = SEAL WEEK
02 = Week 2
|
Seal Week
6: 2006
0: 2010
|
|
|
7: 2007
8: 2008
9: 2009
1: 2011
2: 2012
3: 2013
04 = Week 4
:: : :::: :
:: : :::: ::
|---|---|---|---|---|---|---|---|
A
T
M
L
U
Y
W
W
|---|---|---|---|---|---|---|---|
50 = Week 50
52 = Week 52
4
6
D
1
|---|---|---|---|---|---|---|---|
Lot Number
*
Lot Number to Use ALL Characters in Marking
|---|---|---|---|---|---|---|---|
|
BOTTOM MARK
Pin 1 Indicator (Dot)
No Bottom Mark
5.2
AT93C46D 8-SOIC
TOP MARK
Seal Year
Y = SEAL YEAR
WW = SEAL WEEK
02 = Week 2
|
Seal Week
6: 2006
0: 2010
|
|
|
7: 2007
8: 2008
9: 2009
1: 2011
2: 2012
3: 2013
04 = Week 4
:: : :::: :
:: : :::: ::
|---|---|---|---|---|---|---|---|
A
T
M
L
H
Y
W
W
|---|---|---|---|---|---|---|---|
50 = Week 50
52 = Week 52
4
6
D
1
|---|---|---|---|---|---|---|---|
Lot Number
*
Lot Number to Use ALL Characters in Marking
|---|---|---|---|---|---|---|---|
|
BOTTOM MARK
Pin 1 Indicator (Dot)
No Bottom Mark
12
AT93C46D
5193F–SEEPR–1/08
AT93C46D
5.3
AT93C46D 8-TSSOP
TOP MARK
Pin 1 Indicator (Dot)
Y = SEAL YEAR
WW = SEAL WEEK
|
6: 2006
7: 2007
8: 2008
9: 2009
0: 2010
02 = Week 2
04 = Week 4
:: : :::: :
:: : :::: ::
|---|---|---|---|
1: 2011
2: 2012
3: 2013
*
H
Y
W
W
|---|---|---|---|---|
1 *
|---|---|---|---|---|
4
6
D
50 = Week 50
52 = Week 52
BOTTOM MARK
|---|---|---|---|---|---|---|
C
0
0
|---|---|---|---|---|---|---|
A
A
A
A
A
A
A
|---|---|---|---|---|---|---|
<- Pin 1 Indicator
5.4
AT93C46D 8-Ultra Thin Mini MAP
TOP MARK
Y = YEAR OF ASSEMBLY
|---|---|---|
4
6
D
XX = ATMEL LOT NUMBER TO COORESPOND WITH
NSEB TRACE CODE LOG BOOK.
|---|---|---|
H
1
(e.g. XX = AA, AB, AC,...AX, AY, AZ)
|---|---|---|
Y
X
X
|---|---|---|
Y = SEAL YEAR
*
|
6: 2006
7: 2007
8: 2008
0: 2010
1: 2011
2: 2012
Pin 1 Indicator (Dot)
9: 2009
3: 2013
13
5193F–SEEPR–1/08
5.5
AT93C46D dBGA2
TOP MARK
LINE 1------->
LINE 2------->
46DU
YMTC
|<-- Pin 1 This Corner
Y = ONE DIGIT YEAR CODE
4: 2004
5: 2005
6: 2006
7: 2007
8: 2008
9: 2009
M = SEAL MONTH (USE ALPHA DESIGNATOR A-L)
A = JANUARY
B = FEBRUARY
" " """""""
J = OCTOBER
K = NOVEMBER
L = DECEMBER
TC = TRACE CODE (ATMEL LOT
NUMBERS TO CORRESPOND
WITH ATK TRACE CODE LOG BOOK)
14
AT93C46D
5193F–SEEPR–1/08
AT93C46D
6. Package Information
8P3 - PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
MIN
MAX
NOM
NOTE
SYMBOL
D1
A2 A
A
0.210
0.195
0.022
0.070
0.045
0.014
0.400
2
A2
b
0.115
0.014
0.045
0.030
0.008
0.355
0.005
0.300
0.240
0.130
0.018
0.060
0.039
0.010
0.365
5
6
6
b2
b3
c
D
3
3
4
3
b2
L
D1
E
b3
4 PLCS
0.310
0.250
0.325
0.280
b
E1
e
0.100 BSC
0.300 BSC
0.130
Side View
eA
L
4
2
0.115
0.150
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
8P3
B
R
15
5193F–SEEPR–1/08
8S1 - JEDEC SOIC
C
1
E
E1
L
N
Ø
TOP VIEW
END VIEW
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
MIN
1.35
0.10
MAX
1.75
0.25
NOM
NOTE
SYMBOL
A1
A
–
–
A1
b
C
D
E1
E
0.31
0.17
4.80
3.81
5.79
–
0.51
0.25
5.05
3.99
6.20
–
–
D
–
–
SIDE VIEW
e
1.27 BSC
L
0.40
0°
–
–
1.27
8°
θ
Note:
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
3/17/05
TITLE
DRAWING NO.
REV.
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
8S1
C
Small Outline (JEDEC SOIC)
R
16
AT93C46D
5193F–SEEPR–1/08
AT93C46D
8A2 - TSSOP
3
2 1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
MAX
NOM
3.00
NOTE
SYMBOL
D
2.90
3.10
2, 5
A
b
E
6.40 BSC
4.40
E1
A
4.30
–
4.50
1.20
1.05
0.30
3, 5
4
–
A2
b
0.80
0.19
1.00
e
A2
–
D
e
0.65 BSC
0.60
L
0.45
0.75
Side View
L1
1.00 REF
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
5/30/02
DRAWING NO.
TITLE
REV.
2325 Orchard Parkway
San Jose, CA 95131
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
B
8A2
R
17
5193F–SEEPR–1/08
8U3-1 – dBGA2
E
D
1.
b
A1
PIN 1 BALL PAD CORNER
A2
Top View
A
PIN 1 BALL PAD CORNER
Side Vie
w
1
2
3
4
(d1)
d
7
6
5
8
e
COMMON DIMENSIONS
(Unit of Measure - mm)
(e1)
SYMBOL
NOM
MIN
MAX
NOTE
Bottem View
A
0.73
0.09
0.40
0.20
0.79
0.85
0.19
0.50
0.30
8 SOLDER BALLS
A1
A2
b
0.14
0.45
0.25
2
D
1.50 BSC
2.0 BSC
0.50 BSC
0.25 REF
1.00 BSC
0.25 REF
This drawing is for general information only.
Dimension 'b' is measured at maximum solder ball diameter.
1.
2.
E
e
e1
d
d1
5/3/05
TITLE
REV.
DRAWING NO.
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
8U3-1, 8-ball, 1.50 x 2.00 mm Body, 0.50 mm pitch,
PO8U3-1
B
R
Small Die Ball Grid Array Package (dBGA2)
18
AT93C46D
5193F–SEEPR–1/08
AT93C46D
8Y6 – MLP 2x3
A
D2
b
((88XX))
Pin 11
Inddeex
Area
Pinn 11 ID
L (8X)
D
e (66X)
A2
A1
1.500 RREEFF.
A3
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
MAX
NOM
2.00 BSC
3.00 BSC
1.50
NOTE
SYMBOL
D
E
D2
E2
A
1.40
1.60
1.40
0.60
0.05
0.55
-
-
-
-
A1
A2
A3
L
0.0
-
0.02
-
0.20 REF
0.30
0.20
0.20
0.40
e
0.50 BSC
0.25
b
0.30
2
Notes:
1. This drawing is for general information only. Refer to JEDEC Drawing MO-229, for proper dimensions,
tolerances, datums, etc.
2. Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the
terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area.
3. Soldering the large thermal pad is optional, but not recommended. No electrical connection is accomplished to the
device through this pad, so if soldered it should be tied to ground
10/16/07
DRAWING NO. REV.
TITLE
2325 Orchard Parkway
San Jose, CA 95131
8Y6, 8-lead 2.0 x 3.0 mm Body, 0.50 mm Pitch, Utlra Thin Mini-Map,
Dual No Lead Package (DFN) ,(MLP 2x3)
8Y6
D
R
19
5193F–SEEPR–1/08
7. Revision History
Doc. Rev.
Date
Comments
5193F
5193E
1/2008
11/2007
Removed ‘preliminary’ status
Modified ‘max’ value in AC Characteristics table
Moved Pinout figure
Added new feature for Die Sales
Modified Ordering Information table layout
Modified Park Marking Schemes
5193D
5193C
8/2007
6/2007
Updated to new template
Added Product Markup Scheme
Added Technical email contact
5193C
5193B
5193A
3/2007
2/2007
1/2007
Corrected Figures 4 and 5.
Added ‘Ultra Thin’ description to 8-lead Mini-MAP package.
Initial document release.
20
AT93C46D
5193F–SEEPR–1/08
Headquarters
International
Atmel Corporation
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Sales Contact
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www.atmel.com/literature
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5193F–SEEPR–1/08
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AT93C46DN-SP25-T
EEPROM, 64X16, Serial, CMOS, PDSO8, 0.150 INCH, HALOGEN AND LEAD FREE, PLASTIC, MS-012, SOIC-8
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