ATF22V10C-10JJ [ATMEL]
Flash PLD, 10ns, CMOS, PQCC28, PLASTIC, MS-018AB, LCC-28;
| 型号： | ATF22V10C-10JJ |
| 厂家： | 
ATMEL |
| 描述： | Flash PLD, 10ns, CMOS, PQCC28, PLASTIC, MS-018AB, LCC-28 |
| 文件： | 总22页 (文件大小：391K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Industry-standard Architecture
– Low-cost, Easy-to-use Software Tools
• High-speed, Electrically Erasable Programmable Logic Devices
– 5 ns Maximum Pin-to-pin Delay
• CMOS- and TTL-compatible Inputs and Outputs
– Latch Feature Holds Inputs to Previous Logic States
• Pin-controlled Standby Power (10 µA Typical)
• Advanced Flash Technology
High-
– Reprogrammable
– 100% Tested
performance
EE PLD
• High-reliability CMOS Process
– 20-year Data Retention
– 100 Erase/Write Cycles
– 2,000V ESD Protection
– 200 mA Latch-up Immunity
ATF22V10C
• Dual Inline and Surface Mount Packages in Standard Pinouts
• PCI-compliant
ATF22V10CQ
• True Input Transition Detection “Z” and “QZ” Version
• Green Package Options (Pb/Halide-free/RoHS Compliant) Available
See separate datasheet
for ATF22V10CZ and
ATF22V10CQZ options.
1. Description
The ATF22V10C is a high-performance CMOS (electrically erasable) programmable
logic device (PLD) that utilizes Atmel’s proven electrically erasable Flash memory
technology. Speeds down to 5 ns and power dissipation as low as 100 µA are offered.
All speed ranges are specified over the full 5V 10% range for industrial temperature
ranges, and 5V 5% for commercial temperature ranges.
Several low-power options allow selection of the best solution for various types of
power-limited applications. Each of these options significantly reduces total system
power and enhances system reliability.
0735S–PLD–8/08
Figure 1-1. Logic Diagram
2. Pin Configurations
Table 2-1.
Pin Name
CLK
Pin Configurations (All Pinouts Top View)
Function
Clock
IN
Logic Inputs
Bi-directional Buffers
Ground
I/O
GND
VCC
+5V Supply
Power-down
PD
Figure 2-1. TSSOP
Figure 2-2. DIP/SOIC
CLK/IN
IN
1
2
3
4
5
6
7
8
9
24 VCC
23 I/O
22 I/O
21 I/O
20 I/O
19 I/O
18 I/O
17 I/O
16 I/O
15 I/O
14 I/O
13 IN
CLK/IN
IN
1
24
23
22
21
20
19
18
17
16
15
14
13
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
2
IN
IN
3
IN/PD
IN
IN/PD
IN
4
5
IN
IN
6
IN
IN
7
IN
IN
8
IN
IN
9
IN 10
IN 11
IN
10
11
12
IN
GND 12
GND
Figure 2-3. PLCC
IN/PD
IN
5
6
7
8
9
25 I/O
24 I/O
23 I/O
22 GND*
21 I/O
20 I/O
19 I/O
IN
GND*
IN
IN 10
IN 11
Note:
For all PLCCs (except “-5”), pins 1, 8, 15
and 22 can be left unconnected. How-
ever, if they are connected, superior
performance will be achieved.
2
ATF22V10C(Q)
0735S–PLD–8/08
ATF22V10C(Q)
3. Absolute Maximum Ratings*
Temperature under Bias .................................. -40°C to +85°C
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on Input Pins
with Respect to Ground
during Programming .....................................-2.0V to +14.0V(1)
Note:
1. Minimum voltage is -0.6V DC, which may under-
shoot to -2.0V for pulses of less than 20 ns.
Maximum output pin voltage is VCC + 0.75V DC,
which may overshoot to 7.0V for pulses of less
than 20 ns.
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
4. DC and AC Operating Conditions
Commercial
Industrial
-40°C - 85°C
5V 10%
Operating Temperature (Ambient)
VCC Power Supply
0°C - 70°C
5V 5%
3
0735S–PLD–8/08
4.1
DC Characteristics
Symbol Parameter
Condition
Min
Typ
Max
Units
Input or I/O Low
Leakage Current
IIL
0 ≤VIN ≤VIL (Max)
-35.0
-10.0
µA
Input or I/O High
Leakage Current
IIH
3.5 ≤VIN ≤VCC
10.0
µA
C-5, 7, 10
C-10
Com.
Ind.
85.0
90.0
65.0
65.0
35.0
35.0
130.0
140.0
90.0
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
VCC = Max,
VIN = Max,
Outputs Open
C-15
Com.
Ind.
Power Supply Current,
Standby
ICC
C-15
115.0
55.0
CQ-15
CQ-15
C-5, 7, 10
C-10
Com.
Ind.
70.0
Com.
Ind.
150.0
160.0
90.0
C-15
Com.
Ind.
70.0
70.0
40.0
40.0
10.0
10.0
Clocked Power Supply
Current
VCC = Max, Outputs Open,
f = 15 MHz
ICC2
C-15
90.0
CQ-15
CQ-15
Com.
Ind.
60.0
80.0
VCC = Max
Com.
Ind.
100.0
100.0
Power Supply Current,
PD Mode
IPD
V
IN = 0, Max
OUT = 0.5V
µA
Output Short Circuit
Current
(1)
IOS
V
-130.0
mA
VIL
VIH
Input Low Voltage
Input High Voltage
-0.5
2.0
0.8
V
V
VCC+0.75
Com.,
Ind.
IOL = 16 mA
IOL = 12 mA
IOH = -4.0 mA
0.5
0.5
V
V
V
V
IN = VIH or VIL,
VOL
Output Low Voltage
VCC = Min
Mil.
VIN = VIH or VIL,
VOH
Output High Voltage
2.4
VCC = Min
Note:
1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
4
ATF22V10C(Q)
0735S–PLD–8/08
ATF22V10C(Q)
4.2
AC Waveforms (1)
Note:
1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless oth-
erwise specified.
4.3
AC Characteristics(1)
-5
-7
-10
-15
Symbol Parameter
Min
1.0
1.0
Max
Min
3.0
2.0
Max
Min
3.0
2.0
Max
Min
3.0
2.0
Max
Units
Input or Feedback to Combinatorial
Output
tPD
5.0
7.5
10.0
15.0
ns
tCO
tCF
tS
Clock to Output
4.0
2.5
4.5(2)
2.5
6.5
2.5
8.0
2.5
ns
ns
Clock to Feedback
Input or Feedback Setup Time
Hold Time
3.0
0
3.5
0
4.5
0
10.0
0
ns
tH
ns
External Feedback 1/(tS + tCO
Internal Feedback 1/(tS + tCF
No Feedback 1/(tWH + tWL
Clock Width (tWL and tWH
Input or I/O to Output Enable
)
142.0
166.0
166.0
3.0
125.0(3)
142.0
166.0
3.0
90.0
117.0
125.0
3.0
55.5
80.0
83.3
6.0
MHz
MHz
MHz
ns
fMAX
)
)
tW
)
tEA
tER
2.0
6.0
5.0
3.0
7.5
7.5
3.0
10.0
9.0
3.0
15.0
15.0
ns
Input or I/O to Output Disable
2.0
3.0
3.0
3.0
ns
Input or I/O to Asynchronous Reset of
Register
tAP
3.0
7.0
3.0
10.0
3.0
12.0
3.0
20.0
ns
tAW
tAR
tSP
Asynchronous Reset Width
5.5
4.0
4.0
7.0
5.0
4.5
8.0
6.0
6.0
15.0
10.0
10.0
ns
ns
ns
Asynchronous Reset Recovery Time
Setup Time, Synchronous Preset
Synchronous Preset to Clock
Recovery Time
tSPR
4.0
5.0
8.0
10.0
ns
Notes: 1. See ordering information for valid part numbers.
2. 5.5 ns for DIP package devices.
3. 111 MHz for DIP package devices.
5
0735S–PLD–8/08
4.4
Power-down AC Characteristics(1)(2)(3)
-5
-7
-10
-15
Symbol
tIVDH
Parameter
Min
5.0
0
Max
Min
7.5
0
Max
Min
10.0
0
Max
Min
15.0
0
Max
Units
ns
Valid Input before PD High
Valid OE before PD High
Valid Clock before PD High
Input Don’t Care after PD High
OE Don’t Care after PD High
Clock Don’t Care after PD High
PD Low to Valid Input
tGVDH
tCVDH
tDHIX
ns
0
0
0
ns
5.0
5.0
7.0
7.0
10.0
10.0
10.0
10.0
25.0
25.0
30.0
15.0
15.0
15.0
15.0
30.0
30.0
35.0
ns
tDHGX
tDHCX
tDLIV
ns
5.0
7.0
ns
5.0
7.5
ns
tDLGV
tDLCV
tDLOV
PD Low to Valid OE
15.0
15.0
20.0
20.0
20.0
25.0
ns
PD Low to Valid Clock
PD Low to Valid Output
ns
ns
Notes: 1. Output data is latched and held.
2. High-Z outputs remain high-Z.
3. Clock and input transitions are ignored.
4.5
Input Test Waveforms
4.5.1
Input Test Waveforms and Measurement Levels
4.5.2
Commercial Output Test Loads
4.6
Pin Capacitance
Table 4-1.
Pin Capacitance (f = 1 MHz, T = 25°C(1))
Typ
5
Max
8
Units
pF
Conditions
VIN = 0V
CIN
COUT
6
8
pF
VOUT = 0V
Note:
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100%
tested.
6
ATF22V10C(Q)
0735S–PLD–8/08
ATF22V10C(Q)
4.7
Power-up Reset
The registers in the ATF22V10Cs are designed to reset during power-up. At a point delayed
slightly from VCC crossing VRST, all registers will be reset to the low state. The output state will
depend on the polarity of the output buffer.
This feature is critical for state machine initialization. However, due to the asynchronous nature
of reset and the uncertainty of how VCC actually rises in the system, the following conditions are
required:
1. The VCC rise must be monotonic, and starts below 0.7V,
2. After reset occurs, all input and feedback setup times must be met before driving the
clock pin high, and
3. The clock must remain stable during tPR
.
Figure 4-1. Power-up Reset Timing
V
R
ST
POWER
t
PR
REGISTERED
OUTPUTS
t
S
t
W
CLOCK
4.8
Preload of Registered Outputs
The ATF22V10C’s registers are provided with circuitry to allow loading of each register with
either a high or a low. This feature will simplify testing since any state can be forced into the reg-
isters to control test sequencing. A JEDEC file with preload is generated when a source file with
vectors is compiled. Once downloaded, the JEDEC file preload sequence will be done automati-
cally by most of the approved programmers after the programming.
5. Electronic Signature Word
There are 64 bits of programmable memory that are always available to the user, even if the
device is secured. These bits can be used for user-specific data.
6. Security Fuse Usage
A single fuse is provided to prevent unauthorized copying of the ATF22V10C fuse patterns.
Once programmed, fuse verify and preload are inhibited. However, the 64-bit User Signature
remains accessible.
The security fuse should be programmed last, as its effect is immediate.
7
0735S–PLD–8/08
7. Programming/Erasing
Programming/erasing is performed using standard PLD programmers. See “CMOS PLD Pro-
gramming Hardware & Software Support” for information on software/programming.
Table 7-1.
Parameter
tPR
Programming/Erasing
Description
Typ
600
3.8
Max
1,000
4.5
Units
ns
Power-up Reset Time
Power-up Reset Voltage
VRST
V
8. Input and I/O Pin-keeper Circuits
The ATF22V10C contains internal input and I/O pin-keeper circuits. These circuits allow each
ATF22V10C pin to hold its previous value even when it is not being driven by an external source
or by the device’s output buffer. This helps to ensure that all logic array inputs are at known valid
logic levels. This reduces system power by preventing pins from floating to indeterminate levels.
By using pin-keeper circuits rather than pull-up resistors, there is no DC current required to hold
the pins in either logic state (high or low).
These pin-keeper circuits are implemented as weak feedback inverters, as shown in the Input
Diagram below. These keeper circuits can easily be overdriven by standard TTL- or CMOS-com-
patible drivers. The typical overdrive current required is 40 µA.
Figure 8-1. Input Diagram
8
ATF22V10C(Q)
0735S–PLD–8/08
ATF22V10C(Q)
Figure 8-2. I/O Diagram
9. Power-down Mode
The ATF22V10C includes an optional pin-controlled power-down feature. When this mode is
enabled, the PD pin acts as the power-down pin (Pin 4 on the DIP/SOIC packages and Pin 5 on
the PLCC package). When the PD pin is high, the device supply current is reduced to less than
100 mA. During power-down, all output data and internal logic states are latched and held.
Therefore, all registered and combinatorial output data remain valid. Any outputs that were in an
undetermined state at the onset of power-down will remain at the same state. During power-
down, all input signals except the power-down pin are blocked. Input and I/O hold latches
remain active to ensure that pins do not float to indeterminate levels, further reducing system
power. The power-down pin feature is enabled in the logic design file. Designs using the power-
down pin may not use the PD pin logic array input. However, all other PD pin macrocell
resources may still be used, including the buried feedback and foldback product term array
inputs.
PD pin configuration is controlled by the design file, and appears as a separate fuse bit in the
JEDEC file. When the power-down feature is not specified in the design file, the IN/PD pin will be
configured as a regular logic input.
Note:
Some programmers list the 22V10 JEDEC compatible 22V10C (no PD used) separately from the
non-22V10 JEDEC compatible 22V10CEX (with PD used).
9
0735S–PLD–8/08
10. Compiler Mode Selection
Table 10-1. Compiler Mode Selection
PAL Mode
(5828 Fuses)
GAL Mode
(5892 Fuses)
Power-down Mode(1)
(5893 Fuses)
Synario
ATF22V10C (DIP)
ATTF22V10C DIP (UES)
ATF22C10C PLCC (UES)
ATF22V10C DIP (PWD)
ATF22V10C PLCC (PWD)
ATF22V10C (PLCC)
WINCUPL
P22V10
G22V10
G22V10CP
P22V10LCC
G22V10LCC
G22V10CPLCC
Note:
1. These device types will create a JEDEC file which when programmed in ATF22V10C devices
will enable the power-down mode feature. All other device types have the feature disabled.
10
ATF22V10C(Q)
0735S–PLD–8/08
ATF22V10C(Q)
11. Functional Logic Diagram
11
0735S–PLD–8/08
ATF22V10C/CQ SUPPLY CURRENT VS.
SUPPLY VOLTAGE (TA = 25°C)
ATF22V10C/CQ NORMALIZED ICC VS.
TEMPERATURE
1.1
1.0
0.9
0.8
140.0
120.0
100.0
80.0
60.0
40.0
20.0
0.0
C-5, -7, -10
C-15
CQ-15
4.50
4.75
5.00
5.25
5.50
-40.0
0.0
25.0
75.0
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
ATF22V10C/CQ OUTPUT SOURCE CURRENT VS.
OUTPUT VOLTAGE (VCC = 5V, TA = 25°C)
ATF22V10C/CQ SUPPLY CURRENT VS.
INPUT FREQUENCY (VCC = 5V, TA = 25°C)
0.0
120.0
80.0
40.0
0.0
-10.0
-20.0
-30.0
-40.0
-50.0
-60.0
-70.0
-80.0
-90.0
C-5, 7, 10
C-15
CQ-15
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.0
10.0
20.0
50.0
V
OH (V)
FREQUENCY (MHz)
ATF22V10C/CQ OUTPUT SINK CURRENT VS.
SUPPLY VOLTAGE (VOL = 0.5V)
ATF22V10C/CQ OUTPUT SOURCE CURRENT VS.
SUPPLY VOLTAGE (VOH = 2.4V)
140.0
0.0
-5.0
120.0
100.0
80.0
60.0
40.0
20.0
0.0
-10.0
-15.0
-20.0
-25.0
-30.0
-35.0
-40.0
-45.0
-50.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
ATF22V10C/CQ OUTPUT SINK CURRENT VS.
SUPPLY VOLTAGE (VOL = 0.5V)
ATF22V10C/CQ INPUT CLAMP CURRENT VS.
INPUT VOLTAGE (VCC = 5V, TA = 35°C)
46.0
45.0
44.0
43.0
42.0
41.0
40.0
39.0
38.0
37.0
0.0
-20.0
-40.0
-60.0
-80.0
-100.0
-120.0
4.0
4.5
5.0
5.5
6.0
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
SUPPLY VOLTAGE (V)
INPUT VOLTAGE (V)
12
ATF22V10C(Q)
0735S–PLD–8/08
ATF22V10C(Q)
ATF22V10C/CQ NORMALIZED TPD VS. VCC
ATF22V10C/CQ NORMALIZED TCO VS.
TEMPERATURE
1.2
1.1
1.0
0.9
0.8
1.1
1.0
0.9
0.8
4.50
4.75
5.00
5.25
5.50
5.50
5.50
75.0
-40.0
0.0
25.0
75.0
75.0
300
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
ATF22V10C/CQ NORMALIZED TSU VS.
TEMPERATURE
ATF22V10C/CQ NORMALIZED TCO VS. VCC
1.3
1.2
1.1
1.0
0.9
0.8
1.1
1.0
0.9
0.8
4.50
4.75
5.00
5.25
-40.0
0.0
25.0
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
ATF22V10C/CQ NORMALIZED TSU VS. VCC
ATF22V10C/CQ DELTA TPD VS.
OUTPUT LOADING
1.2
1.1
1.0
0.9
0.8
8.0
6.0
4.0
2.0
0.0
-2.0
0
50
100
150
200
250
4.50
4.75
5.00
5.25
SUPPLY VOLTAGE (V)
OUTPUT LOADING (pF)
ATF22V10C/CQ DELTA TPD VS.
NUMBER OF OUTPUT SWITCHING
ATF22V10C/CQ NORMALIZED TPD VS.
TEMPERATURE
1.1
1.0
0.9
0.8
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
-40.0
0.0
25.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
TEMPERATURE (°C)
NUMBER OF OUTPUTS SWITCHING
13
0735S–PLD–8/08
ATF22V10C/CQ DELTA TCO VS.
OUTPUT LOADING
ATF22V10C/CQ DELTA TCO VS.
NUMBER OF SWITCHING
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
50
100
150
200
250
300
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
NUMBER OF OUTPUTS LOADING
NUMBER OF OUTPUTS SWITCHING
14
ATF22V10C(Q)
0735S–PLD–8/08
ATF22V10C(Q)
12. Ordering Information
12.1 Standard Package Options
tPD (ns)
tS (ns)
tCO (ns)
Ordering Code
Package
Operation Range
Commercial
5
3
4
ATF22V10C-5JC
28J
(0°C to 70° C)
ATF22V10C-7JC
ATF22V10C-7PC
ATF22V10C-7SC
ATF22V10C-7XC
28J
24P3
24S
Commercial
(0°C to 70° C)
7.5
3.5
4.5
24X
Industrial
ATF22V10C-7JI
28J
(-40°C to 85°C)
ATF22V10C-10JC
ATF22V10C-10PC
ATF22V10C-10SC
ATF22V10C-10XC
28J
24P3
24S
Commercial
(0°C to 70° C)
24X
10
4.5
6.5
ATF22V10C-10JI
ATF22V10C-10PI
ATF22V10C-10SI
ATF22V10C-10XI
28J
24P3
24S
Industrial
(-40°C to 85°C)
24X
ATF22V10C-15JC
ATF22V10C-15PC
ATF22V10C-15SC
ATF22V10C-15XC
28J
24P3
24S
Commercial
(0°C to 70° C)
24X
15
10
8
ATF22V10C-15JI
ATF22V10C-15PI
ATF22V10C-15SI
ATF22V10C-15XI
28J
24P3
24S
Industrial
(-40°C to 85°C)
24X
ATF22V10CQ-15JC
ATF22V10CQ-15PC
ATF22V10CQ-15SC
ATF22V10CQ-15XC
28J
24P3
24S
Commercial
(0°C to 70° C)
24X
15
10
8
ATF22V10CQ-15JI
ATF22V10CQ-15PI
ATF22V10CQ-15SI
ATF22V10CQ-15XI
28J
24P3
24S
Industrial
(-40°C to 85°C)
24X
15
0735S–PLD–8/08
12.2 ATF22V10CQ Green Package Options (Pb/Halide-free/RoHS Compliant)
tPD (ns)
tS (ns)
tCO (ns)
Ordering Code
Package
Operation Range
Commercial
5
3
4
ATF22V10C-5JX
28J
(0°C to 70° C)
ATF22V10C-7PX
ATF22V10C-7SX
24P3
24S
Commercial
7.5
7.5
3.5
3.5
4.5
4.5
(0°C to 70° C)
Industrial
ATF22V10C-7JU
28J
(-40°C to 85°C)
ATF22V10C-10JU
ATF22V10C-10PU
ATF22V10C-10SU
ATF22V10C-10XU
28J
24P3
24S
Industrial
10
15
4.5
10
6.5
8
(-40°C to 85°C)
24X
ATF22V10C-15JU
ATF22V10C-15PU
28J
Industrial
24P3
(-40°C to 85°C)
Industrial
ATF22V10CQ-15JU
28J
(-40°C to 85°C)
12.3 Using “C” Product for Industrial
To use commercial product for Industrial temperature ranges, down-grade one speed grade
from the “I” to the “C” device (7 ns “C” = 10 ns “I”) and de-rate power by 30%.
Package Type
28J
28-lead, Plastic J-leaded Chip Carrier (PLCC)
24P3
24S
24X
24-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP)
24-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)
24-lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP)
16
ATF22V10C(Q)
0735S–PLD–8/08
ATF22V10C(Q)
13. Packaging Information
13.1 28J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
D2/E2
E1
E
B1
B
e
A2
A1
D1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
4.191
2.286
0.508
12.319
11.430
12.319
11.430
9.906
0.660
0.330
MAX
4.572
3.048
–
NOM
NOTE
SYMBOL
A
A1
A2
D
–
–
–
–
12.573
D1
E
–
11.582 Note 2
12.573
–
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AB.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
E1
D2/E2
B
–
11.582 Note 2
10.922
–
–
–
0.813
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
B1
e
0.533
1.270 TYP
10/04/01
DRAWING NO. REV.
28J
TITLE
2325 Orchard Parkway
San Jose, CA 95131
28J, 28-lead, Plastic J-leaded Chip Carrier (PLCC)
B
R
17
0735S–PLD–8/08
13.2 24P3 – PDIP
D
PIN
1
E1
A
SEATING PLANE
A1
L
B
B1
e
E
COMMON DIMENSIONS
(Unit of Measure = mm)
C
MIN
–
MAX
5.334
–
NOM
NOTE
SYMBOL
eC
A
–
–
–
–
–
–
–
–
–
–
–
eB
A1
D
0.381
31.623
7.620
6.096
0.356
1.270
2.921
0.203
–
32.131 Note 2
8.255
E
E1
B
7.112 Note 2
0.559
Notes:
1. This package conforms to JEDEC reference MS-001, Variation AF.
2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
B1
L
1.651
3.810
C
0.356
eB
eC
e
10.922
0.000
1.524
2.540 TYP
6/1/04
DRAWING NO. REV.
TITLE
2325 Orchard Parkway
San Jose, CA 95131
24P3, 24-lead (0.300"/7.62 mm Wide) Plastic Dual
Inline Package (PDIP)
24P3
D
R
18
ATF22V10C(Q)
0735S–PLD–8/08
ATF22V10C(Q)
13.3 24S – SOIC
B
D1
D
PIN 1 ID
PIN 1
e
E
A
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
–
MAX
2.65
0.30
10.65
7.60
15.60
0.51
1.27
0.32
NOM
NOTE
SYMBOL
A
–
A1
A1
D
0.10
10.00
7.40
15.20
0.33
0.40
0.23
–
–
D1
E
–
0º ~ 8º
–
L1
B
–
L
–
–
L
L1
e
1.27 BSC
06/17/2002
TITLE
DRAWING NO. REV.
24S
2325 Orchard Parkway
San Jose, CA 95131
24S, 24-lead (0.300" body) Plastic Gull Wing Small Outline (SOIC)
B
R
19
0735S–PLD–8/08
13.4 24X – TSSOP
Dimensions in Millimeter and (Inches)*
JEDEC STANDARD MO-153 AD
Controlling dimension: millimeters
0.30(0.012)
0.19(0.007)
4.48(0.176)
4.30(0.169)
6.50(0.256)
6.25(0.246)
PIN 1
0.65(0.0256)BSC
7.90(0.311)
7.70(0.303)
1.20(0.047)MAX
0.15(0.006)
0.05(0.002)
0.20(0.008)
0.09(0.004)
0º ~ 8º
0.75(0.030)
0.45(0.018)
04/11/2001
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
24X, 24-lead (4.4 mm body width) Plastic Thin Shrink Small Outline
Package (TSSOP)
24X
A
R
20
ATF22V10C(Q)
0735S–PLD–8/08
ATF22V10C(Q)
14. Revision History
Revision Level – Revision Date History
R – June 2006
Updated Green package options.
Added new green part.
S – August 2008
21
0735S–PLD–8/08
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International
Atmel Corporation
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Japan
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Product Contact
Web Site
Technical Support
Sales Contact
www.atmel.com
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www.atmel.com/contacts
Literature Requests
www.atmel.com/literature
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0735S–PLD–8/08
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