ATTINY2313V-10MU-SL383

Features

• Utilizes the AVR^®RISC Architecture

• AVR – High-performance and Low-power RISC Architecture

– 120 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 20 MIPS Throughput at 20 MHz

• Data and Non-volatile Program and Data Memories

– 2K Bytes of In-System Self Programmable Flash

Endurance 10,000 Write/Erase Cycles

– 128 Bytes In-System Programmable EEPROM

Endurance: 100,000 Write/Erase Cycles

– 128 Bytes Internal SRAM

8-bit

Microcontroller

with 2K Bytes

In-System

Programmable

Flash

– Programming Lock for Flash Program and EEPROM Data Security

• Peripheral Features

– One 8-bit Timer/Counter with Separate Prescaler and Compare Mode

– One 16-bit Timer/Counter with Separate Prescaler, Compare and Capture Modes

– Four PWM Channels

– On-chip Analog Comparator

– Programmable Watchdog Timer with On-chip Oscillator

– USI – Universal Serial Interface

– Full Duplex USART

• Special Microcontroller Features

– debugWIRE On-chip Debugging

– In-System Programmable via SPI Port

– External and Internal Interrupt Sources

– Low-power Idle, Power-down, and Standby Modes

– Enhanced Power-on Reset Circuit

– Programmable Brown-out Detection Circuit

– Internal Calibrated Oscillator

ATtiny2313/V

Preliminary

• I/O and Packages

– 18 Programmable I/O Lines

– 20-pin PDIP, 20-pin SOIC, 20-pad QFN/MLF

• Operating Voltages

– 1.8 - 5.5V (ATtiny2313V)

– 2.7 - 5.5V (ATtiny2313)

• Speed Grades

– ATtiny2313V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V

– ATtiny2313: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V

• Typical Power Consumption

– Active Mode

1 MHz, 1.8V: 230 µA

32 kHz, 1.8V: 20 µA (including oscillator)

– Power-down Mode

< 0.1 µA at 1.8V

Rev. 2543I–AVR–04/06

Pin Configurations

Figure 1. Pinout ATtiny2313

PDIP/SOIC

VCC

(RESET/dW) PA2

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

PB7 (UCSK/SCL/PCINT7)

PB6 (MISO/DO/PCINT6)

PB5 (MOSI/DI/SDA/PCINT5)

PB4 (OC1B/PCINT4)

PB3 (OC1A/PCINT3)

PB2 (OC0A/PCINT2)

PB1 (AIN1/PCINT1)

PB0 (AIN0/PCINT0)

PD6 (ICP)

(RXD) PD0

(TXD) PD1

(XTAL2) PA1

(XTAL1) PA0

(CKOUT/XCK/INT0) PD2

(INT1) PD3

(T0) PD4

(OC0B/T1) PD5

GND

MLF

(TXD) PD1

XTAL2) PA1

1

2

3

4

5

15

14

13

12

11

PB5 (MOSI/DI/SDA/PCINT5)

PB4 (OC1B/PCINT4)

PB3 (OC1A/PCINT3)

PB2 (OC0A/PCINT2)

PB1 (AIN1/PCINT1)

(XTAL1) PA0

(CKOUT/XCK/INT0) PD2

(INT1) PD3

NOTE: Bottom pad should be soldered to ground.

Overview

The ATtiny2313 is a low-power CMOS 8-bit microcontroller based on the AVR

enhanced RISC architecture. By executing powerful instructions in a single clock cycle,

the ATtiny2313 achieves throughputs approaching 1 MIPS per MHz allowing the system

designer to optimize power consumption versus processing speed.

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ATtiny2313/V

Block Diagram

Figure 2. Block Diagram

XTAL1

XTAL2

PA0 - PA2

PORTA DRIVERS

DATA DIR.

REG. PORTA

DATA REGISTER

PORTA

INTERNAL

CALIBRATED

OSCILLATOR

VCC

GND

8-BIT DATA BUS

INTERNAL

OSCILLATOR

STACK

POINTER

TIMING AND

CONTROL

PROGRAM

COUNTER

WATCHDOG

TIMER

RESET

MCU CONTROL

REGISTER

PROGRAM

FLASH

SRAM

ON-CHIP

DEBUGGER

MCU STATUS

REGISTER

INSTRUCTION

REGISTER

GENERAL

PURPOSE

REGISTER

TIMER/

COUNTERS

INSTRUCTION

DECODER

INTERRUPT

UNIT

EEPROM

USI

CONTROL

LINES

ALU

STATUS

REGISTER

PROGRAMMING

LOGIC

SPI

USART

DATA DIR.

REG. PORTB

DATA DIR.

REG. PORTD

DATA REGISTER

PORTB

DATA REGISTER

PORTD

PORTB DRIVERS

PORTD DRIVERS

PB0 - PB7

PD0 - PD6

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The AVR core combines a rich instruction set with 32 general purpose working registers.

All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing

two independent registers to be accessed in one single instruction executed in one clock

cycle. The resulting architecture is more code efficient while achieving throughputs up to

ten times faster than conventional CISC microcontrollers.

The ATtiny2313 provides the following features: 2K bytes of In-System Programmable

Flash, 128 bytes EEPROM, 128 bytes SRAM, 18 general purpose I/O lines, 32 general

purpose working registers, a single-wire Interface for On-chip Debugging, two flexible

Timer/Counters with compare modes, internal and external interrupts, a serial program-

mable USART, Universal Serial Interface with Start Condition Detector, a programmable

Watchdog Timer with internal Oscillator, and three software selectable power saving

modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, and

interrupt system to continue functioning. The Power-down mode saves the register con-

tents but freezes the Oscillator, disabling all other chip functions until the next interrupt

or hardware reset. In Standby mode, the crystal/resonator Oscillator is running while the

rest of the device is sleeping. This allows very fast start-up combined with low-power

consumption.

The device is manufactured using Atmel’s high density non-volatile memory technology.

The On-chip ISP Flash allows the program memory to be reprogrammed In-System

through an SPI serial interface, or by a conventional non-volatile memory programmer.

By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a mono-

lithic chip, the Atmel ATtiny2313 is a powerful microcontroller that provides a highly

flexible and cost effective solution to many embedded control applications.

The ATtiny2313 AVR is supported with a full suite of program and system development

tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Cir-

cuit Emulators, and Evaluation kits.

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ATtiny2313/V

Pin Descriptions

VCC

Digital supply voltage.

Ground.

GND

Port A (PA2..PA0)

Port A is a 3-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port A output buffers have symmetrical drive characteristics with both high sink

and source capability. As inputs, Port A pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port A also serves the functions of various special features of the ATtiny2313 as listed

on page 56.

Port B (PB7..PB0)

Port D (PD6..PD0)

RESET

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port B output buffers have symmetrical drive characteristics with both high sink

and source capability. As inputs, Port B pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port B also serves the functions of various special features of the ATtiny2313 as listed

on page 56.

Port D is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port D output buffers have symmetrical drive characteristics with both high sink

and source capability. As inputs, Port D pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port D also serves the functions of various special features of the ATtiny2313 as listed

on page 59.

Reset input. A low level on this pin for longer than the minimum pulse length will gener-

ate a reset, even if the clock is not running. The minimum pulse length is given in Table

15 on page 37. Shorter pulses are not guaranteed to generate a reset. The Reset Input

is an alternate function for PA2 and dW.

XTAL1

XTAL2

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

XTAL1 is an alternate function for PA0.

Output from the inverting Oscillator amplifier. XTAL2 is an alternate function for PA1.

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Resources

A comprehensive set of development tools, application notes and datasheets are avail-

able for downloadon http://www.atmel.com/avr.

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ATtiny2313/V

About Code

Examples

This documentation contains simple code examples that briefly show how to use various

parts of the device. These code examples assume that the part specific header file is

included before compilation. Be aware that not all C compiler vendors include bit defini-

tions in the header files and interrupt handling in C is compiler dependent. Please

confirm with the C compiler documentation for more details.

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Disclaimer

Typical values contained in this data sheet are based on simulations and characteriza-

tion of other AVR microcontrollers manufactured on the same process technology. Min

and Max values will be available after the device is characterized.

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ATtiny2313/V

AVR CPU Core

Introduction

This section discusses the AVR core architecture in general. The main function of the

CPU core is to ensure correct program execution. The CPU must therefore be able to

access memories, perform calculations, control peripherals, and handle interrupts.

Architectural Overview

Figure 3. Block Diagram of the AVR Architecture

Data Bus 8-bit

Program

Counter

Status

and Control

Flash

Program

Memory

Interrupt

Unit

32 x 8

General

Purpose

Registrers

Instruction

Register

SPI

Unit

Instruction

Decoder

Watchdog

Timer

ALU

Analog

Comparator

Control Lines

I/O Module1

I/O Module 2

I/O Module n

Data

SRAM

EEPROM

I/O Lines

In order to maximize performance and parallelism, the AVR uses a Harvard architecture

– with separate memories and buses for program and data. Instructions in the program

memory are executed with a single level pipelining. While one instruction is being exe-

cuted, the next instruction is pre-fetched from the program memory. This concept

enables instructions to be executed in every clock cycle. The program memory is In-

System Reprogrammable Flash memory.

The fast-access Register File contains 32 x 8-bit general purpose working registers with

a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU)

operation. In a typical ALU operation, two operands are output from the Register File,

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the operation is executed, and the result is stored back in the Register File – in one

clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for

Data Space addressing – enabling efficient address calculations. One of the these

address pointers can also be used as an address pointer for look up tables in Flash pro-

gram memory. These added function registers are the 16-bit X-, Y-, and Z-register,

described later in this section.

The ALU supports arithmetic and logic operations between registers or between a con-

stant and a register. Single register operations can also be executed in the ALU. After

an arithmetic operation, the Status Register is updated to reflect information about the

result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions,

able to directly address the whole address space. Most AVR instructions have a single

16-bit word format. Every program memory address contains a 16- or 32-bit instruction.

During interrupts and subroutine calls, the return address Program Counter (PC) is

stored on the Stack. The Stack is effectively allocated in the general data SRAM, and

consequently the Stack size is only limited by the total SRAM size and the usage of the

SRAM. All user programs must initialize the SP in the Reset routine (before subroutines

or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O

space. The data SRAM can easily be accessed through the five different addressing

modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

A flexible interrupt module has its control registers in the I/O space with an additional

Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt

Vector in the Interrupt Vector table. The interrupts have priority in accordance with their

Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control

Registers, and other I/O functions. The I/O Memory can be accessed directly, or as the

Data Space locations following those of the Register File, 0x20 - 0x5F.

ALU – Arithmetic Logic

Unit

The high-performance AVR ALU operates in direct connection with all the 32 general

purpose working registers. Within a single clock cycle, arithmetic operations between

general purpose registers or between a register and an immediate are executed. The

ALU operations are divided into three main categories – arithmetic, logical, and bit-func-

tions. Some implementations of the architecture also provide a powerful multiplier

supporting both signed/unsigned multiplication and fractional format. See the “Instruc-

tion Set” section for a detailed description.

Status Register

The Status Register contains information about the result of the most recently executed

arithmetic instruction. This information can be used for altering program flow in order to

perform conditional operations. Note that the Status Register is updated after all ALU

operations, as specified in the Instruction Set Reference. This will in many cases

remove the need for using the dedicated compare instructions, resulting in faster and

more compact code.

The Status Register is not automatically stored when entering an interrupt routine and

restored when returning from an interrupt. This must be handled by software.

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ATtiny2313/V

The AVR Status Register – SREG – is defined as:

Bit

7

I

6

T

5

H

4

S

3

V

2

N

1

Z

0

C

SREG

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individ-

ual interrupt enable control is then performed in separate control registers. If the Global

Interrupt Enable Register is cleared, none of the interrupts are enabled independent of

the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt

has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-

bit can also be set and cleared by the application with the SEI and CLI instructions, as

described in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or

destination for the operated bit. A bit from a register in the Register File can be copied

into T by the BST instruction, and a bit in T can be copied into a bit in a register in the

Register File by the BLD instruction.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is

useful in BCD arithmetic. See the “Instruction Set Description” for detailed information.

• Bit 4 – S: Sign Bit, S = N ⊕ V

The S-bit is always an exclusive or between the negative flag N and the Two’s Comple-

ment Overflow Flag V. See the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See

the “Instruction Set Description” for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See

the “Instruction Set Description” for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the

“Instruction Set Description” for detailed information.

• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruc-

tion Set Description” for detailed information.

General Purpose

Register File

The Register File is optimized for the AVR Enhanced RISC instruction set. In order to

achieve the required performance and flexibility, the following input/output schemes are

supported by the Register File:

•

One 8-bit output operand and one 8-bit result input

Two 8-bit output operands and one 8-bit result input

Two 8-bit output operands and one 16-bit result input

One 16-bit output operand and one 16-bit result input

Figure 4 shows the structure of the 32 general purpose working registers in the CPU.

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Figure 4. AVR CPU General Purpose Working Registers

7

0

Addr.

R0

R1

0x00

0x01

0x02

R2

…

R13

R14

R15

R16

R17

…

0x0D

0x0E

0x0F

0x10

0x11

General

Purpose

Working

Registers

R26

R27

R28

R29

R30

R31

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

X-register Low Byte

X-register High Byte

Y-register Low Byte

Y-register High Byte

Z-register Low Byte

Z-register High Byte

Most of the instructions operating on the Register File have direct access to all registers,

and most of them are single cycle instructions.

As shown in Figure 4, each register is also assigned a data memory address, mapping

them directly into the first 32 locations of the user Data Space. Although not being phys-

ically implemented as SRAM locations, this memory organization provides great

flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to

index any register in the file.

The X-register, Y-register, and The registers R26..R31 have some added functions to their general purpose usage.

Z-register

These registers are 16-bit address pointers for indirect addressing of the data space.

The three indirect address registers X, Y, and Z are defined as described in Figure 5.

Figure 5. The X-, Y-, and Z-registers

15

XH

XL

0

X-register

7

0

7

R27 (0x1B)

R26 (0x1A)

15

YH

YL

ZL

0

Y-register

Z-register

7

R29 (0x1D)

R28 (0x1C)

15

ZH

0

7

0

R31 (0x1F)

R30 (0x1E)

In the different addressing modes these address registers have functions as fixed dis-

placement, automatic increment, and automatic decrement (see the instruction set

reference for details).

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ATtiny2313/V

Stack Pointer

The Stack is mainly used for storing temporary data, for storing local variables and for

storing return addresses after interrupts and subroutine calls. The Stack Pointer Regis-

ter always points to the top of the Stack. Note that the Stack is implemented as growing

from higher memory locations to lower memory locations. This implies that a Stack

PUSH command decreases the Stack Pointer.

The Stack Pointer points to the data SRAM Stack area where the Subroutine and Inter-

rupt Stacks are located. This Stack space in the data SRAM must be defined by the

program before any subroutine calls are executed or interrupts are enabled. The Stack

Pointer must be set to point above 0x60. The Stack Pointer is decremented by one

when data is pushed onto the Stack with the PUSH instruction, and it is decremented by

two when the return address is pushed onto the Stack with subroutine call or interrupt.

The Stack Pointer is incremented by one when data is popped from the Stack with the

POP instruction, and it is incremented by two when data is popped from the Stack with

return from subroutine RET or return from interrupt RETI.

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The num-

ber of bits actually used is implementation dependent. Note that the data space in some

implementations of the AVR architecture is so small that only SPL is needed. In this

case, the SPH Register will not be present.

Bit

15

–

14

–

13

–

12

–

11

–

10

–

9

–

8

–

SPH

SPL

SP7

7

SP6

6

SP5

5

SP4

4

SP3

3

SP2

2

SP1

1

SP0

0

Read/Write

Initial Value

R

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Instruction Execution

Timing

This section describes the general access timing concepts for instruction execution. The

AVR CPU is driven by the CPU clock clk_CPU, directly generated from the selected clock

source for the chip. No internal clock division is used.

Figure 6 shows the parallel instruction fetches and instruction executions enabled by the

Harvard architecture and the fast-access Register File concept. This is the basic pipelin-

ing concept to obtain up to 1 MIPS per MHz with the corresponding unique results for

functions per cost, functions per clocks, and functions per power-unit.

Figure 6. The Parallel Instruction Fetches and Instruction Executions

T1

T2

T3

T4

clk_CPU

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

Figure 7 shows the internal timing concept for the Register File. In a single clock cycle

an ALU operation using two register operands is executed, and the result is stored back

to the destination register.

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Figure 7. Single Cycle ALU Operation

T1

T2

T3

T4

clk_CPU

Total Execution Time

Register Operands Fetch

ALU Operation Execute

Result Write Back

Reset and Interrupt

Handling

The AVR provides several different interrupt sources. These interrupts and the separate

Reset Vector each have a separate program vector in the program memory space. All

interrupts are assigned individual enable bits which must be written logic one together

with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt.

The lowest addresses in the program memory space are by default defined as the Reset

and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 47.

The list also determines the priority levels of the different interrupts. The lower the

address the higher is the priority level. RESET has the highest priority, and next is INT0

– the External Interrupt Request 0. Refer to “Interrupts” on page 47 for more information.

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts

are disabled. The user software can write logic one to the I-bit to enable nested inter-

rupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is

automatically set when a Return from Interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that

sets the interrupt flag. For these interrupts, the Program Counter is vectored to the

actual Interrupt Vector in order to execute the interrupt handling routine, and hardware

clears the corresponding interrupt flag. Interrupt flags can also be cleared by writing a

logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the

corresponding interrupt enable bit is cleared, the interrupt flag will be set and remem-

bered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or

more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the cor-

responding interrupt flag(s) will be set and remembered until the Global Interrupt Enable

bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present.

These interrupts do not necessarily have interrupt flags. If the interrupt condition disap-

pears before the interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and exe-

cute one more instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt rou-

tine, nor restored when returning from an interrupt routine. This must be handled by

software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately

disabled. No interrupt will be executed after the CLI instruction, even if it occurs simulta-

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ATtiny2313/V

neously with the CLI instruction. The following example shows how this can be used to

avoid interrupts during the timed EEPROM write sequence..

Assembly Code Example

in r16, SREG

; store SREG value

cli ; disable interrupts during timed sequence

sbiEECR, EEMPE ; start EEPROM write

sbiEECR, EEPE

outSREG, r16

; restore SREG value (I-bit)

C Code Example

char cSREG;

cSREG = SREG;/* store SREG value */

/* disable interrupts during timed sequence */

__disable_interrupt();

EECR |= (1<<EEMPE); /* start EEPROM write */

EECR |= (1<<EEPE);

SREG = cSREG; /* restore SREG value (I-bit) */

When using the SEI instruction to enable interrupts, the instruction following SEI will be

executed before any pending interrupts, as shown in this example.

Assembly Code Example

sei ; set Global Interrupt Enable

sleep; enter sleep, waiting for interrupt

; note: will enter sleep before any pending

; interrupt(s)

C Code Example

__enable_interrupt(); /* set Global Interrupt Enable */

__sleep(); /* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

Interrupt Response Time

The interrupt execution response for all the enabled AVR interrupts is four clock cycles

minimum. After four clock cycles the program vector address for the actual interrupt

handling routine is executed. During this four clock cycle period, the Program Counter is

pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this

jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle

instruction, this instruction is completed before the interrupt is served. If an interrupt

occurs when the MCU is in sleep mode, the interrupt execution response time is

increased by four clock cycles. This increase comes in addition to the start-up time from

the selected sleep mode.

A return from an interrupt handling routine takes four clock cycles. During these four

clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack

Pointer is incremented by two, and the I-bit in SREG is set.

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AVR ATtiny2313

Memories

This section describes the different memories in the ATtiny2313. The AVR architecture

has two main memory spaces, the Data Memory and the Program Memory space. In

addition, the ATtiny2313 features an EEPROM Memory for data storage. All three mem-

ory spaces are linear and regular.

In-System

Reprogrammable Flash

Program Memory

The ATtiny2313 contains 2K bytes On-chip In-System Reprogrammable Flash memory

for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is orga-

nized as 1K x 16.

The Flash memory has an endurance of at least 10,000 write/erase cycles. The

ATtiny2313 Program Counter (PC) is 10 bits wide, thus addressing the 1K program

memory locations. “Memory Programming” on page 162 contains a detailed description

on Flash data serial downloading using the SPI pins.

Constant tables can be allocated within the entire program memory address space (see

the LPM – Load Program Memory instruction description).

Timing diagrams for instruction fetch and execution are presented in “Instruction Execu-

tion Timing” on page 13.

Figure 8. Program Memory Map

Program Memory

0x0000

0x03FF

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ATtiny2313/V

SRAM Data Memory

Figure 9 shows how the ATtiny2313 SRAM Memory is organized.

The lower 224 data memory locations address both the Register File, the I/O memory,

Extended I/O memory, and the internal data SRAM. The first 32 locations address the

Register File, the next 64 location the standard I/O memory, and the next 128 locations

address the internal data SRAM.

The five different addressing modes for the data memory cover: Direct, Indirect with Dis-

placement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In

the Register File, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space.

The Indirect with Displacement mode reaches 63 address locations from the base

address given by the Y- or Z-register.

When using register indirect addressing modes with automatic pre-decrement and post-

increment, the address registers X, Y, and Z are decremented or incremented.

The 32 general purpose working registers, 64 I/O Registers, and the 128 bytes of inter-

nal data SRAM in the ATtiny2313 are all accessible through all these addressing

modes. The Register File is described in “General Purpose Register File” on page 11.

Figure 9. Data Memory Map

Data Memory

0x0000 - 0x001F

0x0020 - 0x005F

0x0060

32 Registers

64 I/O Registers

Internal SRAM

(128 x 8)

0x00DF

Data Memory Access Times

This section describes the general access timing concepts for internal memory access.

The internal data SRAM access is performed in two clk_CPUcycles as described in Figure

10.

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Figure 10. On-chip Data SRAM Access Cycles

T1

T2

T3

clk_CPU

Address valid

Compute Address

Address

Data

WR

Data

RD

Memory Access Instruction

Next Instruction

EEPROM Data Memory

The ATtiny2313 contains 128 bytes of data EEPROM memory. It is organized as a sep-

arate data space, in which single bytes can be read and written. The EEPROM has an

endurance of at least 100,000 write/erase cycles. The access between the EEPROM

and the CPU is described in the following, specifying the EEPROM Address Registers,

the EEPROM Data Register, and the EEPROM Control Register. For a detailed descrip-

tion of Serial data downloading to the EEPROM, see page 176.

EEPROM Read/Write Access

The EEPROM Access Registers are accessible in the I/O space.

The write access time for the EEPROM is given in Table 1. A self-timing function, how-

ever, lets the user software detect when the next byte can be written. If the user code

contains instructions that write the EEPROM, some precautions must be taken. In

heavily filtered power supplies, V_CCis likely to rise or fall slowly on power-up/down. This

causes the device for some period of time to run at a voltage lower than specified as

minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page

22. for details on how to avoid problems in these situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be fol-

lowed. Refer to the description of the EEPROM Control Register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next

instruction is executed. When the EEPROM is written, the CPU is halted for two clock

cycles before the next instruction is executed.

The EEPROM Address

Register

Bit

7

–

6

EEAR6

R/W

X

5

EEAR5

R/W

X

4

EEAR4

R/W

X

3

EEAR3

R/W

X

2

EEAR2

R/W

X

1

EEAR1

R/W

X

0

EEAR0

R/W

X

EEAR

Read/Write

Initial Value

R

0

• Bit 7 – Res: Reserved Bit

This bit is reserved in the ATtiny2313 and will always read as zero.

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ATtiny2313/V

• Bits 6..0 – EEAR6..0: EEPROM Address

The EEPROM Address Register – EEAR specify the EEPROM address in the 128 bytes

EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 127.

The initial value of EEAR is undefined. A proper value must be written before the

EEPROM may be accessed.

The EEPROM Data Register –

EEDR

Bit

7

6

5

4

3

2

1

0

MSB

R/W

0

LSB

R/W

0

EEDR

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

• Bits 7..0 – EEDR7..0: EEPROM Data

For the EEPROM write operation, the EEDR Register contains the data to be written to

the EEPROM in the address given by the EEAR Register. For the EEPROM read oper-

ation, the EEDR contains the data read out from the EEPROM at the address given by

EEAR.

The EEPROM Control Register

– EECR

Bit

7

–

6

–

5

EEPM1

R/W

X

4

EEPM0

R/W

X

3

EERIE

R/W

0

2

EEMPE

R/W

0

1

EEPE

R/W

X

0

EERE

R/W

0

EECR

Read/Write

Initial Value

R

0

R

0

• Bits 7..6 – Res: Reserved Bits

These bits are reserved bits in the ATtiny2313 and will always read as zero.

• Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits

The EEPROM Programming mode bits setting defines which programming action that

will be triggered when writing EEPE. It is possible to program data in one atomic opera-

tion (erase the old value and program the new value) or to split the Erase and Write

operations in two different operations. The Programming times for the different modes

are shown in Table 1. While EEPE is set, any write to EEPMn will be ignored. During

reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.

Table 1. EEPROM Mode Bits

Programming

EEPM1 EEPM0

Time

3.4 ms

1.8 ms

–

Operation

0

1

0

1

0

1

Erase and Write in one operation (Atomic Operation)

Erase Only

Write Only

Reserved for future use

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set.

Writing EERIE to zero disables the interrupt. The EEPROM Ready Interrupt generates a

constant interrupt when Non-volatile memory is ready for programming.

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• Bit 2 – EEMPE: EEPROM Master Program Enable

The EEMPE bit determines whether writing EEPE to one will have effect or not.

When EEMPE is set, setting EEPE within four clock cycles will program the EEPROM at

the selected address. If EEMPE is zero, setting EEPE will have no effect. When EEMPE

has been written to one by software, hardware clears the bit to zero after four clock

cycles.

• Bit 1 – EEPE: EEPROM Program Enable

The EEPROM Program Enable Signal EEPE is the programming enable signal to the

EEPROM. When EEPE is written, the EEPROM will be programmed according to the

EEPMn bits setting. The EEMPE bit must be written to one before a logical one is writ-

ten to EEPE, otherwise no EEPROM write takes place. When the write access time has

elapsed, the EEPE bit is cleared by hardware. When EEPE has been set, the CPU is

halted for two cycles before the next instruction is executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal – EERE – is the read strobe to the EEPROM. When

the correct address is set up in the EEAR Register, the EERE bit must be written to one

to trigger the EEPROM read. The EEPROM read access takes one instruction, and the

requested data is available immediately. When the EEPROM is read, the CPU is halted

for four cycles before the next instruction is executed. The user should poll the EEPE bit

before starting the read operation. If a write operation is in progress, it is neither possible

to read the EEPROM, nor to change the EEAR Register.

Atomic Byte Programming

Using Atomic Byte Programming is the simplest mode. When writing a byte to the

EEPROM, the user must write the address into the EEAR Register and data into EEDR

Register. If the EEPMn bits are zero, writing EEPE (within four cycles after EEMPE is

written) will trigger the erase/write operation. Both the erase and write cycle are done in

one operation and the total programming time is given in Table 1. The EEPE bit remains

set until the erase and write operations are completed. While the device is busy with

programming, it is not possible to do any other EEPROM operations.

Split Byte Programming

It is possible to split the erase and write cycle in two different operations. This may be

useful if the system requires short access time for some limited period of time (typically

if the power supply voltage falls). In order to take advantage of this method, it is required

that the locations to be written have been erased before the write operation. But since

the erase and write operations are split, it is possible to do the erase operations when

the system allows doing time-consuming operations (typically after Power-up).

Erase

Write

To erase a byte, the address must be written to EEAR. If the EEPMn bits are 0b01, writ-

ing the EEPE (within four cycles after EEMPE is written) will trigger the erase operation

only (programming time is given in Table 1). The EEPE bit remains set until the erase

operation completes. While the device is busy programming, it is not possible to do any

other EEPROM operations.

To write a location, the user must write the address into EEAR and the data into EEDR.

If the EEPMn bits are 0b10, writing the EEPE (within four cycles after EEMPE is written)

will trigger the write operation only (programming time is given in Table 1). The EEPE bit

remains set until the write operation completes. If the location to be written has not been

erased before write, the data that is stored must be considered as lost. While the device

is busy with programming, it is not possible to do any other EEPROM operations.

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The calibrated Oscillator is used to time the EEPROM accesses. Make sure the Oscilla-

tor frequency is within the requirements described in “Oscillator Calibration Register –

OSCCAL” on page 28.

The following code examples show one assembly and one C function for writing to the

EEPROM. The examples assume that interrupts are controlled (e.g. by disabling inter-

rupts globally) so that no interrupts will occur during execution of these functions.

Assembly Code Example

EEPROM_write:

; Wait for completion of previous write

sbic EECR,EEPE

rjmp EEPROM_write

; Set up address (r17) in address register

out EEAR, r17

; Write data (r16) to data register

out EEDR,r16

; Write logical one to EEMPE

sbi EECR,EEMPE

; Start eeprom write by setting EEPE

sbi EECR,EEPE

ret

C Code Example

void EEPROM_write(unsigned int uiAddress, unsigned char ucData)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEPE))

;

/* Set up address and data registers */

EEAR = uiAddress;

EEDR = ucData;

/* Write logical one to EEMPE */

EECR |= (1<<EEMPE);

/* Start eeprom write by setting EEPE */

EECR |= (1<<EEPE);

}

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The next code examples show assembly and C functions for reading the EEPROM. The

examples assume that interrupts are controlled so that no interrupts will occur during

execution of these functions.

Assembly Code Example

EEPROM_read:

; Wait for completion of previous write

sbic EECR,EEPE

rjmp EEPROM_read

; Set up address (r17) in address register

out EEAR, r17

; Start eeprom read by writing EERE

sbi EECR,EERE

; Read data from data register

in r16,EEDR

ret

C Code Example

unsigned char EEPROM_read(unsigned int uiAddress)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEPE))

;

/* Set up address register */

EEAR = uiAddress;

/* Start eeprom read by writing EERE */

EECR |= (1<<EERE);

/* Return data from data register */

return EEDR;

}

Preventing EEPROM

Corruption

During periods of low V_CC,the EEPROM data can be corrupted because the supply volt-

age is too low for the CPU and the EEPROM to operate properly. These issues are the

same as for board level systems using EEPROM, and the same design solutions should

be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too

low. First, a regular write sequence to the EEPROM requires a minimum voltage to

operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the

supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design

recommendation:

Keep the AVR RESET active (low) during periods of insufficient power supply voltage.

This can be done by enabling the internal Brown-out Detector (BOD). If the detection

level of the internal BOD does not match the needed detection level, an external low

V

_CCreset Protection circuit can be used. If a reset occurs while a write operation is in

progress, the write operation will be completed provided that the power supply voltage is

sufficient.

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ATtiny2313/V

I/O Memory

The I/O space definition of the ATtiny2313 is shown in “Register Summary” on page

215.

All ATtiny2313 I/Os and peripherals are placed in the I/O space. All I/O locations may be

accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between

the 32 general purpose working registers and the I/O space. I/O Registers within the

address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instruc-

tions. In these registers, the value of single bits can be checked by using the SBIS and

SBIC instructions. Refer to the instruction set section for more details. When using the

I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used.

When addressing I/O Registers as data space using LD and ST instructions, 0x20 must

be added to these addresses.

For compatibility with future devices, reserved bits should be written to zero if accessed.

Reserved I/O memory addresses should never be written.

Some of the status flags are cleared by writing a logical one to them. Note that, unlike

most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and

can therefore be used on registers containing such status flags. The CBI and SBI

instructions work with registers 0x00 to 0x1F only.

The I/O and peripherals control registers are explained in later sections.

General Purpose I/O Registers The ATtiny2313 contains three General Purpose I/O Registers. These registers can be

used for storing any information, and they are particularly useful for storing global vari-

ables and status flags. General Purpose I/O Registers within the address range 0x00 -

0x1F are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.

General Purpose I/O Register

2 – GPIOR2

Bit

7

6

5

4

3

2

1

0

MSB

R/W

0

LSB

R/W

0

GPIOR2

GPIOR1

GPIOR0

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

General Purpose I/O Register

1 – GPIOR1

Bit

7

6

5

4

3

2

1

0

MSB

R/W

0

LSB

R/W

0

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

General Purpose I/O Register

0 – GPIOR0

Bit

7

6

5

4

3

2

1

0

MSB

R/W

0

LSB

R/W

0

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

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System Clock and

Clock Options

Clock Systems and their Figure 11 presents the principal clock systems in the AVR and their distribution. All of

the clocks need not be active at a given time. In order to reduce power consumption, the

Distribution

clocks to modules not being used can be halted by using different sleep modes, as

described in “Power Management and Sleep Modes” on page 33. The clock systems

are detailed below.

Figure 11. Clock Distribution

General I/O

Modules

Flash and

EEPROM

CPU Core

RAM

clk_I/O

clk_CPU

AVR Clock

Control Unit

clk_FLASH

Reset Logic

Watchdog Timer

Source clock

Watchdog clock

Clock

Multiplexer

Watchdog

Oscillator

Crystal

Oscillator

Calibrated RC

Oscillator

External Clock

CPU Clock – clk_CPU

I/O Clock – clk_I/O

The CPU clock is routed to parts of the system concerned with operation of the AVR

core. Examples of such modules are the General Purpose Register File, the Status Reg-

ister and the data memory holding the Stack Pointer. Halting the CPU clock inhibits the

core from performing general operations and calculations.

The I/O clock is used by the majority of the I/O modules, like Timer/Counters, and

USART. The I/O clock is also used by the External Interrupt module, but note that some

external interrupts are detected by asynchronous logic, allowing such interrupts to be

detected even if the I/O clock is halted. Also note that start condition detection in the USI

module is carried out asynchronously when clk_I/Ois halted, enabling USI start condition

detection in all sleep modes.

Flash Clock – clk_FLASH

The Flash clock controls operation of the Flash interface. The Flash clock is usually

active simultaneously with the CPU clock.

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ATtiny2313/V

Clock Sources

The device has the following clock source options, selectable by Flash Fuse bits as

shown below. The clock from the selected source is input to the AVR clock generator,

and routed to the appropriate modules.

Table 2. Device Clocking Select⁽¹⁾

Device Clocking Option

External Clock

CKSEL3..0

0000

Calibrated Internal RC Oscillator 4MHz

Calibrated internal RC Oscillator 8MHz

Watchdog Oscillator 128kHz

External Crystal/Ceramic Resonator

Reserved

0010

0100

0110

1000 - 1111

0001/0011/0101/0111

Note:

1. For all fuses “1” means unprogrammed while “0” means programmed.

The various choices for each clocking option is given in the following sections. When the

CPU wakes up from Power-down, the selected clock source is used to time the start-up,

ensuring stable Oscillator operation before instruction execution starts. When the CPU

starts from reset, there is an additional delay allowing the power to reach a stable level

before commencing normal operation. The Watchdog Oscillator is used for timing this

real-time part of the start-up time. The number of WDT Oscillator cycles used for each

time-out is shown in Table 3. The frequency of the Watchdog Oscillator is voltage

dependent as shown in “ATtiny2313 Typical Characteristics” on page 185.

Table 3. Number of Watchdog Oscillator Cycles

Typ Time-out (V_CC= 5.0V)

Typ Time-out (V_CC= 3.0V)

Number of Cycles

512

4.1 ms

65 ms

4.3 ms

69 ms

8K (8,192)

Default Clock Source

Crystal Oscillator

The device is shipped with CKSEL = “0100”, SUT = “10”, and CKDIV8 programmed.

The default clock source setting is the Internal RC Oscillator with longest start-up time

and an initial system clock prescaling of 8, resulting in 1.0 MHz system clock. This

default setting ensures that all users can make their desired clock source setting using

an In-System or Parallel programmer.

XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can

be configured for use as an On-chip Oscillator, as shown in Figure 12 on page 26. Either

a quartz crystal or a ceramic resonator may be used.

C1 and C2 should always be equal for both crystals and resonators. The optimal value

of the capacitors depends on the crystal or resonator in use, the amount of stray capac-

itance, and the electromagnetic noise of the environment. Some initial guidelines for

choosing capacitors for use with crystals are given in Table 4 on page 26. For ceramic

resonators, the capacitor values given by the manufacturer should be used.

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Figure 12. Crystal Oscillator Connections

C2

XTAL2

XTAL1

GND

C1

The Oscillator can operate in three different modes, each optimized for a specific fre-

quency range. The operating mode is selected by the fuses CKSEL3..1 as shown in

Table 4.

Table 4. Crystal Oscillator Operating Modes

Recommended Range for Capacitors C1

CKSEL3..1

100⁽²⁾

101

Frequency Range⁽¹⁾(MHz)

and C2 for Use with Crystals (pF)

0.4 - 0.9

0.9 - 3.0

3.0 - 8.0

8.0 -

–

12 - 22

110

111

Notes: 1. The frequency ranges are preliminary values. Actual values are TBD.

2. This option should not be used with crystals, only with ceramic resonators.

The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown

in Table 5.

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ATtiny2313/V

Table 5. Start-up Times for the Crystal Oscillator Clock Selection

Start-up Time from

Power-down and

Power-save

Additional Delay

from Reset

CKSEL0 SUT1..0

(V_CC= 5.0V)

Recommended Usage

0

1

00

01

10

11

00

01

10

11

258 CK⁽¹⁾

1K CK⁽²⁾

16K CK

14CK + 4.1 ms

14CK + 65 ms

14CK

Ceramic resonator, fast

rising power

Ceramic resonator,

slowly rising power

Ceramic resonator,

BOD enabled

14CK + 4.1 ms

14CK + 65 ms

14CK

Ceramic resonator, fast

rising power

Ceramic resonator,

slowly rising power

Crystal Oscillator, BOD

enabled

1

14CK + 4.1 ms

14CK + 65 ms

Crystal Oscillator, fast

rising power

Crystal Oscillator,

slowly rising power

Notes: 1. These options should only be used when not operating close to the maximum fre-

quency of the device, and only if frequency stability at start-up is not important for the

application. These options are not suitable for crystals.

2. These options are intended for use with ceramic resonators and will ensure fre-

quency stability at start-up. They can also be used with crystals when not operating

close to the maximum frequency of the device, and if frequency stability at start-up is

not important for the application.

Calibrated Internal RC

Oscillator

The calibrated internal RC Oscillator provides a fixed 8.0 MHz clock. The frequency is

nominal value at 3V and 25°C. If 8 MHz frequency exceeds the specification of the

device (depends on V_CC), the CKDIV8 Fuse must be programmed in order to divide the

internal frequency by 8 during start-up. The device is shipped with the CKDIV8 Fuse

programmed. This clock may be selected as the system clock by programming the

CKSEL Fuses as shown in Table 6. If selected, it will operate with no external compo-

nents. During reset, hardware loads the calibration byte into the OSCCAL Register and

thereby automatically calibrates the RC Oscillator. At 3V and 25°C, this calibration gives

a frequency within ± 10% of the nominal frequency. Using calibration methods as

described in application notes available at www.atmel.com/avr it is possible to achieve ±

2% accuracy at any given V_CCand Temperature. When this Oscillator is used as the

chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for the

Reset Time-out. For more information on the pre-programmed calibration value, see the

section “Calibration Byte” on page 164.

Table 6. Internal Calibrated RC Oscillator Operating Modes

CKSEL3..0

0010 - 0011

0100 - 0101

Nominal Frequency

4.0 MHz

8.0 MHz⁽¹⁾

Note:

1. The device is shipped with this option selected.

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When this Oscillator is selected, start-up times are determined by the SUT Fuses as

shown in Table 7.

Table 7. Start-up times for the internal calibrated RC Oscillator clock selection

Start-up Time from Power-

down and Power-save

Additional Delay from

Reset (V_CC= 5.0V)

SUT1..0

00

Recommended Usage

BOD enabled

6 CK

14CK

01

14CK + 4.1 ms

14CK + 65 ms

Reserved

Fast rising power

Slowly rising power

10⁽¹⁾

11

Note:

1. The device is shipped with this option selected.

Oscillator Calibration Register

– OSCCAL

Bit

7

–

6

5

4

3

2

1

0

CAL6

R/W

CAL5

R/W

CAL4

R/W

CAL3

R/W

CAL2

R/W

CAL1

R/W

CAL0

R/W

OSCCAL

Read/Write

Initial Value

R

Device Specific Calibration Value

• Bits 6..0 – CAL6..0: Oscillator Calibration Value

Writing the calibration byte to this address will trim the internal Oscillator to remove pro-

cess variations from the Oscillator frequency. This is done automatically during Chip

Reset. When OSCCAL is zero, the lowest available frequency is chosen. Writing non-

zero values to this register will increase the frequency of the internal Oscillator. Writing

0x7F to the register gives the highest available frequency. The calibrated Oscillator is

used to time EEPROM and Flash access. If EEPROM or Flash is written, do not cali-

brate to more than 10% above the nominal frequency. Otherwise, the EEPROM or Flash

write may fail. Note that the Oscillator is intended for calibration to 8.0/4.0 MHz. Tuning

to other values is not guaranteed, as indicated in Table 8.

Avoid changing the calibration value in large steps when calibrating the Calibrated Inter-

nal RC Oscillator to ensure stable operation of the MCU. A variation in frequency of

more than 2% from one cycle to the next can lead to unpredictable behavior. Changes in

OSCCAL should not exceed 0x20 for each calibration.

Table 8. Internal RC Oscillator Frequency Range.

Min Frequency in Percentage of

Nominal Frequency

Max Frequency in Percentage of

Nominal Frequency

OSCCAL Value

0x00

50%

75%

100%

150%

200%

0x3F

0x7F

100%

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ATtiny2313/V

External Clock

To drive the device from an external clock source, XTAL1 should be driven as shown in

Figure 13. To run the device on an external clock, the CKSEL Fuses must be pro-

grammed to “0000”.

Figure 13. External Clock Drive Configuration

NC

XTAL2

EXTERNAL

CLOCK

XTAL1

GND

SIGNAL

When this clock source is selected, start-up times are determined by the SUT Fuses as

shown in Table 10.

Table 9. Crystal Oscillator Clock Frequency

CKSEL3..0

Frequency Range

0000 - 0001

0 - 16 MHz

Table 10. Start-up Times for the External Clock Selection

Start-up Time from Power-

down and Power-save

Additional Delay from

Reset (V_CC= 5.0V)

SUT1..0

00

Recommended Usage

BOD enabled

6 CK

14CK

01

14CK + 4.1 ms

14CK + 65 ms

Reserved

Fast rising power

Slowly rising power

10

11

When applying an external clock, it is required to avoid sudden changes in the applied

clock frequency to ensure stable operation of the MCU. A variation in frequency of more

than 2% from one clock cycle to the next can lead to unpredictable behavior. It is

required to ensure that the MCU is kept in Reset during such changes in the clock

frequency.

Note that the System Clock Prescaler can be used to implement run-time changes of

the internal clock frequency while still ensuring stable operation.

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128 kHz Internal

Oscillator

The 128 kHz Internal Oscillator is a low power Oscillator providing a clock of 128 kHz.

The frequency is nominal at 3 V and 25°C. This clock may be selected as the system

clock by programming the CKSEL Fuses to 0110.

When this clock source is selected, start-up times are determined by the SUT Fuses as

shown in Table 11.

Table 11. Start-up Times for the 128 kHz Internal Oscillator

Start-up Time from Power-

down and Power-save

Additional Delay from

Reset

SUT1..0

00

Recommended Usage

BOD enabled

6 CK

14CK

01

14CK + 4 ms

14CK + 64 ms

Reserved

Fast rising power

Slowly rising power

10

11

System Clock Prescalar

The ATtiny2313 has a system clock prescaler, and the system clock can be divided by

setting the “CLKPR – Clock Prescale Register” on page 30. This feature can be used to

decrease the system clock frequency and the power consumption when the requirement

for processing power is low. This can be used with all clock source options, and it will

affect the clock frequency of the CPU and all synchronous peripherals. clk_I/O, clk_CPU

and clk_FLASHare divided by a factor as shown in Table 12 on page 32.

,

When switching between prescaler settings, the System Clock Prescaler ensures that

no glitches occurs in the clock system. It also ensures that no intermediate frequency is

higher than neither the clock frequency corresponding to the previous setting, nor the

clock frequency corresponding to the new setting.

The ripple counter that implements the prescaler runs at the frequency of the undivided

clock, which may be faster than the CPU's clock frequency. Hence, it is not possible to

determine the state of the prescaler - even if it were readable, and the exact time it takes

to switch from one clock division to the other cannot be exactly predicted. From the time

the CLKPS values are written, it takes between T1 + T2 and T1 + 2 * T2 before the new

clock frequency is active. In this interval, two active clock edges are produced. Here, T1

is the previous clock period, and T2 is the period corresponding to the new prescaler

setting.

To avoid unintentional changes of clock frequency, a special write procedure must be

followed to change the CLKPS bits:

1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits

in CLKPR to zero.

2. Within four cycles, write the desired value to CLKPS while writing a zero to

CLKPCE.

Interrupts must be disabled when changing prescaler setting to make sure the write pro-

cedure is not interrupted.

CLKPR – Clock Prescale

Register

Bit

7

CLKPCE

R/W

0

6

–

5

–

4

–

3

2

1

0

CLKPS3

R/W

CLKPS2

R/W

CLKPS1

R/W

CLKPS0

R/W

CLKPR

(0x61)

Read/Write

Initial Value

R

0

R

0

R

0

See Bit Description

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ATtiny2313/V

• Bit 7 – CLKPCE: Clock Prescaler Change Enable

The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The

CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to

zero. CLKPCE is cleared by hardware four cycles after it is written or when CLKPS bits

are written. Rewriting the CLKPCE bit within this time-out period does neither extend the

time-out period, nor clear the CLKPCE bit.

• Bits 3:0 – CLKPS3:0: Clock Prescaler Select Bits 3:0

These bits define the division factor between the selected clock source and the internal

system clock. These bits can be written run-time to vary the clock frequency to suit the

application requirements. As the divider divides the master clock input to the MCU, the

speed of all synchronous peripherals is reduced when a division factor is used. The divi-

sion factors are given in Table 12 on page 32.

The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unpro-

grammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits

are reset to “0011”, giving a division factor of 8 at start up. This feature should be used if

the selected clock source has a higher frequency than the maximum frequency of the

device at the present operating conditions. Note that any value can be written to the

CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software must

ensure that a sufficient division factor is chosen if the selected clock source has a higher

frequency than the maximum frequency of the device at the present operating condi-

tions. The device is shipped with the CKDIV8 Fuse programmed.

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Table 12. Clock Prescaler Select

CLKPS3

CLKPS2

CLKPS1

CLKPS0

Clock Division Factor

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

4

8

16

32

64

128

256

Reserved

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ATtiny2313/V

Power Management

and Sleep Modes

Sleep modes enable the application to shut down unused modules in the MCU, thereby

saving power. The AVR provides various sleep modes allowing the user to tailor the

power consumption to the application’s requirements.

To enter any of the three sleep modes, the SE bit in MCUCR must be written to logic

one and a SLEEP instruction must be executed. The SM1 and SM0 bits in the MCUCR

Register select which sleep mode (Idle, Power-down, or Standby) will be activated by

the SLEEP instruction. See Table 13 for a summary. If an enabled interrupt occurs while

the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles

in addition to the start-up time, executes the interrupt routine, and resumes execution

from the instruction following SLEEP. The contents of the register file and SRAM are

unaltered when the device wakes up from sleep. If a reset occurs during sleep mode,

the MCU wakes up and executes from the Reset Vector.

Figure 11 on page 24 presents the different clock systems in the ATtiny2313, and their

distribution. The figure is helpful in selecting an appropriate sleep mode.

MCU Control Register –

MCUCR

The Sleep Mode Control Register contains control bits for power management.

Bit

7

6

5

SE

R/W

0

4

3

ISC11

R/W

0

2

ISC10

R/W

0

1

ISC01

R/W

0

ISC00

R/W

0

PUD

R/W

0

SM1

R/W

0

SM0

R/W

0

MCUCR

Read/Write

Initial Value

• Bits 6, 4 – SM1..0: Sleep Mode Select Bits 1 and 0

These bits select between the five available sleep modes as shown in Table 13.

Table 13. Sleep Mode Select

SM1

SM0

Sleep Mode

Idle

0

1

0

1

0

1

Power-down

Standby

Note:

1. Standby mode is only recommended for use with external crystals or resonators.

• Bit 5 – SE: Sleep Enable

The SE bit must be written to logic one to make the MCU enter the sleep mode when the

SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is

the programmer’s purpose, it is recommended to write the Sleep Enable (SE) bit to one

just before the execution of the SLEEP instruction and to clear it immediately after wak-

ing up.

Idle Mode

When the SM1..0 bits are written to 00, the SLEEP instruction makes the MCU enter

Idle mode, stopping the CPU but allowing the UART, Analog Comparator, ADC, USI,

Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep

mode basically halts clk_CPUand clk_FLASH, while allowing the other clocks to run.

Idle mode enables the MCU to wake up from external triggered interrupts as well as

internal ones like the Timer Overflow and UART Transmit Complete interrupts. If wake-

up from the Analog Comparator interrupt is not required, the Analog Comparator can be

powered down by setting the ACD bit in the Analog Comparator Control and Status

Register – ACSR. This will reduce power consumption in Idle mode.

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Power-down Mode

When the SM1..0 bits are written to 01 or 11, the SLEEP instruction makes the MCU

enter Power-down mode. In this mode, the external Oscillator is stopped, while the

external interrupts, the USI start condition detection, and the Watchdog continue operat-

ing (if enabled). Only an External Reset, a Watchdog Reset, a Brown-out Reset, USI

start condition interrupt, an external level interrupt on INT0, or a pin change interrupt can

wake up the MCU. This sleep mode basically halts all generated clocks, allowing opera-

tion of asynchronous modules only.

Note that if a level triggered interrupt is used for wake-up from Power-down mode, the

changed level must be held for some time to wake up the MCU. Refer to “External Inter-

rupts” on page 62 for details.

When waking up from Power-down mode, there is a delay from the wake-up condition

occurs until the wake-up becomes effective. This allows the clock to restart and become

stable after having been stopped. The wake-up period is defined by the same CKSEL

Fuses that define the Reset Time-out period, as described in “Clock Sources” on page

25.

Standby Mode

When the SM1..0 bits are 10 and an external crystal/resonator clock option is selected,

the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to

Power-down with the exception that the Oscillator is kept running. From Standby mode,

the device wakes up in six clock cycles.

Table 14. Active Clock Domains and Wake-up Sources in the Different Sleep Modes.

Active Clock Domains Oscillators

Wake-up Sources

Sleep Mode

Idle

X

Power-down

Standby⁽¹⁾

X⁽²⁾

Notes: 1. Only recommended with external crystal or resonator selected as clock source.

2. For INT0, only level interrupt.

Minimizing Power

Consumption

There are several issues to consider when trying to minimize the power consumption in

an AVR controlled system. In general, sleep modes should be used as much as possi-

ble, and the sleep mode should be selected so that as few as possible of the device’s

functions are operating. All functions not needed should be disabled. In particular, the

following modules may need special consideration when trying to achieve the lowest

possible power consumption.

Analog Comparator

When entering Idle mode, the Analog Comparator should be disabled if not used. In

other sleep modes, the Analog Comparator is automatically disabled. However, if the

Analog Comparator is set up to use the Internal Voltage Reference as input, the Analog

Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Ref-

erence will be enabled, independent of sleep mode. Refer to “Analog Comparator” on

page 153 for details on how to configure the Analog Comparator.

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Brown-out Detector

If the Brown-out Detector is not needed by the application, this module should be turned

off. If the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in

all sleep modes, and hence, always consume power. In the deeper sleep modes, this

will contribute significantly to the total current consumption. Refer to “Brown-out Detec-

tion” on page 38 for details on how to configure the Brown-out Detector.

Internal Voltage Reference

The Internal Voltage Reference will be enabled when needed by the Brown-out Detec-

tion or the Analog Comparator. If these modules are disabled as described in the

sections above, the internal voltage reference will be disabled and it will not be consum-

ing power. When turned on again, the user must allow the reference to start up before

the output is used. If the reference is kept on in sleep mode, the output can be used

immediately. Refer to “Internal Voltage Reference” on page 41 for details on the start-up

time.

Watchdog Timer

If the Watchdog Timer is not needed in the application, the module should be turned off.

If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence,

always consume power. In the deeper sleep modes, this will contribute significantly to

the total current consumption. Refer to “Interrupts” on page 47 for details on how to con-

figure the Watchdog Timer.

Port Pins

When entering a sleep mode, all port pins should be configured to use minimum power.

The most important is then to ensure that no pins drive resistive loads. In sleep modes

where the I/O clock (clk_I/O) is stopped, the input buffers of the device will be disabled.

This ensures that no power is consumed by the input logic when not needed. In some

cases, the input logic is needed for detecting wake-up conditions, and it will then be

enabled. Refer to the section “Digital Input Enable and Sleep Modes” on page 53 for

details on which pins are enabled. If the input buffer is enabled and the input signal is

left floating or have an analog signal level close to V_CC/2, the input buffer will use exces-

sive power.

For analog input pins, the digital input buffer should be disabled at all times. An analog

signal level close to V_CC/2 on an input pin can cause significant current even in active

mode. Digital input buffers can be disabled by writing to the Digital Input Disable Regis-

ters (DIDR). Refer to “Digital Input Disable Register – DIDR” on page 154.

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System Control and

Reset

Resetting the AVR

During reset, all I/O Registers are set to their initial values, and the program starts exe-

cution from the Reset Vector. The instruction placed at the Reset Vector must be an

RJMP – Relative Jump – instruction to the reset handling routine. If the program never

enables an interrupt source, the Interrupt Vectors are not used, and regular program

code can be placed at these locations. The circuit diagram in Figure 14 shows the reset

logic. Table 15 defines the electrical parameters of the reset circuitry.

The I/O ports of the AVR are immediately reset to their initial state when a reset source

goes active. This does not require any clock source to be running.

After all reset sources have gone inactive, a delay counter is invoked, stretching the

internal reset. This allows the power to reach a stable level before normal operation

starts. The time-out period of the delay counter is defined by the user through the SUT

and CKSEL Fuses. The different selections for the delay period are presented in “Clock

Sources” on page 25.

Reset Sources

The ATtiny2313 has four sources of reset:

•

Power-on Reset. The MCU is reset when the supply voltage is below the Power-on

Reset threshold (V_POT).

External Reset. The MCU is reset when a low level is present on the RESET pin for

longer than the minimum pulse length.

Watchdog Reset. The MCU is reset when the Watchdog Timer period expires, the

Watchdog is enabled, and Watchdog Interrupt is disabled.

Brown-out Reset. The MCU is reset when the supply voltage V_CCis below the

Brown-out Reset threshold (V_BOT) and the Brown-out Detector is enabled.

Figure 14. Reset Logic

DATA BUS

MCU Status

Register (MCUSR)

Power-on Reset

Circuit

Brown-out

Reset Circuit

BODLEVEL [2..0]

Pull-up Resistor

SPIKE

FILTER

Watchdog

Oscillator

Delay Counters

Clock

CK

Generator

TIMEOUT

CKSEL[3:0]

SUT[1:0]

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ATtiny2313/V

Table 15. Reset Characteristics

Symbol

Parameter

Condition

Min⁽¹⁾

Typ⁽¹⁾

Max⁽¹⁾

Units

Power-on Reset

Threshold Voltage

(rising)

T_A= -40 - 85°C

1.2

V

V_POT

Power-on Reset

Threshold Voltage

(falling)⁽²⁾

T_A= -40 - 85°C

1.1

V

RESET Pin Threshold

Voltage

V_RST

t_RST

V_CC= 1.8 - 5.5V 0.2 V_CC

V_CC= 1.8 - 5.5V

0.9 V_CC

2.5

V

Minimum pulse width

on RESET Pin

µs

Notes: 1. Values are guidelines only. Actual values are TBD.

2. The Power-on Reset will not work unless the supply voltage has been below V_POT

(falling)

Power-on Reset

A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detec-

tion level is defined in Table 15. The POR is activated whenever V_CCis below the

detection level. The POR circuit can be used to trigger the start-up Reset, as well as to

detect a failure in supply voltage.

A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reach-

ing the Power-on Reset threshold voltage invokes the delay counter, which determines

how long the device is kept in RESET after V_CCrise. The RESET signal is activated

again, without any delay, when V_CCdecreases below the detection level.

Figure 15. MCU Start-up, RESET Tied to V_CC

V_POT

V_CC

V_RST

RESET

t_TOUT

TIME-OUT

INTERNAL

RESET

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Figure 16. MCU Start-up, RESET Extended Externally

V_POT

V_CC

V_RST

RESET

t_TOUT

TIME-OUT

INTERNAL

RESET

External Reset

Brown-out Detection

38

An External Reset is generated by a low level on the RESET pin. Reset pulses longer

than the minimum pulse width (see Table 15) will generate a reset, even if the clock is

not running. Shorter pulses are not guaranteed to generate a reset. When the applied

signal reaches the Reset Threshold Voltage – V_RST– on its positive edge, the delay

counter starts the MCU after the Time-out period – t_TOUT– has expired.

Figure 17. External Reset During Operation

CC

ATtiny2313 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V_CC

level during operation by comparing it to a fixed trigger level. The trigger level for the

BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to

ensure spike free Brown-out Detection. The hysteresis on the detection level should be

interpreted as V_BOT+= V_BOT+ V_HYST/2 and V_BOT-= V_BOT- V_HYST/2.

Table 16. BODLEVEL Fuse Coding⁽¹⁾

BODLEVEL 2..0 Fuses

Min V_BOT

Typ V_BOT

Max V_BOT

Units

111

110

101

100

BOD Disabled

1.8

2.7

4.3

V

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ATtiny2313/V

Table 16. BODLEVEL Fuse Coding⁽¹⁾

BODLEVEL 2..0 Fuses

Min V_BOT

Typ V_BOT

Max V_BOT

Units

011

010

001

000

Reserved

Note:

1. V_BOTmay be below nominal minimum operating voltage for some devices. For

devices where this is the case, the device is tested down to V_CC= V_BOTduring the

production test. This guarantees that a Brown-Out Reset will occur before V_CCdrops

to a voltage where correct operation of the microcontroller is no longer guaranteed.

The test is performed using BODLEVEL = 110 for ATtiny2313V and

BODLEVEL = 101 for ATtiny2313L.

Table 17. Brown-out Characteristics

Symbol

V_HYST

t_BOD

Parameter

Min

Typ

50

2

Max

Units

mV

Brown-out Detector Hysteresis

Min Pulse Width on Brown-out Reset

ns

When the BOD is enabled, and V_CCdecreases to a value below the trigger level (V_BOT-

in Figure 18), the Brown-out Reset is immediately activated. When V_CCincreases above

the trigger level (V_BOT+in Figure 18), the delay counter starts the MCU after the Time-

out period t_TOUThas expired.

The BOD circuit will only detect a drop in V_CCif the voltage stays below the trigger level

for longer than t_BODgiven in Table 15.

Figure 18. Brown-out Reset During Operation

V_BOT+

V_CC

V_BOT-

RESET

t

TOUT

TIME-OUT

INTERNAL

RESET

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Watchdog Reset

When the Watchdog times out, it will generate a short reset pulse of one CK cycle dura-

tion. On the falling edge of this pulse, the delay timer starts counting the Time-out period

t_TOUT. Refer to page 47 for details on operation of the Watchdog Timer.

Figure 19. Watchdog Reset During Operation

CC

CK

MCU Status Register –

MCUSR

The MCU Status Register provides information on which reset source caused an MCU

reset.

Bit

7

–

6

–

5

–

4

–

3

2

1

0

WDRF

R/W

BORF

R/W

EXTRF

R/W

PORF

R/W

MCUSR

Read/Write

Initial Value

R

0

R

0

R

0

R

See Bit Description

• Bit 3 – WDRF: Watchdog Reset Flag

This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by

writing a logic zero to the flag.

• Bit 2 – BORF: Brown-out Reset Flag

This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by

writing a logic zero to the flag.

• Bit 1 – EXTRF: External Reset Flag

This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by

writing a logic zero to the flag.

• Bit 0 – PORF: Power-on Reset Flag

This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to

the flag.

To make use of the Reset flags to identify a reset condition, the user should read and

then reset the MCUSR as early as possible in the program. If the register is cleared

before another reset occurs, the source of the reset can be found by examining the reset

flags.

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ATtiny2313/V

Internal Voltage

Reference

ATtiny2313 features an internal bandgap reference. This reference is used for Brown-

out Detection, and it can be used as an input to the Analog Comparator.

Voltage Reference Enable

Signals and Start-up Time

The voltage reference has a start-up time that may influence the way it should be used.

The start-up time is given in Table 18. To save power, the reference is not always turned

on. The reference is on during the following situations:

1. When the BOD is enabled (by programming the BODLEVEL [2..0] Fuse).

2. When the bandgap reference is connected to the Analog Comparator (by setting

the ACBG bit in ACSR).

Thus, when the BOD is not enabled, after setting the ACBG bit, the user must always

allow the reference to start up before the output from the Analog Comparator is used. To

reduce power consumption in Power-down mode, the user can avoid the three condi-

tions above to ensure that the reference is turned off before entering Power-down mode.

Table 18. Internal Voltage Reference Characteristics⁽¹⁾

Symbol Parameter

Condition

Min

Typ

Max Units

Bandgap reference voltage

V_CC= 2.7V,

T_A= 25°C

V_BG

t_BG

I_BG

1.0

1.1

1.2

70

V

Bandgap reference start-up time

V_CC= 2.7V,

T_A= 25°C

40

15

µs

µA

Bandgap reference current

consumption

V_CC= 2.7V,

T_A= 25°C

Note:

1. Values are guidelines only. Actual values are TBD.

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Watchdog Timer

ATtiny2313 has an Enhanced Watchdog Timer (WDT). The main features are:

• Clocked from separate On-chip Oscillator

• 3 Operating modes

– Interrupt

– System Reset

– Interrupt and System Reset

• Selectable Time-out period from 16ms to 8s

• Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode

Figure 20. Watchdog Timer

128kHz

OSCILLATOR

WDP0

WDP1

WATCHDOG

WDP2

RESET

WDP3

WDE

MCU RESET

WDIF

INTERRUPT

WDIE

The Watchdog Timer (WDT) is a timer counting cycles of a separate on-chip 128 kHz

oscillator. The WDT gives an interrupt or a system reset when the counter reaches a

given time-out value. In normal operation mode, it is required that the system uses the

WDR - Watchdog Timer Reset - instruction to restart the counter before the time-out

value is reached. If the system doesn't restart the counter, an interrupt or system reset

will be issued.

In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can

be used to wake the device from sleep-modes, and also as a general system timer. One

example is to limit the maximum time allowed for certain operations, giving an interrupt

when the operation has run longer than expected. In System Reset mode, the WDT

gives a reset when the timer expires. This is typically used to prevent system hang-up in

case of runaway code. The third mode, Interrupt and System Reset mode, combines the

other two modes by first giving an interrupt and then switch to System Reset mode. This

mode will for instance allow a safe shutdown by saving critical parameters before a sys-

tem reset.

The Watchdog always on (WDTON) fuse, if programmed, will force the Watchdog Timer

to System Reset mode. With the fuse programmed the System Reset mode bit (WDE)

and Interrupt mode bit (WDIE) are locked to 1 and 0 respectively.

To further ensure program security, alterations to the Watchdog set-up must follow

timed sequences. The sequence for clearing WDE and changing time-out configuration

is as follows:

1. In the same operation, write a logic one to the Watchdog change enable bit

(WDCE) and WDE. A logic one must be written to WDE regardless of the previ-

ous value of the WDE bit.

2. Within the next four clock cycles, write the WDE and Watchdog prescaler bits

(WDP) as desired, but with the WDCE bit cleared. This must be done in one

operation.

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ATtiny2313/V

The following code example shows one assembly and one C function for turning off the

Watchdog Timer. The example assumes that interrupts are controlled (e.g. by disabling

interrupts globally) so that no interrupts will occur during the execution of these

functions.

Assembly Code Example⁽¹⁾

WDT_off:

; Turn off global interrupt

cli

; Reset Watchdog Timer

wdr

; Clear WDRF in MCUSR

in

andi r16, (0xff & (0<<WDRF))

out MCUSR, r16

r16, MCUSR

; Write logical one to WDCE and WDE

; Keep old prescaler setting to prevent unintentional time-out

in

r16, WDTCSR

ori

out

r16, (1<<WDCE) | (1<<WDE)

WDTCSR, r16

; Turn off WDT

ldi

out

r16, (0<<WDE)

WDTCSR, r16

; Turn on global interrupt

sei

ret

C Code Example⁽¹⁾

void WDT_off(void)

{

__disable_interrupt();

__watchdog_reset();

/* Clear WDRF in MCUSR */

MCUSR &= ~(1<<WDRF);

/* Write logical one to WDCE and WDE */

/* Keep old prescaler setting to prevent unintentional time-out

*/

WDTCSR |= (1<<WDCE) | (1<<WDE);

/* Turn off WDT */

WDTCSR = 0x00;

__enable_interrupt();

}

Note:

1. The example code assumes that the part specific header file is included.

Note: If the Watchdog is accidentally enabled, for example by a runaway pointer or

brown-out condition, the device will be reset and the Watchdog Timer will stay enabled.

If the code is not set up to handle the Watchdog, this might lead to an eternal loop of

time-out resets. To avoid this situation, the application software should always clear the

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2543I–AVR–04/06

Watchdog System Reset Flag (WDRF) and the WDE control bit in the initialisation rou-

tine, even if the Watchdog is not in use.

The following code example shows one assembly and one C function for changing the

time-out value of the Watchdog Timer.

Assembly Code Example⁽¹⁾

WDT_Prescaler_Change:

; Turn off global interrupt

cli

; Reset Watchdog Timer

wdr

; Start timed sequence

in

r16, WDTCSR

ori

out

r16, (1<<WDCE) | (1<<WDE)

WDTCSR, r16

; -- Got four cycles to set the new values from here -

; Set new prescaler(time-out) value = 64K cycles (~0.5 s)

ldi

out

r16, (1<<WDE) | (1<<WDP2) | (1<<WDP0)

WDTCSR, r16

; -- Finished setting new values, used 2 cycles -

; Turn on global interrupt

sei

ret

C Code Example⁽¹⁾

void WDT_Prescaler_Change(void)

{

__disable_interrupt();

__watchdog_reset();

/* Start timed equence */

WDTCSR |= (1<<WDCE) | (1<<WDE);

/* Set new prescaler(time-out) value = 64K cycles (~0.5 s) */

WDTCSR = (1<<WDE) | (1<<WDP2) | (1<<WDP0);

__enable_interrupt();

}

Note:

1. The example code assumes that the part specific header file is included.

Note: The Watchdog Timer should be reset before any change of the WDP bits, since a

change in the WDP bits can result in a time-out when switching to a shorter time-out

period.

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ATtiny2313/V

Watchdog Timer Control

Register - WDTCSR

Bit

7

WDIF

R/W

0

6

WDIE

R/W

0

5

WDP3

R/W

0

4

WDCE

R/W

0

3

2

WDP2

R/W

0

1

WDP1

R/W

0

WDP0

R/W

0

WDE

R/W

X

WDTCSR

Read/Write

Initial Value

• Bit 7 - WDIF: Watchdog Interrupt Flag

This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is

configured for interrupt. WDIF is cleared by hardware when executing the corresponding

interrupt handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag.

When the I-bit in SREG and WDIE are set, the Watchdog Time-out Interrupt is

executed.

• Bit 6 - WDIE: Watchdog Interrupt Enable

When this bit is written to one and the I-bit in the Status Register is set, the Watchdog

Interrupt is enabled. If WDE is cleared in combination with this setting, the Watchdog

Timer is in Interrupt Mode, and the corresponding interrupt is executed if time-out in the

Watchdog Timer occurs.

If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first

time-out in the Watchdog Timer will set WDIF. Executing the corresponding interrupt

vector will clear WDIE and WDIF automatically by hardware (the Watchdog goes to Sys-

tem Reset Mode). This is useful for keeping the Watchdog Timer security while using

the interrupt. To stay in Interrupt and System Reset Mode, WDIE must be set after each

interrupt. This should however not be done within the interrupt service routine itself, as

this might compromise the safety-function of the Watchdog System Reset mode. If the

interrupt is not executed before the next time-out, a System Reset will be applied.

Table 19. Watchdog Timer Configuration

WDTON⁽¹⁾

WDE

WDIE

Mode

Action on Time-out

None

1

0

1

0

1

0

Stopped

Interrupt Mode

System Reset Mode

Interrupt

Reset

Interrupt and System

Reset Mode

Interrupt, then go to

System Reset Mode

1

0

1

x

1

x

System Reset Mode

Reset

Note:

1. WDTON Fuse set to “0“ means programmed and “1” means unprogrammed.

• Bit 4 - WDCE: Watchdog Change Enable

This bit is used in timed sequences for changing WDE and prescaler bits. To clear the

WDE bit, and/or change the prescaler bits, WDCE must be set.

Once written to one, hardware will clear WDCE after four clock cycles.

• Bit 3 - WDE: Watchdog System Reset Enable

WDE is overridden by WDRF in MCUSR. This means that WDE is always set when

WDRF is set. To clear WDE, WDRF must be cleared first. This feature ensures multiple

resets during conditions causing failure, and a safe start-up after the failure.

• Bit 5, 2..0 - WDP3..0: Watchdog Timer Prescaler 3, 2, 1 and 0

The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer

is running. The different prescaling values and their corresponding time-out periods are

shown in Table 20 on page 46.

45

2543I–AVR–04/06

Table 20. Watchdog Timer Prescale Select

Number of WDT Oscillator

Typical Time-out at

V_CC= 5.0V

WDP3 WDP2 WDP1 WDP0

Cycles

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2K (2048) cycles

16 ms

32 ms

64 ms

0.125 s

0.25 s

0.5 s

4K (4096) cycles

8K (8192) cycles

16K (16384) cycles

32K (32768) cycles

64K (65536) cycles

128K (131072) cycles

256K (262144) cycles

512K (524288) cycles

1024K (1048576) cycles

1.0 s

2.0 s

4.0 s

8.0 s

Reserved

46

ATtiny2313/V

2543I–AVR–04/06

ATtiny2313/V

Interrupts

This section describes the specifics of the interrupt handling as performed in

ATtiny2313. For a general explanation of the AVR interrupt handling, refer to “Reset and

Interrupt Handling” on page 14.

Interrupt Vectors in

ATtiny2313

Table 21. Reset and Interrupt Vectors

Vector Program

No.

Address Source

Interrupt Definition

1

0x0000

RESET

External Pin, Power-on Reset, Brown-out Reset,

and Watchdog Reset

2

3

0x0001

0x0002

0x0003

0x0004

0x0005

0x0006

0x0007

0x0008

0x0009

0x000A

0x000B

0x000C

0x000D

0x000E

0x000F

0x0010

0x0011

0x0012

INT0

External Interrupt Request 0

External Interrupt Request 1

Timer/Counter1 Capture Event

Timer/Counter1 Compare Match A

Timer/Counter1 Overflow

Timer/Counter0 Overflow

USART0, Rx Complete

INT1

4

TIMER1 CAPT

TIMER1 COMPA

TIMER1 OVF

TIMER0 OVF

USART0, RX

USART0, UDRE

USART0, TX

ANALOG COMP

PCINT

5

6

7

8

9

USART0 Data Register Empty

USART0, Tx Complete

10

11

12

13

14

15

16

17

18

19

Analog Comparator

Pin Change Interrupt

TIMER1 COMPB

TIMER0 COMPA

TIMER0 COMPB

USI START

Timer/Counter1 Compare Match B

Timer/Counter0 Compare Match A

Timer/Counter0 Compare Match B

USI Start Condition

USI OVERFLOW

EE READY

USI Overflow

EEPROM Ready

WDT OVERFLOW Watchdog Timer Overflow

47

2543I–AVR–04/06

The most typical and general program setup for the Reset and Interrupt Vector

Addresses in ATtiny2313 is:

Address Labels Code

Comments

0x0000

0x0001

0x0002

0x0003

0x0004

0x0005

0x0006

0x0007

0x0008

0x0009

0x000A

0x000B

0x000C

0x000D

0x000E

0x000F

0x0010

0x0011

0x0012

rjmp

RESET

; Reset Handler

INT0

; External Interrupt0 Handler

; External Interrupt1 Handler

; Timer1 Capture Handler

; Timer1 CompareA Handler

; Timer1 Overflow Handler

; Timer0 Overflow Handler

; USART0 RX Complete Handler

; USART0,UDR Empty Handler

; USART0 TX Complete Handler

; Analog Comparator Handler

; Pin Change Interrupt

; Timer1 Compare B Handler

; Timer0 Compare A Handler

; Timer0 Compare B Handler

; USI Start Handler

INT1

TIM1_CAPT

TIM1_COMPA

TIM1_OVF

TIM0_OVF

USART0_RXC

USART0_DRE

USART0_TXC

ANA_COMP

PCINT

TIMER1_COMPB

TIMER0_COMPA

TIMER0_COMPB

USI_START

USI_OVERFLOW

EE_READY

; USI Overflow Handler

; EEPROM Ready Handler

; Watchdog Overflow Handler

WDT_OVERFLOW

;

0x0013 RESET: ldi

r16, low(RAMEND); Main program start

SPL,r16 Set Stack Pointer to top of

0x0014

RAM

out

0x0015

0x0016

...

sei

; Enable interrupts

<instr> xxx

... ...

...

48

ATtiny2313/V

2543I–AVR–04/06

ATtiny2313/V

I/O-Ports

Introduction

All AVR ports have true Read-Modify-Write functionality when used as general digital

I/O ports. This means that the direction of one port pin can be changed without uninten-

tionally changing the direction of any other pin with the SBI and CBI instructions. The

same applies when changing drive value (if configured as output) or enabling/disabling

of pull-up resistors (if configured as input). Each output buffer has symmetrical drive

characteristics with both high sink and source capability. The pin driver is strong enough

to drive LED displays directly. All port pins have individually selectable pull-up resistors

with a supply-voltage invariant resistance. All I/O pins have protection diodes to both

V

_CCand Ground as indicated in Figure 21. Refer to “Electrical Characteristics” on page

181 for a complete list of parameters.

Figure 21. I/O Pin Equivalent Schematic

R_pu

Pxn

Logic

C_pin

See Figure

"General Digital I/O" for

Details

All registers and bit references in this section are written in general form. A lower case

“x” represents the numbering letter for the port, and a lower case “n” represents the bit

number. However, when using the register or bit defines in a program, the precise form

must be used. For example, PORTB3 for bit no. 3 in Port B, here documented generally

as PORTxn. The physical I/O Registers and bit locations are listed in “Register Descrip-

tion for I/O-Ports” on page 61.

Three I/O memory address locations are allocated for each port, one each for the Data

Register – PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The

Port Input Pins I/O location is read only, while the Data Register and the Data Direction

Register are read/write. However, writing a logic one to a bit in the PINx Register, will

result in a toggle in the corresponding bit in the Data Register. In addition, the Pull-up

Disable – PUD bit in MCUCR disables the pull-up function for all pins in all ports when

set.

Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O” on

page 50. Most port pins are multiplexed with alternate functions for the peripheral fea-

tures on the device. How each alternate function interferes with the port pin is described

in “Alternate Port Functions” on page 54. Refer to the individual module sections for a

full description of the alternate functions.

49

2543I–AVR–04/06

Note that enabling the alternate function of some of the port pins does not affect the use

of the other pins in the port as general digital I/O.

Ports as General Digital

I/O

The ports are bi-directional I/O ports with optional internal pull-ups. Figure 22 shows a

functional description of one I/O-port pin, here generically called Pxn.

Figure 22. General Digital I/O⁽¹⁾

PUD

Q

D

DDxn

Q _CLR

WDx

RDx

RESET

1

0

Q

D

Pxn

PORTxn

Q _CLR

WPx

WRx

RESET

SLEEP

RRx

SYNCHRONIZER

RPx

D

Q

D

L

Q

PINxn

Q

clk _I/O

WDx:

RDx:

WRx:

RRx:

RPx:

WPx:

WRITE DDRx

READ DDRx

WRITE PORTx

PUD:

PULLUP DISABLE

SLEEP CONTROL

I/O CLOCK

SLEEP:

clk_I/O

:

READ PORTx REGISTER

READ PORTx PIN

WRITE PINx REGISTER

Note:

1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port.

clk_I/O, SLEEP, and PUD are common to all ports.

Configuring the Pin

Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in

“Register Description for I/O-Ports” on page 61, the DDxn bits are accessed at the

DDRx I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at

the PINx I/O address.

The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written

logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is config-

ured as an input pin.

If PORTxn is written logic one when the pin is configured as an input pin, the pull-up

resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic

zero or the pin has to be configured as an output pin. The port pins are tri-stated when

reset condition becomes active, even if no clocks are running.

If PORTxn is written logic one when the pin is configured as an output pin, the port pin is

driven high (one). If PORTxn is written logic zero when the pin is configured as an out-

put pin, the port pin is driven low (zero).

50

ATtiny2313/V

2543I–AVR–04/06

ATtiny2313/V

Toggling the Pin

Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of

DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port.

Switching Between Input and When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn,

Output

PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} =

0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up

enabled state is fully acceptable, as a high-impedant environment will not notice the dif-

ference between a strong high driver and a pull-up. If this is not the case, the PUD bit in

the MCUCR Register can be set to disable all pull-ups in all ports.

Switching between input with pull-up and output low generates the same problem. The

user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state

({DDxn, PORTxn} = 0b11) as an intermediate step.

Table 22 summarizes the control signals for the pin value.

Table 22. Port Pin Configurations

PUD

DDxn PORTxn (in MCUCR)

I/O

Pull-up Comment

0

X

Input

No

Tri-state (Hi-Z)

Pxn will source current if ext. pulled

low.

0

1

0

1

0

1

Input

Yes

No

Tri-state (Hi-Z)

X

Output

Output Low (Sink)

Output High (Source)

Reading the Pin Value

Independent of the setting of Data Direction bit DDxn, the port pin can be read through

the PINxn Register bit. As shown in Figure 22, the PINxn Register bit and the preceding

latch constitute a synchronizer. This is needed to avoid metastability if the physical pin

changes value near the edge of the internal clock, but it also introduces a delay. Figure

23 shows a timing diagram of the synchronization when reading an externally applied

pin value. The maximum and minimum propagation delays are denoted t_pd,maxand t_pd,min

respectively.

Figure 23. Synchronization when Reading an Externally Applied Pin value

SYSTEM CLK

XXX

in r17, PINx

INSTRUCTIONS

SYNC LATCH

PINxn

0x00

t_{pd, max}

0xFF

r17

t_{pd, min}

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2543I–AVR–04/06

Consider the clock period starting shortly after the first falling edge of the system clock.

The latch is closed when the clock is low, and goes transparent when the clock is high,

as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is

latched when the system clock goes low. It is clocked into the PINxn Register at the suc-

ceeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a

single signal transition on the pin will be delayed between ½ and 1½ system clock

period depending upon the time of assertion.

When reading back a software assigned pin value, a nop instruction must be inserted as

indicated in Figure 24. The out instruction sets the “SYNC LATCH” signal at the positive

edge of the clock. In this case, the delay tpd through the synchronizer is 1 system clock

period.

Figure 24. Synchronization when Reading a Software Assigned Pin Value

SYSTEM CLK

0xFF

r16

out PORTx, r16

nop

in r17, PINx

INSTRUCTIONS

SYNC LATCH

PINxn

0x00

t_pd

0xFF

r17

52

ATtiny2313/V

2543I–AVR–04/06

ATtiny2313/V

The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and

define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The

resulting pin values are read back again, but as previously discussed, a nop instruction

is included to be able to read back the value recently assigned to some of the pins.

Assembly Code Example⁽¹⁾

...

; Define pull-ups and set outputs high

; Define directions for port pins

ldi r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0)

ldi r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)

out PORTB,r16

out DDRB,r17

; Insert nop for synchronization

nop

; Read port pins

in

r16,PINB

...

C Code Example

unsigned char i;

...

/* Define pull-ups and set outputs high */

/* Define directions for port pins */

PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0);

DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);

/* Insert nop for synchronization*/

__no_operation();

/* Read port pins */

i = PINB;

...

Note:

1. For the assembly program, two temporary registers are used to minimize the time

from pull-ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set,

defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers.

Digital Input Enable and Sleep As shown in Figure 22, the digital input signal can be clamped to ground at the input of

Modes

the Schmitt Trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep

Controller in Power-down mode, and Standby mode to avoid high power consumption if

some input signals are left floating, or have an analog signal level close to V_CC/2.

SLEEP is overridden for port pins enabled as external interrupt pins. If the external inter-

rupt request is not enabled, SLEEP is active also for these pins. SLEEP is also

overridden by various other alternate functions as described in “Alternate Port Func-

tions” on page 54.

If a logic high level (“one”) is present on an asynchronous external interrupt pin config-

ured as “Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the

external interrupt is not enabled, the corresponding External Interrupt Flag will be set

when resuming from the above mentioned Sleep mode, as the clamping in these sleep

mode produces the requested logic change.

53

2543I–AVR–04/06

Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. Figure

25 shows how the port pin control signals from the simplified Figure 22 can be overrid-

den by alternate functions. The overriding signals may not be present in all port pins, but

the figure serves as a generic description applicable to all port pins in the AVR micro-

controller family.

Figure 25. Alternate Port Functions⁽¹⁾

PUOExn

PUOVxn

1

PUD

0

DDOExn

DDOVxn

1

Q

D

0

DDxn

Q _CLR

WDx

RDx

PVOExn

PVOVxn

RESET

1

0

1

0

Pxn

Q

D

PORTxn

PTOExn

WPx

Q _CLR

DIEOExn

DIEOVxn

SLEEP

RESET

WRx

1

0

RRx

RPx

SYNCHRONIZER

SET

D

Q

D

L

Q

PINxn

_CLRQ

CLR

clk _I/O

DIxn

AIOxn

PUOExn: Pxn PULL-UP OVERRIDE ENABLE

PUOVxn: Pxn PULL-UP OVERRIDE VALUE

DDOExn: Pxn DATA DIRECTION OVERRIDE ENABLE

DDOVxn: Pxn DATA DIRECTION OVERRIDE VALUE

PVOExn: Pxn PORT VALUE OVERRIDE ENABLE

PVOVxn: Pxn PORT VALUE OVERRIDE VALUE

PUD:

WDx:

RDx:

RRx:

WRx:

RPx:

WPx:

PULLUP DISABLE

WRITE DDRx

READ DDRx

READ PORTx REGISTER

WRITE PORTx

READ PORTx PIN

WRITE PINx

I/O CLOCK

DIGITAL INPUT PIN n ON PORTx

ANALOG INPUT/OUTPUT PIN n ON PORTx

DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE

DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE

clk_I/O

DIxn:

AIOxn:

:

SLEEP:

SLEEP CONTROL

PTOExn: Pxn, PORT TOGGLE OVERRIDE ENABLE

Note:

1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port.

clk_I/O, SLEEP, and PUD are common to all ports. All other signals are unique for each

pin.

Table 23 summarizes the function of the overriding signals. The pin and port indexes

from Figure 25 are not shown in the succeeding tables. The overriding signals are gen-

erated internally in the modules having the alternate function.

54

ATtiny2313/V

2543I–AVR–04/06

ATtiny2313/V

Table 23. Generic Description of Overriding Signals for Alternate Functions

Signal Name Full Name Description

PUOE

PUOV

DDOE

DDOV

PVOE

Pull-up Override

Enable

If this signal is set, the pull-up enable is controlled by the

PUOV signal. If this signal is cleared, the pull-up is

enabled when {DDxn, PORTxn, PUD} = 0b010.

Pull-up Override

Value

If PUOE is set, the pull-up is enabled/disabled when

PUOV is set/cleared, regardless of the setting of the

DDxn, PORTxn, and PUD Register bits.

Data Direction

Override Enable

If this signal is set, the Output Driver Enable is controlled

by the DDOV signal. If this signal is cleared, the Output

driver is enabled by the DDxn Register bit.

Data Direction

Override Value

If DDOE is set, the Output Driver is enabled/disabled

when DDOV is set/cleared, regardless of the setting of

the DDxn Register bit.

Port Value

Override Enable

If this signal is set and the Output Driver is enabled, the

port value is controlled by the PVOV signal. If PVOE is

cleared, and the Output Driver is enabled, the port Value

is controlled by the PORTxn Register bit.

PVOV

PTOE

DIEOE

Port Value

Override Value

If PVOE is set, the port value is set to PVOV, regardless

of the setting of the PORTxn Register bit.

Port Toggle

Override Enable

If PTOE is set, the PORTxn Register bit is inverted.

Digital Input

Enable Override

Enable

If this bit is set, the Digital Input Enable is controlled by

the DIEOV signal. If this signal is cleared, the Digital Input

Enable is determined by MCU state (Normal mode, sleep

mode).

DIEOV

DI

Digital Input

Enable Override

Value

If DIEOE is set, the Digital Input is enabled/disabled when

DIEOV is set/cleared, regardless of the MCU state

(Normal mode, sleep mode).

Digital Input

This is the Digital Input to alternate functions. In the

figure, the signal is connected to the output of the schmitt

trigger but before the synchronizer. Unless the Digital

Input is used as a clock source, the module with the

alternate function will use its own synchronizer.

AIO

Analog

Input/Output

This is the Analog Input/output to/from alternate

functions. The signal is connected directly to the pad, and

can be used bi-directionally.

The following subsections shortly describe the alternate functions for each port, and

relate the overriding signals to the alternate function. Refer to the alternate function

description for further details.

55

2543I–AVR–04/06

MCU Control Register –

MCUCR

Bit

7

6

5

SE

R/W

0

4

3

ISC11

R/W

0

2

ISC10

R/W

0

1

ISC01

R/W

0

ISC00

R/W

0

PUD

R/W

0

SM1

R/W

0

SM0

R/W

0

MCUCR

Read/Write

Initial Value

• Bit 7 – PUD: Pull-up Disable

When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn

and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01).

See “Configuring the Pin” on page 50 for more details about this feature.

Alternate Functions of Port A The Port A pins with alternate functions are as shown in Table 5.

Table 24. Port A Pins Alternate Functions

Port Pin

PA2

Alternate Function

RESET, dW

XTAL2

PA1

PA0

XTAL1

Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 25.

Table 25. Port B Pins Alternate Functions

Port Pin Alternate Functions

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

USCK/SCL/PCINT7

DO/PCINT6

DI/SDA/PCINT5

OC1B/PCINT4

OC1A/PCINT3

OC0A/PCINT2

AIN1/PCINT1

AIN0/PCINT0

The alternate pin configuration is as follows:

• USCK/SCL/PCINT7 - Port B, Bit 7

USCK: Three-wire mode Universal Serial Interface Clock.

SCL: Two-wire mode Serial Clock for USI Two-wire mode.

PCINT7: Pin Change Interrupt source 7. The PB7 pin can serve as an external interrupt

source.

• DO/PCINT6 - Port B, Bit 6

DO: Three-wire mode Universal Serial Interface Data output. Three-wire mode Data out-

put overrides PORTB6 value and it is driven to the port when data direction bit DDB6 is

set (one). However the PORTB6 bit still controls the pull-up enabling pull-up, if direction

is input and PORTB6 is set (one).

PCINT6: Pin Change Interrupt Source 6. The PB6 pin can serve as an external interrupt

source.

56

ATtiny2313/V

2543I–AVR–04/06

ATtiny2313/V

• DI/SDA/PCINT5 - Port B, Bit 5

DI: Three-wire mode Universal Serial Interface Data input. Three-wire mode does not

override normal port functions, so pin must be configured as an input. SDA: Two-wire

mode Serial Interface Data.

PCINT5: Pin Change Interrupt Source 5. The PB5 pin can serve as an external interrupt

source.

• OC1B/PCINT4 – Port B, Bit 4

OC1B: Output Compare Match B output: The PB4 pin can serve as an external output

for the Timer/Counter1 Output Compare B. The pin has to be configured as an output

(DDB4 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM

mode timer function.

PCINT4: Pin Change Interrupt Source 4. The PB4 pin can serve as an external interrupt

source.

• OC1A/PCINT3 – Port B, Bit 3

OC1A: Output Compare Match A output: The PB3 pin can serve as an external output

for the Timer/Counter1 Output Compare A. The pin has to be configured as an output

(DDB3 set (one)) to serve this function. The OC1A pin is also the output pin for the PWM

mode timer function.

PCINT3: Pin Change Interrupt Source 3: The PB3 pin can serve as an external interrupt

source.

• OC0A/PCINT2 – Port B, Bit 2

OC0A: Output Compare Match A output. The PB2 pin can serve as an external output

for the Timer/Counter0 Output Compare A. The pin has to be configured as an output

(DDB2 set (one)) to serve this function. The OC0A pin is also the output pin for the PWM

mode timer function.

PCINT2: Pin Change Interrupt Source 2. The PB2 pin can serve as an external interrupt

source.

• AIN1/PCINT1 – Port B, Bit 1

AIN1: Analog Comparator Negative input. Configure the port pin as input with the inter-

nal pull-up switched off to avoid the digital port function from interfering with the function

of the analog comparator.

PCINT1: Pin Change Interrupt Source 1. The PB1 pin can serve as an external interrupt

source.

• AIN0/PCINT0 – Port B, Bit 0

AIN0: Analog Comparator Positive input. Configure the port pin as input with the internal

pull-up switched off to avoid the digital port function from interfering with the function of

the Analog Comparator.

PCINT0: Pin Change Interrupt Source 0. The PB0 pin can serve as an external interrupt

source.

Table 26 and Table 27 relate the alternate functions of Port B to the overriding signals

shown in Figure 25 on page 54. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute

the MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE

INPUT.

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2543I–AVR–04/06

Table 26. Overriding Signals for Alternate Functions in PB7..PB4

Signal

Name

PB7/USCK/

SCL/PCINT7

PB5/SDA/

DI/PCINT5

PB4/OC1B/

PCINT4

PB6/DO/PCINT6

PUOE

PUOV

DDOE

DDOV

USI_TWO_WIRE

0

USI_TWO_WIRE

(USI_SCL_HOLD+

PORTB7)•DDB7

(SDA + PORTB5)•

DDB5

PVOE

USI_TWO_WIRE •

DDB7

USI_THREE_WIRE USI_TWO_WIRE

• DDB5

OC1B_PVOE

PVOV

PTOE

DIEOE

0

DO

0

0OC1B_PVOV

0

USI_PTOE

0

(PCINT7•PCIE)

+USISIE

(PCINT6•PCIE)

(PCINT5•PCIE) +

USISIE

(PCINT4•PCIE)

DIEOV

DI

1

PCINT7 INPUT

USCK INPUT SCL

INPUT

PCINT6 INPUT

PCINT5 INPUT

SDA INPUT

DI INPUT

PCINT4 INPUT

AIO

–

Table 27. Overriding Signals for Alternate Functions in PB3..PB0

Signal

Name

PB3/OC1A/

PCINT3

PB2/OC0A/

PCINT2

PB1/AIN1/

PCINT1

PB0/AIN0/

PCINT0

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

PTOE

DIEOE

DIEOV

DI

0

OC1A_PVOE

OC0A_PVOE

0

OC1A_PVOV

OC0A_PVOV

0

(PCINT3 • PCIE)

(PCINT2 • PCIE)

(PCINT1 • PCIE)

(PCINT0 • PCIE)

1

PCINT7 INPUT

–

PCINT6 INPUT

–

PCINT5 INPUT

AIN1

PCINT4 INPUT

AIN0

AIO

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ATtiny2313/V

Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 28.

Table 28. Port D Pins Alternate Functions

Port Pin

PD6

Alternate Function

ICP

PD5

OC0B/T1

PD4

T0

PD3

INT1

PD2

INT0/XCK/CKOUT

PD1

TXD

RXD

PD0

The alternate pin configuration is as follows:

• ICP – Port D, Bit 6

ICP: Timer/Counter1 Input Capture Pin. The PD6 pin can act as an Input Capture pin for

Timer/Counter1

• OC0B/T1 – Port D, Bit 5

OC0B: Output Compare Match B output: The PD5 pin can serve as an external output

for the Timer/Counter0 Output Compare B. The pin has to be configured as an output

(DDD5 set (one)) to serve this function. The OC0B pin is also the output pin for the

PWM mode timer function.

T1: Timer/Counter1 External Counter Clock input is enabled by setting (one) the bits

CS02 and CS01 in the Timer/Counter1 Control Register (TCCR1).

• T0 – Port D, Bit 4

T0: Timer/Counter0 External Counter Clock input is enabled by setting (one) the bits

CS02 and CS01 in the Timer/Counter0 Control Register (TCCR0).

• INT1 – Port D, Bit 3

INT1: External Interrupt Source 1. The PD3 pin can serve as an external interrupt

source to the MCU.

• INT0/XCK/CKOUT – Port D, Bit 2

INT0: External Interrupt Source 0. The PD2 pin can serve as en external interrupt

source to the MCU.

XCK: USART Transfer Clock used only by Synchronous Transfer mode.

CKOUT: System Clock Output

• TXD – Port D, Bit 1

TXD: UART Data Transmitter.

• RXD – Port D, Bit 0

RXD: UART Data Receiver.

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Table 29 and Table 30 relates the alternate functions of Port D to the overriding signals

shown in Figure 25 on page 54.

Table 29. Overriding Signals for Alternate Functions PD7..PD4

Signal

Name

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

PTOE

DIEOE

DIEOV

DI

PD6/ICP

PD5/OC1B/T1

PD4/T0

0

OC1B_PVOE

0

OC1B_PVOV

0

ICP ENABLE

T1 ENABLE

T0 ENABLE

1

ICP INPUT

–

T1 INPUT

–

T0 INPUT

AIN1

AIO

Table 30. Overriding Signals for Alternate Functions in PD3..PD0

Signal

Name

PD2/INT0/XCK/

CKOUT

PD3/INT1

PD1/TXD

PD0/RXD

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

PTOE

DIEOE

0

TXD_OE

RXD_OE

0

PORTD0 • PUD

0

TXD_OE

RXD_EN

0

1

0

XCKO_PVOE

XCKO_PVOV

0

TXD_OE

0

TXD_PVOV

0

INT1 ENABLE

INT0 ENABLE/

XCK INPUT

ENABLE

DIEOV

DI

1

0

–

0

INT1 INPUT

INT0 INPUT/

XCK INPUT

RXD INPUT

AIO

–

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ATtiny2313/V

Register Description for I/O-Ports

Port A Data Register – PORTA

Bit

7

–

6

–

5

–

4

–

3

–

2

PORTA2

R/W

0

1

PORTA1

R/W

0

PORTA0

R/W

0

PORTA

DDRA

PINA

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

Port A Data Direction Register

– DDRA

Bit

7

–

6

–

5

–

4

–

3

–

2

DDA2

R/W

0

1

DDA1

R/W

0

DDA0

R/W

0

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

Port A Input Pins Address –

PINA

Bit

7

–

6

–

5

–

4

–

3

–

2

1

0

PINA2

R/W

N/A

PINA1

R/W

N/A

PINA0

R/W

N/A

Read/Write

Initial Value

R

N/A

Port B Data Register – PORTB

Bit

7

PORTB7

R/W

0

6

PORTB6

R/W

0

5

PORTB5

R/W

0

4

PORTB4

R/W

0

3

PORTB3

R/W

0

2

PORTB2

R/W

0

1

PORTB1

R/W

0

PORTB0

R/W

0

PORTB

DDRB

PINB

Read/Write

Initial Value

Port B Data Direction Register

– DDRB

Bit

7

DDB7

R/W

0

6

DDB6

R/W

0

5

DDB5

R/W

0

4

DDB4

R/W

0

3

DDB3

R/W

0

2

DDB2

R/W

0

1

DDB1

R/W

0

DDB0

R/W

0

Read/Write

Initial Value

Port B Input Pins Address –

PINB

Bit

7

6

5

4

3

2

1

0

PINB7

R/W

N/A

PINB6

R/W

N/A

PINB5

R/W

N/A

PINB4

R/W

N/A

PINB3

R/W

N/A

PINB2

R/W

N/A

PINB1

R/W

N/A

PINB0

R/W

N/A

Read/Write

Initial Value

Port D Data Register – PORTD

Bit

7

–

6

PORTD6

R/W

0

5

PORTD5

R/W

0

4

PORTD4

R/W

0

3

PORTD3

R/W

0

2

PORTD2

R/W

0

1

PORTD1

R/W

0

PORTD0

R/W

0

PORTD

DDRD

PIND

Read/Write

Initial Value

R

0

Port D Data Direction Register

– DDRD

Bit

7

–

6

DDD6

R/W

0

5

DDD5

R/W

0

4

DDD4

R/W

0

3

DDD3

R/W

0

2

DDD2

R/W

0

1

DDD1

R/W

0

DDD0

R/W

0

Read/Write

Initial Value

R

0

Port D Input Pins Address –

PIND

Bit

7

–

6

5

4

3

2

1

0

PIND6

R/W

N/A

PIND5

R/W

N/A

PIND4

R/W

N/A

PIND3

R/W

N/A

PIND2

R/W

N/A

PIND1

R/W

N/A

PIND0

R/W

N/A

Read/Write

Initial Value

R

N/A

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External Interrupts

The External Interrupts are triggered by the INT0 pin, INT1 pin or any of the PCINT7..0

pins. Observe that, if enabled, the interrupts will trigger even if the INT0, INT1 or

PCINT7..0 pins are configured as outputs. This feature provides a way of generating a

software interrupt. The pin change interrupt PCIF will trigger if any enabled PCINT7..0

pin toggles. The PCMSK Register control which pins contribute to the pin change inter-

rupts. Pin change interrupts on PCINT7..0 are detected asynchronously. This implies

that these interrupts can be used for waking the part also from sleep modes other than

Idle mode.

The INT0 and INT1 interrupts can be triggered by a falling or rising edge or a low level.

This is set up as indicated in the specification for the “MCU Control Register – MCUCR”

on page 33. When the INT0 or INT1 interrupt is enabled and is configured as level trig-

gered, the interrupt will trigger as long as the pin is held low. Note that recognition of

falling or rising edge interrupts on INT0 and INT1 requires the presence of an I/O clock,

described in “Clock Systems and their Distribution” on page 24. Low level interrupt on

INT0 and INT1 is detected asynchronously. This implies that this interrupt can be used

for waking the part from sleep modes other than Idle mode. The I/O clock is halted in all

sleep modes except Idle mode.

Note that if a level triggered interrupt is used for wake-up from Power-down, the

required level must be held long enough for the MCU to complete the wake-up to trigger

the level interrupt. If the level disappears before the end of the Start-up Time, the MCU

will still wake up, but no interrupt will be generated. The start-up time is defined by the

SUT and CKSEL Fuses as described in “System Clock and Clock Options” on page 24.

Pin Change Interrupt

Timing

An example of timing of a pin change interrupt is shown in Figure 26.

Figure 26.

pin_lat

pcint_in_(0)

PCINT(0)

clk

0

x

D

Q

pcint_syn

pcint_setflag

PCIF

pin_sync

PCINT(0) in PCMSK(x)

LE

clk

PCINT(n)

pin_lat

pin_sync

pcint_in_(n)

pcint_syn

pcint_setflag

PCIF

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ATtiny2313/V

MCU Control Register –

MCUCR

The External Interrupt Control Register contains control bits for interrupt sense control.

Bit

7

6

5

SE

R/W

0

4

SMD

R/W

0

3

ISC11

R/W

0

2

ISC10

R/W

0

1

ISC01

R/W

0

ISC00

R/W

0

PUD

R/W

0

SM1

R/W

0

MCUCR

Read/Write

Initial Value

• Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0

The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the

corresponding interrupt mask are set. The level and edges on the external INT1 pin that

activate the interrupt are defined in Table 32. The value on the INT1 pin is sampled

before detecting edges. If edge or toggle interrupt is selected, pulses that last longer

than one clock period will generate an interrupt. Shorter pulses are not guaranteed to

generate an interrupt. If low level interrupt is selected, the low level must be held until

the completion of the currently executing instruction to generate an interrupt.

Table 31. Interrupt 1 Sense Control

ISC11

ISC10

Description

0

1

0

1

0

1

The low level of INT1 generates an interrupt request.

Any logical change on INT1 generates an interrupt request.

The falling edge of INT1 generates an interrupt request.

The rising edge of INT1 generates an interrupt request.

• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0

The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the

corresponding interrupt mask are set. The level and edges on the external INT0 pin that

activate the interrupt are defined in Table 32. The value on the INT0 pin is sampled

before detecting edges. If edge or toggle interrupt is selected, pulses that last longer

than one clock period will generate an interrupt. Shorter pulses are not guaranteed to

generate an interrupt. If low level interrupt is selected, the low level must be held until

the completion of the currently executing instruction to generate an interrupt.

Table 32. Interrupt 0 Sense Control

ISC01

ISC00

Description

0

1

0

1

0

1

The low level of INT0 generates an interrupt request.

Any logical change on INT0 generates an interrupt request.

The falling edge of INT0 generates an interrupt request.

The rising edge of INT0 generates an interrupt request.

General Interrupt Mask

Register – GIMSK

Bit

7

6

5

PCIE

R/W

0

4

–

3

–

2

–

1

–

0

–

INT1

R/W

0

INT0

R/W

0

GIMSK

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

• Bit 7 – INT1: External Interrupt Request 1 Enable

When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),

the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and

ISC10) in the MCU Control Register – MCUCR – define whether the external interrupt is

activated on rising and/or falling edge of the INT1 pin or level sensed. Activity on the pin

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2543I–AVR–04/06

will cause an interrupt request even if INT1 is configured as an output. The correspond-

ing interrupt of External Interrupt Request 1 is executed from the INT1 Interrupt Vector.

• Bit 6 – INT0: External Interrupt Request 0 Enable

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),

the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and

ISC00) in the MCU Control Register – MCUCR – define whether the external interrupt is

activated on rising and/or falling edge of the INT0 pin or level sensed. Activity on the pin

will cause an interrupt request even if INT0 is configured as an output. The correspond-

ing interrupt of External Interrupt Request 0 is executed from the INT0 Interrupt Vector.

• Bit 5 – PCIE: Pin Change Interrupt Enable

When the PCIE bit is set (one) and the I-bit in the Status Register (SREG) is set (one),

pin change interrupt 1 is enabled. Any change on any enabled PCINT7..0 pin will cause

an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed

from the PCI Interrupt Vector. PCINT7..0 pins are enabled individually by the PCMSK

Register.

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ATtiny2313/V

External Interrupt Flag

Register – EIFR

Bit

7

INTF1

R/W

0

6

INTF0

R/W

0

5

PCIF

R/W

0

4

–

3

–

2

–

1

–

0

–

EIFR

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

• Bit 7 – INTF1: External Interrupt Flag 1

When an edge or logic change on the INT1 pin triggers an interrupt request, INTF1

becomes set (one). If the I-bit in SREG and the INT1 bit in GIMSK are set (one), the

MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the inter-

rupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to

it. This flag is always cleared when INT1 is configured as a level interrupt.

• Bit 6 – INTF0: External Interrupt Flag 0

When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0

becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the

MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the inter-

rupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to

it. This flag is always cleared when INT0 is configured as a level interrupt.

• Bit 5 – PCIF: Pin Change Interrupt Flag

When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF becomes

set (one). If the I-bit in SREG and the PCIE bit in GIMSK are set (one), the MCU will

jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine

is executed. Alternatively, the flag can be cleared by writing a logical one to it.

Pin Change Mask Register –

PCMSK

Bit

7

PCINT7

R/W

0

6

PCINT6

R/W

0

5

PCINT5

R/W

0

4

PCINT4

R/W

0

3

PCINT3

R/W

0

2

PCINT2

R/W

0

1

PCINT1

R/W

0

PCINT0

R/W

0

PCMSK

Read/Write

Initial Value

• Bit 7..0 – PCINT7..0: Pin Change Enable Mask 7..0

Each PCINT7..0-bit selects whether pin change interrupt is enabled on the correspond-

ing I/O pin. If PCINT7..0 is set and the PCIE bit in GIMSK is set, pin change interrupt is

enabled on the corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on

the corresponding I/O pin is disabled.

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8-bit Timer/Counter0 Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent

Output Compare Units, and with PWM support. It allows accurate program execution

timing (event management) and wave generation. The main features are:

• Two Independent Output Compare Units

with PWM

• Double Buffered Output Compare Registers

• Clear Timer on Compare Match (Auto Reload)

• Glitch Free, Phase Correct Pulse Width Modulator (PWM)

• Variable PWM Period

• Frequency Generator

• Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B)

Overview

A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 27. For the

actual placement of I/O pins, refer to “Pinout ATtiny2313” on page 2. CPU accessible

I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O

Register and bit locations are listed in the “8-bit Timer/Counter Register Description” on

page 77.

Figure 27. 8-bit Timer/Counter Block Diagram

Count

TOVn

(Int.Req.)

Clear

Control Logic

Clock Select

Direction

clk_Tn

Edge

Detector

Tn

TOP

BOTTOM

( From Prescaler )

Timer/Counter

TCNTn

=

= 0

OCFnA

(Int.Req.)

Waveform

Generation

OCFnA

OCFnB

=

OCRnA

Fixed

TOP

Value

OCFnB

(Int.Req.)

Waveform

Generation

=

OCRnB

TCCRnA

TCCRnB

Registers

The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A and OCR0B) are

8-bit registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all vis-

ible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked

with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the

figure.

The Timer/Counter can be clocked internally, via the prescaler, or by an external clock

source on the T0 pin. The Clock Select logic block controls which clock source and edge

the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is

inactive when no clock source is selected. The output from the Clock Select logic is

referred to as the timer clock (clk_T0).

The double buffered Output Compare Registers (OCR0A and OCR0B) is compared with

the Timer/Counter value at all times. The result of the compare can be used by the

Waveform Generator to generate a PWM or variable frequency output on the Output

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ATtiny2313/V

Compare pins (OC0A and OC0B). See “Output Compare Unit” on page 68. for details.

The Compare Match event will also set the Compare Flag (OCF0A or OCF0B) which

can be used to generate an Output Compare interrupt request.

Definitions

Many register and bit references in this section are written in general form. A lower case

“n” replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the

Output Compare Unit, in this case Compare Unit A or Compare Unit B. However, when

using the register or bit defines in a program, the precise form must be used, i.e.,

TCNT0 for accessing Timer/Counter0 counter value and so on.

The definitions in Table 33 are also used extensively throughout the document.

Table 33. Definitions

BOTTOM The counter reaches the BOTTOM when it becomes 0x00.

MAX

TOP

The counter reaches its MAXimum when it becomes 0xFF (decimal 255).

The counter reaches the TOP when it becomes equal to the highest

value in the count sequence. The TOP value can be assigned to be the

fixed value 0xFF (MAX) or the value stored in the OCR0A Register. The

assignment is dependent on the mode of operation.

Timer/Counter Clock

Sources

The Timer/Counter can be clocked by an internal or an external clock source. The clock

source is selected by the Clock Select logic which is controlled by the Clock Select

(CS02:0) bits located in the Timer/Counter Control Register (TCCR0B). For details on

clock sources and prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers” on

page 84.

Counter Unit

The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.

Figure 28 shows a block diagram of the counter and its surroundings.

Figure 28. Counter Unit Block Diagram

TOVn

(Int.Req.)

DATA BUS

Clock Select

count

clear

Edge

Detector

Tn

clk_Tn

TCNTn

Control Logic

direction

( From Prescaler )

bottom

top

Signal description (internal signals):

count Increment or decrement TCNT0 by 1.

direction Select between increment and decrement.

clear

clk_Tn

top

Clear TCNT0 (set all bits to zero).

Timer/Counter clock, referred to as clk_T0in the following.

Signalize that TCNT0 has reached maximum value.

Signalize that TCNT0 has reached minimum value (zero).

bottom

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2543I–AVR–04/06

Depending of the mode of operation used, the counter is cleared, incremented, or dec-

remented at each timer clock (clk_T0). clk_T0can be generated from an external or internal

clock source, selected by the Clock Select bits (CS02:0). When no clock source is

selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessed

by the CPU, regardless of whether clk_T0is present or not. A CPU write overrides (has

priority over) all counter clear or count operations.

The counting sequence is determined by the setting of the WGM01 and WGM00 bits

located in the Timer/Counter Control Register (TCCR0A) and the WGM02 bit located in

the Timer/Counter Control Register B (TCCR0B). There are close connections between

how the counter behaves (counts) and how waveforms are generated on the Output

Compare output OC0A. For more details about advanced counting sequences and

waveform generation, see “Modes of Operation” on page 98.

The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation

selected by the WGM01:0 bits. TOV0 can be used for generating a CPU interrupt.

Output Compare Unit

The 8-bit comparator continuously compares TCNT0 with the Output Compare Regis-

ters (OCR0A and OCR0B). Whenever TCNT0 equals OCR0A or OCR0B, the

comparator signals a match. A match will set the Output Compare Flag (OCF0A or

OCF0B) at the next timer clock cycle. If the corresponding interrupt is enabled, the Out-

put Compare Flag generates an Output Compare interrupt. The Output Compare Flag is

automatically cleared when the interrupt is executed. Alternatively, the flag can be

cleared by software by writing a logical one to its I/O bit location. The Waveform Gener-

ator uses the match signal to generate an output according to operating mode set by the

WGM02:0 bits and Compare Output mode (COM0x1:0) bits. The max and bottom sig-

nals are used by the Waveform Generator for handling the special cases of the extreme

values in some modes of operation (see “Modes of Operation” on page 98).

Figure 29 shows a block diagram of the Output Compare unit.

Figure 29. Output Compare Unit, Block Diagram

DATA BUS

OCRnx

TCNTn

= (8-bit Comparator )

OCFnx (Int.Req.)

top

bottom

FOCn

Waveform Generator

OCnx

WGMn1:0

COMnX1:0

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ATtiny2313/V

The OCR0x Registers are double buffered when using any of the Pulse Width Modula-

tion (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of

operation, the double buffering is disabled. The double buffering synchronizes the

update of the OCR0x Compare Registers to either top or bottom of the counting

sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical

PWM pulses, thereby making the output glitch-free.

The OCR0x Register access may seem complex, but this is not case. When the double

buffering is enabled, the CPU has access to the OCR0x Buffer Register, and if double

buffering is disabled the CPU will access the OCR0x directly.

Force Output Compare

In non-PWM waveform generation modes, the match output of the comparator can be

forced by writing a one to the Force Output Compare (FOC0x) bit. Forcing Compare

Match will not set the OCF0x Flag or reload/clear the timer, but the OC0x pin will be

updated as if a real Compare Match had occurred (the COM0x1:0 bits settings define

whether the OC0x pin is set, cleared or toggled).

Compare Match Blocking by

TCNT0 Write

All CPU write operations to the TCNT0 Register will block any Compare Match that

occur in the next timer clock cycle, even when the timer is stopped. This feature allows

OCR0x to be initialized to the same value as TCNT0 without triggering an interrupt when

the Timer/Counter clock is enabled.

Using the Output Compare

Unit

Since writing TCNT0 in any mode of operation will block all Compare Matches for one

timer clock cycle, there are risks involved when changing TCNT0 when using the Output

Compare Unit, independently of whether the Timer/Counter is running or not. If the

value written to TCNT0 equals the OCR0x value, the Compare Match will be missed,

resulting in incorrect waveform generation. Similarly, do not write the TCNT0 value

equal to BOTTOM when the counter is down-counting.

The setup of the OC0x should be performed before setting the Data Direction Register

for the port pin to output. The easiest way of setting the OC0x value is to use the Force

Output Compare (FOC0x) strobe bits in Normal mode. The OC0x Registers keep their

values even when changing between Waveform Generation modes.

Be aware that the COM0x1:0 bits are not double buffered together with the compare

value. Changing the COM0x1:0 bits will take effect immediately.

Compare Match Output

Unit

The Compare Output mode (COM0x1:0) bits have two functions. The Waveform Gener-

ator uses the COM0x1:0 bits for defining the Output Compare (OC0x) state at the next

Compare Match. Also, the COM0x1:0 bits control the OC0x pin output source. Figure 30

shows a simplified schematic of the logic affected by the COM0x1:0 bit setting. The I/O

Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the

general I/O Port Control Registers (DDR and PORT) that are affected by the COM0x1:0

bits are shown. When referring to the OC0x state, the reference is for the internal OC0x

Register, not the OC0x pin. If a system reset occur, the OC0x Register is reset to “0”.

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Figure 30. Compare Match Output Unit, Schematic

COMnx1

Waveform

Generator

COMnx0

FOCn

D

Q

1

0

OCn

OCnx

D

Q

PORT

D

Q

DDR

clk_I/O

The general I/O port function is overridden by the Output Compare (OC0x) from the

Waveform Generator if either of the COM0x1:0 bits are set. However, the OC0x pin

direction (input or output) is still controlled by the Data Direction Register (DDR) for the

port pin. The Data Direction Register bit for the OC0x pin (DDR_OC0x) must be set as

output before the OC0x value is visible on the pin. The port override function is indepen-

dent of the Waveform Generation mode.

The design of the Output Compare pin logic allows initialization of the OC0x state before

the output is enabled. Note that some COM0x1:0 bit settings are reserved for certain

modes of operation. See “8-bit Timer/Counter Register Description” on page 77.

Compare Output Mode and

Waveform Generation

The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM

modes. For all modes, setting the COM0x1:0 = 0 tells the Waveform Generator that no

action on the OC0x Register is to be performed on the next Compare Match. For com-

pare output actions in the non-PWM modes refer to Figure 29 on page 68. For fast PWM

mode, refer to Table 26 on page 58, and for phase correct PWM refer to Table 27 on

page 58.

A change of the COM0x1:0 bits state will have effect at the first Compare Match after

the bits are written. For non-PWM modes, the action can be forced to have immediate

effect by using the FOC0x strobe bits.

Modes of Operation

The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare

pins, is defined by the combination of the Waveform Generation mode (WGM02:0) and

Compare Output mode (COM0x1:0) bits. The Compare Output mode bits do not affect

the counting sequence, while the Waveform Generation mode bits do. The COM0x1:0

bits control whether the PWM output generated should be inverted or not (inverted or

non-inverted PWM). For non-PWM modes the COM0x1:0 bits control whether the out-

put should be set, cleared, or toggled at a Compare Match (See “Compare Match

Output Unit” on page 69.).

For detailed timing information refer to Figure 34, Figure 35, Figure 36 and Figure 37 in

“Timer/Counter Timing Diagrams” on page 75.

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Normal Mode

The simplest mode of operation is the Normal mode (WGM02:0 = 0). In this mode the

counting direction is always up (incrementing), and no counter clear is performed. The

counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then

restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag

(TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero. The

TOV0 Flag in this case behaves like a ninth bit, except that it is only set, not cleared.

However, combined with the timer overflow interrupt that automatically clears the TOV0

Flag, the timer resolution can be increased by software. There are no special cases to

consider in the Normal mode, a new counter value can be written anytime.

The Output Compare Unit can be used to generate interrupts at some given time. Using

the Output Compare to generate waveforms in Normal mode is not recommended,

since this will occupy too much of the CPU time.

Clear Timer on Compare

Match (CTC) Mode

In Clear Timer on Compare or CTC mode (WGM02:0 = 2), the OCR0A Register is used

to manipulate the counter resolution. In CTC mode the counter is cleared to zero when

the counter value (TCNT0) matches the OCR0A. The OCR0A defines the top value for

the counter, hence also its resolution. This mode allows greater control of the Compare

Match output frequency. It also simplifies the operation of counting external events.

The timing diagram for the CTC mode is shown in Figure 31. The counter value

(TCNT0) increases until a Compare Match occurs between TCNT0 and OCR0A, and

then counter (TCNT0) is cleared.

Figure 31. CTC Mode, Timing Diagram

OCnx Interrupt Flag Set

TCNTn

OCn

(Toggle)

(COMnx1:0 = 1)

1

2

3

4

Period

An interrupt can be generated each time the counter value reaches the TOP value by

using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be

used for updating the TOP value. However, changing TOP to a value close to BOTTOM

when the counter is running with none or a low prescaler value must be done with care

since the CTC mode does not have the double buffering feature. If the new value written

to OCR0A is lower than the current value of TCNT0, the counter will miss the Compare

Match. The counter will then have to count to its maximum value (0xFF) and wrap

around starting at 0x00 before the Compare Match can occur.

For generating a waveform output in CTC mode, the OC0A output can be set to toggle

its logical level on each Compare Match by setting the Compare Output mode bits to

toggle mode (COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless

the data direction for the pin is set to output. The waveform generated will have a maxi-

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mum frequency of f_OC0= f_{clk_I/O}/2 when OCR0A is set to zero (0x00). The waveform

frequency is defined by the following equation:

f

clk_I/O

f

= -------------------------------------------------

OCnx

2 ⋅ N ⋅ (1 + OCRnx)

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle

that the counter counts from MAX to 0x00.

Fast PWM Mode

The fast Pulse Width Modulation or fast PWM mode (WGM02:0 = 3 or 7) provides a high

frequency PWM waveform generation option. The fast PWM differs from the other PWM

option by its single-slope operation. The counter counts from BOTTOM to TOP then

restarts from BOTTOM. TOP is defined as 0xFF when WGM2:0 = 3, and OCR0A when

WGM2:0 = 7. In non-inverting Compare Output mode, the Output Compare (OC0x) is

cleared on the Compare Match between TCNT0 and OCR0x, and set at BOTTOM. In

inverting Compare Output mode, the output is set on Compare Match and cleared at

BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM

mode can be twice as high as the phase correct PWM mode that use dual-slope opera-

tion. This high frequency makes the fast PWM mode well suited for power regulation,

rectification, and DAC applications. High frequency allows physically small sized exter-

nal components (coils, capacitors), and therefore reduces total system cost.

In fast PWM mode, the counter is incremented until the counter value matches the TOP

value. The counter is then cleared at the following timer clock cycle. The timing diagram

for the fast PWM mode is shown in Figure 30. The TCNT0 value is in the timing diagram

shown as a histogram for illustrating the single-slope operation. The diagram includes

non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0

slopes represent Compare Matches between OCR0x and TCNT0.

Figure 32. Fast PWM Mode, Timing Diagram

OCRnx Interrupt Flag Set

OCRnx Update and

TOVn Interrupt Flag Set

TCNTn

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCn

1

2

3

4

5

6

7

Period

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. If

the interrupt is enabled, the interrupt handler routine can be used for updating the com-

pare value.

In fast PWM mode, the compare unit allows generation of PWM waveforms on the

OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM and an

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inverted PWM output can be generated by setting the COM0x1:0 to three: Setting the

COM0A1:0 bits to one allows the AC0A pin to toggle on Compare Matches if the

WGM02 bit is set. This option is not available for the OC0B pin (See Table 26 on page

58). The actual OC0x value will only be visible on the port pin if the data direction for the

port pin is set as output. The PWM waveform is generated by setting (or clearing) the

OC0x Register at the Compare Match between OCR0x and TCNT0, and clearing (or

setting) the OC0x Register at the timer clock cycle the counter is cleared (changes from

TOP to BOTTOM).

The PWM frequency for the output can be calculated by the following equation:

f

clk_I/O

f

= -----------------

OCnxPWM

N ⋅ 256

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

The extreme values for the OCR0A Register represents special cases when generating

a PWM waveform output in the fast PWM mode. If the OCR0A is set equal to BOTTOM,

the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0A

equal to MAX will result in a constantly high or low output (depending on the polarity of

the output set by the COM0A1:0 bits.)

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved

by setting OC0x to toggle its logical level on each Compare Match (COM0x1:0 = 1). The

waveform generated will have a maximum frequency of f_OC0= f_{clk_I/O}/2 when OCR0A is

set to zero. This feature is similar to the OC0A toggle in CTC mode, except the double

buffer feature of the Output Compare unit is enabled in the fast PWM mode.

Phase Correct PWM Mode

The phase correct PWM mode (WGM02:0 = 1 or 5) provides a high resolution phase

correct PWM waveform generation option. The phase correct PWM mode is based on a

dual-slope operation. The counter counts repeatedly from BOTTOM to TOP and then

from TOP to BOTTOM. TOP is defined as 0xFF when WGM2:0 = 1, and OCR0A when

WGM2:0 = 5. In non-inverting Compare Output mode, the Output Compare (OC0x) is

cleared on the Compare Match between TCNT0 and OCR0x while upcounting, and set

on the Compare Match while down-counting. In inverting Output Compare mode, the

operation is inverted. The dual-slope operation has lower maximum operation frequency

than single slope operation. However, due to the symmetric feature of the dual-slope

PWM modes, these modes are preferred for motor control applications.

In phase correct PWM mode the counter is incremented until the counter value matches

TOP. When the counter reaches TOP, it changes the count direction. The TCNT0 value

will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct

PWM mode is shown on Figure 33. The TCNT0 value is in the timing diagram shown as

a histogram for illustrating the dual-slope operation. The diagram includes non-inverted

and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes repre-

sent Compare Matches between OCR0x and TCNT0.

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Figure 33. Phase Correct PWM Mode, Timing Diagram

OCnx Interrupt Flag Set

OCRnx Update

TOVn Interrupt Flag Set

TCNTn

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCn

1

2

3

Period

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOT-

TOM. The Interrupt Flag can be used to generate an interrupt each time the counter

reaches the BOTTOM value.

In phase correct PWM mode, the compare unit allows generation of PWM waveforms on

the OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. An

inverted PWM output can be generated by setting the COM0x1:0 to three: Setting the

COM0A0 bits to one allows the OC0A pin to toggle on Compare Matches if the WGM02

bit is set. This option is not available for the OC0B pin (See Table 27 on page 58). The

actual OC0x value will only be visible on the port pin if the data direction for the port pin

is set as output. The PWM waveform is generated by clearing (or setting) the OC0x

Register at the Compare Match between OCR0x and TCNT0 when the counter incre-

ments, and setting (or clearing) the OC0x Register at Compare Match between OCR0x

and TCNT0 when the counter decrements. The PWM frequency for the output when

using phase correct PWM can be calculated by the following equation:

f

clk_I/O

f

= -----------------

OCnxPCPWM

N ⋅ 510

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

The extreme values for the OCR0A Register represent special cases when generating a

PWM waveform output in the phase correct PWM mode. If the OCR0A is set equal to

BOTTOM, the output will be continuously low and if set equal to MAX the output will be

continuously high for non-inverted PWM mode. For inverted PWM the output will have

the opposite logic values.

At the very start of period 2 in Figure 33 OCn has a transition from high to low even

though there is no Compare Match. The point of this transition is to guarantee symmetry

around BOTTOM. There are two cases that give a transition without Compare Match.

•

OCR0A changes its value from MAX, like in Figure 33. When the OCR0A value is

MAX the OCn pin value is the same as the result of a down-counting Compare

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Match. To ensure symmetry around BOTTOM the OCn value at MAX must

correspond to the result of an up-counting Compare Match.

•

The timer starts counting from a value higher than the one in OCR0A, and for that

reason misses the Compare Match and hence the OCn change that would have

happened on the way up.

Timer/Counter Timing

Diagrams

The Timer/Counter is a synchronous design and the timer clock (clk_T0) is therefore

shown as a clock enable signal in the following figures. The figures include information

on when Interrupt Flags are set. Figure 34 contains timing data for basic Timer/Counter

operation. The figure shows the count sequence close to the MAX value in all modes

other than phase correct PWM mode.

Figure 34. Timer/Counter Timing Diagram, no Prescaling

clk_I/O

clk_Tn

(clk_I/O/1)

TCNTn

TOVn

MAX - 1

MAX

BOTTOM

BOTTOM + 1

Figure 34 shows the same timing data, but with the prescaler enabled.

Figure 35. Timer/Counter Timing Diagram, with Prescaler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

TOVn

MAX - 1

MAX

BOTTOM

BOTTOM + 1

Figure 36 shows the setting of OCF0B in all modes and OCF0A in all modes except

CTC mode and PWM mode, where OCR0A is TOP.

Figure 36. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

OCRnx

OCFnx

OCRnx - 1

OCRnx

OCRnx + 1

OCRnx + 2

OCRnx Value

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Figure 37 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast

PWM mode where OCR0A is TOP.

Figure 37. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with

Prescaler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

(CTC)

TOP - 1

TOP

BOTTOM

BOTTOM + 1

OCRnx

TOP

OCFnx

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8-bit Timer/Counter

Register Description

Timer/Counter Control

Register A – TCCR0A

Bit

7

COM0A1

R/W

6

COM0A0

R/W

5

COM0B1

R/W

4

COM0B0

R/W

3

–

2

–

1

WGM01

R/W

0

WGM00

R/W

0

TCCR0A

Read/Write

Initial Value

R

0

R

0

• Bits 7:6 – COM0A1:0: Compare Match Output A Mode

These bits control the Output Compare pin (OC0A) behavior. If one or both of the

COM0A1:0 bits are set, the OC0A output overrides the normal port functionality of the

I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit cor-

responding to the OC0A pin must be set in order to enable the output driver.

When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the

WGM02:0 bit setting. Table 34 shows the COM0A1:0 bit functionality when the

WGM02:0 bits are set to a normal or CTC mode (non-PWM).

Table 34. Compare Output Mode, non-PWM Mode

COM0A1

COM0A0

Description

0

1

0

1

0

1

Normal port operation, OC0A disconnected.

Toggle OC0A on Compare Match

Clear OC0A on Compare Match

Set OC0A on Compare Match

Table 35 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast

PWM mode.

Table 35. Compare Output Mode, Fast PWM Mode⁽¹⁾

COM0A1

COM0A0

Description

0

1

Normal port operation, OC0A disconnected.

WGM02 = 0: Normal Port Operation, OC0A Disconnected.

WGM02 = 1: Toggle OC0A on Compare Match.

1

0

1

Clear OC0A on Compare Match, set OC0A at TOP

Set OC0A on Compare Match, clear OC0A at TOP

Note:

1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case,

the Compare Match is ignored, but the set or clear is done at TOP. See “Fast PWM

Mode” on page 72 for more details.

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Table 36 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to

phase correct PWM mode.

Table 36. Compare Output Mode, Phase Correct PWM Mode⁽¹⁾

COM0A1

COM0A0

Description

0

1

Normal port operation, OC0A disconnected.

WGM02 = 0: Normal Port Operation, OC0A Disconnected.

WGM02 = 1: Toggle OC0A on Compare Match.

1

0

1

Clear OC0A on Compare Match when up-counting. Set OC0A on

Compare Match when down-counting.

Set OC0A on Compare Match when up-counting. Clear OC0A on

Compare Match when down-counting.

Note:

1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case,

the Compare Match is ignored, but the set or clear is done at TOP. See “Phase Cor-

rect PWM Mode” on page 73 for more details.

• Bits 5:4 – COM0B1:0: Compare Match Output B Mode

These bits control the Output Compare pin (OC0B) behavior. If one or both of the

COM0B1:0 bits are set, the OC0B output overrides the normal port functionality of the

I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit cor-

responding to the OC0B pin must be set in order to enable the output driver.

When OC0B is connected to the pin, the function of the COM0B1:0 bits depends on the

WGM02:0 bit setting. Table 37 shows the COM0A1:0 bit functionality when the

WGM02:0 bits are set to a normal or CTC mode (non-PWM).

Table 37. Compare Output Mode, non-PWM Mode

COM0B1

COM0B0

Description

0

1

0

1

0

1

Normal port operation, OC0B disconnected.

Toggle OC0B on Compare Match

Clear OC0B on Compare Match

Set OC0B on Compare Match

Table 38 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to fast

PWM mode.

Table 38. Compare Output Mode, Fast PWM Mode⁽¹⁾

COM0B1

COM0B0

Description

0

1

0

1

0

1

Normal port operation, OC0B disconnected.

Reserved

Clear OC0B on Compare Match, set OC0B at TOP

Set OC0B on Compare Match, clear OC0B at TOP

Note:

1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case,

the Compare Match is ignored, but the set or clear is done at TOP. See “Fast PWM

Mode” on page 72 for more details.

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Table 39 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to

phase correct PWM mode.

Table 39. Compare Output Mode, Phase Correct PWM Mode⁽¹⁾

COM0B1

COM0B0

Description

0

1

0

1

0

Normal port operation, OCR0B disconnected.

Reserved

Clear ORC0B on Compare Match when up-counting. Set OCR0B

on Compare Match when down-counting.

1

Set OCR0B on Compare Match when up-counting. Clear OCR0B

on Compare Match when down-counting.

Note:

1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case,

the Compare Match is ignored, but the set or clear is done at TOP. See “Phase Cor-

rect PWM Mode” on page 73 for more details.

• Bits 3, 2 – Res: Reserved Bits

These bits are reserved bits in the ATtiny2313 and will always read as zero.

• Bits 1:0 – WGM01:0: Waveform Generation Mode

Combined with the WGM02 bit found in the TCCR0B Register, these bits control the

counting sequence of the counter, the source for maximum (TOP) counter value, and

what type of waveform generation to be used, see Table 40. Modes of operation sup-

ported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare

Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes (see

“Modes of Operation” on page 70).

Table 40. Waveform Generation Mode Bit Description

Timer/Count

er Mode of

Update of

OCRx at

TOV Flag

Mode WGM2 WGM1 WGM0 Operation

TOP

0xFF

Set on⁽¹⁾⁽²⁾

0

1

0

1

Normal

Immediate

TOP

MAX

PWM, Phase

Correct

BOTTOM

2

3

4

5

0

1

0

1

0

1

CTC

OCR0A

0xFF

–

Immediate

TOP

MAX

Fast PWM

Reserved

–

PWM, Phase

Correct

OCR0A

TOP

BOTTOM

6

7

1

0

1

Reserved

Fast PWM

–

OCR0A

TOP

Notes: 1. MAX

= 0xFF

2. BOTTOM = 0x00

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Timer/Counter Control

Register B – TCCR0B

Bit

7

FOC0A

W

6

FOC0B

W

5

–

4

–

3

WGM02

R/W

0

2

CS02

R/W

0

1

CS01

R/W

0

CS00

R/W

0

TCCR0B

Read/Write

Initial Value

R

0

R

0

• Bit 7 – FOC0A: Force Output Compare A

The FOC0A bit is only active when the WGM bits specify a non-PWM mode.

However, for ensuring compatibility with future devices, this bit must be set to zero when

TCCR0B is written when operating in PWM mode. When writing a logical one to the

FOC0A bit, an immediate Compare Match is forced on the Waveform Generation unit.

The OC0A output is changed according to its COM0A1:0 bits setting. Note that the

FOC0A bit is implemented as a strobe. Therefore it is the value present in the

COM0A1:0 bits that determines the effect of the forced compare.

A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode

using OCR0A as TOP.

The FOC0A bit is always read as zero.

• Bit 6 – FOC0B: Force Output Compare B

The FOC0B bit is only active when the WGM bits specify a non-PWM mode.

However, for ensuring compatibility with future devices, this bit must be set to zero when

TCCR0B is written when operating in PWM mode. When writing a logical one to the

FOC0B bit, an immediate Compare Match is forced on the Waveform Generation unit.

The OC0B output is changed according to its COM0B1:0 bits setting. Note that the

FOC0B bit is implemented as a strobe. Therefore it is the value present in the

COM0B1:0 bits that determines the effect of the forced compare.

A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode

using OCR0B as TOP.

The FOC0B bit is always read as zero.

• Bits 5:4 – Res: Reserved Bits

These bits are reserved bits in the ATtiny2313 and will always read as zero.

• Bit 3 – WGM02: Waveform Generation Mode

See the description in the “Timer/Counter Control Register A – TCCR0A” on page 77.

• Bits 2:0 – CS02:0: Clock Select

The three Clock Select bits select the clock source to be used by the Timer/Counter.

See Table 41 on page 81.

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Table 41. Clock Select Bit Description

CS02

CS01

CS00 Description

0

1

0

1

0

1

0

1

0

1

0

1

0

1

No clock source (Timer/Counter stopped)

clk_I/O/(No prescaling)

clk_I/O/8 (From prescaler)

clk_I/O/64 (From prescaler)

clk_I/O/256 (From prescaler)

clk_I/O/1024 (From prescaler)

External clock source on T0 pin. Clock on falling edge.

External clock source on T0 pin. Clock on rising edge.

If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will

clock the counter even if the pin is configured as an output. This feature allows software

control of the counting.

Timer/Counter Register –

TCNT0

Bit

7

6

5

4

3

2

1

0

TCNT0[7:0]

TCNT0

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Timer/Counter Register gives direct access, both for read and write operations, to

the Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes)

the Compare Match on the following timer clock. Modifying the counter (TCNT0) while

the counter is running, introduces a risk of missing a Compare Match between TCNT0

and the OCR0x Registers.

Output Compare Register A –

OCR0A

Bit

7

6

5

4

3

2

1

0

OCR0A[7:0]

R/W R/W

OCR0A

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Output Compare Register A contains an 8-bit value that is continuously compared

with the counter value (TCNT0). A match can be used to generate an Output Compare

interrupt, or to generate a waveform output on the OC0A pin.

Output Compare Register B –

OCR0B

Bit

7

6

5

4

3

2

1

0

OCR0B[7:0]

R/W R/W

OCR0B

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Output Compare Register B contains an 8-bit value that is continuously compared

with the counter value (TCNT0). A match can be used to generate an Output Compare

interrupt, or to generate a waveform output on the OC0B pin.

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Timer/Counter Interrupt Mask

Register – TIMSK

Bit

7

TOIE1

R/W

0

6

OCIE1A

R/W

0

5

OCIE1B

R/W

0

4

–

3

ICIE1

R/W

0

2

OCIE0B

R/W

0

1

TOIE0

R/W

0

OCIE0A

R/W

0

TIMSK

Read/Write

Initial Value

R

0

• Bit 4 – Res: Reserved Bit

This bit is reserved bit in the ATtiny2313 and will always read as zero.

• Bit 2 – OCIE0B: Timer/Counter0 Output Compare Match B Interrupt Enable

When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the

Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is

executed if a Compare Match in Timer/Counter occurs, i.e., when the OCF0B bit is set in

the Timer/Counter Interrupt Flag Register – TIFR.

• Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable

When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the

Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if

an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the

Timer/Counter 0 Interrupt Flag Register – TIFR.

• Bit 0 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable

When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the

Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is

executed if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set

in the Timer/Counter 0 Interrupt Flag Register – TIFR.

Timer/Counter Interrupt Flag

Register – TIFR

Bit

7

TOV1

R/W

0

6

OCF1A

R/W

0

5

OCF1B

R/W

0

4

–

3

2

OCF0B

R/W

0

1

TOV0

R/W

0

OCF0A

R/W

0

ICF1

R/W

0

TIFR

Read/Write

Initial Value

R

0

• Bit 4 – Res: Reserved Bit

This bit is reserved bit in the ATtiny2313 and will always read as zero.

• Bit 2 – OCF0B: Output Compare Flag 0 B

The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and

the data in OCR0B – Output Compare Register0 B. OCF0B is cleared by hardware

when executing the corresponding interrupt handling vector. Alternatively, OCF0B is

cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0B

(Timer/Counter Compare B Match Interrupt Enable), and OCF0B are set, the

Timer/Counter Compare Match Interrupt is executed.

• Bit 1 – TOV0: Timer/Counter0 Overflow Flag

The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by

hardware when executing the corresponding interrupt handling vector. Alternatively,

TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0

(Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0

Overflow interrupt is executed.

The setting of this flag is dependent of the WGM02:0 bit setting. Refer to Table 40,

“Waveform Generation Mode Bit Description” on page 79.

• Bit 0 – OCF0A: Output Compare Flag 0 A

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The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and

the data in OCR0A – Output Compare Register0 A. OCF0A is cleared by hardware

when executing the corresponding interrupt handling vector. Alternatively, OCF0A is

cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0A

(Timer/Counter0 Compare Match Interrupt Enable), and OCF0A are set, the

Timer/Counter0 Compare Match Interrupt is executed.

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Timer/Counter0 and

Timer/Counter1

Prescalers

Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the

Timer/Counters can have different prescaler settings. The description below applies to

both Timer/Counter1 and Timer/Counter0.

Internal Clock Source

The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 =

1). This provides the fastest operation, with a maximum Timer/Counter clock frequency

equal to system clock frequency (f_{CLK_I/O}). Alternatively, one of four taps from the pres-

caler can be used as a clock source. The prescaled clock has a frequency of either

f_{CLK_I/O}/8, f_{CLK_I/O}/64, f_{CLK_I/O}/256, or f_{CLK_I/O}/1024.

Prescaler Reset

The prescaler is free running, i.e., operates independently of the Clock Select logic of

the Timer/Counter, and it is shared by Timer/Counter1 and Timer/Counter0. Since the

prescaler is not affected by the Timer/Counter’s clock select, the state of the prescaler

will have implications for situations where a prescaled clock is used. One example of

prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (6 >

CSn2:0 > 1). The number of system clock cycles from when the timer is enabled to the

first count occurs can be from 1 to N+1 system clock cycles, where N equals the pres-

caler divisor (8, 64, 256, or 1024).

It is possible to use the prescaler reset for synchronizing the Timer/Counter to program

execution. However, care must be taken if the other Timer/Counter that shares the

same prescaler also uses prescaling. A prescaler reset will affect the prescaler period

for all Timer/Counters it is connected to.

External Clock Source

An external clock source applied to the T1/T0 pin can be used as Timer/Counter clock

(clk_T1/clk_T0). The T1/T0 pin is sampled once every system clock cycle by the pin syn-

chronization logic. The synchronized (sampled) signal is then passed through the edge

detector. Figure 38 shows a functional equivalent block diagram of the T1/T0 synchroni-

zation and edge detector logic. The registers are clocked at the positive edge of the

internal system clock (clk_I/O). The latch is transparent in the high period of the internal

system clock.

The edge detector generates one clk_T1/clk_T₀pulse for each positive (CSn2:0 = 7) or neg-

ative (CSn2:0 = 6) edge it detects.

Figure 38. T1/T0 Pin Sampling

Tn_sync

(To Clock

Tn

D

Q

D

Q

D

Q

Select Logic)

LE

clk_I/O

Synchronization

Edge Detector

The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system

clock cycles from an edge has been applied to the T1/T0 pin to the counter is updated.

Enabling and disabling of the clock input must be done when T1/T0 has been stable for

at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock

pulse is generated.

Each half period of the external clock applied must be longer than one system clock

cycle to ensure correct sampling. The external clock must be guaranteed to have less

than half the system clock frequency (f_ExtClk< f_{clk_I/O}/2) given a 50/50% duty cycle. Since

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the edge detector uses sampling, the maximum frequency of an external clock it can

detect is half the sampling frequency (Nyquist sampling theorem). However, due to vari-

ation of the system clock frequency and duty cycle caused by Oscillator source (crystal,

resonator, and capacitors) tolerances, it is recommended that maximum frequency of an

external clock source is less than f_{clk_I/O}/2.5.

An external clock source can not be prescaled.

Figure 39. Prescaler for Timer/Counter0 and Timer/Counter1⁽¹⁾

clk_I/O

Clear

PSR10

T0

Synchronization

T1

Synchronization

clk_T1

clk_T0

Note:

1. The synchronization logic on the input pins (T1/T0) is shown in Figure 38.

General Timer/Counter

Control Register – GTCCR

Bit

7

—

R

0

6

–

5

–

4

–

3

–

2

–

1

—

R

0

PSR10

R/W

0

GTCCR

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

• Bits 7..1 – Res: Reserved Bits

These bits are reserved bits in the ATtiny2313 and will always read as zero.

• Bit 0 – PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0

When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This

bit is normally cleared immediately by hardware. Note that Timer/Counter1 and

Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both

timers.

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16-bit

Timer/Counter1

The 16-bit Timer/Counter unit allows accurate program execution timing (event man-

agement), wave generation, and signal timing measurement. The main features are:

• True 16-bit Design (i.e., Allows 16-bit PWM)

• Two independent Output Compare Units

• Double Buffered Output Compare Registers

• One Input Capture Unit

• Input Capture Noise Canceler

• Clear Timer on Compare Match (Auto Reload)

• Glitch-free, Phase Correct Pulse Width Modulator (PWM)

• Variable PWM Period

• Frequency Generator

• External Event Counter

• Four independent interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1)

Overview

Most register and bit references in this section are written in general form. A lower case

“n” replaces the Timer/Counter number, and a lower case “x” replaces the Output Com-

pare unit channel. However, when using the register or bit defines in a program, the

precise form must be used, i.e., TCNT1 for accessing Timer/Counter1 counter value

and so on.

A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 40. For the

actual placement of I/O pins, refer to “Pinout ATtiny2313” on page 2. CPU accessible

I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O

Register and bit locations are listed in the “16-bit Timer/Counter Register Description”

on page 108.

Figure 40. 16-bit Timer/Counter Block Diagram⁽¹⁾

Count

TOVn

(Int.Req.)

Clear

Control Logic

Clock Select

Direction

clk_Tn

Edge

Detector

Tn

TOP

BOTTOM

( From Prescaler )

Timer/Counter

TCNTn

=

= 0

OCnA

(Int.Req.)

Waveform

Generation

OCnA

OCnB

=

OCRnA

OCnB

(Int.Req.)

Fixed

TOP

Values

Waveform

Generation

=

OCRnB

( From Analog

Comparator Ouput )

ICFn (Int.Req.)

Edge

Detector

Noise

Canceler

ICRn

ICPn

TCCRnA

TCCRnB

Note:

1. Refer to Figure 1 on page 2 for Timer/Counter1 pin placement and description.

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Registers

The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture

Register (ICR1) are all 16-bit registers. Special procedures must be followed when

accessing the 16-bit registers. These procedures are described in the section “Access-

ing 16-bit Registers” on page 88. The Timer/Counter Control Registers (TCCR1A/B) are

8-bit registers and have no CPU access restrictions. Interrupt requests (abbreviated to

Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR).

All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK).

TIFR and TIMSK are not shown in the figure.

The Timer/Counter can be clocked internally, via the prescaler, or by an external clock

source on the T1 pin. The Clock Select logic block controls which clock source and edge

the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is

inactive when no clock source is selected. The output from the Clock Select logic is

referred to as the timer clock (clk ).

1

T

The double buffered Output Compare Registers (OCR1A/B) are compared with the

Timer/Counter value at all time. The result of the compare can be used by the Waveform

Generator to generate a PWM or variable frequency output on the Output Compare pin

(OC1A/B). See “Output Compare Units” on page 95.. The compare match event will also

set the Compare Match Flag (OCF1A/B) which can be used to generate an Output

Compare interrupt request.

The Input Capture Register can capture the Timer/Counter value at a given external

(edge triggered) event on either the Input Capture pin (ICP1) or on the Analog Compar-

ator pins (See “Analog Comparator” on page 153.) The Input Capture unit includes a

digital filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes.

The TOP value, or maximum Timer/Counter value, can in some modes of operation be

defined by either the OCR1A Register, the ICR1 Register, or by a set of fixed values.

When using OCR1A as TOP value in a PWM mode, the OCR1A Register can not be

used for generating a PWM output. However, the TOP value will in this case be double

buffered allowing the TOP value to be changed in run time. If a fixed TOP value is

required, the ICR1 Register can be used as an alternative, freeing the OCR1A to be

used as PWM output.

Definitions

The following definitions are used extensively throughout the section:

Table 42. Definitions

BOTTOM The counter reaches the BOTTOM when it becomes 0x0000.

MAX

TOP

The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535).

The counter reaches the TOP when it becomes equal to the highest value in the

count sequence. The TOP value can be assigned to be one of the fixed values:

0x00FF, 0x01FF, or 0x03FF, or to the value stored in the OCR1A or ICR1 Regis-

ter. The assignment is dependent of the mode of operation.

Compatibility

The 16-bit Timer/Counter has been updated and improved from previous versions of the

16-bit AVR Timer/Counter. This 16-bit Timer/Counter is fully compatible with the earlier

version regarding:

•

All 16-bit Timer/Counter related I/O Register address locations, including Timer

Interrupt Registers.

Bit locations inside all 16-bit Timer/Counter Registers, including Timer Interrupt

Registers.

Interrupt Vectors.

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The following control bits have changed name, but have same functionality and register

location:

•

PWM10 is changed to WGM10.

PWM11 is changed to WGM11.

CTC1 is changed to WGM12.

The following bits are added to the 16-bit Timer/Counter Control Registers:

•

FOC1A and FOC1B are added to TCCR1A.

WGM13 is added to TCCR1B.

The 16-bit Timer/Counter has improvements that will affect the compatibility in some

special cases.

Accessing 16-bit

Registers

The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR

CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or

write operations. Each 16-bit timer has a single 8-bit register for temporary storing of the

high byte of the 16-bit access. The same temporary register is shared between all 16-bit

registers within each 16-bit timer. Accessing the low byte triggers the 16-bit read or write

operation. When the low byte of a 16-bit register is written by the CPU, the high byte

stored in the temporary register, and the low byte written are both copied into the 16-bit

register in the same clock cycle. When the low byte of a 16-bit register is read by the

CPU, the high byte of the 16-bit register is copied into the temporary register in the

same clock cycle as the low byte is read.

Not all 16-bit accesses uses the temporary register for the high byte. Reading the

OCR1A/B 16-bit registers does not involve using the temporary register.

To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read,

the low byte must be read before the high byte.

The following code examples show how to access the 16-bit timer registers assuming

that no interrupts updates the temporary register. The same principle can be used

directly for accessing the OCR1A/B and ICR1 Registers. Note that when using “C”, the

compiler handles the 16-bit access.

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Assembly Code Examples⁽¹⁾

...

; Set TCNT1 to 0x01FF

ldir17,0x01

ldir16,0xFF

outTCNT1H,r17

outTCNT1L,r16

; Read TCNT1 into r17:r16

in r16,TCNT1L

in r17,TCNT1H

...

C Code Examples⁽¹⁾

unsigned int i;

...

/* Set TCNT1 to 0x01FF */

TCNT1 = 0x1FF;

/* Read TCNT1 into i */

i = TCNT1;

...

Note:

1. The example code assumes that the part specific header file is included.

For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”,

and “SBI” instructions must be replaced with instructions that allow access to

extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and

“CBR”.

The assembly code example returns the TCNT1 value in the r17:r16 register pair.

It is important to notice that accessing 16-bit registers are atomic operations. If an inter-

rupt occurs between the two instructions accessing the 16-bit register, and the interrupt

code updates the temporary register by accessing the same or any other of the 16-bit

timer registers, then the result of the access outside the interrupt will be corrupted.

Therefore, when both the main code and the interrupt code update the temporary regis-

ter, the main code must disable the interrupts during the 16-bit access.

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The following code examples show how to do an atomic read of the TCNT1 Register

contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the

same principle.

Assembly Code Example⁽¹⁾

TIM16_ReadTCNT1:

; Save global interrupt flag

in r18,SREG

; Disable interrupts

cli

; Read TCNT1 into r17:r16

in r16,TCNT1L

in r17,TCNT1H

; Restore global interrupt flag

outSREG,r18

ret

C Code Example⁽¹⁾

unsigned int TIM16_ReadTCNT1( void )

{

unsigned char sreg;

unsigned int i;

/* Save global interrupt flag */

sreg = SREG;

/* Disable interrupts */

__disable_interrupt();

/* Read TCNT1 into i */

i = TCNT1;

/* Restore global interrupt flag */

SREG = sreg;

return i;

}

Note:

1. The example code assumes that the part specific header file is included.

For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”,

and “SBI” instructions must be replaced with instructions that allow access to

extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and

“CBR”.

The assembly code example returns the TCNT1 value in the r17:r16 register pair.

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The following code examples show how to do an atomic write of the TCNT1 Register

contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the

same principle.

Assembly Code Example⁽¹⁾

TIM16_WriteTCNT1:

; Save global interrupt flag

in r18,SREG

; Disable interrupts

cli

; Set TCNT1 to r17:r16

outTCNT1H,r17

outTCNT1L,r16

; Restore global interrupt flag

outSREG,r18

ret

C Code Example⁽¹⁾

void TIM16_WriteTCNT1( unsigned int i )

{

unsigned char sreg;

unsigned int i;

/* Save global interrupt flag */

sreg = SREG;

/* Disable interrupts */

__disable_interrupt();

/* Set TCNT1 to i */

TCNT1 = i;

/* Restore global interrupt flag */

SREG = sreg;

}

Note:

1. The example code assumes that the part specific header file is included.

For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”,

and “SBI” instructions must be replaced with instructions that allow access to

extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and

“CBR”.

The assembly code example requires that the r17:r16 register pair contains the value to

be written to TCNT1.

Reusing the Temporary High

Byte Register

If writing to more than one 16-bit register where the high byte is the same for all registers

written, then the high byte only needs to be written once. However, note that the same

rule of atomic operation described previously also applies in this case.

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Timer/Counter Clock

Sources

The Timer/Counter can be clocked by an internal or an external clock source. The clock

source is selected by the Clock Select logic which is controlled by the Clock Select

(CS12:0) bits located in the Timer/Counter control Register B (TCCR1B). For details on

clock sources and prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers” on

page 84.

Counter Unit

The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional

counter unit. Figure 41 shows a block diagram of the counter and its surroundings.

Figure 41. Counter Unit Block Diagram

DATA BUS (8-bit)

TOVn

(Int.Req.)

TEMP (8-bit)

Clock Select

Count

Clear

Edge

Detector

Tn

TCNTnH (8-bit)

TCNTnL (8-bit)

clk_Tn

Control Logic

Direction

TCNTn (16-bit Counter)

( From Prescaler )

TOP

BOTTOM

Signal description (internal signals):

Count Increment or decrement TCNT1 by 1.

Direction Select between increment and decrement.

Clear

Clear TCNT1 (set all bits to zero).

Timer/Counter clock.

clk_T

1

TOP

Signalize that TCNT1 has reached maximum value.

BOTTOM Signalize that TCNT1 has reached minimum value (zero).

The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High

(TCNT1H) containing the upper eight bits of the counter, and Counter Low (TCNT1L)

containing the lower eight bits. The TCNT1H Register can only be indirectly accessed

by the CPU. When the CPU does an access to the TCNT1H I/O location, the CPU

accesses the high byte temporary register (TEMP). The temporary register is updated

with the TCNT1H value when the TCNT1L is read, and TCNT1H is updated with the

temporary register value when TCNT1L is written. This allows the CPU to read or write

the entire 16-bit counter value within one clock cycle via the 8-bit data bus. It is impor-

tant to notice that there are special cases of writing to the TCNT1 Register when the

counter is counting that will give unpredictable results. The special cases are described

in the sections where they are of importance.

Depending on the mode of operation used, the counter is cleared, incremented, or dec-

remented at each timer clock (clk ). The clk can be generated from an external or

1

T

internal clock source, selected by the Clock Select bits (CS12:0). When no clock source

is selected (CS12:0 = 0) the timer is stopped. However, the TCNT1 value can be

accessed by the CPU, independent of whether clk_T₁is present or not. A CPU write over-

rides (has priority over) all counter clear or count operations.

The counting sequence is determined by the setting of the Waveform Generation mode

bits (WGM13:0) located in the Timer/Counter Control Registers A and B (TCCR1A and

TCCR1B). There are close connections between how the counter behaves (counts) and

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how waveforms are generated on the Output Compare outputs OC1x. For more details

about advanced counting sequences and waveform generation, see “Modes of Opera-

tion” on page 98.

The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation

selected by the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt.

Input Capture Unit

The Timer/Counter incorporates an Input Capture unit that can capture external events

and give them a time-stamp indicating time of occurrence. The external signal indicating

an event, or multiple events, can be applied via the ICP1 pin or alternatively, via the

analog-comparator unit. The time-stamps can then be used to calculate frequency, duty-

cycle, and other features of the signal applied. Alternatively the time-stamps can be

used for creating a log of the events.

The Input Capture unit is illustrated by the block diagram shown in Figure 42. The ele-

ments of the block diagram that are not directly a part of the Input Capture unit are gray

shaded. The small “n” in register and bit names indicates the Timer/Counter number.

Figure 42. Input Capture Unit Block Diagram

DATA BUS (8-bit)

TEMP (8-bit)

ICRnH (8-bit)

ICRnL (8-bit)

TCNTnH (8-bit)

TCNTnL (8-bit)

ICRn (16-bit Register)

TCNTn (16-bit Counter)

WRITE

ACO*

ACIC*

ICNC

ICES

Analog

Comparator

Noise

Canceler

Edge

Detector

ICFn (Int.Req.)

ICPn

When a change of the logic level (an event) occurs on the Input Capture pin (ICP1),

alternatively on the Analog Comparator output (ACO), and this change confirms to the

setting of the edge detector, a capture will be triggered. When a capture is triggered, the

16-bit value of the counter (TCNT1) is written to the Input Capture Register (ICR1). The

Input Capture Flag (ICF1) is set at the same system clock as the TCNT1 value is copied

into ICR1 Register. If enabled (ICIE1 = 1), the Input Capture Flag generates an Input

Capture interrupt. The ICF1 flag is automatically cleared when the interrupt is executed.

Alternatively the ICF1 flag can be cleared by software by writing a logical one to its I/O

bit location.

Reading the 16-bit value in the Input Capture Register (ICR1) is done by first reading the

low byte (ICR1L) and then the high byte (ICR1H). When the low byte is read the high

byte is copied into the high byte temporary register (TEMP). When the CPU reads the

ICR1H I/O location it will access the TEMP Register.

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The ICR1 Register can only be written when using a Waveform Generation mode that

utilizes the ICR1 Register for defining the counter’s TOP value. In these cases the

Waveform Generation mode (WGM13:0) bits must be set before the TOP value can be

written to the ICR1 Register. When writing the ICR1 Register the high byte must be writ-

ten to the ICR1H I/O location before the low byte is written to ICR1L.

For more information on how to access the 16-bit registers refer to “Accessing 16-bit

Registers” on page 88.

Input Capture Trigger Source

The main trigger source for the Input Capture unit is the Input Capture pin (ICP1).

Timer/Counter1 can alternatively use the Analog Comparator output as trigger source

for the Input Capture unit. The Analog Comparator is selected as trigger source by set-

ting the Analog Comparator Input Capture (ACIC) bit in the Analog Comparator Control

and Status Register (ACSR). Be aware that changing trigger source can trigger a cap-

ture. The Input Capture Flag must therefore be cleared after the change.

Both the Input Capture pin (ICP1) and the Analog Comparator output (ACO) inputs are

sampled using the same technique as for the T1 pin (Figure 38 on page 84). The edge

detector is also identical. However, when the noise canceler is enabled, additional logic

is inserted before the edge detector, which increases the delay by four system clock

cycles. Note that the input of the noise canceler and edge detector is always enabled

unless the Timer/Counter is set in a Waveform Generation mode that uses ICR1 to

define TOP.

An Input Capture can be triggered by software by controlling the port of the ICP1 pin.

Noise Canceler

The noise canceler improves noise immunity by using a simple digital filtering scheme.

The noise canceler input is monitored over four samples, and all four must be equal for

changing the output that in turn is used by the edge detector.

The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNC1) bit

in Timer/Counter Control Register B (TCCR1B). When enabled the noise canceler intro-

duces additional four system clock cycles of delay from a change applied to the input, to

the update of the ICR1 Register. The noise canceler uses the system clock and is there-

fore not affected by the prescaler.

Using the Input Capture Unit

The main challenge when using the Input Capture unit is to assign enough processor

capacity for handling the incoming events. The time between two events is critical. If the

processor has not read the captured value in the ICR1 Register before the next event

occurs, the ICR1 will be overwritten with a new value. In this case the result of the cap-

ture will be incorrect.

When using the Input Capture interrupt, the ICR1 Register should be read as early in the

interrupt handler routine as possible. Even though the Input Capture interrupt has rela-

tively high priority, the maximum interrupt response time is dependent on the maximum

number of clock cycles it takes to handle any of the other interrupt requests.

Using the Input Capture unit in any mode of operation when the TOP value (resolution)

is actively changed during operation, is not recommended.

Measurement of an external signal’s duty cycle requires that the trigger edge is changed

after each capture. Changing the edge sensing must be done as early as possible after

the ICR1 Register has been read. After a change of the edge, the Input Capture Flag

(ICF1) must be cleared by software (writing a logical one to the I/O bit location). For

measuring frequency only, the clearing of the ICF1 flag is not required (if an interrupt

handler is used).

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Output Compare Units

The 16-bit comparator continuously compares TCNT1 with the Output Compare Regis-

ter (OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set

the Output Compare Flag (OCF1x) at the next timer clock cycle. If enabled (OCIE1x =

1), the Output Compare Flag generates an Output Compare interrupt. The OCF1x flag is

automatically cleared when the interrupt is executed. Alternatively the OCF1x flag can

be cleared by software by writing a logical one to its I/O bit location. The Waveform Gen-

erator uses the match signal to generate an output according to operating mode set by

the Waveform Generation mode (WGM13:0) bits and Compare Output mode

(COM1x1:0) bits. The TOP and BOTTOM signals are used by the Waveform Generator

for handling the special cases of the extreme values in some modes of operation (See

“Modes of Operation” on page 98.)

A special feature of Output Compare unit A allows it to define the Timer/Counter TOP

value (i.e., counter resolution). In addition to the counter resolution, the TOP value

defines the period time for waveforms generated by the Waveform Generator.

Figure 43 shows a block diagram of the Output Compare unit. The small “n” in the regis-

ter and bit names indicates the device number (n = 1 for Timer/Counter 1), and the “x”

indicates Output Compare unit (A/B). The elements of the block diagram that are not

directly a part of the Output Compare unit are gray shaded.

Figure 43. Output Compare Unit, Block Diagram

DATA BUS (8-bit)

TEMP (8-bit)

OCRnxH Buf. (8-bit)

OCRnxL Buf. (8-bit)

TCNTnH (8-bit)

TCNTnL (8-bit)

OCRnx Buffer (16-bit Register)

TCNTn (16-bit Counter)

OCRnxH (8-bit)

OCRnxL (8-bit)

OCRnx (16-bit Register)

= (16-bit Comparator )

OCFnx (Int.Req.)

TOP

OCnx

Waveform Generator

BOTTOM

WGMn3:0

COMnx1:0

The OCR1x Register is double buffered when using any of the twelve Pulse Width Mod-

ulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of

operation, the double buffering is disabled. The double buffering synchronizes the

update of the OCR1x Compare Register to either TOP or BOTTOM of the counting

sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical

PWM pulses, thereby making the output glitch-free.

The OCR1x Register access may seem complex, but this is not case. When the double

buffering is enabled, the CPU has access to the OCR1x Buffer Register, and if double

buffering is disabled the CPU will access the OCR1x directly. The content of the OCR1x

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(Buffer or Compare) Register is only changed by a write operation (the Timer/Counter

does not update this register automatically as the TCNT1 and ICR1 Register). Therefore

OCR1x is not read via the high byte temporary register (TEMP). However, it is a good

practice to read the low byte first as when accessing other 16-bit registers. Writing the

OCR1x Registers must be done via the TEMP Register since the compare of all 16 bits

is done continuously. The high byte (OCR1xH) has to be written first. When the high

byte I/O location is written by the CPU, the TEMP Register will be updated by the value

written. Then when the low byte (OCR1xL) is written to the lower eight bits, the high byte

will be copied into the upper 8-bits of either the OCR1x buffer or OCR1x Compare Reg-

ister in the same system clock cycle.

For more information of how to access the 16-bit registers refer to “Accessing 16-bit

Registers” on page 88.

Force Output Compare

In non-PWM Waveform Generation modes, the match output of the comparator can be

forced by writing a one to the Force Output Compare (FOC1x) bit. Forcing compare

match will not set the OCF1x flag or reload/clear the timer, but the OC1x pin will be

updated as if a real compare match had occurred (the COM11:0 bits settings define

whether the OC1x pin is set, cleared or toggled).

Compare Match Blocking by

TCNT1 Write

All CPU writes to the TCNT1 Register will block any compare match that occurs in the

next timer clock cycle, even when the timer is stopped. This feature allows OCR1x to be

initialized to the same value as TCNT1 without triggering an interrupt when the

Timer/Counter clock is enabled.

Using the Output Compare

Unit

Since writing TCNT1 in any mode of operation will block all compare matches for one

timer clock cycle, there are risks involved when changing TCNT1 when using any of the

Output Compare channels, independent of whether the Timer/Counter is running or not.

If the value written to TCNT1 equals the OCR1x value, the compare match will be

missed, resulting in incorrect waveform generation. Do not write the TCNT1 equal to

TOP in PWM modes with variable TOP values. The compare match for the TOP will be

ignored and the counter will continue to 0xFFFF. Similarly, do not write the TCNT1 value

equal to BOTTOM when the counter is downcounting.

The setup of the OC1x should be performed before setting the Data Direction Register

for the port pin to output. The easiest way of setting the OC1x value is to use the Force

Output Compare (FOC1x) strobe bits in Normal mode. The OC1x Register keeps its

value even when changing between Waveform Generation modes.

Be aware that the COM1x1:0 bits are not double buffered together with the compare

value. Changing the COM1x1:0 bits will take effect immediately.

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Compare Match Output

Unit

The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Gener-

ator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next

compare match. Secondly the COM1x1:0 bits control the OC1x pin output source. Fig-

ure 44 shows a simplified schematic of the logic affected by the COM1x1:0 bit setting.

The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of

the general I/O port control registers (DDR and PORT) that are affected by the

COM1x1:0 bits are shown. When referring to the OC1x state, the reference is for the

internal OC1x Register, not the OC1x pin. If a system reset occur, the OC1x Register is

reset to “0”.

Figure 44. Compare Match Output Unit, Schematic

COMnx1

Waveform

Generator

COMnx0

FOCnx

D

Q

1

0

OCnx

D

Q

PORT

D

Q

DDR

clk_I/O

The general I/O port function is overridden by the Output Compare (OC1x) from the

Waveform Generator if either of the COM1x1:0 bits are set. However, the OC1x pin

direction (input or output) is still controlled by the Data Direction Register (DDR) for the

port pin. The Data Direction Register bit for the OC1x pin (DDR_OC1x) must be set as

output before the OC1x value is visible on the pin. The port override function is generally

independent of the Waveform Generation mode, but there are some exceptions. Refer

to Table 43, Table 44 and Table 45 for details.

The design of the Output Compare pin logic allows initialization of the OC1x state before

the output is enabled. Note that some COM1x1:0 bit settings are reserved for certain

modes of operation. See “16-bit Timer/Counter Register Description” on page 108.

The COM1x1:0 bits have no effect on the Input Capture unit.

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Compare Output Mode and

Waveform Generation

The Waveform Generator uses the COM1x1:0 bits differently in normal, CTC, and PWM

modes. For all modes, setting the COM1x1:0 = 0 tells the Waveform Generator that no

action on the OC1x Register is to be performed on the next compare match. For com-

pare output actions in the non-PWM modes refer to Table 43 on page 108. For fast

PWM mode refer to Table 44 on page 108, and for phase correct and phase and fre-

quency correct PWM refer to Table 45 on page 109.

A change of the COM1x1:0 bits state will have effect at the first compare match after the

bits are written. For non-PWM modes, the action can be forced to have immediate effect

by using the FOC1x strobe bits.

Modes of Operation

The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare

pins, is defined by the combination of the Waveform Generation mode (WGM13:0) and

Compare Output mode (COM1x1:0) bits. The Compare Output mode bits do not affect

the counting sequence, while the Waveform Generation mode bits do. The COM1x1:0

bits control whether the PWM output generated should be inverted or not (inverted or

non-inverted PWM). For non-PWM modes the COM1x1:0 bits control whether the out-

put should be set, cleared or toggle at a compare match (See “Compare Match Output

Unit” on page 97.)

For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 106.

Normal Mode

The simplest mode of operation is the Normal mode (WGM13:0 = 0). In this mode the

counting direction is always up (incrementing), and no counter clear is performed. The

counter simply overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and

then restarts from the BOTTOM (0x0000). In normal operation the Timer/Counter Over-

flow Flag (TOV1) will be set in the same timer clock cycle as the TCNT1 becomes zero.

The TOV1 flag in this case behaves like a 17th bit, except that it is only set, not cleared.

However, combined with the timer overflow interrupt that automatically clears the TOV1

flag, the timer resolution can be increased by software. There are no special cases to

consider in the Normal mode, a new counter value can be written anytime.

The Input Capture unit is easy to use in Normal mode. However, observe that the maxi-

mum interval between the external events must not exceed the resolution of the counter.

If the interval between events are too long, the timer overflow interrupt or the prescaler

must be used to extend the resolution for the capture unit.

The Output Compare units can be used to generate interrupts at some given time. Using

the Output Compare to generate waveforms in Normal mode is not recommended,

since this will occupy too much of the CPU time.

Clear Timer on Compare

Match (CTC) Mode

In Clear Timer on Compare or CTC mode (WGM13:0 = 4 or 12), the OCR1A or ICR1

Register are used to manipulate the counter resolution. In CTC mode the counter is

cleared to zero when the counter value (TCNT1) matches either the OCR1A (WGM13:0

= 4) or the ICR1 (WGM13:0 = 12). The OCR1A or ICR1 define the top value for the

counter, hence also its resolution. This mode allows greater control of the compare

match output frequency. It also simplifies the operation of counting external events.

The timing diagram for the CTC mode is shown in Figure 45 on page 99. The counter

value (TCNT1) increases until a compare match occurs with either OCR1A or ICR1, and

then counter (TCNT1) is cleared.

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Figure 45. CTC Mode, Timing Diagram

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

TCNTn

OCnA

(Toggle)

(COMnA1:0 = 1)

1

2

3

4

Period

An interrupt can be generated at each time the counter value reaches the TOP value by

either using the OCF1A or ICF1 flag according to the register used to define the TOP

value. If the interrupt is enabled, the interrupt handler routine can be used for updating

the TOP value. However, changing the TOP to a value close to BOTTOM when the

counter is running with none or a low prescaler value must be done with care since the

CTC mode does not have the double buffering feature. If the new value written to

OCR1A or ICR1 is lower than the current value of TCNT1, the counter will miss the com-

pare match. The counter will then have to count to its maximum value (0xFFFF) and

wrap around starting at 0x0000 before the compare match can occur. In many cases

this feature is not desirable. An alternative will then be to use the fast PWM mode using

OCR1A for defining TOP (WGM13:0 = 15) since the OCR1A then will be double

buffered.

For generating a waveform output in CTC mode, the OCFA output can be set to toggle

its logical level on each compare match by setting the Compare Output mode bits to tog-

gle mode (COM1A1:0 = 1). The OCF1A value will not be visible on the port pin unless

the data direction for the pin is set to output (DDR_OCF1A = 1). The waveform gener-

ated will have a maximum frequency of f_{OC A}= f_{clk_I/O}/2 when OCR1A is set to zero

1

(0x0000). The waveform frequency is defined by the following equation:

f

clk_I/O

f

= --------------------------------------------------

OCnA

2 ⋅ N ⋅ (1 + OCRnA)

The N variable represents the prescaler factor (1, 8, 64, 256, or 1024).

As for the Normal mode of operation, the TOV1 flag is set in the same timer clock cycle

that the counter counts from MAX to 0x0000.

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Fast PWM Mode

The fast Pulse Width Modulation or fast PWM mode (WGM13:0 = 5, 6, 7, 14, or 15) pro-

vides a high frequency PWM waveform generation option. The fast PWM differs from

the other PWM options by its single-slope operation. The counter counts from BOTTOM

to TOP then restarts from BOTTOM. In non-inverting Compare Output mode, the Output

Compare (OC1x) is set on the compare match between TCNT1 and OCR1x, and

cleared at TOP. In inverting Compare Output mode output is cleared on compare match

and set at TOP. Due to the single-slope operation, the operating frequency of the fast

PWM mode can be twice as high as the phase correct and phase and frequency correct

PWM modes that use dual-slope operation. This high frequency makes the fast PWM

mode well suited for power regulation, rectification, and DAC applications. High fre-

quency allows physically small sized external components (coils, capacitors), hence

reduces total system cost.

The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either

ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to

0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM

resolution in bits can be calculated by using the following equation:

log(TOP + 1)

R

= ----------------------------------

FPWM

log(2)

In fast PWM mode the counter is incremented until the counter value matches either

one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 5, 6, or 7), the value in

ICR1 (WGM13:0 = 14), or the value in OCR1A (WGM13:0 = 15). The counter is then

cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is

shown in Figure 46. The figure shows fast PWM mode when OCR1A or ICR1 is used to

define TOP. The TCNT1 value is in the timing diagram shown as a histogram for illus-

trating the single-slope operation. The diagram includes non-inverted and inverted PWM

outputs. The small horizontal line marks on the TCNT1 slopes represent compare

matches between OCR1x and TCNT1. The OC1x interrupt flag will be set when a com-

pare match occurs.

Figure 46. Fast PWM Mode, Timing Diagram

OCRnx/TOP Update and

TOVn Interrupt Flag Set and

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

TCNTn

(COMnx1:0 = 2)

OCnx

(COMnx1:0 = 3)

OCnx

1

2

3

4

5

6

7

8

Period

The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches TOP. In

addition the OCF1A or ICF1 flag is set at the same timer clock cycle as TOV1 is set

when either OCR1A or ICR1 is used for defining the TOP value. If one of the interrupts

are enabled, the interrupt handler routine can be used for updating the TOP and com-

pare values.

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When changing the TOP value the program must ensure that the new TOP value is

higher or equal to the value of all of the Compare Registers. If the TOP value is lower

than any of the Compare Registers, a compare match will never occur between the

TCNT1 and the OCR1x. Note that when using fixed TOP values the unused bits are

masked to zero when any of the OCR1x Registers are written.

The procedure for updating ICR1 differs from updating OCR1A when used for defining

the TOP value. The ICR1 Register is not double buffered. This means that if ICR1 is

changed to a low value when the counter is running with none or a low prescaler value,

there is a risk that the new ICR1 value written is lower than the current value of TCNT1.

The result will then be that the counter will miss the compare match at the TOP value.

The counter will then have to count to the MAX value (0xFFFF) and wrap around start-

ing at 0x0000 before the compare match can occur. The OCR1A Register however, is

double buffered. This feature allows the OCR1A I/O location to be written anytime.

When the OCR1A I/O location is written the value written will be put into the OCR1A

Buffer Register. The OCR1A Compare Register will then be updated with the value in

the Buffer Register at the next timer clock cycle the TCNT1 matches TOP. The update is

done at the same timer clock cycle as the TCNT1 is cleared and the TOV1 flag is set.

Using the ICR1 Register for defining TOP works well when using fixed TOP values. By

using ICR1, the OCR1A Register is free to be used for generating a PWM output on

OC1A. However, if the base PWM frequency is actively changed (by changing the TOP

value), using the OCR1A as TOP is clearly a better choice due to its double buffer

feature.

In fast PWM mode, the compare units allow generation of PWM waveforms on the

OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and an

inverted PWM output can be generated by setting the COM1x1:0 to three (see Table 43

on page 108). The actual OC1x value will only be visible on the port pin if the data direc-

tion for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by

setting (or clearing) the OC1x Register at the compare match between OCR1x and

TCNT1, and clearing (or setting) the OC1x Register at the timer clock cycle the counter

is cleared (changes from TOP to BOTTOM).

The PWM frequency for the output can be calculated by the following equation:

f

clk_I/O

f

= ----------------------------------

OCnxPWM

N ⋅ (1 + TOP)

The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).

The extreme values for the OCR1x Register represents special cases when generating

a PWM waveform output in the fast PWM mode. If the OCR1x is set equal to BOTTOM

(0x0000) the output will be a narrow spike for each TOP+1 timer clock cycle. Setting the

OCR1x equal to TOP will result in a constant high or low output (depending on the polar-

ity of the output set by the COM1x1:0 bits.)

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved

by setting OCF1A to toggle its logical level on each compare match (COM1A1:0 = 1).

The waveform generated will have a maximum frequency of f_{OC A}= f_{clk_I/O}/2 when

1

OCR1A is set to zero (0x0000). This feature is similar to the OCF1A toggle in CTC

mode, except the double buffer feature of the Output Compare unit is enabled in the fast

PWM mode.

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Phase Correct PWM Mode

The phase correct Pulse Width Modulation or phase correct PWM mode (WGM13:0 = 1,

2, 3, 10, or 11) provides a high resolution phase correct PWM waveform generation

option. The phase correct PWM mode is, like the phase and frequency correct PWM

mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM

(0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output

mode, the Output Compare (OC1x) is cleared on the compare match between TCNT1

and OCR1x while upcounting, and set on the compare match while downcounting. In

inverting Output Compare mode, the operation is inverted. The dual-slope operation has

lower maximum operation frequency than single slope operation. However, due to the

symmetric feature of the dual-slope PWM modes, these modes are preferred for motor

control applications.

The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or

defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or

OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to

MAX). The PWM resolution in bits can be calculated by using the following equation:

log(TOP + 1)

R

= ----------------------------------

PCPWM

log(2)

In phase correct PWM mode the counter is incremented until the counter value matches

either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the

value in ICR1 (WGM13:0 = 10), or the value in OCR1A (WGM13:0 = 11). The counter

has then reached the TOP and changes the count direction. The TCNT1 value will be

equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM

mode is shown on Figure 47. The figure shows phase correct PWM mode when OCR1A

or ICR1 is used to define TOP. The TCNT1 value is in the timing diagram shown as a

histogram for illustrating the dual-slope operation. The diagram includes non-inverted

and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes repre-

sent compare matches between OCR1x and TCNT1. The OC1x interrupt flag will be set

when a compare match occurs.

Figure 47. Phase Correct PWM Mode, Timing Diagram

OCRnx/TOP Update and

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

TOVn Interrupt Flag Set

(Interrupt on Bottom)

TCNTn

(COMnx1:0 = 2)

OCnx

(COMnx1:0 = 3)

OCnx

1

2

3

4

Period

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The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOT-

TOM. When either OCR1A or ICR1 is used for defining the TOP value, the OCF1A or

ICF1 flag is set accordingly at the same timer clock cycle as the OCR1x Registers are

updated with the double buffer value (at TOP). The interrupt flags can be used to gener-

ate an interrupt each time the counter reaches the TOP or BOTTOM value.

When changing the TOP value the program must ensure that the new TOP value is

higher or equal to the value of all of the Compare Registers. If the TOP value is lower

than any of the Compare Registers, a compare match will never occur between the

TCNT1 and the OCR1x. Note that when using fixed TOP values, the unused bits are

masked to zero when any of the OCR1x Registers are written. As the third period shown

in Figure 47 illustrates, changing the TOP actively while the Timer/Counter is running in

the phase correct mode can result in an unsymmetrical output. The reason for this can

be found in the time of update of the OCR1x Register. Since the OCR1x update occurs

at TOP, the PWM period starts and ends at TOP. This implies that the length of the fall-

ing slope is determined by the previous TOP value, while the length of the rising slope is

determined by the new TOP value. When these two values differ the two slopes of the

period will differ in length. The difference in length gives the unsymmetrical result on the

output.

It is recommended to use the phase and frequency correct mode instead of the phase

correct mode when changing the TOP value while the Timer/Counter is running. When

using a static TOP value there are practically no differences between the two modes of

operation.

In phase correct PWM mode, the compare units allow generation of PWM waveforms on

the OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and

an inverted PWM output can be generated by setting the COM1x1:0 to three (See Table

44 on page 108). The actual OC1x value will only be visible on the port pin if the data

direction for the port pin is set as output (DDR_OC1x). The PWM waveform is gener-

ated by setting (or clearing) the OC1x Register at the compare match between OCR1x

and TCNT1 when the counter increments, and clearing (or setting) the OC1x Register at

compare match between OCR1x and TCNT1 when the counter decrements. The PWM

frequency for the output when using phase correct PWM can be calculated by the fol-

lowing equation:

f

clk_I/O

f

= ---------------------------

OCnxPCPWM

2 ⋅ N ⋅ TOP

The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).

The extreme values for the OCR1x Register represent special cases when generating a

PWM waveform output in the phase correct PWM mode. If the OCR1x is set equal to

BOTTOM the output will be continuously low and if set equal to TOP the output will be

continuously high for non-inverted PWM mode. For inverted PWM the output will have

the opposite logic values.

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Phase and Frequency Correct The phase and frequency correct Pulse Width Modulation, or phase and frequency cor-

PWM Mode

rect PWM mode (WGM13:0 = 8 or 9) provides a high resolution phase and frequency

correct PWM waveform generation option. The phase and frequency correct PWM

mode is, like the phase correct PWM mode, based on a dual-slope operation. The

counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOT-

TOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is cleared

on the compare match between TCNT1 and OCR1x while upcounting, and set on the

compare match while downcounting. In inverting Compare Output mode, the operation

is inverted. The dual-slope operation gives a lower maximum operation frequency com-

pared to the single-slope operation. However, due to the symmetric feature of the dual-

slope PWM modes, these modes are preferred for motor control applications.

The main difference between the phase correct, and the phase and frequency correct

PWM mode is the time the OCR1x Register is updated by the OCR1x Buffer Register,

(see Figure 47 and Figure 48).

The PWM resolution for the phase and frequency correct PWM mode can be defined by

either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to

0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM

resolution in bits can be calculated using the following equation:

log(TOP + 1)

R

= ----------------------------------

PFCPWM

log(2)

In phase and frequency correct PWM mode the counter is incremented until the counter

value matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A

(WGM13:0 = 9). The counter has then reached the TOP and changes the count direc-

tion. The TCNT1 value will be equal to TOP for one timer clock cycle. The timing

diagram for the phase correct and frequency correct PWM mode is shown on Figure 48.

The figure shows phase and frequency correct PWM mode when OCR1A or ICR1 is

used to define TOP. The TCNT1 value is in the timing diagram shown as a histogram for

illustrating the dual-slope operation. The diagram includes non-inverted and inverted

PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare

matches between OCR1x and TCNT1. The OC1x interrupt flag will be set when a com-

pare match occurs.

Figure 48. Phase and Frequency Correct PWM Mode, Timing Diagram

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

OCRnx/TOP Updateand

TOVn Interrupt Flag Set

(Interrupt on Bottom)

TCNTn

(COMnx1:0 = 2)

OCnx

(COMnx1:0 = 3)

OCnx

1

2

3

4

Period

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The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the

OCR1x Registers are updated with the double buffer value (at BOTTOM). When either

OCR1A or ICR1 is used for defining the TOP value, the OCF1A or ICF1 flag set when

TCNT1 has reached TOP. The interrupt flags can then be used to generate an interrupt

each time the counter reaches the TOP or BOTTOM value.

When changing the TOP value the program must ensure that the new TOP value is

higher or equal to the value of all of the Compare Registers. If the TOP value is lower

than any of the Compare Registers, a compare match will never occur between the

TCNT1 and the OCR1x.

As Figure 48 shows the output generated is, in contrast to the phase correct mode, sym-

metrical in all periods. Since the OCR1x Registers are updated at BOTTOM, the length

of the rising and the falling slopes will always be equal. This gives symmetrical output

pulses and is therefore frequency correct.

Using the ICR1 Register for defining TOP works well when using fixed TOP values. By

using ICR1, the OCR1A Register is free to be used for generating a PWM output on

OC1A. However, if the base PWM frequency is actively changed by changing the TOP

value, using the OCR1A as TOP is clearly a better choice due to its double buffer

feature.

In phase and frequency correct PWM mode, the compare units allow generation of

PWM waveforms on the OC1x pins. Setting the COM1x1:0 bits to two will produce a

non-inverted PWM and an inverted PWM output can be generated by setting the

COM1x1:0 to three (See Table 45 on page 109). The actual OC1Fx value will only be

visible on the port pin if the data direction for the port pin is set as output (DDR_OCF1x).

The PWM waveform is generated by setting (or clearing) the OCF1x Register at the

compare match between OCR1x and TCNT1 when the counter increments, and clear-

ing (or setting) the OCF1x Register at compare match between OCR1x and TCNT1

when the counter decrements. The PWM frequency for the output when using phase

and frequency correct PWM can be calculated by the following equation:

f

clk_I/O

f

= ---------------------------

OCnxPFCPWM

2 ⋅ N ⋅ TOP

The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).

The extreme values for the OCR1x Register represents special cases when generating

a PWM waveform output in the phase correct PWM mode. If the OCR1x is set equal to

BOTTOM the output will be continuously low and if set equal to TOP the output will be

set to high for non-inverted PWM mode. For inverted PWM the output will have the

opposite logic values.

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Timer/Counter Timing

Diagrams

The Timer/Counter is a synchronous design and the timer clock (clk_T1) is therefore

shown as a clock enable signal in the following figures. The figures include information

on when interrupt flags are set, and when the OCR1x Register is updated with the

OCR1x buffer value (only for modes utilizing double buffering). Figure 49 shows a timing

diagram for the setting of OCF1x.

Figure 49. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling

clk_I/O

clk_Tn

(clk_I/O/1)

TCNTn

OCRnx

OCFnx

OCRnx - 1

OCRnx

OCRnx + 1

OCRnx + 2

OCRnx Value

Figure 50 shows the same timing data, but with the prescaler enabled.

Figure 50. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

OCRnx

OCFnx

OCRnx - 1

OCRnx

OCRnx + 1

OCRnx + 2

OCRnx Value

Figure 51 shows the count sequence close to TOP in various modes. When using phase

and frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The

timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by

BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 flag at

BOTTOM.

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Figure 51. Timer/Counter Timing Diagram, no Prescaling

clk_I/O

clk_Tn

(clk_I/O/1)

TCNTn

TOP - 1

TOP

BOTTOM

BOTTOM + 1

TOP - 2

(CTC and FPWM)

TCNTn

(PC and PFC PWM)

TOP - 1

TOVn (FPWM)

and ICFn (if used

as TOP)

OCRnx

(Update at TOP)

New OCRnx Value

Old OCRnx Value

Figure 52 shows the same timing data, but with the prescaler enabled.

Figure 52. Timer/Counter Timing Diagram, with Prescaler (f_{clk_I/O}/8)

clk

I/O

clk

(clk^T/ⁿ8)

I/O

TCNTn

TOP - 1

TOP

BOTTOM

TOP - 1

BOTTOM + 1

TOP - 2

(CTC and FPWM)

TCNTn

(PC and PFC PWM)

TOVn(FPWM)

and ICFn(if used

as TOP)

OCRnx

(Update at TOP)

Old OCRnx Value

New OCRnx Value

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16-bit Timer/Counter

Register Description

Timer/Counter1 Control

Register A – TCCR1A

Bit

7

COM1A1

R/W

6

COM1A0

R/W

5

COM1B1

R/W

4

COM1B0

R/W

3

–

2

–

1

WGM11

R/W

0

WGM10

R/W

0

TCCR1A

Read/Write

Initial Value

R

0

R

0

• Bit 7:6 – COM1A1:0: Compare Output Mode for Channel A

• Bit 5:4 – COM1B1:0: Compare Output Mode for Channel B

The COM1A1:0 and COM1B1:0 control the Output Compare pins (OC1A and OC1B

respectively) behavior. If one or both of the COM1A1:0 bits are written to one, the OC1A

output overrides the normal port functionality of the I/O pin it is connected to. If one or

both of the COM1B1:0 bit are written to one, the OC1B output overrides the normal port

functionality of the I/O pin it is connected to. However, note that the Data Direction Reg-

ister (DDR) bit corresponding to the OC1A or OC1B pin must be set in order to enable

the output driver.

When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is

dependent of the WGM13:0 bits setting. Table 43 shows the COM1x1:0 bit functionality

when the WGM13:0 bits are set to a Normal or a CTC mode (non-PWM).

Table 43. Compare Output Mode, non-PWM

COM1A1/COM1B1 COM1A0/COM1B0 Description

0

Normal port operation, OC1A/OC1B

disconnected.

0

1

0

Toggle OC1A/OC1B on Compare Match.

Clear OC1A/OC1B on Compare Match (Set

output to low level).

1

Set OC1A/OC1B on Compare Match (Set output

to high level).

Table 44 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the

fast PWM mode.

Table 44. Compare Output Mode, Fast PWM⁽¹⁾

COM1A1/COM1B1 COM1A0/COM1B0 Description

0

Normal port operation, OC1A/OC1B

disconnected.

0

1

WGM13=0: Normal port operation, OC1A/OC1B

disconnected.

WGM13=1: Toggle OC1A on Compare Match,

OC1B reserved.

1

0

1

Clear OC1A/OC1B on Compare Match, set

OC1A/OC1B at TOP

Set OC1A/OC1B on Compare Match, clear

OC1A/OC1B at TOP

Note:

1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is

set. In this case the compare match is ignored, but the set or clear is done at TOP.

See “Fast PWM Mode” on page 100. for more details.

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ATtiny2313/V

Table 45 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the

phase correct or the phase and frequency correct, PWM mode.

Table 45. Compare Output Mode, Phase Correct and Phase and Frequency Correct

PWM⁽¹⁾

COM1A1/COM1B1 COM1A0/COM1B0 Description

0

Normal port operation, OC1A/OC1B

disconnected.

0

1

WGM13=0: Normal port operation, OC1A/OC1B

disconnected.

WGM13=1: Toggle OC1A on Compare Match,

OC1B reserved.

1

0

1

Clear OC1A/OC1B on Compare Match when up-

counting. Set OC1A/OC1B on Compare Match

when downcounting.

Set OC1A/OC1B on Compare Match when up-

counting. Clear OC1A/OC1B on Compare Match

when downcounting.

Note:

1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is

set. See “Phase Correct PWM Mode” on page 102. for more details.

• Bit 1:0 – WGM11:0: Waveform Generation Mode

Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the

counting sequence of the counter, the source for maximum (TOP) counter value, and

what type of waveform generation to be used, see Table 46. Modes of operation sup-

ported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare

match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (See

“Modes of Operation” on page 98.).

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Table 46. Waveform Generation Mode Bit Description⁽¹⁾

WGM12

(CTC1)

WGM11

WGM10

Timer/Counter Mode of

Update of

OCR1x at

TOV1 Flag

Set on

Mode

WGM13

(PWM11) (PWM10) Operation

TOP

0

1

2

3

4

5

6

7

8

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Normal

0xFFFF

0x00FF

0x01FF

0x03FF

OCR1A

0x00FF

0x01FF

0x03FF

ICR1

Immediate

TOP

MAX

PWM, Phase Correct, 8-bit

PWM, Phase Correct, 9-bit

PWM, Phase Correct, 10-bit

CTC

BOTTOM

MAX

TOP

Immediate

TOP

Fast PWM, 8-bit

TOP

Fast PWM, 9-bit

TOP

Fast PWM, 10-bit

TOP

PWM, Phase and Frequency

Correct

BOTTOM

9

1

0

1

PWM, Phase and Frequency

Correct

OCR1A

BOTTOM

10

11

12

13

14

15

1

0

1

0

1

0

1

0

1

0

1

PWM, Phase Correct

CTC

ICR1

OCR1A

ICR1

–

TOP

Immediate

–

BOTTOM

MAX

(Reserved)

–

Fast PWM

ICR1

OCR1A

TOP

Fast PWM

TOP

Note:

1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the WGM12:0 definitions. However, the functionality and

location of these bits are compatible with previous versions of the timer.

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ATtiny2313/V

Timer/Counter1 Control

Register B – TCCR1B

Bit

7

ICNC1

R/W

0

6

ICES1

R/W

0

5

–

4

WGM13

R/W

0

3

WGM12

R/W

0

2

CS12

R/W

0

1

CS11

R/W

0

CS10

R/W

0

TCCR1B

Read/Write

Initial Value

R

0

• Bit 7 – ICNC1: Input Capture Noise Canceler

Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise can-

celer is activated, the input from the Input Capture pin (ICP1) is filtered. The filter

function requires four successive equal valued samples of the ICP1 pin for changing its

output. The Input Capture is therefore delayed by four Oscillator cycles when the noise

canceler is enabled.

• Bit 6 – ICES1: Input Capture Edge Select

This bit selects which edge on the Input Capture pin (ICP1) that is used to trigger a cap-

ture event. When the ICES1 bit is written to zero, a falling (negative) edge is used as

trigger, and when the ICES1 bit is written to one, a rising (positive) edge will trigger the

capture.

When a capture is triggered according to the ICES1 setting, the counter value is copied

into the Input Capture Register (ICR1). The event will also set the Input Capture Flag

(ICF1), and this can be used to cause an Input Capture Interrupt, if this interrupt is

enabled.

When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in

the TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently

the Input Capture function is disabled.

• Bit 5 – Reserved Bit

This bit is reserved for future use. For ensuring compatibility with future devices, this bit

must be written to zero when TCCR1B is written.

• Bit 4:3 – WGM13:2: Waveform Generation Mode

See TCCR1A Register description.

• Bit 2:0 – CS12:0: Clock Select

The three Clock Select bits select the clock source to be used by the Timer/Counter, see

Figure 49 and Figure 50.

Table 47. Clock Select Bit Description

CS12

CS11

CS10

Description

0

1

0

1

0

1

0

1

0

1

0

1

0

1

No clock source (Timer/Counter stopped).

clk_I/O/1 (No prescaling)

clk_I/O/8 (From prescaler)

clk_I/O/64 (From prescaler)

clk_I/O/256 (From prescaler)

clk_I/O/1024 (From prescaler)

External clock source on T1 pin. Clock on falling edge.

External clock source on T1 pin. Clock on rising edge.

If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will

clock the counter even if the pin is configured as an output. This feature allows software

control of the counting.

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Timer/Counter1 Control

Register C – TCCR1C

Bit

7

FOC1A

W

6

FOC1B

W

5

–

4

–

3

–

2

–

1

–

0

–

TCCR1C

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

R

0

• Bit 7 – FOC1A: Force Output Compare for Channel A

• Bit 6 – FOC1B: Force Output Compare for Channel B

The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM

mode. However, for ensuring compatibility with future devices, these bits must be set to

zero when TCCR1A is written when operating in a PWM mode. When writing a logical

one to the FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform

Generation unit. The OC1A/OC1B output is changed according to its COM1x1:0 bits

setting. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore it is

the value present in the COM1x1:0 bits that determine the effect of the forced compare.

A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear

Timer on Compare match (CTC) mode using OCR1A as TOP.

The FOC1A/FOC1B bits are always read as zero.

Timer/Counter1 – TCNT1H

and TCNT1L

Bit

7

6

5

4

3

2

1

0

TCNT1[15:8]

TCNT1[7:0]

TCNT1H

TCNT1L

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give

direct access, both for read and for write operations, to the Timer/Counter unit 16-bit

counter. To ensure that both the high and low bytes are read and written simultaneously

when the CPU accesses these registers, the access is performed using an 8-bit tempo-

rary high byte register (TEMP). This temporary register is shared by all the other 16-bit

registers. See “Accessing 16-bit Registers” on page 88.

Modifying the counter (TCNT1) while the counter is running introduces a risk of missing

a compare match between TCNT1 and one of the OCR1x Registers.

Writing to the TCNT1 Register blocks (removes) the compare match on the following

timer clock for all compare units.

Output Compare Register 1 A

– OCR1AH and OCR1AL

Bit

7

6

5

4

3

2

1

0

OCR1A[15:8]

OCR1A[7:0]

OCR1AH

OCR1AL

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

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Output Compare Register 1 B

- OCR1BH and OCR1BL

Bit

7

6

5

4

3

2

1

0

OCR1B[15:8]

OCR1B[7:0]

OCR1BH

OCR1BL

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Output Compare Registers contain a 16-bit value that is continuously compared

with the counter value (TCNT1). A match can be used to generate an Output Compare

interrupt, or to generate a waveform output on the OC1x pin.

The Output Compare Registers are 16-bit in size. To ensure that both the high and low

bytes are written simultaneously when the CPU writes to these registers, the access is

performed using an 8-bit temporary high byte register (TEMP). This temporary register

is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 88.

Input Capture Register 1 –

ICR1H and ICR1L

Bit

7

6

5

4

3

2

1

0

ICR1[15:8]

ICR1[7:0]

ICR1H

ICR1L

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Input Capture is updated with the counter (TCNT1) value each time an event occurs

on the ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1).

The Input Capture can be used for defining the counter TOP value.

The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes

are read simultaneously when the CPU accesses these registers, the access is per-

formed using an 8-bit temporary high byte register (TEMP). This temporary register is

shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 88.

Timer/Counter Interrupt Mask

Register – TIMSK

Bit

7

TOIE1

R/W

0

6

OCIE1A

R/W

0

5

OCIE1B

R/W

0

4

–

3

ICIE1

R/W

0

2

OCIE0B

R/W

0

1

TOIE0

R/W

0

OCIE0A

R/W

0

TIMSK

Read/Write

Initial Value

R

0

• Bit 7 – TOIE1: Timer/Counter1, Overflow Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-

bally enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding

Interrupt Vector (See “Interrupts” on page 47.) is executed when the TOV1 flag, located

in TIFR, is set.

• Bit 6 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-

bally enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The

corresponding Interrupt Vector (See “Interrupts” on page 47.) is executed when the

OCF1A flag, located in TIFR, is set.

• Bit 5 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-

bally enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The

corresponding Interrupt Vector (See “Interrupts” on page 47.) is executed when the

OCF1B flag, located in TIFR, is set.

• Bit 3 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable

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2543I–AVR–04/06

When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-

bally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The

corresponding Interrupt Vector (See “Interrupts” on page 47.) is executed when the

ICF1 flag, located in TIFR, is set.

Timer/Counter Interrupt Flag

Register – TIFR

Bit

7

TOV1

R/W

0

6

OCF1A

R/W

0

5

OCF1B

R/W

0

4

–

3

2

OCF0B

R/W

0

1

TOV0

R/W

0

OCF0A

R/W

0

ICF1

R/W

0

TIFR

Read/Write

Initial Value

R

0

• Bit 7 – TOV1: Timer/Counter1, Overflow Flag

The setting of this flag is dependent of the WGM13:0 bits setting. In Normal and CTC

modes, the TOV1 flag is set when the timer overflows. Refer to Table 46 on page 110

for the TOV1 flag behavior when using another WGM13:0 bit setting.

TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is

executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location.

• Bit 6 – OCF1A: Timer/Counter1, Output Compare A Match Flag

This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Out-

put Compare Register A (OCR1A).

Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A flag.

OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is

executed. Alternatively, OCF1A can be cleared by writing a logic one to its bit location.

• Bit 5 – OCF1B: Timer/Counter1, Output Compare B Match Flag

This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Out-

put Compare Register B (OCR1B).

Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B flag.

OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is

executed. Alternatively, OCF1B can be cleared by writing a logic one to its bit location.

• Bit 3 – ICF1: Timer/Counter1, Input Capture Flag

This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture

Register (ICR1) is set by the WGM13:0 to be used as the TOP value, the ICF1 flag is set

when the counter reaches the TOP value.

ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alter-

natively, ICF1 can be cleared by writing a logic one to its bit location.

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ATtiny2313/V

USART

The Universal Synchronous and Asynchronous serial Receiver and Transmitter

(USART) is a highly flexible serial communication device. The main features are:

• Full Duplex Operation (Independent Serial Receive and Transmit Registers)

• Asynchronous or Synchronous Operation

• Master or Slave Clocked Synchronous Operation

• High Resolution Baud Rate Generator

• Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits

• Odd or Even Parity Generation and Parity Check Supported by Hardware

• Data OverRun Detection

• Framing Error Detection

• Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter

• Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete

• Multi-processor Communication Mode

• Double Speed Asynchronous Communication Mode

Overview

A simplified block diagram of the USART Transmitter is shown in Figure 53. CPU acces-

sible I/O Registers and I/O pins are shown in bold.

Figure 53. USART Block Diagram⁽¹⁾

Clock Generator

UBRR[H:L]

OSC

BAUD RATE GENERATOR

SYNC LOGIC

XCK

CONTROL

Transmitter

TX

CONTROL

UDR (Transmit)

PARITY

GENERATOR

CONTROL

TRANSMIT SHIFT REGISTER

TxD

Receiver

CLOCK

RECOVERY

RX

CONTROL

DATA

RECOVERY

CONTROL

RECEIVE SHIFT REGISTER

RxD

PARITY

CHECKER

UDR (Receive)

UCSRA

UCSRB

UCSRC

Note:

1. Refer to Figure 1 on page 2, Table 29 on page 60, and Table 26 on page 58 for

USART pin placement.

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2543I–AVR–04/06

The dashed boxes in the block diagram separate the three main parts of the USART

(listed from the top): Clock Generator, Transmitter and Receiver. Control registers are

shared by all units. The Clock Generation logic consists of synchronization logic for

external clock input used by synchronous slave operation, and the baud rate generator.

The XCK (Transfer Clock) pin is only used by synchronous transfer mode. The Trans-

mitter consists of a single write buffer, a serial Shift Register, Parity Generator and

Control logic for handling different serial frame formats. The write buffer allows a contin-

uous transfer of data without any delay between frames. The Receiver is the most

complex part of the USART module due to its clock and data recovery units. The recov-

ery units are used for asynchronous data reception. In addition to the recovery units, the

Receiver includes a Parity Checker, Control logic, a Shift Register and a two level

receive buffer (UDR). The Receiver supports the same frame formats as the Transmit-

ter, and can detect Frame Error, Data OverRun and Parity Errors.

AVR USART vs. AVR UART –

Compatibility

The USART is fully compatible with the AVR UART regarding:

•

Bit locations inside all USART Registers.

Baud Rate Generation.

Transmitter Operation.

Transmit Buffer Functionality.

Receiver Operation.

However, the receive buffering has two improvements that will affect the compatibility in

some special cases:

•

A second Buffer Register has been added. The two Buffer Registers operate as a

circular FIFO buffer. Therefore the UDR must only be read once for each incoming

data! More important is the fact that the error flags (FE and DOR) and the ninth data

bit (RXB8) are buffered with the data in the receive buffer. Therefore the status bits

must always be read before the UDR Register is read. Otherwise the error status

will be lost since the buffer state is lost.

•

The Receiver Shift Register can now act as a third buffer level. This is done by

allowing the received data to remain in the serial Shift Register (see Figure 53) if the

Buffer Registers are full, until a new start bit is detected. The USART is therefore

more resistant to Data OverRun (DOR) error conditions.

The following control bits have changed name, but have same functionality and register

location:

•

CHR9 is changed to UCSZ2.

OR is changed to DOR.

Clock Generation

The Clock Generation logic generates the base clock for the Transmitter and Receiver.

The USART supports four modes of clock operation: Normal asynchronous, Double

Speed asynchronous, Master synchronous and Slave synchronous mode. The UMSEL

bit in USART Control and Status Register C (UCSRC) selects between asynchronous

and synchronous operation. Double Speed (asynchronous mode only) is controlled by

the U2X found in the UCSRA Register. When using synchronous mode (UMSEL = 1),

the Data Direction Register for the XCK pin (DDR_XCK) controls whether the clock

source is internal (Master mode) or external (Slave mode). The XCK pin is only active

when using synchronous mode.

Figure 54 shows a block diagram of the clock generation logic.

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Figure 54. Clock Generation Logic, Block Diagram

UBRR

U2X

fosc

UBRR+1

Prescaling

Down-Counter

/2

/4

/2

0

1

0

OSC

txclk

1

DDR_XCK

Sync

Register

Edge

Detector

xcki

0

UMSEL

XCK

xcko

1

DDR_XCK

UCPOL

1

rxclk

0

Signal description:

txclk Transmitter clock (Internal Signal).

rxclk Receiver base clock (Internal Signal).

xcki

Input from XCK pin (internal Signal). Used for synchronous slave operation.

xcko Clock output to XCK pin (Internal Signal). Used for synchronous master

operation.

fosc

XTAL pin frequency (System Clock).

Internal Clock Generation –

The Baud Rate Generator

Internal clock generation is used for the asynchronous and the synchronous master

modes of operation. The description in this section refers to Figure 54.

The USART Baud Rate Register (UBRR) and the down-counter connected to it function

as a programmable prescaler or baud rate generator. The down-counter, running at sys-

tem clock (f_osc), is loaded with the UBRR value each time the counter has counted down

to zero or when the UBRRL Register is written. A clock is generated each time the

counter reaches zero. This clock is the baud rate generator clock output (=

f_osc/(UBRR+1)). The Transmitter divides the baud rate generator clock output by 2, 8 or

16 depending on mode. The baud rate generator output is used directly by the

Receiver’s clock and data recovery units. However, the recovery units use a state

machine that uses 2, 8 or 16 states depending on mode set by the state of the UMSEL,

U2X and DDR_XCK bits.

Table 48 contains equations for calculating the baud rate (in bits per second) and for

calculating the UBRR value for each mode of operation using an internally generated

clock source.

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Table 48. Equations for Calculating Baud Rate Register Setting

Equation for Calculating

Baud Rate⁽¹⁾

Equation for Calculating

Operating Mode

UBRR Value

Asynchronous Normal

mode (U2X = 0)

f

OSC

f

OSC

BAUD = --------------------------------------

UBRR = ----------------------- – 1

16(UBRR + 1)

16BAUD

Asynchronous Double

Speed mode (U2X = 1)

f

OSC

f

OSC

BAUD = -----------------------------------

UBRR = -------------------- – 1

8(UBRR + 1)

8BAUD

Synchronous Master

mode

f

OSC

f

OSC

BAUD = -----------------------------------

UBRR = -------------------- – 1

2(UBRR + 1)

2BAUD

Note:

BAUD Baud rate (in bits per second, bps)

f_OSCSystem Oscillator clock frequency

1. The baud rate is defined to be the transfer rate in bit per second (bps)

UBRR Contents of the UBRRH and UBRRL Registers, (0-4095)

Some examples of UBRR values for some system clock frequencies are found in Table

56 (see page 138).

Double Speed Operation

(U2X)

The transfer rate can be doubled by setting the U2X bit in UCSRA. Setting this bit only

has effect for the asynchronous operation. Set this bit to zero when using synchronous

operation.

Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively

doubling the transfer rate for asynchronous communication. Note however that the

Receiver will in this case only use half the number of samples (reduced from 16 to 8) for

data sampling and clock recovery, and therefore a more accurate baud rate setting and

system clock are required when this mode is used. For the Transmitter, there are no

downsides.

External Clock

External clocking is used by the synchronous slave modes of operation. The description

in this section refers to Figure 54 for details.

External clock input from the XCK pin is sampled by a synchronization register to mini-

mize the chance of meta-stability. The output from the synchronization register must

then pass through an edge detector before it can be used by the Transmitter and

Receiver. This process introduces a two CPU clock period delay and therefore the max-

imum external XCK clock frequency is limited by the following equation:

f

OSC

-----------

f

<

XCK

4

Note that f_oscdepends on the stability of the system clock source. It is therefore recom-

mended to add some margin to avoid possible loss of data due to frequency variations.

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Synchronous Clock Operation When synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock

input (Slave) or clock output (Master). The dependency between the clock edges and

data sampling or data change is the same. The basic principle is that data input (on

RxD) is sampled at the opposite XCK clock edge of the edge the data output (TxD) is

changed.

Figure 55. Synchronous Mode XCK Timing.

UCPOL = 1

XCK

RxD / TxD

Sample

UCPOL = 0

XCK

RxD / TxD

Sample

The UCPOL bit UCRSC selects which XCK clock edge is used for data sampling and

which is used for data change. As Figure 55 shows, when UCPOL is zero the data will

be changed at rising XCK edge and sampled at falling XCK edge. If UCPOL is set, the

data will be changed at falling XCK edge and sampled at rising XCK edge.

Frame Formats

A serial frame is defined to be one character of data bits with synchronization bits (start

and stop bits), and optionally a parity bit for error checking. The USART accepts all 30

combinations of the following as valid frame formats:

•

1 start bit

5, 6, 7, 8, or 9 data bits

no, even or odd parity bit

1 or 2 stop bits

A frame starts with the start bit followed by the least significant data bit. Then the next

data bits, up to a total of nine, are succeeding, ending with the most significant bit. If

enabled, the parity bit is inserted after the data bits, before the stop bits. When a com-

plete frame is transmitted, it can be directly followed by a new frame, or the

communication line can be set to an idle (high) state. Figure 56 illustrates the possible

combinations of the frame formats. Bits inside brackets are optional.

Figure 56. Frame Formats

FRAME

(IDLE)

St

0

1

2

3

4

[5]

[6]

[7]

[8]

[P] Sp1 [Sp2] (St / IDLE)

St

(n)

P

Start bit, always low.

Data bits (0 to 8).

Parity bit. Can be odd or even.

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Sp

Stop bit, always high.

IDLE No transfers on the communication line (RxD or TxD). An IDLE line must be

high.

The frame format used by the USART is set by the UCSZ2:0, UPM1:0 and USBS bits in

UCSRB and UCSRC. The Receiver and Transmitter use the same setting. Note that

changing the setting of any of these bits will corrupt all ongoing communication for both

the Receiver and Transmitter.

The USART Character SiZe (UCSZ2:0) bits select the number of data bits in the frame.

The USART Parity mode (UPM1:0) bits enable and set the type of parity bit. The selec-

tion between one or two stop bits is done by the USART Stop Bit Select (USBS) bit. The

Receiver ignores the second stop bit. An FE (Frame Error) will therefore only be

detected in the cases where the first stop bit is zero.

Parity Bit Calculation

The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is

used, the result of the exclusive or is inverted. The relation between the parity bit and

data bits is as follows:

P

= d

⊕ … ⊕ d ⊕ d ⊕ d ⊕ d ⊕ 0

3 2 1 0

even

n – 1

⊕ … ⊕ d ⊕ d ⊕ d ⊕ d ⊕ 1

odd

3 2 1 0

P_evenParity bit using even parity

P_odd

d_n

Parity bit using odd parity

Data bit n of the character

If used, the parity bit is located between the last data bit and first stop bit of a serial

frame.

USART Initialization

The USART has to be initialized before any communication can take place. The initial-

ization process normally consists of setting the baud rate, setting frame format and

enabling the Transmitter or the Receiver depending on the usage. For interrupt driven

USART operation, the Global Interrupt Flag should be cleared (and interrupts globally

disabled) when doing the initialization.

Before doing a re-initialization with changed baud rate or frame format, be sure that

there are no ongoing transmissions during the period the registers are changed. The

TXC flag can be used to check that the Transmitter has completed all transfers, and the

RXC flag can be used to check that there are no unread data in the receive buffer. Note

that the TXC flag must be cleared before each transmission (before UDR is written) if it

is used for this purpose.

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The following simple USART initialization code examples show one assembly and one

C function that are equal in functionality. The examples assume asynchronous opera-

tion using polling (no interrupts enabled) and a fixed frame format. The baud rate is

given as a function parameter. For the assembly code, the baud rate parameter is

assumed to be stored in the r17:r16 Registers.

Assembly Code Example⁽¹⁾

USART_Init:

; Set baud rate

out UBRRH, r17

out UBRRL, r16

; Enable receiver and transmitter

ldi r16, (1<<RXEN)|(1<<TXEN)

out UCSRB,r16

; Set frame format: 8data, 2stop bit

ldi r16, (1<<USBS)|(3<<UCSZ0)

out UCSRC,r16

ret

C Code Example⁽¹⁾

void USART_Init( unsigned int baud )

{

/* Set baud rate */

UBRRH = (unsigned char)(baud>>8);

UBRRL = (unsigned char)baud;

/* Enable receiver and transmitter */

UCSRB = (1<<RXEN)|(1<<TXEN);

/* Set frame format: 8data, 2stop bit */

UCSRC = (1<<USBS)|(3<<UCSZ0);

}

Note:

1. The example code assumes that the part specific header file is included.

For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”,

and “SBI” instructions must be replaced with instructions that allow access to

extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and

“CBR”.

More advanced initialization routines can be made that include frame format as parame-

ters, disable interrupts and so on. However, many applications use a fixed setting of the

baud and control registers, and for these types of applications the initialization code can

be placed directly in the main routine, or be combined with initialization code for other

I/O modules.

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Data Transmission – The The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the

UCSRB Register. When the Transmitter is enabled, the normal port operation of the

USART Transmitter

TxD pin is overridden by the USART and given the function as the Transmitter’s serial

output. The baud rate, mode of operation and frame format must be set up once before

doing any transmissions. If synchronous operation is used, the clock on the XCK pin will

be overridden and used as transmission clock.

Sending Frames with 5 to 8

Data Bit

A data transmission is initiated by loading the transmit buffer with the data to be trans-

mitted. The CPU can load the transmit buffer by writing to the UDR I/O location. The

buffered data in the transmit buffer will be moved to the Shift Register when the Shift

Register is ready to send a new frame. The Shift Register is loaded with new data if it is

in idle state (no ongoing transmission) or immediately after the last stop bit of the previ-

ous frame is transmitted. When the Shift Register is loaded with new data, it will transfer

one complete frame at the rate given by the Baud Register, U2X bit or by XCK depend-

ing on mode of operation.

The following code examples show a simple USART transmit function based on polling

of the Data Register Empty (UDRE) flag. When using frames with less than eight bits,

the most significant bits written to the UDR are ignored. The USART has to be initialized

before the function can be used. For the assembly code, the data to be sent is assumed

to be stored in Register R16

Assembly Code Example⁽¹⁾

USART_Transmit:

; Wait for empty transmit buffer

sbis UCSRA,UDRE

rjmp USART_Transmit

; Put data (r16) into buffer, sends the data

out UDR,r16

ret

C Code Example⁽¹⁾

void USART_Transmit( unsigned char data )

{

/* Wait for empty transmit buffer */

while ( !( UCSRA & (1<<UDRE)) )

;

/* Put data into buffer, sends the data */

UDR = data;

}

Note:

1. The example code assumes that the part specific header file is included.

For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”,

and “SBI” instructions must be replaced with instructions that allow access to

extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and

“CBR”.

The function simply waits for the transmit buffer to be empty by checking the UDRE flag,

before loading it with new data to be transmitted. If the Data Register Empty interrupt is

utilized, the interrupt routine writes the data into the buffer.

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Sending Frames with 9 Data

Bit

If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit in

UCSRB before the low byte of the character is written to UDR. The following code

examples show a transmit function that handles 9-bit characters. For the assembly

code, the data to be sent is assumed to be stored in registers R17:R16.

Assembly Code Example⁽¹⁾⁽²⁾

USART_Transmit:

; Wait for empty transmit buffer

sbis UCSRA,UDRE

rjmp USART_Transmit

; Copy 9th bit from r17 to TXB8

cbi UCSRB,TXB8

sbrc r17,0

sbi UCSRB,TXB8

; Put LSB data (r16) into buffer, sends the data

out UDR,r16

ret

C Code Example⁽¹⁾⁽²⁾

void USART_Transmit( unsigned int data )

{

/* Wait for empty transmit buffer */

while ( !( UCSRA & (1<<UDRE))) )

;

/* Copy 9th bit to TXB8 */

UCSRB &= ~(1<<TXB8);

if ( data & 0x0100 )

UCSRB |= (1<<TXB8);

/* Put data into buffer, sends the data */

UDR = data;

}

Notes: 1. These transmit functions are written to be general functions. They can be optimized if

the contents of the UCSRB is static. For example, only the TXB8 bit of the UCSRB

Register is used after initialization.

2. The example code assumes that the part specific header file is included.

For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”,

and “SBI” instructions must be replaced with instructions that allow access to

extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and

“CBR”.

The ninth bit can be used for indicating an address frame when using multi processor

communication mode or for other protocol handling as for example synchronization.

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Transmitter Flags and

Interrupts

The USART Transmitter has two flags that indicate its state: USART Data Register

Empty (UDRE) and Transmit Complete (TXC). Both flags can be used for generating

interrupts.

The Data Register Empty (UDRE) flag indicates whether the transmit buffer is ready to

receive new data. This bit is set when the transmit buffer is empty, and cleared when the

transmit buffer contains data to be transmitted that has not yet been moved into the Shift

Register. For compatibility with future devices, always write this bit to zero when writing

the UCSRA Register.

When the Data Register Empty Interrupt Enable (UDRIE) bit in UCSRB is written to one,

the USART Data Register Empty Interrupt will be executed as long as UDRE is set (pro-

vided that global interrupts are enabled). UDRE is cleared by writing UDR. When

interrupt-driven data transmission is used, the Data Register Empty interrupt routine

must either write new data to UDR in order to clear UDRE or disable the Data Register

Empty interrupt, otherwise a new interrupt will occur once the interrupt routine

terminates.

The Transmit Complete (TXC) flag bit is set one when the entire frame in the Transmit

Shift Register has been shifted out and there are no new data currently present in the

transmit buffer. The TXC flag bit is automatically cleared when a transmit complete inter-

rupt is executed, or it can be cleared by writing a one to its bit location. The TXC flag is

useful in half-duplex communication interfaces (like the RS-485 standard), where a

transmitting application must enter receive mode and free the communication bus

immediately after completing the transmission.

When the Transmit Compete Interrupt Enable (TXCIE) bit in UCSRB is set, the USART

Transmit Complete Interrupt will be executed when the TXC flag becomes set (provided

that global interrupts are enabled). When the transmit complete interrupt is used, the

interrupt handling routine does not have to clear the TXC flag, this is done automatically

when the interrupt is executed.

Parity Generator

The Parity Generator calculates the parity bit for the serial frame data. When parity bit is

enabled (UPM1 = 1), the transmitter control logic inserts the parity bit between the last

data bit and the first stop bit of the frame that is sent.

Disabling the Transmitter

The disabling of the Transmitter (setting the TXEN to zero) will not become effective

until ongoing and pending transmissions are completed, i.e., when the Transmit Shift

Register and Transmit Buffer Register do not contain data to be transmitted. When dis-

abled, the Transmitter will no longer override the TxD pin.

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Data Reception – The

USART Receiver

The USART Receiver is enabled by writing the Receive Enable (RXEN) bit in the

UCSRB Register to one. When the Receiver is enabled, the normal pin operation of the

RxD pin is overridden by the USART and given the function as the Receiver’s serial

input. The baud rate, mode of operation and frame format must be set up once before

any serial reception can be done. If synchronous operation is used, the clock on the

XCK pin will be used as transfer clock.

Receiving Frames with 5 to 8

Data Bits

The Receiver starts data reception when it detects a valid start bit. Each bit that follows

the start bit will be sampled at the baud rate or XCK clock, and shifted into the Receive

Shift Register until the first stop bit of a frame is received. A second stop bit will be

ignored by the Receiver. When the first stop bit is received, i.e., a complete serial frame

is present in the Receive Shift Register, the contents of the Shift Register will be moved

into the receive buffer. The receive buffer can then be read by reading the UDR I/O

location.

The following code example shows a simple USART receive function based on polling

of the Receive Complete (RXC) flag. When using frames with less than eight bits the

most significant bits of the data read from the UDR will be masked to zero. The USART

has to be initialized before the function can be used.

Assembly Code Example⁽¹⁾

USART_Receive:

; Wait for data to be received

sbis UCSRA, RXC

rjmp USART_Receive

; Get and return received data from buffer

in

r16, UDR

ret

C Code Example⁽¹⁾

unsigned char USART_Receive( void )

{

/* Wait for data to be received */

while ( !(UCSRA & (1<<RXC)) )

;

/* Get and return received data from buffer */

return UDR;

}

Note:

1. The example code assumes that the part specific header file is included.

For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”,

and “SBI” instructions must be replaced with instructions that allow access to

extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and

“CBR”.

The function simply waits for data to be present in the receive buffer by checking the

RXC flag, before reading the buffer and returning the value.

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Receiving Frames with 9 Data If 9-bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8 bit in

Bits

UCSRB before reading the low bits from the UDR. This rule applies to the FE, DOR and

UPE Status Flags as well. Read status from UCSRA, then data from UDR. Reading the

UDR I/O location will change the state of the receive buffer FIFO and consequently the

TXB8, FE, DOR and UPE bits, which all are stored in the FIFO, will change.

The following code example shows a simple USART receive function that handles both

nine bit characters and the status bits.

Assembly Code Example⁽¹⁾

USART_Receive:

; Wait for data to be received

sbis UCSRA, RXC

rjmp USART_Receive

; Get status and 9th bit, then data from buffer

in

r18, UCSRA

r17, UCSRB

r16, UDR

; If error, return -1

andi r18,(1<<FE)|(1<<DOR)|(1<<UPE)

breq USART_ReceiveNoError

ldi r17, HIGH(-1)

ldi r16, LOW(-1)

USART_ReceiveNoError:

; Filter the 9th bit, then return

lsr r17

andi r17, 0x01

ret

C Code Example⁽¹⁾

unsigned int USART_Receive( void )

{

unsigned char status, resh, resl;

/* Wait for data to be received */

while ( !(UCSRA & (1<<RXC)) )

;

/* Get status and 9th bit, then data */

/* from buffer */

status = UCSRA;

resh = UCSRB;

resl = UDR;

/* If error, return -1 */

if ( status & (1<<FE)|(1<<DOR)|(1<<UPE) )

return -1;

/* Filter the 9th bit, then return */

resh = (resh >> 1) & 0x01;

return ((resh << 8) | resl);

}

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Note:

1. The example code assumes that the part specific header file is included.

For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”,

and “SBI” instructions must be replaced with instructions that allow access to

extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and

“CBR”.

The receive function example reads all the I/O Registers into the Register File before

any computation is done. This gives an optimal receive buffer utilization since the buffer

location read will be free to accept new data as early as possible.

Receive Compete Flag and

Interrupt

The USART Receiver has one flag that indicates the Receiver state.

The Receive Complete (RXC) flag indicates if there are unread data present in the

receive buffer. This flag is one when unread data exist in the receive buffer, and zero

when the receive buffer is empty (i.e., does not contain any unread data). If the Receiver

is disabled (RXEN = 0), the receive buffer will be flushed and consequently the RXC bit

will become zero.

When the Receive Complete Interrupt Enable (RXCIE) in UCSRB is set, the USART

Receive Complete interrupt will be executed as long as the RXC flag is set (provided

that global interrupts are enabled). When interrupt-driven data reception is used, the

receive complete routine must read the received data from UDR in order to clear the

RXC flag, otherwise a new interrupt will occur once the interrupt routine terminates.

Receiver Error Flags

The USART Receiver has three error flags: Frame Error (FE), Data OverRun (DOR) and

Parity Error (UPE). All can be accessed by reading UCSRA. Common for the error flags

is that they are located in the receive buffer together with the frame for which they indi-

cate the error status. Due to the buffering of the error flags, the UCSRA must be read

before the receive buffer (UDR), since reading the UDR I/O location changes the buffer

read location. Another equality for the error flags is that they can not be altered by soft-

ware doing a write to the flag location. However, all flags must be set to zero when the

UCSRA is written for upward compatibility of future USART implementations. None of

the error flags can generate interrupts.

The Frame Error (FE) flag indicates the state of the first stop bit of the next readable

frame stored in the receive buffer. The FE flag is zero when the stop bit was correctly

read (as one), and the FE flag will be one when the stop bit was incorrect (zero). This

flag can be used for detecting out-of-sync conditions, detecting break conditions and

protocol handling. The FE flag is not affected by the setting of the USBS bit in UCSRC

since the Receiver ignores all, except for the first, stop bits. For compatibility with future

devices, always set this bit to zero when writing to UCSRA.

The Data OverRun (DOR) flag indicates data loss due to a receiver buffer full condition.

A Data OverRun occurs when the receive buffer is full (two characters), it is a new char-

acter waiting in the Receive Shift Register, and a new start bit is detected. If the DOR

flag is set there was one or more serial frame lost between the frame last read from

UDR, and the next frame read from UDR. For compatibility with future devices, always

write this bit to zero when writing to UCSRA. The DOR flag is cleared when the frame

received was successfully moved from the Shift Register to the receive buffer.

The Parity Error (UPE) Flag indicates that the next frame in the receive buffer had a Par-

ity Error when received. If Parity Check is not enabled the UPE bit will always be read

zero. For compatibility with future devices, always set this bit to zero when writing to

UCSRA. For more details see “Parity Bit Calculation” on page 120 and “Parity Checker”

on page 128.

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Parity Checker

The Parity Checker is active when the high USART Parity mode (UPM1) bit is set. Type

of Parity Check to be performed (odd or even) is selected by the UPM0 bit. When

enabled, the Parity Checker calculates the parity of the data bits in incoming frames and

compares the result with the parity bit from the serial frame. The result of the check is

stored in the receive buffer together with the received data and stop bits. The Parity

Error (UPE) flag can then be read by software to check if the frame had a Parity Error.

The UPE bit is set if the next character that can be read from the receive buffer had a

Parity Error when received and the Parity Checking was enabled at that point (UPM1 =

1). This bit is valid until the receive buffer (UDR) is read.

Disabling the Receiver

In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from

ongoing receptions will therefore be lost. When disabled (i.e., the RXEN is set to zero)

the Receiver will no longer override the normal function of the RxD port pin. The

Receiver buffer FIFO will be flushed when the Receiver is disabled. Remaining data in

the buffer will be lost

Flushing the Receive Buffer

The receiver buffer FIFO will be flushed when the Receiver is disabled, i.e., the buffer

will be emptied of its contents. Unread data will be lost. If the buffer has to be flushed

during normal operation, due to for instance an error condition, read the UDR I/O loca-

tion until the RXC flag is cleared. The following code example shows how to flush the

receive buffer.

Assembly Code Example⁽¹⁾

USART_Flush:

sbis UCSRA, RXC

ret

in

rjmp USART_Flush

C Code Example⁽¹⁾

r16, UDR

void USART_Flush( void )

{

unsigned char dummy;

while ( UCSRA & (1<<RXC) ) dummy = UDR;

}

Note:

1. The example code assumes that the part specific header file is included.

For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”,

and “SBI” instructions must be replaced with instructions that allow access to

extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and

“CBR”.

Asynchronous Data

Reception

The USART includes a clock recovery and a data recovery unit for handling asynchro-

nous data reception. The clock recovery logic is used for synchronizing the internally

generated baud rate clock to the incoming asynchronous serial frames at the RxD pin.

The data recovery logic samples and low pass filters each incoming bit, thereby improv-

ing the noise immunity of the Receiver. The asynchronous reception operational range

depends on the accuracy of the internal baud rate clock, the rate of the incoming

frames, and the frame size in number of bits.

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Asynchronous Clock

Recovery

The clock recovery logic synchronizes internal clock to the incoming serial frames. Fig-

ure 57 illustrates the sampling process of the start bit of an incoming frame. The sample

rate is 16 times the baud rate for Normal mode, and eight times the baud rate for Double

Speed mode. The horizontal arrows illustrate the synchronization variation due to the

sampling process. Note the larger time variation when using the Double Speed mode

(U2X = 1) of operation. Samples denoted zero are samples done when the RxD line is

idle (i.e., no communication activity).

Figure 57. Start Bit Sampling

RxD

IDLE

START

BIT 0

Sample

(U2X = 0)

0

1

2

3

2

4

5

3

6

7

4

8

9

5

10

11

6

12

13

7

14

15

8

16

1

2

3

Sample

(U2X = 1)

0

2

When the clock recovery logic detects a high (idle) to low (start) transition on the RxD

line, the start bit detection sequence is initiated. Let sample 1 denote the first zero-sam-

ple as shown in the figure. The clock recovery logic then uses samples 8, 9, and 10 for

Normal mode, and samples 4, 5, and 6 for Double Speed mode (indicated with sample

numbers inside boxes on the figure), to decide if a valid start bit is received. If two or

more of these three samples have logical high levels (the majority wins), the start bit is

rejected as a noise spike and the Receiver starts looking for the next high to low-transi-

tion. If however, a valid start bit is detected, the clock recovery logic is synchronized and

the data recovery can begin. The synchronization process is repeated for each start bit.

Asynchronous Data Recovery When the receiver clock is synchronized to the start bit, the data recovery can begin.

The data recovery unit uses a state machine that has 16 states for each bit in Normal

mode and eight states for each bit in Double Speed mode. Figure 58 shows the sam-

pling of the data bits and the parity bit. Each of the samples is given a number that is

equal to the state of the recovery unit.

Figure 58. Sampling of Data and Parity Bit

RxD

BIT n

Sample

(U2X = 0)

1

2

3

2

4

5

3

6

7

4

8

9

5

10

11

6

12

13

7

14

15

8

16

1

Sample

(U2X = 1)

The decision of the logic level of the received bit is taken by doing a majority voting of

the logic value to the three samples in the center of the received bit. The center samples

are emphasized on the figure by having the sample number inside boxes. The majority

voting process is done as follows: If two or all three samples have high levels, the

received bit is registered to be a logic 1. If two or all three samples have low levels, the

received bit is registered to be a logic 0. This majority voting process acts as a low pass

filter for the incoming signal on the RxD pin. The recovery process is then repeated until

a complete frame is received. Including the first stop bit. Note that the Receiver only

uses the first stop bit of a frame.

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Figure 59 shows the sampling of the stop bit and the earliest possible beginning of the

start bit of the next frame.

Figure 59. Stop Bit Sampling and Next Start Bit Sampling

(A)

(B)

(C)

RxD

STOP 1

Sample

(U2X = 0)

1

2

3

2

4

5

3

6

7

4

8

9

5

10

0/1 0/1 0/1

Sample

(U2X = 1)

6

0/1

The same majority voting is done to the stop bit as done for the other bits in the frame. If

the stop bit is registered to have a logic 0 value, the Frame Error (FE) flag will be set.

A new high to low transition indicating the start bit of a new frame can come right after

the last of the bits used for majority voting. For Normal Speed mode, the first low level

sample can be at point marked (A) in Figure 59. For Double Speed mode the first low

level must be delayed to (B). (C) marks a stop bit of full length. The early start bit detec-

tion influences the operational range of the Receiver.

Asynchronous Operational

Range

The operational range of the Receiver is dependent on the mismatch between the

received bit rate and the internally generated baud rate. If the Transmitter is sending

frames at too fast or too slow bit rates, or the internally generated baud rate of the

Receiver does not have a similar (see Table 49) base frequency, the Receiver will not

be able to synchronize the frames to the start bit.

The following equations can be used to calculate the ratio of the incoming data rate and

internal receiver baud rate.

(D + 1)S

S – 1 + D ⋅ S + S

(D + 2)S

(D + 1)S + S

R

= ------------------------------------------

R

= -----------------------------------

slow

fast

F

M

D

S

Sum of character size and parity size (D = 5 to 10 bit)

Samples per bit. S = 16 for Normal Speed mode and S = 8 for Double Speed

mode.

S_F

First sample number used for majority voting. S_F= 8 for normal speed and S_F= 4

for Double Speed mode.

S_MMiddle sample number used for majority voting. S_M= 9 for normal speed and

S_M= 5 for Double Speed mode.

R_slowis the ratio of the slowest incoming data rate that can be accepted in relation to the

receiver baud rate. R_fastis the ratio of the fastest incoming data rate that can be

accepted in relation to the receiver baud rate.

Table 49 and Table 50 list the maximum receiver baud rate error that can be tolerated.

Note that Normal Speed mode has higher toleration of baud rate variations.

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Table 49. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode

(U2X = 0)

D

Recommended Max

Receiver Error (%)

# (Data+Parity Bit)

R

_slow(%)

93.20

94.12

94.81

95.36

95.81

96.17

R_fast(%)

106.67

105.79

105.11

104.58

104.14

103.78

Max Total Error (%)

+6.67/-6.8

5

6

± 3.0

± 2.5

± 2.0

± 1.5

+5.79/-5.88

+5.11/-5.19

+4.58/-4.54

+4.14/-4.19

+3.78/-3.83

7

8

9

10

Table 50. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode

(U2X = 1)

D

Recommended Max

Receiver Error (%)

# (Data+Parity Bit) R_slow(%) R_fast(%) Max Total Error (%)

5

6

94.12

94.92

95.52

96.00

96.39

96.70

105.66

104.92

104,35

103.90

103.53

103.23

+5.66/-5.88

+4.92/-5.08

+4.35/-4.48

+3.90/-4.00

+3.53/-3.61

+3.23/-3.30

± 2.5

± 2.0

± 1.5

± 1.0

7

8

9

10

The recommendations of the maximum receiver baud rate error was made under the

assumption that the Receiver and Transmitter equally divides the maximum total error.

There are two possible sources for the receivers baud rate error. The Receiver’s system

clock (XTAL) will always have some minor instability over the supply voltage range and

the temperature range. When using a crystal to generate the system clock, this is rarely

a problem, but for a resonator the system clock may differ more than 2% depending of

the resonators tolerance. The second source for the error is more controllable. The baud

rate generator can not always do an exact division of the system frequency to get the

baud rate wanted. In this case an UBRR value that gives an acceptable low error can be

used if possible.

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Multi-processor

Communication Mode

Setting the Multi-processor Communication mode (MPCM) bit in UCSRA enables a fil-

tering function of incoming frames received by the USART Receiver. Frames that do not

contain address information will be ignored and not put into the receive buffer. This

effectively reduces the number of incoming frames that has to be handled by the CPU,

in a system with multiple MCUs that communicate via the same serial bus. The Trans-

mitter is unaffected by the MPCM setting, but has to be used differently when it is a part

of a system utilizing the Multi-processor Communication mode.

If the Receiver is set up to receive frames that contain 5 to 8 data bits, then the first stop

bit indicates if the frame contains data or address information. If the Receiver is set up

for frames with nine data bits, then the ninth bit (RXB8) is used for identifying address

and data frames. When the frame type bit (the first stop or the ninth bit) is one, the frame

contains an address. When the frame type bit is zero the frame is a data frame.

The Multi-processor Communication mode enables several slave MCUs to receive data

from a master MCU. This is done by first decoding an address frame to find out which

MCU has been addressed. If a particular slave MCU has been addressed, it will receive

the following data frames as normal, while the other slave MCUs will ignore the received

frames until another address frame is received.

Using MPCM

For an MCU to act as a master MCU, it can use a 9-bit character frame format (UCSZ =

7). The ninth bit (TXB8) must be set when an address frame (TXB8 = 1) or cleared when

a data frame (TXB = 0) is being transmitted. The slave MCUs must in this case be set to

use a 9-bit character frame format.

The following procedure should be used to exchange data in Multi-processor Communi-

cation mode:

1. All Slave MCUs are in Multi-processor Communication mode (MPCM in UCSRA

is set).

2. The Master MCU sends an address frame, and all slaves receive and read this

frame. In the Slave MCUs, the RXC flag in UCSRA will be set as normal.

3. Each Slave MCU reads the UDR Register and determines if it has been

selected. If so, it clears the MPCM bit in UCSRA, otherwise it waits for the next

address byte and keeps the MPCM setting.

4. The addressed MCU will receive all data frames until a new address frame is

received. The other Slave MCUs, which still have the MPCM bit set, will ignore

the data frames.

5. When the last data frame is received by the addressed MCU, the addressed

MCU sets the MPCM bit and waits for a new address frame from master. The

process then repeats from 2.

Using any of the 5- to 8-bit character frame formats is possible, but impractical since the

Receiver must change between using n and n+1 character frame formats. This makes

full-duplex operation difficult since the Transmitter and Receiver uses the same charac-

ter size setting. If 5- to 8-bit character frames are used, the Transmitter must be set to

use two stop bit (USBS = 1) since the first stop bit is used for indicating the frame type.

Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCM bit.

The MPCM bit shares the same I/O location as the TXC flag and this might accidentally

be cleared when using SBI or CBI instructions.

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USART Register

Description

USART I/O Data Register –

UDR

Bit

7

6

5

4

3

2

1

0

RXB[7:0]

TXB[7:0]

UDR (Read)

UDR (Write)

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers

share the same I/O address referred to as USART Data Register or UDR. The Transmit

Data Buffer Register (TXB) will be the destination for data written to the UDR Register

location. Reading the UDR Register location will return the contents of the Receive Data

Buffer Register (RXB).

For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter

and set to zero by the Receiver.

The transmit buffer can only be written when the UDRE flag in the UCSRA Register is

set. Data written to UDR when the UDRE flag is not set, will be ignored by the USART

Transmitter. When data is written to the transmit buffer, and the Transmitter is enabled,

the Transmitter will load the data into the Transmit Shift Register when the Shift Register

is empty. Then the data will be serially transmitted on the TxD pin.

The receive buffer consists of a two level FIFO. The FIFO will change its state whenever

the receive buffer is accessed. Due to this behavior of the receive buffer, do not use

Read-Modify-Write instructions (SBI and CBI) on this location. Be careful when using bit

test instructions (SBIC and SBIS), since these also will change the state of the FIFO.

USART Control and Status

Register A – UCSRA

Bit

7

RXC

R

6

5

UDRE

R

4

FE

R

3

DOR

R

2

UPE

R

1

0

MPCM

R/W

0

TXC

R/W

0

U2X

R/W

0

UCSRA

Read/Write

Initial Value

0

1

0

• Bit 7 – RXC: USART Receive Complete

This flag bit is set when there are unread data in the receive buffer and cleared when the

receive buffer is empty (i.e., does not contain any unread data). If the Receiver is dis-

abled, the receive buffer will be flushed and consequently the RXC bit will become zero.

The RXC flag can be used to generate a Receive Complete interrupt (see description of

the RXCIE bit).

• Bit 6 – TXC: USART Transmit Complete

This flag bit is set when the entire frame in the Transmit Shift Register has been shifted

out and there are no new data currently present in the transmit buffer (UDR). The TXC

flag bit is automatically cleared when a transmit complete interrupt is executed, or it can

be cleared by writing a one to its bit location. The TXC flag can generate a Transmit

Complete interrupt (see description of the TXCIE bit).

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• Bit 5 – UDRE: USART Data Register Empty

The UDRE flag indicates if the transmit buffer (UDR) is ready to receive new data. If

UDRE is one, the buffer is empty, and therefore ready to be written. The UDRE flag can

generate a Data Register Empty interrupt (see description of the UDRIE bit).

UDRE is set after a reset to indicate that the Transmitter is ready.

• Bit 4 – FE: Frame Error

This bit is set if the next character in the receive buffer had a Frame Error when

received. I.e., when the first stop bit of the next character in the receive buffer is zero.

This bit is valid until the receive buffer (UDR) is read. The FE bit is zero when the stop

bit of received data is one. Always set this bit to zero when writing to UCSRA.

• Bit 3 – DOR: Data OverRun

This bit is set if a Data OverRun condition is detected. A Data OverRun occurs when the

receive buffer is full (two characters), it is a new character waiting in the Receive Shift

Register, and a new start bit is detected. This bit is valid until the receive buffer (UDR) is

read. Always set this bit to zero when writing to UCSRA.

• Bit 2 – UPE: USART Parity Error

This bit is set if the next character in the receive buffer had a Parity Error when received

and the Parity Checking was enabled at that point (UPM1 = 1). This bit is valid until the

receive buffer (UDR) is read. Always set this bit to zero when writing to UCSRA.

• Bit 1 – U2X: Double the USART Transmission Speed

This bit only has effect for the asynchronous operation. Write this bit to zero when using

synchronous operation.

Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effec-

tively doubling the transfer rate for asynchronous communication.

• Bit 0 – MPCM: Multi-processor Communication Mode

This bit enables the Multi-processor Communication mode. When the MPCM bit is writ-

ten to one, all the incoming frames received by the USART Receiver that do not contain

address information will be ignored. The Transmitter is unaffected by the MPCM setting.

For more detailed information see “Multi-processor Communication Mode” on page 132.

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USART Control and Status

Register B – UCSRB

Bit

7

RXCIE

R/W

0

6

TXCIE

R/W

0

5

UDRIE

R/W

0

4

RXEN

R/W

0

3

TXEN

R/W

0

2

UCSZ2

R/W

0

1

RXB8

R

0

TXB8

R/W

0

UCSRB

Read/Write

Initial Value

0

• Bit 7 – RXCIE: RX Complete Interrupt Enable

Writing this bit to one enables interrupt on the RXC flag. A USART Receive Complete

interrupt will be generated only if the RXCIE bit is written to one, the Global Interrupt

Flag in SREG is written to one and the RXC bit in UCSRA is set.

• Bit 6 – TXCIE: TX Complete Interrupt Enable

Writing this bit to one enables interrupt on the TXC flag. A USART Transmit Complete

interrupt will be generated only if the TXCIE bit is written to one, the Global Interrupt

Flag in SREG is written to one and the TXC bit in UCSRA is set.

• Bit 5 – UDRIE: USART Data Register Empty Interrupt Enable

Writing this bit to one enables interrupt on the UDRE flag. A Data Register Empty inter-

rupt will be generated only if the UDRIE bit is written to one, the Global Interrupt Flag in

SREG is written to one and the UDRE bit in UCSRA is set.

• Bit 4 – RXEN: Receiver Enable

Writing this bit to one enables the USART Receiver. The Receiver will override normal

port operation for the RxD pin when enabled. Disabling the Receiver will flush the

receive buffer invalidating the FE, DOR, and UPE Flags.

• Bit 3 – TXEN: Transmitter Enable

Writing this bit to one enables the USART Transmitter. The Transmitter will override nor-

mal port operation for the TxD pin when enabled. The disabling of the Transmitter

(writing TXEN to zero) will not become effective until ongoing and pending transmis-

sions are completed, i.e., when the Transmit Shift Register and Transmit Buffer Register

do not contain data to be transmitted. When disabled, the Transmitter will no longer

override the TxD port.

• Bit 2 – UCSZ2: Character Size

The UCSZ2 bits combined with the UCSZ1:0 bit in UCSRC sets the number of data bits

(Character SiZe) in a frame the Receiver and Transmitter use.

• Bit 1 – RXB8: Receive Data Bit 8

RXB8 is the ninth data bit of the received character when operating with serial frames

with nine data bits. Must be read before reading the low bits from UDR.

• Bit 0 – TXB8: Transmit Data Bit 8

TXB8 is the ninth data bit in the character to be transmitted when operating with serial

frames with nine data bits. Must be written before writing the low bits to UDR.

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USART Control and Status

Register C – UCSRC

Bit

7

–

6

UMSEL

R/W

0

5

UPM1

R/W

0

4

UPM0

R/W

0

3

USBS

R/W

0

2

UCSZ1

R/W

1

UCSZ0

R/W

1

0

UCPOL

R/W

0

UCSRC

Read/Write

Initial Value

R

0

• Bit 6 – UMSEL: USART Mode Select

This bit selects between asynchronous and synchronous mode of operation.

Table 51. UMSEL Bit Settings

UMSEL

Mode

0

1

Asynchronous Operation

Synchronous Operation

• Bit 5:4 – UPM1:0: Parity Mode

These bits enable and set type of parity generation and check. If enabled, the Transmit-

ter will automatically generate and send the parity of the transmitted data bits within

each frame. The Receiver will generate a parity value for the incoming data and com-

pare it to the UPM0 setting. If a mismatch is detected, the UPE Flag in UCSRA will be

set.

Table 52. UPM Bits Settings

UPM1

UPM0

Parity Mode

0

1

0

1

0

1

Disabled

Reserved

Enabled, Even Parity

Enabled, Odd Parity

• Bit 3 – USBS: Stop Bit Select

This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver

ignores this setting.

Table 53. USBS Bit Settings

USBS

Stop Bit(s)

1-bit

0

1

2-bit

• Bit 2:1 – UCSZ1:0: Character Size

The UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits

(Character SiZe) in a frame the Receiver and Transmitter use. See Table 54 on page

137.

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Table 54. UCSZ Bits Settings

UCSZ2

UCSZ1

UCSZ0

Character Size

0

1

0

1

0

1

0

1

0

1

0

1

0

1

5-bit

6-bit

7-bit

8-bit

Reserved

9-bit

• Bit 0 – UCPOL: Clock Polarity

This bit is used for synchronous mode only. Write this bit to zero when asynchronous

mode is used. The UCPOL bit sets the relationship between data output change and

data input sample, and the synchronous clock (XCK).

Table 55. UCPOL Bit Settings

Transmitted Data Changed (Output of

UCPOL TxD Pin)

Received Data Sampled (Input on

RxD Pin)

0

1

Rising XCK Edge

Falling XCK Edge

Rising XCK Edge

USART Baud Rate Registers –

UBRRL and UBRRH

Bit

15

14

13

12

11

10

9

8

–

UBRR[11:8]

UBRRH

UBRRL

UBRR[7:0]

7

R

6

R

5

R

4

R

3

R/W

0

2

R/W

0

1

R/W

0

R/W

0

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

• Bit 15:12 – Reserved Bits

These bits are reserved for future use. For compatibility with future devices, these bit

must be written to zero when UBRRH is written.

• Bit 11:0 – UBRR11:0: USART Baud Rate Register

This is a 12-bit register which contains the USART baud rate. The UBRRH contains the

four most significant bits, and the UBRRL contains the eight least significant bits of the

USART baud rate. Ongoing transmissions by the Transmitter and Receiver will be cor-

rupted if the baud rate is changed. Writing UBRRL will trigger an immediate update of

the baud rate prescaler.

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Examples of Baud Rate

Setting

For standard crystal and resonator frequencies, the most commonly used baud rates for

asynchronous operation can be generated by using the UBRR settings in Table 56.

UBRR values which yield an actual baud rate differing less than 0.5% from the target

baud rate, are bold in the table. Higher error ratings are acceptable, but the Receiver will

have less noise resistance when the error ratings are high, especially for large serial

frames (see “Asynchronous Operational Range” on page 130). The error values are cal-

culated using the following equation:

BaudRate_{Closest Match}

⎛

⎞

Error[%] = ------------------------------------------------------- – 1 • 100%

⎝

⎠

BaudRate

Table 56. Examples of UBRR Settings for Commonly Used Oscillator Frequencies

f_osc= 1.0000 MHz f_osc= 1.8432 MHz

U2X = 0 U2X = 1 U2X = 0 U2X = 1

UBRR UBRR UBRR UBRR

f_osc= 2.0000 MHz

U2X = 0 U2X = 1

UBRR UBRR

Baud

Rate

(bps)

Error

0.2%

-7.0%

8.5%

-18.6%

8.5%

–

Error

0.2%

-3.5%

-7.0%

8.5%

-18.6%

8.5%

–

Error

0.0%

-25.0%

0.0%

–

Error

0.0%

–

Error

0.2%

-3.5%

-7.0%

8.5%

-18.6%

8.5%

–

Error

0.2%

2.1%

0.2%

-3.5%

-7.0%

8.5%

–

2400

25

12

6

51

25

12

8

47

23

11

7

95

47

23

15

11

7

51

25

12

8

103

51

25

16

12

8

4800

9600

14.4k

19.2k

28.8k

38.4k

57.6k

76.8k

115.2k

230.4k

250k

3

2

6

5

6

1

3

1

2

5

2

6

0

1

3

1

3

–

1

2

1

2

–

0

1

0

1

–

0

–

0

0.0%

Max. ⁽¹⁾

62.5 kbps

UBRR = 0, Error = 0.0%

125 kbps

115.2 kbps

230.4 kbps

125 kbps

250 kbps

1.

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Table 57. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued)

f_osc= 3.6864 MHz

U2X = 0

f_osc= 4.0000 MHz

U2X = 0

f_osc= 7.3728 MHz

U2X = 0

UBRR

Baud

Rate

(bps)

U2X = 1

UBRR Error

U2X = 1

UBRR Error

U2X = 1

UBRR

Error

0.0%

-7.8%

–

UBRR

Error

0.2%

2.1%

0.2%

-3.5%

-7.0%

8.5%

0.0%

–

Error

0.0%

-7.8%

–

Error

0.0%

-7.8%

2400

4800

9600

14.4k

19.2k

28.8k

38.4k

57.6k

76.8k

115.2k

230.4k

250k

95

47

23

15

11

7

191

95

47

31

23

15

11

7

0.0%

-7.8%

–

103

51

25

16

12

8

207

103

51

34

25

16

12

8

0.2%

-0.8%

0.2%

2.1%

0.2%

-3.5%

-7.0%

8.5%

0.0%

–

191

95

47

31

23

15

11

7

383

191

95

63

47

31

23

15

11

7

5

6

3

2

5

2

6

5

1

3

1

3

0

1

0

1

3

0

1

0

1

3

0.5M

1M

–

0

–

0

1

–

0

Max. ⁽¹⁾

230.4 kbps

UBRR = 0, Error = 0.0%

460.8 kbps

250 kbps

0.5 Mbps

460.8 kbps

921.6 kbps

1.

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Table 58. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued)

f_osc= 8.0000 MHz f_osc= 11.0592 MHz f_osc= 14.7456 MHz

U2X = 0 U2X = 1 U2X = 0 U2X = 1 U2X = 0 U2X = 1

UBRR UBRR UBRR UBRR UBRR UBRR

Baud

Rate

(bps)

Error

0.2%

-0.8%

0.2%

2.1%

0.2%

-3.5%

-7.0%

8.5%

0.0%

–

Error

-0.1%

0.2%

0.6%

0.2%

-0.8%

0.2%

2.1%

0.2%

-3.5%

8.5%

0.0%

Error

0.0%

-7.8%

–

Error

0.0%

-7.8%

–

Error

0.0%

-7.8%

Error

0.0%

5.3%

-7.8%

2400

4800

9600

14.4k

19.2k

28.8k

38.4k

57.6k

76.8k

115.2k

230.4k

250k

207

103

51

34

25

16

12

8

416

207

103

68

51

34

25

16

12

8

287

143

71

47

35

23

17

11

8

575

287

143

95

71

47

35

23

17

11

5

383

191

95

63

47

31

23

15

11

7

767

383

191

127

95

63

47

31

23

15

7

6

3

5

1

3

2

3

1

3

2

5

3

6

0.5M

1M

0

1

–

2

1

3

–

0

–

0

1

Max. ⁽¹⁾

0.5 Mbps

UBRR = 0, Error = 0.0%

1 Mbps

691.2 kbps

1.3824 Mbps

921.6 kbps

1.8432 Mbps

1.

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Table 59.

Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued)

f_osc= 16.0000 MHz

U2X = 0

Error

U2X = 1

Error

Baud Rate

(bps)

UBRR

832

2400

4800

9600

14.4k

19.2k

28.8k

38.4k

57.6k

76.8k

115.2k

230.4k

250k

416

207

103

68

51

34

25

16

12

8

-0.1%

0.2%

0.6%

0.2%

-0.8%

0.2%

2.1%

0.2%

-3.5%

8.5%

0.0%

-0.1%

0.2%

-0.1%

0.2%

0.6%

0.2%

-0.8%

0.2%

2.1%

-3.5%

0.0%

416

207

138

103

68

51

34

25

16

8

3

7

0.5M

1

3

1M

0

1

Max. ⁽¹⁾

1 Mbps

2 Mbps

1.

UBRR = 0, Error = 0.0%

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Universal Serial

Interface – USI

The Universal Serial Interface, or USI, provides the basic hardware resources needed

for serial communication. Combined with a minimum of control software, the USI allows

significantly higher transfer rates and uses less code space than solutions based on

software only. Interrupts are included to minimize the processor load. The main features

of the USI are:

• Two-wire Synchronous Data Transfer (Master or Slave, f_SCLmax= f_CK/16)

• Three-wire Synchronous Data Transfer (Master, f_SCKmax= f_CK/2, Slave f_SCKmax= f_CK/4)

• Data Received Interrupt

• Wake-up from Idle Mode

• In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode

• Two-wire Start Condition Detector with Interrupt Capability

Overview

A simplified block diagram of the USI is shown on Figure 60. For the actual placement of

I/O pins, refer to “Pinout ATtiny2313” on page 2. CPU accessible I/O Registers, includ-

ing I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit

locations are listed in the “USI Register Descriptions” on page 148.

Figure 60. Universal Serial Interface, Block Diagram

(Output only)

DO

D

Q

LE

(Input/Open Drain)

DI/SDA

3

2

USIDR

1

0

TIM0 OVF

3

2

0

1

(Input/Open Drain)

USCK/SCL

4-bit Counter

1

0

CLOCK

HOLD

[1]

Two-wire Clock

Control Unit

USISR

2

USICR

The 8-bit Shift Register is directly accessible via the data bus and contains the incoming

and outgoing data. The register has no buffering so the data must be read as quickly as

possible to ensure that no data is lost. The most significant bit is connected to one of two

output pins depending of the wire mode configuration. A transparent latch is inserted

between the serial register output and output pin, which delays the change of data out-

put to the opposite clock edge of the data input sampling. The serial input is always

sampled from the Data Input (DI) pin independent of the configuration.

The 4-bit counter can be both read and written via the data bus, and can generate an

overflow interrupt. Both the serial register and the counter are clocked simultaneously

by the same clock source. This allows the counter to count the number of bits received

or transmitted and generate an interrupt when the transfer is complete. Note that when

an external clock source is selected the counter counts both clock edges. In this case

the counter counts the number of edges, and not the number of bits. The clock can be

selected from three different sources: The USCK pin, Timer0 overflow, or from software.

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The Two-wire clock control unit can generate an interrupt when a start condition is

detected on the Two-wire bus. It can also generate wait states by holding the clock pin

low after a start condition is detected, or after the counter overflows.

Functional Descriptions

Three-wire Mode

The USI Three-wire mode is compliant to the Serial Peripheral Interface (SPI) mode 0

and 1, but does not have the slave select (SS) pin functionality. However, this feature

can be implemented in software if necessary. Pin names used by this mode are: DI, DO,

and USCK.

Figure 61. Three-wire Mode Operation, Simplified Diagram

DO

DI

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

USCK

SLAVE

DO

DI

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

USCK

PORTxn

MASTER

Figure 61 shows two USI units operating in Three-wire mode, one as Master and one as

Slave. The two Shift Registers are interconnected in such way that after eight USCK

clocks, the data in each register are interchanged. The same clock also increments the

USI’s 4-bit counter. The Counter Overflow (interrupt) Flag, or USIOIF, can therefore be

used to determine when a transfer is completed. The clock is generated by the Master

device software by toggling the USCK pin via the PORT Register or by writing a one to

the USITC bit in USICR.

Figure 62. Three-wire Mode, Timing Diagram

( Reference )

1

2

3

4

5

6

7

8

CYCLE

USCK

DO

MSB

6

5

4

3

2

1

LSB

6

5

4

3

2

1

DI

A

B

C

D

E

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The Three-wire mode timing is shown in Figure 62. At the top of the figure is a USCK

cycle reference. One bit is shifted into the USI Shift Register (USIDR) for each of these

cycles. The USCK timing is shown for both external clock modes. In External Clock

mode 0 (USICS0 = 0), DI is sampled at positive edges, and DO is changed (data regis-

ter is shifted by one) at negative edges. External Clock mode 1 (USICS0 = 1) uses the

opposite edges versus mode 0, i.e., samples data at negative and changes the output at

positive edges. The USI clock modes corresponds to the SPI data mode 0 and 1.

Referring to the timing diagram (Figure 62.), a bus transfer involves the following steps:

1. The Slave device and Master device sets up its data output and, depending on

the protocol used, enables its output driver (mark A and B). The output is set up

by writing the data to be transmitted to the Serial Data Register. Enabling of the

output is done by setting the corresponding bit in the port Data Direction Regis-

ter. Note that point A and B does not have any specific order, but both must be at

least one half USCK cycle before point C where the data is sampled. This must

be done to ensure that the data setup requirement is satisfied. The 4-bit counter

is reset to zero.

2. The Master generates a clock pulse by software toggling the USCK line twice (C

and D). The bit value on the slave and master’s data input (DI) pin is sampled by

the USI on the first edge (C), and the data output is changed on the opposite

edge (D). The 4-bit counter will count both edges.

3. Step 2. is repeated eight times for a complete register (byte) transfer.

4. After eight clock pulses (i.e., 16 clock edges) the counter will overflow and indi-

cate that the transfer is completed. The data bytes transferred must now be

processed before a new transfer can be initiated. The overflow interrupt will wake

up the processor if it is set to Idle mode. Depending of the protocol used the

slave device can now set its output to high impedance.

SPI Master Operation

Example

The following code demonstrates how to use the USI module as a SPI Master:

SPITransfer:

out

ldi

out

ldi

USIDR,r16

r16,(1<<USIOIF)

USISR,r16

r16,(1<<USIWM0)|(1<<USICS1)|(1<<USICLK)|(1<<USITC)

SPITransfer_loop:

out

sbis

rjmp

in

USICR,r16

USISR,USIOIF

SPITransfer_loop

r16,USIDR

ret

The code is size optimized using only eight instructions (+ ret). The code example

assumes that the DO and USCK pins are enabled as output in the DDRB Register. The

value stored in register r16 prior to the function is called is transferred to the Slave

device, and when the transfer is completed the data received from the Slave is stored

back into the r16 Register.

The second and third instructions clears the USI Counter Overflow Flag and the USI

counter value. The fourth and fifth instruction set Three-wire mode, positive edge Shift

Register clock, count at USITC strobe, and toggle USCK. The loop is repeated 16 times.

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The following code demonstrates how to use the USI module as a SPI Master with max-

imum speed (fsck = fck/2):

SPITransfer_Fast:

out

ldi

USIDR,r16

r16,(1<<USIWM0)|(0<<USICS0)|(1<<USITC)

r17,(1<<USIWM0)|(0<<USICS0)|(1<<USITC)|(1<<USICLK)

out

USICR,r16 ; MSB

USICR,r17

USICR,r16

USICR,r17

USICR,r16

USICR,r17

USICR,r16

USICR,r17

USICR,r16

USICR,r17

USICR,r16

USICR,r17

USICR,r16

USICR,r17

USICR,r16 ; LSB

USICR,r17

in

r16,USIDR

ret

SPI Slave Operation Example The following code demonstrates how to use the USI module as a SPI Slave:

init:

ldi

out

r16,(1<<USIWM0)|(1<<USICS1)

USICR,r16

...

SlaveSPITransfer:

out

ldi

out

USIDR,r16

r16,(1<<USIOIF)

USISR,r16

SlaveSPITransfer_loop:

sbis

rjmp

in

USISR,USIOIF

SlaveSPITransfer_loop

r16,USIDR

ret

The code is size optimized using only eight instructions (+ ret). The code example

assumes that the DO is configured as output and USCK pin is configured as input in the

DDR Register. The value stored in register r16 prior to the function is called is trans-

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ferred to the master device, and when the transfer is completed the data received from

the Master is stored back into the r16 Register.

Note that the first two instructions is for initialization only and needs only to be executed

once.These instructions sets Three-wire mode and positive edge Shift Register clock.

The loop is repeated until the USI Counter Overflow Flag is set.

Two-wire Mode

The USI Two-wire mode does not incorporate slew rate limiting on outputs and input

noise filtering. Pin names used by this mode are SCL and SDA.

Figure 63. Two-wire Mode Operation, Simplified Diagram

VCC

SDA

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SCL

HOLD

SCL

Two-wire Clock

Control Unit

SLAVE

SDA

SCL

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

PORTxn

MASTER

Figure 63 shows two USI units operating in Two-wire mode, one as Master and one as

Slave. It is only the physical layer that is shown since the system operation is highly

dependent of the communication scheme used. The main differences between the Mas-

ter and Slave operation at this level, is the serial clock generation which is always done

by the Master, and only the Slave uses the clock control unit. Clock generation must be

implemented in software, but the shift operation is done automatically by both devices.

Note that only clocking on negative edge for shifting data is of practical use in this mode.

The slave can insert wait states at start or end of transfer by forcing the SCL clock low.

This means that the Master must always check if the SCL line was actually released

after it has generated a positive edge.

Since the clock also increments the counter, a counter overflow can be used to indicate

that the transfer is completed. The clock is generated by the master by toggling the

USCK pin via the PORT Register.

The data direction is not given by the physical layer. A protocol, like the one used by the

TWI-bus, must be implemented to control the data flow.

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Figure 64. Two-wire Mode, Typical Timing Diagram

SDA

1 - 7

8

9

1 - 8

9

1 - 8

9

SCL

S

P

ADDRESS

R/W

ACK

DATA

ACK

DATA

ACK

A

B

C

D

E

F

Referring to the timing diagram (Figure 64.), a bus transfer involves the following steps:

1. The a start condition is generated by the Master by forcing the SDA low line while

the SCL line is high (A). SDA can be forced low either by writing a zero to bit 7 of

the Shift Register, or by setting the corresponding bit in the PORT Register to

zero. Note that the Data Direction Register bit must be set to one for the output to

be enabled. The slave device’s start detector logic (Figure 65.) detects the start

condition and sets the USISIF flag. The flag can generate an interrupt if

necessary.

2. In addition, the start detector will hold the SCL line low after the Master has

forced an negative edge on this line (B). This allows the Slave to wake up from

sleep or complete its other tasks before setting up the Shift Register to receive

the address. This is done by clearing the start condition flag and reset the

counter.

3. The Master set the first bit to be transferred and releases the SCL line (C). The

Slave samples the data and shift it into the serial register at the positive edge of

the SCL clock.

4. After eight bits are transferred containing slave address and data direction (read

or write), the Slave counter overflows and the SCL line is forced low (D). If the

slave is not the one the Master has addressed, it releases the SCL line and waits

for a new start condition.

5. If the Slave is addressed it holds the SDA line low during the acknowledgment

cycle before holding the SCL line low again (i.e., the Counter Register must be

set to 14 before releasing SCL at (D)). Depending of the R/W bit the Master or

Slave enables its output. If the bit is set, a master read operation is in progress

(i.e., the slave drives the SDA line) The slave can hold the SCL line low after the

acknowledge (E).

6. Multiple bytes can now be transmitted, all in same direction, until a stop condition

is given by the Master (F). Or a new start condition is given.

If the Slave is not able to receive more data it does not acknowledge the data byte it has

last received. When the Master does a read operation it must terminate the operation by

force the acknowledge bit low after the last byte transmitted.

Figure 65. Start Condition Detector, Logic Diagram

USISIF

CLOCK

HOLD

D Q

SDA

CLR

SCL

Write( USISIF)

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Start Condition Detector

The start condition detector is shown in Figure 65. The SDA line is delayed (in the range

of 50 to 300 ns) to ensure valid sampling of the SCL line.

The start condition detector is working asynchronously and can therefore wake up the

processor from the Power-down sleep mode. However, the protocol used might have

restrictions on the SCL hold time. Therefore, when using this feature in this case the

Oscillator start-up time set by the CKSEL Fuses (see “Clock Systems and their Distribu-

tion” on page 24) must also be taken into the consideration.

Alternative USI Usage

When the USI unit is not used for serial communication, it can be set up to do alternative

tasks due to its flexible design.

Half-duplex Asynchronous

Data Transfer

By utilizing the Shift Register in Three-wire mode, it is possible to implement a more

compact and higher performance UART than by software only.

4-bit Counter

The 4-bit counter can be used as a stand-alone counter with overflow interrupt. Note

that if the counter is clocked externally, both clock edges will generate an increment.

12-bit Timer/Counter

Combining the USI 4-bit counter and Timer/Counter0 allows them to be used as a 12-bit

counter.

Edge Triggered External

Interrupt

By setting the counter to maximum value (F) it can function as an additional external

interrupt. The overflow flag and interrupt enable bit are then used for the external inter-

rupt. This feature is selected by the USICS1 bit.

Software Interrupt

The counter overflow interrupt can be used as a software interrupt triggered by a clock

strobe.

USI Register

Descriptions

USI Data Register – USIDR

Bit

7

6

5

4

3

2

1

0

MSB

R/W

0

LSB

R/W

0

USIDR

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The USI uses no buffering of the serial register, i.e., when accessing the Data Register

(USIDR) the serial register is accessed directly. If a serial clock occurs at the same cycle

the register is written, the register will contain the value written and no shift is performed.

A (left) shift operation is performed depending of the USICS1..0 bits setting. The shift

operation can be controlled by an external clock edge, by a Timer/Counter0 overflow, or

directly by software using the USICLK strobe bit. Note that even when no wire mode is

selected (USIWM1..0 = 0) both the external data input (DI/SDA) and the external clock

input (USCK/SCL) can still be used by the Shift Register.

The output pin in use, DO or SDA depending on the wire mode, is connected via the out-

put latch to the most significant bit (bit 7) of the Data Register. The output latch is open

(transparent) during the first half of a serial clock cycle when an external clock source is

selected (USICS1 = 1), and constantly open when an internal clock source is used

(USICS1 = 0). The output will be changed immediately when a new MSB written as long

as the latch is open. The latch ensures that data input is sampled and data output is

changed on opposite clock edges.

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Note that the corresponding Data Direction Register to the pin must be set to one for

enabling data output from the Shift Register.

USI Status Register – USISR

Bit

7

USISIF

R/W

0

6

USIOIF

R/W

0

5

USIPF

R/W

0

4

USIDC

R

3

USICNT3

R/W

2

USICNT2

R/W

1

USICNT1

R/W

0

USICNT0

R/W

USISR

Read/Write

Initial Value

0

The Status Register contains interrupt flags, line status flags and the counter value.

• Bit 7 – USISIF: Start Condition Interrupt Flag

When Two-wire mode is selected, the USISIF flag is set (to one) when a start condition

is detected. When output disable mode or Three-wire mode is selected and (USICSx =

0b11 & USICLK = 0) or (USICS = 0b10 & USICLK = 0), any edge on the SCK pin sets

the flag.

An interrupt will be generated when the flag is set while the USISIE bit in USICR and the

Global Interrupt Enable Flag are set. The flag will only be cleared by writing a logical one

to the USISIF bit. Clearing this bit will release the start detection hold of USCL in Two-

wire mode.

A start condition interrupt will wake-up the processor from all sleep modes.

• Bit 6 – USIOIF: Counter Overflow Interrupt Flag

This flag is set (one) when the 4-bit counter overflows (i.e., at the transition from 15 to

0). An interrupt will be generated when the flag is set while the USIOIE bit in USICR and

the Global Interrupt Enable Flag are set. The flag will only be cleared if a one is written

to the USIOIF bit. Clearing this bit will release the counter overflow hold of SCL in Two-

wire mode.

A counter overflow interrupt will wake-up the processor from Idle sleep mode.

• Bit 5 – USIPF: Stop Condition Flag

When Two-wire mode is selected, the USIPF flag is set (one) when a stop condition is

detected. The flag is cleared by writing a one to this bit. Note that this is not an interrupt

flag. This signal is useful when implementing Two-wire bus master arbitration.

• Bit 4 – USIDC: Data Output Collision

This bit is logical one when bit 7 in the Shift Register differs from the physical pin value.

The flag is only valid when Two-wire mode is used. This signal is useful when imple-

menting Two-wire bus master arbitration.

• Bits 3..0 – USICNT3..0: Counter Value

These bits reflect the current 4-bit counter value. The 4-bit counter value can directly be

read or written by the CPU.

The 4-bit counter increments by one for each clock generated either by the external

clock edge detector, by a Timer/Counter0 overflow, or by software using USICLK or

USITC strobe bits. The clock source depends of the setting of the USICS1..0 bits. For

external clock operation a special feature is added that allows the clock to be generated

by writing to the USITC strobe bit. This feature is enabled by write a one to the USICLK

bit while setting an external clock source (USICS1 = 1).

Note that even when no wire mode is selected (USIWM1..0 = 0) the external clock input

(USCK/SCL) are can still be used by the counter.

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USI Control Register – USICR

Bit

7

USISIE

R/W

0

6

USIOIE

R/W

0

5

USIWM1

R/W

4

USIWM0

R/W

3

USICS1

R/W

0

2

USICS0

R/W

0

1

0

USITC

W

USICLK

USICR

Read/Write

Initial Value

W

0

The Control Register includes interrupt enable control, wire mode setting, Clock Select

setting, and clock strobe.

• Bit 7 – USISIE: Start Condition Interrupt Enable

Setting this bit to one enables the Start Condition detector interrupt. If there is a pending

interrupt when the USISIE and the Global Interrupt Enable Flag is set to one, this will

immediately be executed.

• Bit 6 – USIOIE: Counter Overflow Interrupt Enable

Setting this bit to one enables the Counter Overflow interrupt. If there is a pending inter-

rupt when the USIOIE and the Global Interrupt Enable Flag is set to one, this will

immediately be executed.

• Bit 5..4 – USIWM1..0: Wire Mode

These bits set the type of wire mode to be used. Basically only the function of the

outputs are affected by these bits. Data and clock inputs are not affected by the mode

selected and will always have the same function. The counter and Shift Register can

therefore be clocked externally, and data input sampled, even when outputs are

disabled. The relations between USIWM1..0 and the USI operation is summarized in

Table 60 on page 151.

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Table 60. Relations between USIWM1..0 and the USI Operation

USIWM1 USIWM0 Description

0

Outputs, clock hold, and start detector disabled. Port pins operates as

normal.

0

1

Three-wire mode. Uses DO, DI, and USCK pins.

The Data Output (DO) pin overrides the corresponding bit in the PORT

Register in this mode. However, the corresponding DDR bit still

controls the data direction. When the port pin is set as input the pins

pull-up is controlled by the PORT bit.

The Data Input (DI) and Serial Clock (USCK) pins do not affect the

normal port operation. When operating as master, clock pulses are

software generated by toggling the PORT Register, while the data

direction is set to output. The USITC bit in the USICR Register can be

used for this purpose.

1

0

Two-wire mode. Uses SDA (DI) and SCL (USCK) pins⁽¹⁾

.

The Serial Data (SDA) and the Serial Clock (SCL) pins are bi-

directional and uses open-collector output drives. The output drivers

are enabled by setting the corresponding bit for SDA and SCL in the

DDR Register.

When the output driver is enabled for the SDA pin, the output driver will

force the line SDA low if the output of the Shift Register or the

corresponding bit in the PORT Register is zero. Otherwise the SDA

line will not be driven (i.e., it is released). When the SCL pin output

driver is enabled the SCL line will be forced low if the corresponding bit

in the PORT Register is zero, or by the start detector. Otherwise the

SCL line will not be driven.

The SCL line is held low when a start detector detects a start condition

and the output is enabled. Clearing the start condition flag (USISIF)

releases the line. The SDA and SCL pin inputs is not affected by

enabling this mode. Pull-ups on the SDA and SCL port pin are

disabled in Two-wire mode.

1

Two-wire mode. Uses SDA and SCL pins.

Same operation as for the Two-wire mode described above, except

that the SCL line is also held low when a counter overflow occurs, and

is held low until the Timer Overflow Flag (USIOIF) is cleared.

Note:

1. The DI and USCK pins are renamed to Serial Data (SDA) and Serial Clock (SCL)

respectively to avoid confusion between the modes of operation.

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• Bit 3..2 – USICS1..0: Clock Source Select

These bits set the clock source for the Shift Register and counter. The data output latch

ensures that the output is changed at the opposite edge of the sampling of the data

input (DI/SDA) when using external clock source (USCK/SCL). When software strobe or

Timer0 overflow clock option is selected, the output latch is transparent and therefore

the output is changed immediately. Clearing the USICS1..0 bits enables software strobe

option. When using this option, writing a one to the USICLK bit clocks both the Shift

Register and the counter. For external clock source (USICS1 = 1), the USICLK bit is no

longer used as a strobe, but selects between external clocking and software clocking by

the USITC strobe bit.

Table 61 shows the relationship between the USICS1..0 and USICLK setting and clock

source used for the Shift Register and the 4-bit counter.

Table 61. Relations between the USICS1..0 and USICLK Setting

Shift Register Clock

USICS1 USICS0 USICLK Source

4-bit Counter Clock

Source

0

1

No Clock

Software clock strobe

(USICLK)

Software clock strobe

(USICLK)

0

1

0

1

0

X

0

1

Timer/Counter0 overflow

External, positive edge

External, negative edge

External, positive edge

Timer/Counter0 overflow

External, both edges

Software clock strobe

(USITC)

1

External, negative edge

Software clock strobe

(USITC)

• Bit 1 – USICLK: Clock Strobe

Writing a one to this bit location strobes the Shift Register to shift one step and the

counter to increment by one, provided that the USICS1..0 bits are set to zero and by

doing so the software clock strobe option is selected. The output will change immedi-

ately when the clock strobe is executed, i.e., in the same instruction cycle. The value

shifted into the Shift Register is sampled the previous instruction cycle. The bit will be

read as zero.

When an external clock source is selected (USICS1 = 1), the USICLK function is

changed from a clock strobe to a Clock Select Register. Setting the USICLK bit in this

case will select the USITC strobe bit as clock source for the 4-bit counter (see Table 61).

• Bit 0 – USITC: Toggle Clock Port Pin

Writing a one to this bit location toggles the USCK/SCL value either from 0 to 1, or from

1 to 0. The toggling is independent of the setting in the Data Direction Register, but if the

PORT value is to be shown on the pin the DDB7 must be set as output (to one). This

feature allows easy clock generation when implementing master devices. The bit will be

read as zero.

When an external clock source is selected (USICS1 = 1) and the USICLK bit is set to

one, writing to the USITC strobe bit will directly clock the 4-bit counter. This allows an

early detection of when the transfer is done when operating as a master device.

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Analog Comparator

The Analog Comparator compares the input values on the positive pin AIN0 and nega-

tive pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on

the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator’s

output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the

comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The

user can select Interrupt triggering on comparator output rise, fall or toggle. A block dia-

gram of the comparator and its surrounding logic is shown in Figure 66.

Figure 66. Analog Comparator Block Diagram

BANDGAP

REFERENCE

ACBG

Analog Comparator Control

and Status Register – ACSR

Bit

7

6

ACBG

R/W

0

5

ACO

R

4

ACI

R/W

0

3

ACIE

R/W

0

2

ACIC

R/W

0

1

ACIS1

R/W

0

ACIS0

R/W

0

ACD

R/W

0

ACSR

Read/Write

Initial Value

N/A

• Bit 7 – ACD: Analog Comparator Disable

When this bit is written logic one, the power to the Analog Comparator is switched off.

This bit can be set at any time to turn off the Analog Comparator. This will reduce power

consumption in Active and Idle mode. When changing the ACD bit, the Analog Compar-

ator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt

can occur when the bit is changed.

• Bit 6 – ACBG: Analog Comparator Bandgap Select

When this bit is set, a fixed bandgap reference voltage replaces the positive input to the

Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the

Analog Comparator. When the bandgap reference is used as input to the Analog Com-

parator, it will take a certain time for the voltage to stabilize. If not stibilized, the first

conversion may give a wrong value. See “Internal Voltage Reference” on page 41.

• Bit 5 – ACO: Analog Comparator Output

The output of the Analog Comparator is synchronized and then directly connected to

ACO. The synchronization introduces a delay of 1 - 2 clock cycles.

• Bit 4 – ACI: Analog Comparator Interrupt Flag

This bit is set by hardware when a comparator output event triggers the interrupt mode

defined by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if

the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hardware when execut-

ing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a

logic one to the flag.

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• Bit 3 – ACIE: Analog Comparator Interrupt Enable

When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Ana-

log Comparator interrupt is activated. When written logic zero, the interrupt is disabled.

• Bit 2 – ACIC: Analog Comparator Input Capture Enable

When written logic one, this bit enables the input capture function in Timer/Counter1 to

be triggered by the Analog Comparator. The comparator output is in this case directly

connected to the input capture front-end logic, making the comparator utilize the noise

canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When

written logic zero, no connection between the Analog Comparator and the input capture

function exists. To make the comparator trigger the Timer/Counter1 Input Capture inter-

rupt, the ICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set.

• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select

These bits determine which comparator events that trigger the Analog Comparator inter-

rupt. The different settings are shown in Table 62.

Table 62. ACIS1/ACIS0 Settings

ACIS1

ACIS0

Interrupt Mode

0

1

0

1

0

1

Comparator Interrupt on Output Toggle.

Reserved

Comparator Interrupt on Falling Output Edge.

Comparator Interrupt on Rising Output Edge.

When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be dis-

abled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt

can occur when the bits are changed.

Digital Input Disable Register

– DIDR

Bit

7

–

6

–

5

–

4

–

3

–

2

–

1

AIN1D

R/W

0

AIN0D

R/W

0

DIDR

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

R

0

• Bit 1, 0 – AIN1D, AIN0D: AIN1, AIN0 Digital Input Disable

When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled.

The corresponding PIN Register bit will always read as zero when this bit is set. When

an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not

needed, this bit should be written logic one to reduce power consumption in the digital

input buffer.

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ATtiny2313/V

debugWIRE On-chip

Debug System

Features

• Complete Program Flow Control

• Emulates All On-chip Functions, Both Digital and Analog, except RESET Pin

• Real-time Operation

• Symbolic Debugging Support (Both at C and Assembler Source Level, or for other HLLs)

• Unlimited Number of Program Break Points (Using Software Break Points)

• Non-intrusive Operation

• Electrical Characteristics Identical to Real Device

• Automatic Configuration System

• High-Speed Operation

• Programming of Non-volatile Memories

Overview

The debugWIRE On-chip debug system uses a One-wire, bi-directional interface to con-

trol the program flow, execute AVR instructions in the CPU and to program the different

non-volatile memories.

Physical Interface

When the debugWIRE Enable (DWEN) Fuse is programmed and Lock bits are unpro-

grammed, the debugWIRE system within the target device is activated. The RESET port

pin is configured as a wire-AND (open-drain) bi-directional I/O pin with pull-up enabled

and becomes the communication gateway between target and emulator.

Figure 67. The debugWIRE Setup

1.8 - 5.5V

VCC

dW

dW(RESET)

GND

Figure 67 shows the schematic of a target MCU, with debugWIRE enabled, and the

emulator connector. The system clock is not affected by debugWIRE and will always be

the clock source selected by the CKSEL Fuses.

When designing a system where debugWIRE will be used, the following observations

must be made for correct operation:

•

Pull-Up resistor on the dW/(RESET) line must be larger than 10k. However, the pull-

up resistor is optional.

•

Connecting the RESET pin directly to V_CCwill not work.

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•

Capacitors inserted on the RESET pin must be disconnected when using

debugWire.

All external reset sources must be disconnected.

Software Break Points

debugWIRE supports Program memory Break Points by the AVR Break instruction. Set-

ting a Break Point in AVR Studio^®will insert a BREAK instruction in the Program

memory. The instruction replaced by the BREAK instruction will be stored. When pro-

gram execution is continued, the stored instruction will be executed before continuing

from the Program memory. A break can be inserted manually by putting the BREAK

instruction in the program.

The Flash must be re-programmed each time a Break Point is changed. This is auto-

matically handled by AVR Studio through the debugWIRE interface. The use of Break

Points will therefore reduce the Flash Data retention. Devices used for debugging pur-

poses should not be shipped to end customers.

Limitations of

debugWIRE

The debugWIRE communication pin (dW) is physically located on the same pin as

External Reset (RESET). An External Reset source is therefore not supported when the

debugWIRE is enabled.

The debugWIRE system accurately emulates all I/O functions when running at full

speed, i.e., when the program in the CPU is running. When the CPU is stopped, care

must be taken while accessing some of the I/O Registers via the debugger (AVR Stu-

dio). See the debugWIRE documentation for detailed description of the limitations.

A programmed DWEN Fuse enables some parts of the clock system to be running in all

sleep modes. This will increase the power consumption while in sleep. Thus, the DWEN

Fuse should be disabled when debugWire is not used.

debugWIRE Related

The following section describes the registers used with the debugWire.

Register in I/O Memory

debugWire Data Register –

DWDR

Bit

7

6

5

4

3

2

1

0

DWDR[7:0]

DWDR

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The DWDR Register provides a communication channel from the running program in

the MCU to the debugger. This register is only accessible by the debugWIRE and can

therefore not be used as a general purpose register in the normal operations.

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ATtiny2313/V

Self-Programming

the Flash

The device provides a Self-Programming mechanism for downloading and uploading

program code by the MCU itself. The Self-Programming can use any available data

interface and associated protocol to read code and write (program) that code into the

Program memory.

The Program memory is updated in a page by page fashion. Before programming a

page with the data stored in the temporary page buffer, the page must be erased. The

temporary page buffer is filled one word at a time using SPM and the buffer can be filled

either before the Page Erase command or between a Page Erase and a Page Write

operation:

Alternative 1, fill the buffer before a Page Erase

•

Fill temporary page buffer

Perform a Page Erase

Perform a Page Write

Alternative 2, fill the buffer after Page Erase

•

Perform a Page Erase

Fill temporary page buffer

Perform a Page Write

If only a part of the page needs to be changed, the rest of the page must be stored (for

example in the temporary page buffer) before the erase, and then be re-written. When

using alternative 1, the Boot Loader provides an effective Read-Modify-Write feature

which allows the user software to first read the page, do the necessary changes, and

then write back the modified data. If alternative 2 is used, it is not possible to read the

old data while loading since the page is already erased. The temporary page buffer can

be accessed in a random sequence. It is essential that the page address used in both

the Page Erase and Page Write operation is addressing the same page.

Performing Page Erase by

SPM

To execute Page Erase, set up the address in the Z-pointer, write “00000011” to

SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in

R1 and R0 is ignored. The page address must be written to PCPAGE in the Z-register.

Other bits in the Z-pointer will be ignored during this operation.

•

The CPU is halted during the Page Erase operation.

Filling the Temporary Buffer

(Page Loading)

To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write

“00000001” to SPMCSR and execute SPM within four clock cycles after writing

SPMCSR. The content of PCWORD in the Z-register is used to address the data in the

temporary buffer. The temporary buffer will auto-erase after a Page Write operation or

by writing the CTPB bit in SPMCSR. It is also erased after a system reset. Note that it is

not possible to write more than one time to each address without erasing the temporary

buffer.

If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded

will be lost.

Performing a Page Write

To execute Page Write, set up the address in the Z-pointer, write “00000101” to

SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in

R1 and R0 is ignored. The page address must be written to PCPAGE. Other bits in the

Z-pointer must be written to zero during this operation.

•

The CPU is halted during the Page Write operation.

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Addressing the Flash

During Self-

Programming

The Z-pointer is used to address the SPM commands.

Bit

15

Z15

Z7

7

14

Z14

Z6

6

13

Z13

Z5

5

12

Z12

Z4

4

11

Z11

Z3

3

10

Z10

Z2

2

9

Z9

Z1

1

8

Z8

Z0

0

ZH (R31)

ZL (R30)

Since the Flash is organized in pages (see Table 69 on page 164), the Program Counter

can be treated as having two different sections. One section, consisting of the least sig-

nificant bits, is addressing the words within a page, while the most significant bits are

addressing the pages. This is shown in Figure 68. Note that the Page Erase and Page

Write operations are addressed independently. Therefore it is of major importance that

the software addresses the same page in both the Page Erase and Page Write

operation.

The LPM instruction uses the Z-pointer to store the address. Since this instruction

addresses the Flash byte-by-byte, also the LSB (bit Z0) of the Z-pointer is used.

Figure 68. Addressing the Flash During SPM⁽¹⁾

BIT 15

ZPCMSB

ZPAGEMSB

1

0

Z - REGISTER

PCMSB

PAGEMSB

PCWORD

PROGRAM

COUNTER

PCPAGE

PAGE ADDRESS

WITHIN THE FLASH

WORD ADDRESS

WITHIN A PAGE

PROGRAM MEMORY

PAGE

INSTRUCTION WORD

PCWORD[PAGEMSB:0]:

00

01

02

PAGEEND

Note:

1. The different variables used in Figure 68 are listed in Table 69 on page 164.

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ATtiny2313/V

Store Program Memory

The Store Program Memory Control and Status Register contains the control bits

Control and Status Register – needed to control the Program memory operations.

SPMCSR

Bit

7

–

6

–

5

–

4

CTPB

R/W

0

3

RFLB

R/W

0

2

PGWRT

R/W

0

1

PGERS

R/W

0

SELFPRGEN

SPMCSR

Read/Write

Initial Value

R

0

R

0

R

0

R/W

0

• Bits 7..5 – Res: Reserved Bits

These bits are reserved bits in the ATtiny2313 and always read as zero.

• Bit 4 – CTPB: Clear Temporary Page Buffer

If the CTPB bit is written while filling the temporary page buffer, the temporary page

buffer will be cleared and the data will be lost.

• Bit 3 – RFLB: Read Fuse and Lock Bits

An LPM instruction within three cycles after RFLB and SELFPRGEN are set in the

SPMCSR Register, will read either the Lock bits or the Fuse bits (depending on Z0 in

the Z-pointer) into the destination register. See “EEPROM Write Prevents Writing to

SPMCSR” on page 160 for details.

• Bit 2 – PGWRT: Page Write

If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction

within four clock cycles executes Page Write, with the data stored in the temporary

buffer. The page address is taken from the high part of the Z-pointer. The data in R1 and

R0 are ignored. The PGWRT bit will auto-clear upon completion of a Page Write, or if no

SPM instruction is executed within four clock cycles. The CPU is halted during the entire

Page Write operation.

• Bit 1 – PGERS: Page Erase

If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction

within four clock cycles executes Page Erase. The page address is taken from the high

part of the Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear

upon completion of a Page Erase, or if no SPM instruction is executed within four clock

cycles. The CPU is halted during the entire Page Write operation.

• Bit 0 – SELFPRGEN: Self Programming Enable

This bit enables the SPM instruction for the next four clock cycles. If written to one

together with either CTPB, RFLB, PGWRT, or PGERS, the following SPM instruction

will have a special meaning, see description above. If only SELFPRGEN is written, the

following SPM instruction will store the value in R1:R0 in the temporary page buffer

addressed by the Z-pointer. The LSB of the Z-pointer is ignored. The SELFPRGEN bit

will auto-clear upon completion of an SPM instruction, or if no SPM instruction is exe-

cuted within four clock cycles. During Page Erase and Page Write, the SELFPRGEN bit

remains high until the operation is completed.

Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the

lower five bits will have no effect.

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EEPROM Write Prevents

Writing to SPMCSR

Note that an EEPROM write operation will block all software programming to Flash.

Reading the Fuses and Lock bits from software will also be prevented during the

EEPROM write operation. It is recommended that the user checks the status bit (EEPE)

in the EECR Register and verifies that the bit is cleared before writing to the SPMCSR

Register.

Reading the Fuse and Lock

Bits from Software

It is possible to read both the Fuse and Lock bits from software. To read the Lock bits,

load the Z-pointer with 0x0001 and set the RFLB and SELFPRGEN bits in SPMCSR.

When an LPM instruction is executed within three CPU cycles after the RFLB and

SELFPRGEN bits are set in SPMCSR, the value of the Lock bits will be loaded in the

destination register. The RFLB and SELFPRGEN bits will auto-clear upon completion of

reading the Lock bits or if no LPM instruction is executed within three CPU cycles or no

SPM instruction is executed within four CPU cycles. When RFLB and SELFPRGEN are

cleared, LPM will work as described in the Instruction set Manual.

Bit

Rd

7

6

5

4

3

2

1

0

–

LB2

LB1

The algorithm for reading the Fuse Low byte is similar to the one described above for

reading the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and

set the RFLB and SELFPRGEN bits in SPMCSR. When an LPM instruction is executed

within three cycles after the RFLB and SELFPRGEN bits are set in the SPMCSR, the

value of the Fuse Low byte (FLB) will be loaded in the destination register as shown

below. Refer to Table 68 on page 164 for a detailed description and mapping of the

Fuse Low byte.

Bit

Rd

7

6

5

4

3

2

1

0

FLB7

FLB6

FLB5

FLB4

FLB3

FLB2

FLB1

FLB0

Similarly, when reading the Fuse High byte, load 0x0003 in the Z-pointer. When an LPM

instruction is executed within three cycles after the RFLB and SELFPRGEN bits are set

in the SPMCSR, the value of the Fuse High byte (FHB) will be loaded in the destination

register as shown below. Refer to Table 67 on page 163 for detailed description and

mapping of the Fuse High byte.

Bit

Rd

7

6

5

4

3

2

1

0

FHB7

FHB6

FHB5

FHB4

FHB3

FHB2

FHB1

FHB0

Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that

are unprogrammed, will be read as one.

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ATtiny2313/V

Preventing Flash Corruption

During periods of low V_CC, the Flash program can be corrupted because the supply volt-

age is too low for the CPU and the Flash to operate properly. These issues are the same

as for board level systems using the Flash, and the same design solutions should be

applied.

A Flash program corruption can be caused by two situations when the voltage is too low.

First, a regular write sequence to the Flash requires a minimum voltage to operate cor-

rectly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage

for executing instructions is too low.

Flash corruption can easily be avoided by following these design recommendations (one

is sufficient):

1. Keep the AVR RESET active (low) during periods of insufficient power supply

voltage. This can be done by enabling the internal Brown-out Detector (BOD) if

the operating voltage matches the detection level. If not, an external low V_CC

reset protection circuit can be used. If a reset occurs while a write operation is in

progress, the write operation will be completed provided that the power supply

voltage is sufficient.

2. Keep the AVR core in Power-down sleep mode during periods of low V_CC. This

will prevent the CPU from attempting to decode and execute instructions, effec-

tively protecting the SPMCSR Register and thus the Flash from unintentional

writes.

Programming Time for Flash

when Using SPM

The calibrated RC Oscillator is used to time Flash accesses. Table 63 shows the typical

programming time for Flash accesses from the CPU.

Table 63. SPM Programming Time

Symbol

Min Programming Time Max Programming Time

3.7 ms 4.5 ms

Flash write (Page Erase, Page Write,

and write Lock bits by SPM)

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Memory

Programming

Program And Data

Memory Lock Bits

The ATtiny2313 provides two Lock bits which can be left unprogrammed (“1”) or can be

programmed (“0”) to obtain the additional features listed in Table 65. The Lock bits can

only be erased to “1” with the Chip Erase command.

Table 64. Lock Bit Byte⁽¹⁾

Lock Bit Byte

Bit No

Description

Default Value

7

6

5

4

3

2

1

0

–

1 (unprogrammed)

–

LB2

LB1

Lock bit

Note:

1. “1” means unprogrammed, “0” means programmed

Table 65. Lock Bit Protection Modes⁽¹⁾⁽²⁾

Memory Lock Bits Protection Type

LB Mode

LB2

LB1

1

2

1

No memory lock features enabled.

Further programming of the Flash and EEPROM is

disabled in Parallel and Serial Programming mode. The

Fuse bits are locked in both Serial and Parallel

Programming mode.⁽¹⁾

1

0

Further programming and verification of the Flash and

EEPROM is disabled in Parallel and Serial Programming

mode. The Boot Lock bits and Fuse bits are locked in both

Serial and Parallel Programming mode.⁽¹⁾

3

Notes: 1. Program the Fuse bits and Boot Lock bits before programming the LB1 and LB2.

2. “1” means unprogrammed, “0” means programmed

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ATtiny2313/V

Fuse Bits

The ATtiny2313 has three Fuse bytes. Table 67 and Table 68 describe briefly the func-

tionality of all the fuses and how they are mapped into the Fuse bytes. Note that the

fuses are read as logical zero, “0”, if they are programmed.

Table 66. Fuse Extended Byte

Fuse Extended

Byte

Bit

No

Description

Default Value

7

6

5

4

3

2

1

0

–

1 (unprogrammed)

–

SELFPRGEN

Self Programming Enable

Table 67. Fuse High Byte

Bit

Fuse High Byte

No

Description

Default Value

DWEN⁽³⁾

7

debugWIRE Enable

1 (unprogrammed)

EEPROM memory is preserved

through the Chip Erase

1 (unprogrammed, EEPROM

not preserved)

EESAVE

SPIEN⁽¹⁾

6

5

Enable Serial Program and Data

Downloading

0 (programmed, SPI prog.

enabled)

WDTON⁽²⁾

4

3

2

1

0

Watchdog Timer always on

Brown-out Detector trigger level

External Reset disable

1 (unprogrammed)

BODLEVEL2⁽⁴⁾

BODLEVEL1⁽⁴⁾

BODLEVEL0⁽⁴⁾

RSTDISBL⁽⁵⁾

Note:

1. The SPIEN Fuse is not accessible in serial programming mode.

2. See “Watchdog Timer Control Register - WDTCSR” on page 45 for details.

3. Never ship a product with the DWEN Fuse programmed regardless of the setting of

Lock bits. A programmed DWEN Fuse enables some parts of the clock system to be

running in all sleep modes. This may increase the power consumption.

4. See Table 16 on page 38 for BODLEVEL Fuse decoding.

5. See “Alternate Functions of Port A” on page 56 for description of RSTDISBL Fuse.

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Table 68. Fuse Low Byte

Fuse Low Byte

CKDIV8

CKOUT

Bit No

Description

Default Value

7

6

5

4

3

2

1

0

Divide clock by 8

0 (programmed)

Output Clock on CKOUT pin

Select start-up time

Select Clock source

1 (unprogrammed)

1 (unprogrammed)⁽¹⁾

0 (programmed)⁽¹⁾

0 (programmed)⁽²⁾

1 (unprogrammed)⁽²⁾

0 (programmed)⁽²⁾

SUT1

SUT0

CKSEL3

CKSEL2

CKSEL1

CKSEL0

Note:

1. The default value of SUT1..0 results in maximum start-up time for the default clock

source. See Table 15 on page 37 for details.

2. The default setting of CKSEL3..0 results in internal RC Oscillator @ 8 MHz.

The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are

locked if Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the

Lock bits.

Latching of Fuses

The fuse values are latched when the device enters programming mode and changes of

the fuse values will have no effect until the part leaves Programming mode. This does

not apply to the EESAVE Fuse which will take effect once it is programmed. The fuses

are also latched on Power-up in Normal mode.

Signature Bytes

All Atmel microcontrollers have a three-byte signature code which identifies the device.

This code can be read in both serial and parallel mode, also when the device is locked.

The three bytes reside in a separate address space.

For the ATtiny2313 the signature bytes are:

1. 0x000: 0x1E (indicates manufactured by Atmel).

2. 0x001: 0x91 (indicates 2KB Flash memory).

3. 0x002: 0x0A (indicates ATtiny2313 device when 0x001 is 0x91).

Calibration Byte

Page Size

The ATtiny2313 stores two different calibration values for the internal RC Oscillator.

These bytes resides in the high byte of address 0x0001 and 0x0000 in the signature

address space for 4 and 8 MHz respectively. During reset, the 8 MHz value is automati-

cally written to the “Oscillator Calibration Register – OSCCAL” on page 28, to ensure

correct frequency of the calibrated RC Oscillator.

Table 69. No. of Words in a Page and No. of Pages in the Flash

Flash Size

Page Size

PCWORD

No. of Pages

PCPAGE

PCMSB

1K words (2K bytes)

16 words

PC[3:0]

64

PC[9:4]

9

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Table 70. No. of Words in a Page and No. of Pages in the EEPROM

EEPROM Size

Page Size

PCWORD

No. of Pages

PCPAGE

EEAMSB

128 bytes

4 bytes

EEA[1:0]

32

EEA[6:2]

6

Parallel Programming

Parameters, Pin

Mapping, and

This section describes how to parallel program and verify Flash Program memory,

EEPROM Data memory, Memory Lock bits, and Fuse bits in the ATtiny2313. Pulses are

assumed to be at least 250 ns unless otherwise noted.

Commands

Signal Names

In this section, some pins of the ATtiny2313 are referenced by signal names describing

their functionality during parallel programming, see Figure 69 and Table 71. Pins not

described in the following table are referenced by pin names.

The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a posi-

tive pulse. The bit coding is shown in Table 73.

When pulsing WR or OE, the command loaded determines the action executed. The dif-

ferent Commands are shown in Table 74.

Figure 69. Parallel Programming

+5V

RDY/BSY

OE

PD1

PD2

PD3

PD4

PD5

PD6

VCC

WR

BS1/PAGEL

XA0

PB7 - PB0

DATA I/O

XA1/BS2

+12 V

RESET

XTAL1

GND

Table 71. Pin Name Mapping

Signal Name

in

Programming

Mode

Name

I/O

Function

0: Device is busy programming, 1: Device is ready for

new command.

RDY/BSY

PD1

O

OE

PD2

PD3

I

Output Enable (Active low).

Write Pulse (Active low).

WR

Byte Select 1 (“0” selects low byte, “1” selects high

byte).

BS1/PAGEL

PD4

I

Program Memory and EEPROM Data Page Load.

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Table 71. Pin Name Mapping (Continued)

Signal Name

in

Programming

Mode

Name

I/O

Function

XA0

PD5

PD6

I

XTAL Action Bit 0

XTAL Action Bit 1.

Byte Select 2 (“0” selects low byte, “1” selects 2’nd high

byte).

XA1/BS2

DATA I/O

I

PB7-0

I/O

Bi-directional Data bus (Output when OE is low).

Table 72. Pin Values Used to Enter Programming Mode

XA1

XA0

BS1

WR

Symbol

Value

Prog_enable[3]

Prog_enable[2]

Prog_enable[1]

Prog_enable[0]

0

Table 73. XA1 and XA0 Coding

XA1

XA0

Action when XTAL1 is Pulsed

0

Load Flash or EEPROM Address (High or low address byte

determined by BS1).

0

1

0

1

Load Data (High or Low data byte for Flash determined by BS1).

Load Command

No Action, Idle

Table 74. Command Byte Bit Coding

Command Byte

1000 0000

0100 0000

0010 0000

0001 0000

0001 0001

0000 1000

0000 0100

0000 0010

0000 0011

Command Executed

Chip Erase

Write Fuse bits

Write Lock bits

Write Flash

Write EEPROM

Read Signature Bytes and Calibration byte

Read Fuse and Lock bits

Read Flash

Read EEPROM

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ATtiny2313/V

Serial Programming Pin

Mapping

Table 75. Pin Mapping Serial Programming

Symbol

MOSI

MISO

SCK

Pins

PB5

PB6

PB7

I/O

Description

Serial Data in

Serial Data out

Serial Clock

I

O

I

Parallel Programming

Enter Programming Mode

The following algorithm puts the device in Parallel programming mode:

1. Set Prog_enable pins listed in Table 72 on page 166 to “0000”, RESET pin and

V

_CCto 0V.

2. Apply 4.5 - 5.5V between V_CCand GND.

3. Ensure that V_CCreaches at least 1.8V within the next 20 µs.

4. Wait 20 - 60 µs, and apply 11.5 - 12.5V to RESET.

5. Keep the Prog_enable pins unchanged for at least 10µs after the High-voltage

has been applied to ensure the Prog_enable Signature has been latched.

6. Wait at least 300 µs before giving any parallel programming commands.

7. Exit Programming mode by power the device down or by bringing RESET pin to

0V.

If the rise time of the V_CCis unable to fulfill the requirements listed above, the following

alternative algorithm can be used.

1. Set Prog_enable pins listed in Table 72 on page 166 to “0000”, RESET pin to 0V

and V_CCto 0V.

2. Apply 4.5 - 5.5V between V_CCand GND.

3. Monitor V_CC, and as soon as V_CCreaches 0.9 - 1.1V, apply 11.5 - 12.5V to

RESET.

4. Keep the Prog_enable pins unchanged for at least 10µs after the High-voltage

has been applied to ensure the Prog_enable Signature has been latched.

5. Wait until V_CCactually reaches 4.5 -5.5V before giving any parallel programming

commands.

6. Exit Programming mode by power the device down or by bringing RESET pin to

0V.

Considerations for Efficient

Programming

The loaded command and address are retained in the device during programming. For

efficient programming, the following should be considered.

•

The command needs only be loaded once when writing or reading multiple memory

locations.

Skip writing the data value 0xFF, that is the contents of the entire EEPROM (unless

the EESAVE Fuse is programmed) and Flash after a Chip Erase.

Address high byte needs only be loaded before programming or reading a new 256

word window in Flash or 256 byte EEPROM. This consideration also applies to

Signature bytes reading.

Chip Erase

The Chip Erase will erase the Flash and EEPROM⁽¹⁾memories plus Lock bits. The Lock

bits are not reset until the program memory has been completely erased. The Fuse bits

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are not changed. A Chip Erase must be performed before the Flash and/or EEPROM

are reprogrammed.

Note:

1. The EEPRPOM memory is preserved during Chip Erase if the EESAVE Fuse is

programmed.

Load Command “Chip Erase”

1. Set XA1, XA0 to “10”. This enables command loading.

2. Set BS1 to “0”.

3. Set DATA to “1000 0000”. This is the command for Chip Erase.

4. Give XTAL1 a positive pulse. This loads the command.

5. Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low.

6. Wait until RDY/BSY goes high before loading a new command.

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ATtiny2313/V

Programming the Flash

The Flash is organized in pages, see Table 69 on page 164. When programming the

Flash, the program data is latched into a page buffer. This allows one page of program

data to be programmed simultaneously. The following procedure describes how to pro-

gram the entire Flash memory:

A. Load Command “Write Flash”

1. Set XA1, XA0 to “10”. This enables command loading.

2. Set BS1 to “0”.

3. Set DATA to “0001 0000”. This is the command for Write Flash.

4. Give XTAL1 a positive pulse. This loads the command.

B. Load Address Low byte

1. Set XA1, XA0 to “00”. This enables address loading.

2. Set BS1 to “0”. This selects low address.

3. Set DATA = Address low byte (0x00 - 0xFF).

4. Give XTAL1 a positive pulse. This loads the address low byte.

C. Load Data Low Byte

1. Set XA1, XA0 to “01”. This enables data loading.

2. Set DATA = Data low byte (0x00 - 0xFF).

3. Give XTAL1 a positive pulse. This loads the data byte.

D. Load Data High Byte

1. Set BS1 to “1”. This selects high data byte.

2. Set XA1, XA0 to “01”. This enables data loading.

3. Set DATA = Data high byte (0x00 - 0xFF).

4. Give XTAL1 a positive pulse. This loads the data byte.

E. Repeat B through E until the entire buffer is filled or until all data within the page is

loaded.

While the lower bits in the address are mapped to words within the page, the higher bits

address the pages within the FLASH. This is illustrated in Figure 70 on page 170. Note

that if less than eight bits are required to address words in the page (pagesize < 256),

the most significant bit(s) in the address low byte are used to address the page when

performing a Page Write.

F. Load Address High byte

1. Set XA1, XA0 to “00”. This enables address loading.

2. Set BS1 to “1”. This selects high address.

3. Set DATA = Address high byte (0x00 - 0xFF).

4. Give XTAL1 a positive pulse. This loads the address high byte.

G. Program Page

1. Give WR a negative pulse. This starts programming of the entire page of data.

RDY/BSY goes low.

2. Wait until RDY/BSY goes high (See Figure 71 for signal waveforms).

H. Repeat B through H until the entire Flash is programmed or until all data has been

programmed.

I. End Page Programming

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1. 1. Set XA1, XA0 to “10”. This enables command loading.

2. Set DATA to “0000 0000”. This is the command for No Operation.

3. Give XTAL1 a positive pulse. This loads the command, and the internal write sig-

nals are reset.

Figure 70. Addressing the Flash Which is Organized in Pages⁽¹⁾

PCMSB

PAGEMSB

PCWORD

PROGRAM

COUNTER

PCPAGE

PAGE ADDRESS

WITHIN THE FLASH

WORD ADDRESS

WITHIN A PAGE

PROGRAM MEMORY

PAGE

INSTRUCTION WORD

PCWORD[PAGEMSB:0]:

00

01

02

PAGEEND

Note:

1. PCPAGE and PCWORD are listed in Table 69 on page 164.

Figure 71. Programming the Flash Waveforms⁽¹⁾

F

A

B

C

D

E

B

C

D

E

G

H

0x10

ADDR. LOW

DATA LOW

DATA HIGH

ADDR. LOW DATA LOW

DATA HIGH

ADDR. HIGH

XX

DATA

XA1

XA0

BS1

XTAL1

WR

RDY/BSY

RESET +12V

OE

PAGEL

BS2

Note:

1. “XX” is don’t care. The letters refer to the programming description above.

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ATtiny2313/V

Programming the EEPROM

The EEPROM is organized in pages, see Table 70 on page 165. When programming

the EEPROM, the program data is latched into a page buffer. This allows one page of

data to be programmed simultaneously. The programming algorithm for the EEPROM

data memory is as follows (refer to “Programming the Flash” on page 169 for details on

Command, Address and Data loading):

1. A: Load Command “0001 0001”.

2. G: Load Address High Byte (0x00 - 0xFF).

3. B: Load Address Low Byte (0x00 - 0xFF).

4. C: Load Data (0x00 - 0xFF).

J: Repeat 3 through 4 until the entire buffer is filled.

K: Program EEPROM page

1. Set BS to “0”.

2. Give WR a negative pulse. This starts programming of the EEPROM page.

RDY/BSY goes low.

3. Wait until to RDY/BSY goes high before programming the next page (See Figure

72 for signal waveforms).

Figure 72. Programming the EEPROM Waveforms

K

A

G

B

C

E

B

C

E

L

0x11

ADDR. HIGH

ADDR. LOW

DATA

ADDR. LOW

DATA

XX

DATA

XA1

XA0

BS1

XTAL1

WR

RDY/BSY

RESET +12V

OE

PAGEL

BS2

Reading the Flash

The algorithm for reading the Flash memory is as follows (refer to “Programming the

Flash” on page 169 for details on Command and Address loading):

1. A: Load Command “0000 0010”.

2. G: Load Address High Byte (0x00 - 0xFF).

3. B: Load Address Low Byte (0x00 - 0xFF).

4. Set OE to “0”, and BS1 to “0”. The Flash word low byte can now be read at DATA.

5. Set BS to “1”. The Flash word high byte can now be read at DATA.

6. Set OE to “1”.

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Reading the EEPROM

The algorithm for reading the EEPROM memory is as follows (refer to “Programming the

Flash” on page 169 for details on Command and Address loading):

1. A: Load Command “0000 0011”.

2. G: Load Address High Byte (0x00 - 0xFF).

3. B: Load Address Low Byte (0x00 - 0xFF).

4. Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at

DATA.

5. Set OE to “1”.

Programming the Fuse Low

Bits

The algorithm for programming the Fuse Low bits is as follows (refer to “Programming

the Flash” on page 169 for details on Command and Data loading):

1. A: Load Command “0100 0000”.

2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

3. Give WR a negative pulse and wait for RDY/BSY to go high.

Programming the Fuse High

Bits

The algorithm for programming the Fuse High bits is as follows (refer to “Programming

the Flash” on page 169 for details on Command and Data loading):

1. A: Load Command “0100 0000”.

2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

3. Set BS1 to “1” and BS2 to “0”. This selects high data byte.

4. Give WR a negative pulse and wait for RDY/BSY to go high.

5. Set BS1 to “0”. This selects low data byte.

Programming the Extended

Fuse Bits

The algorithm for programming the Extended Fuse bits is as follows (refer to “Program-

ming the Flash” on page 169 for details on Command and Data loading):

1. 1. A: Load Command “0100 0000”.

2. 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse

bit.

3. 3. Set BS1 to “0” and BS2 to “1”. This selects extended data byte.

4. 4. Give WR a negative pulse and wait for RDY/BSY to go high.

5. 5. Set BS2 to “0”. This selects low data byte.

Figure 73. Programming the FUSES Waveforms

Write Fuse Low byte

Write Fuse high byte

Write Extended Fuse byte

A

C

A

C

A

C

0x40

DATA

XX

0x40

DATA

XX

0x40

DATA

XX

DATA

XA1

XA0

BS1

BS2

XTAL1

WR

RDY/BSY

RESET +12V

OE

PAGEL

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ATtiny2313/V

Programming the Lock Bits

The algorithm for programming the Lock bits is as follows (refer to “Programming the

Flash” on page 169 for details on Command and Data loading):

1. A: Load Command “0010 0000”.

2. C: Load Data Low Byte. Bit n = “0” programs the Lock bit. If LB mode 3 is pro-

grammed (LB1 and LB2 is programmed), it is not possible to program the Boot

Lock bits by any External Programming mode.

3. Give WR a negative pulse and wait for RDY/BSY to go high.

The Lock bits can only be cleared by executing Chip Erase.

Reading the Fuse and Lock

Bits

The algorithm for reading the Fuse and Lock bits is as follows (refer to “Programming

the Flash” on page 169 for details on Command loading):

1. A: Load Command “0000 0100”.

2. Set OE to “0”, BS2 to “0” and BS1 to “0”. The status of the Fuse Low bits can

now be read at DATA (“0” means programmed).

3. Set OE to “0”, BS2 to “1” and BS1 to “1”. The status of the Fuse High bits can

now be read at DATA (“0” means programmed).

4. Set OE to “0”, BS2 to “1”, and BS1 to “0”. The status of the Extended Fuse bits

can now be read at DATA (“0” means programmed).

5. Set OE to “0”, BS2 to “0” and BS1 to “1”. The status of the Lock bits can now be

read at DATA (“0” means programmed).

6. Set OE to “1”.

Figure 74. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read

0

Fuse Low Byte

Extended Fuse Byte

Lock Bits

0

1

0

DATA

BS2

BS1

Fuse High Byte

1

BS2

Reading the Signature Bytes

The algorithm for reading the Signature bytes is as follows (refer to “Programming the

Flash” on page 169 for details on Command and Address loading):

1. A: Load Command “0000 1000”.

2. B: Load Address Low Byte (0x00 - 0x02).

3. Set OE to “0”, and BS to “0”. The selected Signature byte can now be read at

DATA.

4. Set OE to “1”.

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Reading the Calibration Byte

The algorithm for reading the Calibration byte is as follows (refer to “Programming the

Flash” on page 169 for details on Command and Address loading):

1. A: Load Command “0000 1000”.

2. B: Load Address Low Byte, 0x00.

3. Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA.

4. Set OE to “1”.

Parallel Programming

Characteristics

Figure 75. Parallel Programming Timing, Including some General Timing

Requirements

t_XLWL

t_XHXL

XTAL1

t_DVXH

t_XLDX

Data & Contol

(DATA, XA0/1, BS1, BS2)

t_BVPH

t_PLBXt_BVWL

t_WLBX

PAGEL

t_PHPL

t_WLWH

WR

t_PLWL

WLRL

RDY/BSY

t_WLRH

Figure 76. Parallel Programming Timing, Loading Sequence with Timing

Requirements⁽¹⁾

LOAD DATA

LOAD ADDRESS

(LOW BYTE)

LOAD DATA

(LOW BYTE)

LOAD DATA

(HIGH BYTE)

LOAD ADDRESS

(LOW BYTE)

t_XLPH

t_XLXH

t_PLXH

XTAL1

BS1

PAGEL

DATA

ADDR0 (Low Byte)

DATA (Low Byte)

DATA (High Byte)

ADDR1 (Low Byte)

XA0

XA1

Note:

1. The timing requirements shown in Figure 75 (i.e., t_DVXH, t_XHXL, and t_XLDX) also apply

to loading operation.

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ATtiny2313/V

Figure 77. Parallel Programming Timing, Reading Sequence (within the Same Page)

with Timing Requirements⁽¹⁾

LOAD ADDRESS

(LOW BYTE)

READ DATA

(LOW BYTE)

READ DATA

(HIGH BYTE)

LOAD ADDRESS

(LOW BYTE)

t_XLOL

XTAL1

BS1

t_BVDV

t_OLDV

OE

t_OHDZ

ADDR1 (Low Byte)

DATA (High Byte)

DATA

ADDR0 (Low Byte)

DATA (Low Byte)

XA0

XA1

Note:

1. The timing requirements shown in Figure 75 (i.e., t_DVXH, t_XHXL, and t_XLDX) also apply

to reading operation.

Table 76. Parallel Programming Characteristics, V_CC= 5V ± 10%

Symbol

V_PP

Parameter

Min

Typ

Max

12.5

250

Units

V

Programming Enable Voltage

Programming Enable Current

Data and Control Valid before XTAL1 High

XTAL1 Low to XTAL1 High

XTAL1 Pulse Width High

11.5

I_PP

µA

ns

µs

ms

ns

t_DVXH

t_XLXH

t_XHXL

t_XLDX

t_XLWL

t_XLPH

t_PLXH

t_BVPH

t_PHPL

t_PLBX

t_WLBX

t_PLWL

t_BVWL

t_WLWH

t_WLRL

t_WLRH

t_{WLRH_CE}

t_XLOL

67

200

150

67

0

Data and Control Hold after XTAL1 Low

XTAL1 Low to WR Low

XTAL1 Low to PAGEL high

PAGEL low to XTAL1 high

BS1 Valid before PAGEL High

PAGEL Pulse Width High

BS1 Hold after PAGEL Low

BS2/1 Hold after WR Low

PAGEL Low to WR Low

0

150

67

150

67

150

0

BS1 Valid to WR Low

WR Pulse Width Low

WR Low to RDY/BSY Low

WR Low to RDY/BSY High⁽¹⁾

WR Low to RDY/BSY High for Chip Erase⁽²⁾

XTAL1 Low to OE Low

1

4.5

9

3.7

7.5

0

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Table 76. Parallel Programming Characteristics, V_CC= 5V ± 10% (Continued)

Symbol

t_BVDV

Parameter

Min

Typ

Max

250

Units

ns

BS1 Valid to DATA valid

OE Low to DATA Valid

OE High to DATA Tri-stated

0

t_OLDV

ns

t_OHDZ

ns

Notes: 1. t_WLRHis valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock

bits commands.

2. t_{WLRH_CE}is valid for the Chip Erase command.

Serial Downloading

Both the Flash and EEPROM memory arrays can be programmed using the serial SPI

bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI

(input) and MISO (output). After RESET is set low, the Programming Enable instruction

needs to be executed first before program/erase operations can be executed. NOTE, in

Table 75 on page 167, the pin mapping for SPI programming is listed. Not all parts use

the SPI pins dedicated for the internal SPI interface.

Figure 78. Serial Programming and Verify⁽¹⁾

+1.8 - 5.5V

VCC

MOSI

MISO

SCK

XTAL1

RESET

GND

Notes: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock

source to the XTAL1 pin.

2. V_CC- 0.3V < AVCC < V_CC+ 0.3V, however, AVCC should always be within 1.8 - 5.5V

When programming the EEPROM, an auto-erase cycle is built into the self-timed pro-

gramming operation (in the Serial mode ONLY) and there is no need to first execute the

Chip Erase instruction. The Chip Erase operation turns the content of every memory

location in both the Program and EEPROM arrays into 0xFF.

Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high

periods for the serial clock (SCK) input are defined as follows:

Low:> 2 CPU clock cycles for f_ck< 12 MHz, 3 CPU clock cycles for f_ck>= 12 MHz

High:> 2 CPU clock cycles for f_ck< 12 MHz, 3 CPU clock cycles for f_ck>= 12 MHz

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ATtiny2313/V

Serial Programming

Algorithm

When writing serial data to the ATtiny2313, data is clocked on the rising edge of SCK.

When reading data from the ATtiny2313, data is clocked on the falling edge of SCK. See

Figure 79, Figure 80 and Table 79 for timing details.

To program and verify the ATtiny2313 in the serial programming mode, the following

sequence is recommended (See four byte instruction formats in Table 78 on page 178):

1. Power-up sequence:

Apply power between V_CCand GND while RESET and SCK are set to “0”. In

some systems, the programmer can not guarantee that SCK is held low during

power-up. In this case, RESET must be given a positive pulse of at least two

CPU clock cycles duration after SCK has been set to “0”.

2. Wait for at least 20 ms and enable serial programming by sending the Program-

ming Enable serial instruction to pin MOSI.

3. The serial programming instructions will not work if the communication is out of

synchronization. When in sync. the second byte (0x53), will echo back when

issuing the third byte of the Programming Enable instruction. Whether the echo

is correct or not, all four bytes of the instruction must be transmitted. If the 0x53

did not echo back, give RESET a positive pulse and issue a new Programming

Enable command.

4. The Flash is programmed one page at a time. The memory page is loaded one

byte at a time by supplying the 4 LSB of the address and data together with the

Load Program Memory Page instruction. To ensure correct loading of the page,

the data low byte must be loaded before data high byte is applied for a given

address. The Program Memory Page is stored by loading the Write Program

Memory Page instruction with the 6 MSB of the address. If polling (RDY/BSY) is

not used, the user must wait at least t_{WD_FLASH}before issuing the next page. (See

Table 77 on page 178.) Accessing the serial programming interface before the

Flash write operation completes can result in incorrect programming.

5. A: The EEPROM array is programmed one byte at a time by supplying the

address and data together with the appropriate Write instruction. An EEPROM

memory location is first automatically erased before new data is written. If polling

(RDY/BSY) is not used, the user must wait at least t_{WD_EEPROM}before issuing the

next byte. (See Table 77 on page 178.) In a chip erased device, no 0xFFs in the

data file(s) need to be programmed.

B: The EEPROM array is programmed one page at a time. The Memory page is

loaded one byte at a time by supplying the 2 LSB of the address and data

together with the Load EEPROM Memory Page instruction. The EEPROM Mem-

ory Page is stored by loading the Write EEPROM Memory Page Instruction with

the 5 MSB of the address. When using EEPROM page access only byte loca-

tions loaded with the Load EEPROM Memory Page instruction is altered. The

remaining locations remain unchanged. If polling (RDY/BSY) is not used, the used

must wait at least t_{WD_EEPROM}before issuing the next page (See Table 77 on

page 178). In a chip erased device, no 0xFF in the data file(s) need to be

programmed.

6. Any memory location can be verified by using the Read instruction which returns

the content at the selected address at serial output MISO.

7. At the end of the programming session, RESET can be set high to commence

normal operation.

8. Power-off sequence (if needed):

Set RESET to “1”.

Turn V_CCpower off.

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Table 77. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location

Symbol

Minimum Wait Delay

4.5 ms

t_{WD_FLASH}

t_{WD_EEPROM}

t_{WD_ERASE}

t_{WD_FUSE}

4.0 ms

4.5 ms

Figure 79. Serial Programming Waveforms

SERIAL DATA INPUT

MSB

LSB

(MOSI)

SERIAL DATA OUTPUT

MSB

(MISO)

SERIAL CLOCK INPUT

(SCK)

SAMPLE

Table 78. Serial Programming Instruction Set

Instruction Format

Byte 2 Byte 3

Instruction

Byte 1

Byte4

Operation

Programming Enable

1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable Serial Programming after

RESET goes low.

Chip Erase

1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase EEPROM and Flash.

Read Program Memory

0010 H000 0000 00aa bbbb bbbb oooo oooo Read H (high or low) data o from

Program memory at word address a:b.

Load Program Memory Page

0100 H000 000x xxxx xxxx bbbb iiii iiii Write H (high or low) data i to Program

Memory page at word address b. Data

low byte must be loaded before Data

high byte is applied within the same

address.

Write Program Memory Page 0100 1100 0000 00aa bbbb xxxx xxxx xxxx Write Program Memory Page at

address a:b.

Read EEPROM Memory

1010 0000 000x xxxx xbbb bbbb oooo oooo Read data o from EEPROM memory at

address b.

Write EEPROM Memory

1100 0000 000x xxxx xbbb bbbb iiii iiii Write data i to EEPROM memory at

address b.

Load EEPROM Memory

Page (page access)

1100 0001 0000 0000 0000 00bb iiii iiii Load data i to EEPROM memory page

buffer. After data is loaded, program

EEPROM page.

Write EEPROM Memory

Page (page access)

1100 0010 00xx xxxx xbbb bb00 xxxx xxxx

Write EEPROM page at address b.

178

ATtiny2313/V

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ATtiny2313/V

Table 78. Serial Programming Instruction Set

Instruction Format

Byte 2 Byte 3

Instruction

Byte 1

Byte4

Operation

Read Lock bits

0101 1000 0000 0000 xxxx xxxx xxoo oooo Read Lock bits. “0” = programmed, “1”

= unprogrammed. See Table 64 on

page 162 for details.

Write Lock bits

1010 1100 111x xxxx xxxx xxxx 11ii iiii Write Lock bits. Set bits = “0” to

program Lock bits. See Table 64 on

page 162 for details.

Read Signature Byte

Write Fuse bits

0011 0000 000x xxxx xxxx xxbb oooo oooo Read Signature Byte o at address b.

1010 1100 1010 0000 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to

unprogram.

Write Fuse High bits

Write Extended Fuse Bits

Read Fuse bits

1010 1100 1010 1000 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to

unprogram.

1010 1100 1010 0100 xxxx xxxx xxxx xxxi Set bits = “0” to program, “1” to

unprogram.

0101 0000 0000 0000 xxxx xxxx oooo oooo Read Fuse bits. “0” = programmed, “1”

= unprogrammed.

Read Fuse High bits

Read Extended Fuse Bits

0101 1000 0000 1000 xxxx xxxx oooo oooo Read Fuse High bits. “0” = pro-

grammed, “1” = unprogrammed.

0101 0000 0000 1000 xxxx xxxx oooo oooo Read Extended Fuse bits. “0” = pro-

grammed, “1” = unprogrammed.

Read Calibration Byte

Poll RDY/BSY

0011 1000 000x xxxx 0000 000b oooo oooo Read Calibration Byte at address b.

1111 0000 0000 0000 xxxx xxxx xxxx xxxo If o = “1”, a programming operation is

still busy. Wait until this bit returns to

“0” before applying another command.

Note:

a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care

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Serial Programming

Characteristics

Figure 80. Serial Programming Timing

MOSI

t_OVSH

t_SLSH

t_SHOX

SCK

t_SHSL

MISO

t_SLIV

Table 79. Serial Programming Characteristics, T_A= -40°C to 85°C, V_CC= 2.7V - 5.5V

(Unless Otherwise Noted)

Symbol Parameter

1/t_CLCLOscillator Frequency (ATtiny2313L)

t_CLCL

Min

0

Typ

Max Units

10

20

MHz

ns

Oscillator Period (ATtiny2313L)

125

Oscillator Frequency (ATtiny2313, V_CC= 4.5V -

5.5V)

1/t_CLCL

0

MHz

Oscillator Period (ATtiny2313, V_CC= 4.5V -

5.5V)

t_CLCL

t_SHSL

t_SLSH

t_OVSH

t_SHOX

t_SLIV

67

ns

SCK Pulse Width High

SCK Pulse Width Low

MOSI Setup to SCK High

MOSI Hold after SCK High

SCK Low to MISO Valid

2 t_CLCL*

2 t_CLCL

*

t_CLCL

2 t_CLCL

TBD

TBD TBD

Note:

1. 2 t_CLCLfor f_ck< 12 MHz, 3 t_CLCLfor f_ck>= 12 MHz

180

ATtiny2313/V

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ATtiny2313/V

Electrical Characteristics

Absolute Maximum Ratings*

*NOTICE:

Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect

device reliability.

Operating Temperature.................................. -55°C to +125°C

Storage Temperature..................................... -65°C to +150°C

Voltage on any Pin except RESET

with respect to Ground ................................-0.5V to V_CC+0.5V

Voltage on RESET with respect to Ground......-0.5V to +13.0V

Maximum Operating Voltage ............................................ 6.0V

DC Current per I/O Pin ............................................... 40.0 mA

DC Current V_CCand GND Pins................................ 200.0 mA

DC Characteristics

T_A= -40°C to 85°C, V_CC= 1.8V to 5.5V (unless otherwise noted)⁽¹⁾

Symbol

Parameter

Condition

Min.

Typ.

Max.

Units

V_CC= 1.8V - 2.4V

V_CC= 2.4V - 5.5V

0.2V_CC

0.3V_CC

Input Low Voltage except

XTAL1 and RESET pin

V_IL

-0.5

V

(3)

V_CC= 1.8V - 2.4V

V_CC= 2.4V - 5.5V

0.7V_CC

0.6V_CC

Input High-voltage except

XTAL1 and RESET pins

V_IH

V_CC+0.5

0.1V_CC

V

Input Low Voltage

XTAL1 pin

V_IL1

V_CC= 1.8V - 5.5V

-0.5

(3)

V_CC= 1.8V - 2.4V

V_CC= 2.4V - 5.5V

0.8V_CC

0.7V_CC

Input High-voltage

XTAL1 pin

V_IH1

V_IL2

V_IH2

V_IL3

V_CC+0.5

0.2V_CC

V

Input Low Voltage

RESET pin

V_CC= 1.8V - 5.5V

-0.5

0.9V_CC

-0.5

Input High-voltage

RESET pin

(3)

V_CC= 1.8V - 5.5V

V_CC+0.5

V_CC= 1.8V - 2.4V

V_CC= 2.4V - 5.5V

0.2V_CC

0.3V_CC

Input Low Voltage

RESET pin as I/O

(3)

V_CC= 1.8V - 2.4V

V_CC= 2.4V - 5.5V

0.7V_CC

0.6V_CC

Input High-voltage

RESET pin as I/O

V_IH3

V_OL

V_OH

I_IL

V_CC+0.5

V

Output Low Voltage⁽⁴⁾

(Port A, Port B, Port D)

I

_OL= 20 mA, V_CC= 5V

0.7

0.5

V

I_OL= 10 mA, V_CC= 3V

Output High-voltage⁽⁵⁾

(Port A, Port B, Port D)

I

_OH= -20 mA, V_CC= 5V

4.2

2.5

V

I_OH= -10 mA, V_CC= 3V

Input Leakage

Current I/O Pin

V_CC= 5.5V, pin low

(absolute value)

1

µA

Input Leakage

Current I/O Pin

V_CC= 5.5V, pin high

(absolute value)

I_IH

R_RST

R_pu

Reset Pull-up Resistor

I/O Pin Pull-up Resistor

30

20

60

50

kΩ

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T_A= -40°C to 85°C, V_CC= 1.8V to 5.5V (unless otherwise noted)⁽¹⁾(Continued)

Symbol

Parameter

Condition

Min.

Typ.

Max.

Units

mA

µA

Active 1MHz, V_CC= 2V

Active 4MHz, V_CC= 3V

Active 8MHz, V_CC= 5V

Idle 1MHz, V_CC= 2V

Idle 4MHz, V_CC= 3V

Idle 8MHz, V_CC= 5V

WDT enabled, V_CC= 3V

WDT disabled, V_CC= 3V

0.35

2

6

Power Supply Current

0.08

0.41

1.6

0.2

1

I_CC

3

< 3

6

Power-down mode

< 0.5

2

µA

Analog Comparator

Input Offset Voltage

V_CC= 5V

V_in= V_CC/2

V_ACIO

I_ACLK

t_ACPD

<10

40

50

mV

nA

ns

Analog Comparator

Input Leakage Current

V_CC= 5V

V_in= V_CC/2

-50

Analog Comparator

Propagation Delay

V_CC= 2.7V

V_CC= 5.0V

750

500

Notes: 1. All DC Characteristics contained in this data sheet are based on simulation and characterization of other AVR microcontrol-

lers manufactured in the same process technology. These values are preliminary values representing design targets, and

will be updated after characterization of actual silicon.

2. “Max” means the highest value where the pin is guaranteed to be read as low.

3. “Min” means the lowest value where the pin is guaranteed to be read as high.

4. Although each I/O port can sink more than the test conditions (10 mA at V_CC= 5V, 5 mA at V_CC= 3V) under steady state

conditions (non-transient), the following must be observed:

1] The sum of all IOL, for all ports, should not exceed 60 mA.

If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater

than the listed test condition.

5. Although each I/O port can source more than the test conditions (10 mA at V_CC= 5V, 5 mA at V_CC= 3V) under steady state

conditions (non-transient), the following must be observed:

1] The sum of all IOH, for all ports, should not exceed 60 mA.

If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current

greater than the listed test condition.

182

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ATtiny2313/V

External Clock Drive

Waveforms

Figure 81. External Clock Drive Waveforms

V

IH1

V

IL1

External Clock Drive

Table 80. External Clock Drive (Estimated Values)

_CC= 1.8 - 5.5V V_CC= 2.7 - 5.5V V_CC= 4.5 - 5.5V

V

Symbol Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Units

Oscillator

0

4

0

10

0

20

MHz

1/t_CLCL

t_CLCL

Frequency

Clock Period

High Time

Low Time

Rise Time

Fall Time

250

100

40

50

20

ns

µs

t_CHCX

t_CLCX

t_CLCH

t_CHCL

40

2.0

1.6

0.5

Change in

period from one

clock cycle to

the next

2

%

∆t_CLCL

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Maximum Speed vs. V_CCMaximum frequency is dependent on V_CC.As shown in Figure 82 and Figure 83, the

Maximum Frequency vs. V_CCcurve is linear between 1.8V < V_CC< 2.7V and between

2.7V < V_CC< 4.5V.

Figure 82. Maximum Frequency vs. V_CC, ATtiny2313V

10 MHz

Safe Operating Area

4 MHz

1.8V

2.7V

5.5V

Figure 83. Maximum Frequency vs. V_CC, ATtiny2313

20 MHz

10 MHz

Safe Operating Area

2.7V

4.5V

5.5V

184

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ATtiny2313/V

ATtiny2313 Typical

Characteristics

The following charts show typical behavior. These figures are not tested during manu-

facturing. All current consumption measurements are performed with all I/O pins

configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-

to-rail output is used as clock source.

The power consumption in Power-down mode is independent of clock selection.

The current consumption is a function of several factors such as: operating voltage,

operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and

ambient temperature. The dominating factors are operating voltage and frequency.

The current drawn from capacitive loaded pins may be estimated (for one pin) as

C_L*V_CC*f where C_L= load capacitance, V_CC= operating voltage and f = average switch-

ing frequency of I/O pin.

The parts are characterized at frequencies higher than test limits. Parts are not guaran-

teed to function properly at frequencies higher than the ordering code indicates.

The difference between current consumption in Power-down mode with Watchdog

Timer enabled and Power-down mode with Watchdog Timer disabled represents the dif-

ferential current drawn by the Watchdog Timer.

Active Supply Current

Figure 84. Active Supply Current vs. Frequency (0.1 - 1.0 MHz)

ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY

0.1 - 1.0 MHz

1.2

5.5 V

1

5.0 V

0.8

4.5 V

4.0 V

0.6

3.3 V

0.4

2.7 V

1.8 V

0.2

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

185

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Figure 85. Active Supply Current vs. Frequency (1 - 20 MHz)

ACTIVE SUPPLY CURRENT vs. FREQUENCY

1 - 20 MHz

14

5.5 V

12

10

8

5.0 V

4.5 V

6

4.0 V

3.3 V

4

2.7 V

2

1.8 V

0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

Figure 86. Active Supply Current vs. V_CC(Internal RC Oscillator, 8 MHz)

ACTIVE SUPPLY CURRENT vs. V

CC

INTERNAL RC OSCILLATOR, 8 MHz

9

85 ˚C

25 ˚C

-40 ˚C

8

7

6

5

4

3

2

1

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V

_CC(V)

186

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ATtiny2313/V

Figure 87. Active Supply Current vs. V_CC(Internal RC Oscillator, 4 MHz)

ACTIVE SUPPLY CURRENT vs. V

cc

INTERNAL RC OSCILLATOR, 4 MHz

6

5

4

3

2

1

0

-40 °C

85 °C

25 °C

1.5

2

2.5

3

3.5

(V)

4

4.5

5

5.5

V

cc

Figure 88. Active Supply Current vs. V_CC(Internal RC Oscillator, 1 MHz)

ACTIVE SUPPLY CURRENT vs. V

cc

INTERNAL RC OSCILLATOR, 1 MHz

1.8

1.6

1.4

1.2

1

85 °C

25 °C

-40 °C

0.8

0.6

0.4

0.2

0

1.5

2

2.5

3

3.5

(V)

4

4.5

5

5.5

V

cc

187

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Figure 89. Active Supply Current vs. V_CC(Internal RC Oscillator, 0.5 MHz)

ACTIVE SUPPLY CURRENT vs. V

cc

INTERNAL RC OSCILLATOR, 0.5 MHz

1.2

1

85 °C

25 °C

-40 °C

0.8

0.6

0.4

0.2

0

1.5

2

2.5

3

3.5

(V)

4

4.5

5

5.5

V

cc

Figure 90. Active Supply Current vs. V_CC(Internal RC Oscillator, 128 KHz)

ACTIVE SUPPLY CURRENT vs. V

cc

INTERNAL RC OSCILLATOR, 128 KHz

0.14

0.12

0.1

-40 °C

25 °C

85 °C

0.08

0.06

0.04

0.02

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

6

V

cc

(V)

188

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ATtiny2313/V

Idle Supply Current

Figure 91. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz)

IDLE SUPPLY CURRENT vs. FREQUENCY

0.1 - 1.0 MHz

0.25

5.5 V

5.0 V

0.2

0.15

0.1

4.5 V

4.0 V

3.3 V

2.7 V

0.05

0

1.8 V

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

Figure 92. Idle Supply Current vs. Frequency (1 - 20 MHz)

IDLE SUPPLY CURRENT vs. FREQUENCY

1 - 20 MHz

5

4.5

4

5.5 V

5.0 V

3.5

3

4.5 V

2.5

2

1.5

1

4.0 V

3.3 V

2.7 V

0.5

0

1.8 V

0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

189

2543I–AVR–04/06

Figure 93. Idle Supply Current vs. V_CC(Internal RC Oscillator, 8 MHz)

IDLE SUPPLY CURRENT vs. V

cc

INTERNAL RC OSCILLATOR, 8 MHz

3

2.5

2

85 °C

25 °C

-40 °C

1.5

1

0.5

0

1.5

2

2.5

3

3.5

(V)

4

4.5

5

5.5

V

cc

Figure 94. Idle Supply Current vs. V_CC(Internal RC Oscillator, 4 MHz)

IDLE SUPPLY CURRENT vs. V

cc

INTERNAL RC OSCILLATOR, 4 MHz

1.6

1.4

1.2

1

85 °C

25 °C

-40 °C

0.8

0.6

0.4

0.2

0

1.5

2

2.5

3

3.5

(V)

4

4.5

5

5.5

V

cc

190

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ATtiny2313/V

Figure 95. Idle Supply Current vs. V_CC(Internal RC Oscillator, 1 MHz)

IDLE SUPPLY CURRENT vs. V

cc

INTERNAL RC OSCILLATOR, 1 MHz

0.5

0.4

0.3

0.2

0.1

0

85 °C

25 °C

-40 °C

1.5

2

2.5

3

3.5

(V)

4

4.5

5

5.5

V

cc

Figure 96. Idle Supply Current vs. V_CC(Internal RC Oscillator, 0.5 MHz)

IDLE SUPPLY CURRENT vs. V

cc

INTERNAL RC OSCILLATOR, 0.5 MHz

0.3

0.25

0.2

85 °C

25 °C

-40 °C

0.15

0.1

0.05

0

1.5

2

2.5

3

3.5

(V)

4

4.5

5

5.5

V

cc

191

2543I–AVR–04/06

Figure 97. Idle Supply Current vs. V_CC(Internal RC Oscillator, 128 KHz)

IDLE SUPPLY CURRENT vs. V

cc

INTERNAL RC OSCILLATOR, 128 KHz

0.035

0.03

0.025

0.02

0.015

0.01

0.005

0

-40 °C

25 °C

85 °C

1.5

2

2.5

3

3.5

(V)

4

4.5

5

5.5

V

cc

Power-down Supply Current

Figure 98. Power-down Supply Current vs. V_CC(Watchdog Timer Disabled)

POWER-DOWN SUPPLY CURRENT vs. V

cc

WATCHDOG TIMER DISABLED

1.5

1.25

1

85 °C

-40 °C

25 °C

0.75

0.5

0.25

0

1.5

2

2.5

3

3.5

(V)

4

4.5

5

5.5

V

cc

192

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ATtiny2313/V

Figure 99. Power-down Supply Current vs. V_CC(Watchdog Timer Enabled)

POWER-DOWN SUPPLY CURRENT vs. V

cc

WATCHDOG TIMER ENABLED

20

18

16

14

12

10

8

85 °C

25 °C

-40 °C

6

4

2

0

1.5

2

2.5

3

3.5

(V)

4

4.5

5

5.5

V

cc

Standby Supply Current

Figure 100. Standby Supply Current vs. V_CC

STANDBY SUPPLY CURRENT vs. V

cc

0.08

0.07

0.06

0.05

0.04

0.03

0.02

0.01

0

2MHz Res

2MHz Xtal

455KHz Res

1MHz Res

1.5

2

2.5

3

3.5

(V)

4

4.5

5

5.5

V

cc

193

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Pin Pull-up

Figure 101. I/O Pin Pull-up Resistor Current vs. Input Voltage (V_CC= 5V)

I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

Vcc = 5V

160

140

85 °C

25 °C

120

-40 °C

100

80

60

40

20

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

V_OP(V)

Figure 102. I/O Pin Pull-up Resistor Current vs. Input Voltage (V_CC= 2.7V)

I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

Vcc = 2.7V

80

25 °C

85 °C

70

-40 °C

60

50

40

30

20

10

0

0.5

1

1.5

2

2.5

3

V_OP(V)

194

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ATtiny2313/V

Figure 103. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V_CC= 5V)

RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE

Vcc = 5V

120

25 °C

-40 °C

100

85 °C

80

60

40

20

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

V_RESET(V)

Figure 104. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V_CC= 2.7V)

RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE

V

= 2.7V

cc

60

25 °C

85 °C

-40 °C

50

40

30

20

10

0

0.5

1

1.5

V_RESET(V)

2

2.5

3

195

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Pin Driver Strength

Figure 105. I/O Pin Source Current vs. Output Voltage (V_CC= 5V)

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE

Vcc = 5V

90

80

85 °C

70

-40 °C

60

25 °C

50

40

30

20

10

0

3

3.2

3.4

3.6

3.8

4

4.2

4.4

4.6

4.8

5

V_OH(V)

Figure 106. I/O Pin Source Current vs. Output Voltage (V_CC= 2.7V)

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE

Vcc = 2.7V

35

30

-40 °C

25 °C

25

85 °C

20

15

10

5

0

0.5

1

1.5

2

2.5

3

V_OH(V)

196

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ATtiny2313/V

Figure 107. I/O Pin Source Current vs. Output Voltage (V_CC= 1.8V)

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE

V

= 1.8V

cc

9

8

7

6

5

4

3

2

1

0

-40 °C

85 °C

25 °C

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

V_OH(V)

Figure 108. I/O Pin Sink Current vs. Output Voltage (V_CC= 5V)

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE

V

cc

= 5V

100

90

80

70

60

50

40

30

20

10

0

-40 °C

25 °C

85 °C

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

V_OL(V)

197

2543I–AVR–04/06

Figure 109. I/O Pin Sink Current vs. Output Voltage (V_CC= 2.7V)

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE

V

= 2.7V

cc

40

35

30

25

20

15

10

5

-40 °C

25 °C

85 °C

0

0.2

0.4

0.6

0.8

1

V_OL(V)

1.2

1.4

1.6

1.8

2

Figure 110. I/O Pin Sink Current vs. Output Voltage (V_CC= 1.8V)

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE

V

= 1.8V

cc

14

12

10

8

-40 °C

25 °C

85 °C

6

4

2

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

V_OL(V)

198

ATtiny2313/V

2543I–AVR–04/06

ATtiny2313/V

Figure 111. Reset I/O Pin Source Current vs. Output Voltage (V_CC= 5V)

RESET I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE

V

= 5V

cc

16

14

-40 °C

12

25 °C

10

8

85 °C

6

4

2

0

0.5

1

1.5

2

2.5

V_OH(V)

3

3.5

4

4.5

5

Figure 112. Reset I/O Pin Source Current vs. Output Voltage (V_CC= 2.7V)

RESET I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE

V

= 2.7V

cc

4.5

4

-40 °C

3.5

25 °C

3

2.5

2

85 °C

1.5

1

0.5

0

0.5

1

1.5

_OH(V)

2

2.5

3

V

199

2543I–AVR–04/06

Figure 113. Reset I/O Pin Source Current vs. Output Voltage (V_CC= 1.8V)

RESET I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE

V

= 1.8V

cc

1.4

-40 °C

1.2

25 °C

1

0.8

0.6

0.4

0.2

0

85 °C

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

V_OH(V)

Figure 114. Reset I/O Pin Sink Current vs. Output Voltage (V_CC= 5V)

RESET I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE

V

= 5V

cc

16

14

12

10

8

-40 °C

25 °C

85 °C

6

4

2

0

0.5

1

1.5

2

2.5

_OL(V)

3

3.5

4

4.5

5

V

200

ATtiny2313/V

2543I–AVR–04/06

ATtiny2313/V

Figure 115. Reset I/O Pin Sink Current vs. Output Voltage (V_CC= 2.7V)

RESET I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE

V

= 2.7V

cc

4.5

4

-40 °C

25 °C

85 °C

3.5

3

2.5

2

1.5

1

0.5

0

0.5

1

1.5

2

2.5

V_OL(V)

3

3.5

4

4.5

5

Figure 116. Reset I/O Pin Sink Current vs. Output Voltage (V_CC= 1.8V)

RESET I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE

V

= 1.8V

cc

1.4

1.2

1

-40 °C

25 °C

85 °C

0.8

0.6

0.4

0.2

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

V_OL(V)

201

2543I–AVR–04/06

Pin Thresholds and

Hysteresis

Figure 117. I/O Pin Input Threshold Voltage vs. V_CC(V_IH, I/O Pin Read as “1”)

I/O PIN INPUT THRESHOLD VOLTAGE vs. V

cc

VIH, IO PIN READ AS '1'

3

2.5

2

85 °C

-40 °C

25 °C

1.5

1

0.5

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

Figure 118. I/O Pin Input Threshold Voltage vs. V_CC(V_IL, I/O Pin Read as “0”)

I/O PIN INPUT THRESHOLD VOLTAGE vs. V

cc

VIL, IO PIN READ AS '0'

3

2.5

2

85 °C

25 °C

-40 °C

1.5

1

0.5

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

202

ATtiny2313/V

2543I–AVR–04/06

ATtiny2313/V

Figure 119. Reset I/O Input Threshold Voltage vs. V_CC(V_IH,Reset Pin Read as “1”)

RESET I/O PIN INPUT THRESHOLD VOLTAGE vs. V

cc

VIH, IO PIN READ AS '1'

3

2.5

2

85 °C

25 °C

-40 °C

1.5

1

0.5

0

1.5

2

2.5

3

3.5

(V)

4

4.5

5

5.5

V

cc

Figure 120. Reset I/O Input Threshold Voltage vs. V_CC(V_IL,Reset Pin Read as “0”)

RESET I/O PIN INPUT THRESHOLD VOLTAGE vs. V

cc

VIL, IO PIN READ AS '0'

2.5

2

85°C

25°C

-40°C

1.5

1

0.5

0

1.5

2

2.5

3

3.5

(V)

4

4.5

5

5.5

V

cc

203

2543I–AVR–04/06

Figure 121. Reset I/O Input Pin Hysteresis vs. V_CC

RESET I/O INPUT PIN HYSTERESIS vs. V

cc

1

0.9

0.8

-40 °C

0.7

0.6

25 °C

0.5

85 °C

0.4

0.3

0.2

0.1

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

Figure 122. Reset Input Threshold Voltage vs. V_CC(V_IH,Reset Pin Read as “1”)

RESET INPUT THRESHOLD VOLTAGE vs. V

cc

VIH, IO PIN READ AS '1'

2.5

2

1.5

1

-40 °C

25 °C

85 °C

0.5

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

204

ATtiny2313/V

2543I–AVR–04/06

ATtiny2313/V

Figure 123. Reset Input Threshold Voltage vs. V_CC(V_IL,Reset Pin Read as “0”)

RESET INPUT THRESHOLD VOLTAGE vs. V

cc

VIL, IO PIN READ AS '0'

2.5

2

1.5

1

85 °C

25 °C

-40 °C

0.5

0

1.5

2

2.5

3

3.5

(V)

4

4.5

5

5.5

V

cc

Figure 124. Reset Input Pin Hysteresis vs. V_CC

RESET INPUT PIN HYSTERESIS vs. V

cc

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

-40 °C

25 °C

85 °C

1.5

2

2.5

3

3.5

(V)

4

4.5

5

5.5

V

cc

205

2543I–AVR–04/06

BOD Thresholds and Analog

Comparator Offset

Figure 125. BOD Thresholds vs. Temperature (BOD Level is 4.3V)

BOD THRESHOLDS vs. TEMPERATURE

BODLEVEL IS 4.3V

4.45

Rising Vcc

4.4

4.35

Falling Vcc

4.3

4.25

-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

Temperature (C)

Figure 126. BOD Thresholds vs. Temperature (BOD Level is 2.7V)

BOD THRESHOLDS vs. TEMPERATURE

BODLEVEL IS 2.7V

2.85

Rising Vcc

2.8

2.75

Falling Vcc

2.7

2.65

-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

Temperature (C)

206

ATtiny2313/V

2543I–AVR–04/06

ATtiny2313/V

Figure 127. BOD Thresholds vs. Temperature (BOD Level is 1.8V)

BOD THRESHOLDS vs. TEMPERATURE

BODLEVEL IS 1.8V

1.88

1.86

1.84

1.82

1.8

Rising Vcc

Falling Vcc

1.78

-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

Temperature (C)

Internal Oscillator Speed

Figure 128. Watchdog Oscillator Frequency vs. V_CC

WATCHDOG OSCILLATOR FREQUENCY vs. VCC

0.104

0.103

0.102

0.101

0.1

-40 °C

25 °C

0.099

0.098

0.097

0.096

0.095

85 °C

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V

_CC(V)

207

2543I–AVR–04/06

Figure 129. Watchdog Oscillator Frequency vs. Temperature

WATCHDOG OSCILLATOR FREQUENCY vs. TEMPERATURE

0.105

0.104

0.103

0.102

0.101

0.1

1.8 V

2.7 V

0.099

0.098

0.097

0.096

3.3 V

4.0 V

5.5 V

5.0 V

4.5 V

-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

Temperature (°C)

Figure 130. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature

CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE

8.4

5.5 V

5.0 V

4.5 V

4.0 V

3.3 V

2.7 V

1.8 V

8.3

8.2

8.1

8

7.9

7.8

7.7

-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

Temperature (°C)

208

ATtiny2313/V

2543I–AVR–04/06

ATtiny2313/V

Figure 131. Calibrated 8 MHz RC Oscillator Frequency vs. V_CC

CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. V

cc

8.4

8.3

8.2

8.1

8

85 °C

25 °C

-40 °C

7.9

7.8

7.7

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

Figure 132. Calibrated 8 MHz RC Oscillator Frequency vs. Osccal Value

CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE

14

25 °C

12

10

8

6

4

2

0

16

32

48

64

80

96

112

128

OSCCAL VALUE

209

2543I–AVR–04/06

Figure 133. Calibrated 4 MHz RC Oscillator Frequency vs. Temperature

CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE

4.2

5.5 V

5.0 V

3.3 V

1.8 V

4.15

4.1

4.05

4

3.95

3.9

-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

Temperature (°C)

Figure 134. Calibrated 4 MHz RC Oscillator Frequency vs. V_CC

CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. V

cc

4.2

4.15

4.1

85 °C

4.05

4

25 °C

-40 °C

3.95

3.9

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V

_CC(V)

210

ATtiny2313/V

2543I–AVR–04/06

ATtiny2313/V

Figure 135. Calibrated 4 MHz RC Oscillator Frequency vs. Osccal Value

CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE

7

6

5

4

3

2

1

0

25 °C

0

8

16

24

32

40

48

56

64

72

80

88

96 104 112 120 128

OSCCAL VALUE

Current Consumption of

Peripheral Units

Figure 136. Brownout Detector Current vs. V_CC

BROWNOUT DETECTOR CURRENT vs. V

cc

30

25

20

15

10

5

-40 °C

85 °C

25 °C

0

1.5

2

2.5

3

3.5

(V)

4

4.5

5

5.5

V

cc

211

2543I–AVR–04/06

Figure 137. Analog Comparator Current vs. V_CC

ANALOG COMPARATOR CURRENT vs. V

cc

70

60

50

40

30

20

10

0

-40 °C

25 °C

85 °C

1.5

2

2.5

3

3.5

(V)

4

4.5

5

5.5

V

cc

Figure 138. Programming Current vs. V_CC

PROGRAMMING CURRENT vs. V

cc

4.5

4

3.5

3

-40 °C

2.5

2

25 °C

85 °C

1.5

1

0.5

0

1.5

2

2.5

3

3.5

(V)

4

4.5

5

5.5

V

cc

212

ATtiny2313/V

2543I–AVR–04/06

ATtiny2313/V

Current Consumption in

Figure 139. Reset Supply Current vs. V_CC(0.1 - 1.0 MHz, Excluding Current Through

Reset and Reset Pulsewidth

The Reset Pull-up)

RESET SUPPLY CURRENT vs. V

0.1 - 1.0 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP

cc

0.14

0.12

0.1

5.5 V

5.0 V

4.5 V

4.0 V

0.08

0.06

0.04

0.02

0

3.3 V

2.7 V

1.8 V

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

Figure 140. Reset Supply Current vs. V_CC(1 - 20 MHz, Excluding Current Through The

Reset Pull-up)

RESET SUPPLY CURRENT vs. V

1 - 20 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP

cc

2.5

2

5.5 V

5.0 V

4.5 V

4.0 V

1.5

1

3.3 V

2.7 V

0.5

0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

213

2543I–AVR–04/06

Figure 141. Minimum Reset Pulse Width vs. V_CC

MINIMUM RESET PULSE WIDTH vs. V

cc

2500

2000

1500

1000

500

85 °C

25 °C

-40 °C

0

1.5

2

2.5

3

3.5

(V)

4

4.5

5

5.5

V

cc

214

ATtiny2313/V

2543I–AVR–04/06

ATtiny2313/V

Register Summary

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

0x3F (0x5F)

0x3E (0x5E)

0x3D (0x5D)

0x3C (0x5C)

0x3B (0x5B)

0x3A (0x5A)

0x39 (0x59)

0x38 (0x58)

0x37 (0x57)

0x36 (0x56)

0x35 (0x55)

0x34 (0x54)

0x33 (0x53)

0x32 (0x52)

0x31 (0x51)

0x30 (0x50)

0x2F (0x4F)

0x2E (0x4E)

0x2D (0x4D)

0x2C (0x4C)

0x2B (0x4B)

0x2A (0x4A)

0x29 (0x49)

0x28 (0x48)

0x27 (0x47)

0x26 (0x46)

0x25 (0x45)

0x24 (0x44)

0x23 (0x43)

0x22 (ox42)

0x21 (0x41)

0x20 (0x40)

0x1F (0x3F)

0x1E (0x3E)

0x1D (0x3D)

0x1C (0x3C)

0x1B (0x3B)

0x1A (0x3A)

0x19 (0x39)

0x18 (0x38)

0x17 (0x37)

0x16 (0x36)

0x15 (0x35)

0x14 (0x34)

0x13 (0x33)

0x12 (0x32)

0x11 (0x31)

0x10 (0x30)

0x0F (0x2F)

0x0E (0x2E)

0x0D (0x2D)

0x0C (0x2C)

0x0B (0x2B)

0x0A (0x2A)

0x09 (0x29)

0x08 (0x28)

0x07 (0x27)

0x06 (0x26)

0x05 (0x25)

0x04 (0x24)

0x03 (0x23)

0x02 (0x22)

0x01 (0x21)

0x00 (0x20)

SREG

Reserved

SPL

I

–

T

–

H

–

S

–

V

–

N

–

Z

–

C

–

10

SP7

SP6

SP5

SP4

SP3

SP2

SP1

SP0

13

81

OCR0B

GIMSK

EIFR

Timer/Counter0 – Compare Register B

INT1

INTF1

TOIE1

TOV1

–

INT0

INTF0

OCIE1A

OCF1A

–

PCIE

PCIF

–

63

–

65

TIMSK

OCIE1B

OCF1B

–

ICIE1

ICF1

RFLB

OCIE0B

OCF0B

PGWRT

TOIE0

TOV0

PGERS

OCIE0A

OCF0A

SELFPRGEN

82, 113

82

TIFR

–

SPMCSR

OCR0A

MCUCR

MCUSR

TCCR0B

TCNT0

OSCCAL

TCCR0A

TCCR1A

TCCR1B

TCNT1H

TCNT1L

OCR1AH

OCR1AL

OCR1BH

OCR1BL

Reserved

CLKPR

ICR1H

CTPB

159

81

Timer/Counter0 – Compare Register A

PUD

–

SM1

–

SE

–

SM0

ISC11

WDRF

WGM02

ISC10

BORF

CS02

ISC01

EXTRF

CS01

ISC00

PORF

CS00

56

–

40

FOC0A

FOC0B

–

80

Timer/Counter0 (8-bit)

81

–

CAL6

COM0A0

COM1A0

ICES1

CAL5

COM0B1

COM1B1

–

CAL4

CAL3

CAL2

–

CAL1

WGM01

WGM11

CS11

CAL0

WGM00

WGM10

CS10

28

COM0A1

COM1A1

ICNC1

COM0B0

COM1BO

WGM13

–

77

–

108

111

112

113

WGM12

CS12

Timer/Counter1 – Counter Register High Byte

Timer/Counter1 – Counter Register Low Byte

Timer/Counter1 – Compare Register A High Byte

Timer/Counter1 – Compare Register A Low Byte

Timer/Counter1 – Compare Register B High Byte

Timer/Counter1 – Compare Register B Low Byte

–

CLKPCE

CLKPS3

CLKPS2

CLKPS1

CLKPS0

30

113

85

Timer/Counter1 - Input Capture Register High Byte

Timer/Counter1 - Input Capture Register Low Byte

ICR1L

GTCCR

TCCR1C

WDTCSR

PCMSK

Reserved

EEAR

–

FOC1A

WDIF

PCINT7

–

PSR10

–

FOC1B

WDIE

PCINT6

–

112

45

WDP3

PCINT5

–

WDCE

PCINT4

–

WDE

PCINT3

–

WDP2

PCINT2

–

WDP1

PCINT1

–

WDP0

PCINT0

–

65

–

EEPROM Address Register

EEPROM Data Register

18

19

EEDR

EECR

–

EEPM1

EEPM0

EERIE

EEMPE

PORTA2

DDA2

EEPE

PORTA1

DDA1

EERE

PORTA0

DDA0

19

PORTA

DDRA

–

61

PINA

–

PINA2

PINA1

PINA0

61

PORTB

DDRB

PORTB7

DDB7

PINB7

PORTB6

DDB6

PINB6

PORTB5

DDB5

PINB5

PORTB4

DDB4

PINB4

PORTB3

DDB3

PINB3

PORTB2

DDB2

PORTB1

DDB1

PORTB0

DDB0

61

PINB

PINB2

PINB1

PINB0

61

GPIOR2

GPIOR1

GPIOR0

PORTD

DDRD

General Purpose I/O Register 2

General Purpose I/O Register 1

General Purpose I/O Register 0

23

–

PORTD6

DDD6

PORTD5

DDD5

PORTD4

DDD4

PORTD3

DDD3

PORTD2

DDD2

PORTD1

DDD1

PORTD0

DDD0

61

PIND

PIND6

PIND5

PIND4

PIND3

PIND2

PIND1

PIND0

61

USIDR

USI Data Register

148

149

150

133

135

137

153

USISR

USISIF

USISIE

USIOIF

USIOIE

USIPF

USIDC

USICNT3

USICS1

USICNT2

USICS0

USICNT1

USICLK

USICNT0

USITC

USICR

USIWM1

USIWM0

UDR

UART Data Register (8-bit)

UCSRA

UCSRB

UBRRL

ACSR

RXC

TXC

UDRE

UDRIE

FE

DOR

UPE

U2X

MPCM

TXB8

RXCIE

TXCIE

RXEN

TXEN

UCSZ2

RXB8

UBRRH[7:0]

ACD

ACBG

ACO

ACI

ACIE

ACIC

ACIS1

ACIS0

Reserved

UCSRC

UBRRH

DIDR

–

UMSEL

UPM1

UPM0

USBS

UCSZ1

UCSZ0

UCPOL

136

137

154

UBRRH[11:8]

–

AIN1D

–

AIN0D

–

Reserved

215

2543I–AVR–04/06

Note:

1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these

registers, the value of single bits can be checked by using the SBIS and SBIC instructions.

3. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI

instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The

CBI and SBI instructions work with registers 0x00 to 0x1F only.

4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O

Registers as data space using LD and ST instructions, 0x20 must be added to these addresses.

216

ATtiny2313/V

2543I–AVR–04/06

ATtiny2313/V

Instruction Set Summary

Mnemonics

Operands

Description

Operation

Flags

#Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD

ADC

ADIW

SUB

SUBI

SBC

SBCI

SBIW

AND

ANDI

OR

Rd, Rr

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd

Add two Registers

Rd ← Rd + Rr

Z,C,N,V,H

Z,C,N,V,S

Z,C,N,V,H

Z,C,N,V,S

Z,N,V

1

2

1

2

1

Add with Carry two Registers

Add Immediate to Word

Subtract two Registers

Subtract Constant from Register

Subtract with Carry two Registers

Subtract with Carry Constant from Reg.

Subtract Immediate from Word

Logical AND Registers

Logical AND Register and Constant

Logical OR Registers

Rd ← Rd + Rr + C

Rdh:Rdl ← Rdh:Rdl + K

Rd ← Rd - Rr

Rd ← Rd - K

Rd ← Rd - Rr - C

Rd ← Rd - K - C

Rdh:Rdl ← Rdh:Rdl - K

Rd ← Rd • Rr

Rd ← Rd • K

Z,N,V

Rd ← Rd v Rr

Z,N,V

ORI

Logical OR Register and Constant

Exclusive OR Registers

One’s Complement

Rd ← Rd v K

Z,N,V

EOR

COM

NEG

SBR

CBR

INC

Rd ← Rd ⊕ Rr

Rd ← 0xFF − Rd

Rd ← 0x00 − Rd

Rd ← Rd v K

Z,N,V

Z,C,N,V

Z,C,N,V,H

Z,N,V

Rd

Two’s Complement

Rd,K

Rd

Set Bit(s) in Register

Clear Bit(s) in Register

Increment

Rd ← Rd • (0xFF - K)

Rd ← Rd + 1

Z,N,V

DEC

TST

Rd

Decrement

Rd ← Rd − 1

Z,N,V

Rd

Test for Zero or Minus

Clear Register

Rd ← Rd • Rd

Rd ← Rd ⊕ Rd

Rd ← 0xFF

Z,N,V

CLR

SER

Rd

Z,N,V

Rd

Set Register

None

BRANCH INSTRUCTIONS

RJMP

IJMP

k

Relative Jump

PC ← PC + k + 1

None

I

2

Indirect Jump to (Z)

PC ← Z

RCALL

ICALL

RET

Relative Subroutine Call

Indirect Call to (Z)

PC ← PC + k + 1

3

PC ← Z

3

Subroutine Return

PC ← STACK

4

RETI

Interrupt Return

PC ← STACK

4

CPSE

CP

Rd,Rr

Compare, Skip if Equal

Compare

if (Rd = Rr) PC ← PC + 2 or 3

Rd − Rr

None

Z, N,V,C,H

None

1/2/3

1

Rd,Rr

CPC

Rd,Rr

Compare with Carry

Rd − Rr − C

1

CPI

Rd,K

Compare Register with Immediate

Skip if Bit in Register Cleared

Skip if Bit in Register is Set

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register is Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Rd − K

1

SBRC

SBRS

SBIC

Rr, b

if (Rr(b)=0) PC ← PC + 2 or 3

if (Rr(b)=1) PC ← PC + 2 or 3

if (P(b)=0) PC ← PC + 2 or 3

if (P(b)=1) PC ← PC + 2 or 3

if (SREG(s) = 1) then PC←PC+k + 1

if (SREG(s) = 0) then PC←PC+k + 1

if (Z = 1) then PC ← PC + k + 1

if (Z = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (C = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (N = 1) then PC ← PC + k + 1

if (N = 0) then PC ← PC + k + 1

if (N ⊕ V= 0) then PC ← PC + k + 1

if (N ⊕ V= 1) then PC ← PC + k + 1

if (H = 1) then PC ← PC + k + 1

if (H = 0) then PC ← PC + k + 1

if (T = 1) then PC ← PC + k + 1

if (T = 0) then PC ← PC + k + 1

if (V = 1) then PC ← PC + k + 1

if (V = 0) then PC ← PC + k + 1

if ( I = 1) then PC ← PC + k + 1

if ( I = 0) then PC ← PC + k + 1

1/2/3

1/2

Rr, b

P, b

s, k

k

SBIS

BRBS

BRBC

BREQ

BRNE

BRCS

BRCC

BRSH

BRLO

BRMI

BRPL

BRGE

BRLT

BRHS

BRHC

BRTS

BRTC

BRVS

BRVC

BRIE

BRID

k

Branch if Not Equal

k

Branch if Carry Set

k

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

k

Branch if Minus

k

Branch if Plus

k

Branch if Greater or Equal, Signed

Branch if Less Than Zero, Signed

Branch if Half Carry Flag Set

Branch if Half Carry Flag Cleared

Branch if T Flag Set

k

Branch if T Flag Cleared

Branch if Overflow Flag is Set

Branch if Overflow Flag is Cleared

Branch if Interrupt Enabled

Branch if Interrupt Disabled

k

BIT AND BIT-TEST INSTRUCTIONS

SBI

P,b

Rd

Set Bit in I/O Register

Clear Bit in I/O Register

Logical Shift Left

I/O(P,b) ← 1

None

2

1

CBI

LSL

LSR

ROL

I/O(P,b) ← 0

None

Rd(n+1) ← Rd(n), Rd(0) ← 0

Rd(n) ← Rd(n+1), Rd(7) ← 0

Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)

Z,C,N,V

Logical Shift Right

Rotate Left Through Carry

217

2543I–AVR–04/06

Mnemonics

Operands

Description

Operation

Flags

#Clocks

ROR

Rd

Rotate Right Through Carry

Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)

Z,C,N,V

1

ASR

SWAP

BSET

BCLR

BST

BLD

SEC

CLC

SEN

CLN

SEZ

CLZ

SEI

Rd

s

Arithmetic Shift Right

Swap Nibbles

Rd(n) ← Rd(n+1), n=0..6

Z,C,N,V

Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)

None

Flag Set

SREG(s) ← 1

SREG(s) ← 0

T ← Rr(b)

Rd(b) ← T

C ← 1

SREG(s)

s

Flag Clear

SREG(s)

Rr, b

Rd, b

Bit Store from Register to T

Bit load from T to Register

Set Carry

T

None

C

N

Z

Clear Carry

C ← 0

Set Negative Flag

N ← 1

Clear Negative Flag

Set Zero Flag

N ← 0

Z ← 1

Clear Zero Flag

Z ← 0

Z

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

Clear Signed Test Flag

Set Twos Complement Overflow.

Clear Twos Complement Overflow

Set T in SREG

I ← 1

I

CLI

I ← 0

I

SES

CLS

SEV

CLV

SET

CLT

SEH

CLH

S ← 1

S

V

T

S ← 0

V ← 1

V ← 0

T ← 1

Clear T in SREG

T ← 0

T

Set Half Carry Flag in SREG

Clear Half Carry Flag in SREG

H ← 1

H

H ← 0

DATA TRANSFER INSTRUCTIONS

MOV

MOVW

LDI

LD

Rd, Rr

Rd, K

Move Between Registers

Copy Register Word

Rd ← Rr

None

1

2

3

-

Rd+1:Rd ← Rr+1:Rr

Load Immediate

Rd ← K

Rd, X

Load Indirect

Rd ← (X)

LD

Rd, X+

Rd, - X

Rd, Y

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect

Rd ← (X), X ← X + 1

X ← X - 1, Rd ← (X)

Rd ← (Y)

LD

Rd, Y+

Rd, - Y

Rd,Y+q

Rd, Z

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Indirect

Rd ← (Y), Y ← Y + 1

Y ← Y - 1, Rd ← (Y)

Rd ← (Y + q)

Rd ← (Z)

LD

LDD

LD

Rd, Z+

Rd, -Z

Rd, Z+q

Rd, k

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Direct from SRAM

Store Indirect

Rd ← (Z), Z ← Z+1

Z ← Z - 1, Rd ← (Z)

Rd ← (Z + q)

Rd ← (k)

LD

LDD

LDS

ST

X, Rr

(X) ← Rr

ST

X+, Rr

- X, Rr

Y, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect

(X) ← Rr, X ← X + 1

X ← X - 1, (X) ← Rr

(Y) ← Rr

ST

Y+, Rr

- Y, Rr

Y+q,Rr

Z, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Indirect

(Y) ← Rr, Y ← Y + 1

Y ← Y - 1, (Y) ← Rr

(Y + q) ← Rr

ST

STD

ST

(Z) ← Rr

ST

Z+, Rr

-Z, Rr

Z+q,Rr

k, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Direct to SRAM

Load Program Memory

Load Program Memory and Post-Inc

Store Program Memory

In Port

(Z) ← Rr, Z ← Z + 1

Z ← Z - 1, (Z) ← Rr

(Z + q) ← Rr

ST

STD

STS

LPM

SPM

IN

(k) ← Rr

R0 ← (Z)

Rd, Z

Rd ← (Z)

Rd, Z+

Rd ← (Z), Z ← Z+1

(Z) ← R1:R0

Rd, P

P, Rr

Rr

Rd ← P

1

2

OUT

PUSH

POP

Out Port

P ← Rr

Push Register on Stack

Pop Register from Stack

STACK ← Rr

Rd ← STACK

Rd

MCU CONTROL INSTRUCTIONS

NOP

No Operation

Sleep

None

1

SLEEP

WDR

(see specific descr. for Sleep function)

(see specific descr. for WDR/timer)

For On-chip Debug Only

Watchdog Reset

Break

1

BREAK

N/A

218

ATtiny2313/V

2543I–AVR–04/06

ATtiny2313/V

Ordering Information

Speed (MHz)⁽³⁾

Power Supply

Ordering Code

Package⁽¹⁾

Operation Range

ATtiny2313V-10PI

20P3

20S

20M1

ATtiny2313V-10PU⁽²⁾

ATtiny2313V-10SI

Industrial

(-40°C to 85°C)

10

1.8 - 5.5V

2.7 - 5.5V

ATtiny2313V-10SU⁽²⁾

ATtiny2313V-10MU⁽²⁾

ATtiny2313-20PI

20P3

20S

20M1

ATtiny2313-20PU⁽²⁾

ATtiny2313-20SI

Industrial

(-40°C to 85°C)

20

ATtiny2313-20SU⁽²⁾

ATtiny2313-20MU⁽²⁾

Note:

1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS direc-

tive).Also Halide free and fully Green.

3. For Speed vs. V_CC,see Figure 82 on page 184 and Figure 83 on page 184.

Package Type

20P3

20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

20S

20-lead, 0.300" Wide, Plastic Gull Wing Small Outline Package (SOIC)

20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (MLF)

20M1

219

2543I–AVR–04/06

Packaging Information

20P3

D

1

E1

A

SEATING PLANE

A1

L

B

B1

e

E

COMMON DIMENSIONS

(Unit of Measure = mm)

C

MIN

–

MAX

5.334

–

NOM

NOTE

SYMBOL

eC

A

–

eB

A1

D

0.381

25.493

7.620

6.096

0.356

1.270

2.921

0.203

–

25.984 Note 2

8.255

E

E1

B

7.112 Note 2

0.559

B1

L

1.551

Notes:

1. This package conforms to JEDEC reference MS-001, Variation AD.

2. Dimensions D and E1 do not include mold Flash or Protrusion.

Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").

3.810

C

0.356

eB

eC

e

10.922

0.000

1.524

2.540 TYP

1/12/04

DRAWING NO. REV.

TITLE

2325 Orchard Parkway

San Jose, CA 95131

20P3, 20-lead (0.300"/7.62 mm Wide) Plastic Dual

Inline Package (PDIP)

20P3

C

R

220

ATtiny2313/V

2543I–AVR–04/06

ATtiny2313/V

20S

C

1

H

E

N

A1

Top View

End View

COMMON DIMENSIONS

(Unit of Measure = inches)

MIN

MAX

NOM

NOTE

SYMBOL

e

b

A

A1

b

0.0926

0.0040

0.0130

0.0091

0.4961

0.2914

0.3940

0.0160

0.1043

0.0118

0.0200

0.0125

0.5118

0.2992

0.4190

0.050

A

4

C

D

E

H

L

D

1

2

Side View

3

e

0.050 BSC

Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-013, Variation AC for additional information.

2. Dimension "D" does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed

0.15 mm (0.006") per side.

3. Dimension "E" does not include inter-lead Flash or protrusion. Inter-lead Flash and protrusions shall not exceed 0.25 mm

(0.010") per side.

4. "L" is the length of the terminal for soldering to a substrate.

5. The lead width "b", as measured 0.36 mm (0.014") or greater above the seating plane, shall not exceed a maximum value of 0.61 mm

1/9/02

(0.024") per side.

TITLE

DRAWING NO.

REV.

20S2, 20-lead, 0.300" Wide Body, Plastic Gull

Wing Small Outline Package (SOIC)

2325 Orchard Parkway

San Jose, CA 95131

A

20S2

R

221

2543I–AVR–04/06

20M1

D

1

2

Pin 1 ID

SIDE VIEW

E

3

TOP VIEW

A2

A1

D2

A

0.08

C

1

2

3

Pin #1

Notch

(0.20 R)

COMMON DIMENSIONS

(Unit of Measure = mm)

E2

MIN

0.70

–

MAX

0.80

0.05

b

NOM

0.75

NOTE

SYMBOL

A

A1

A2

b

0.01

L

0.20 REF

0.23

0.18

2.45

0.35

0.30

2.75

0.55

e

D

4.00 BSC

2.60

D2

E

BOTTOM VIEW

4.00 BSC

2.60

E2

e

0.50 BSC

0.40

Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5.

Note:

L

10/27/04

DRAWING NO. REV.

TITLE

2325 Orchard Parkway

San Jose, CA 95131

20M1, 20-pad, 4 x 4 x 0.8 mm Body, Lead Pitch 0.50 mm,

20M1

A

R

2.6 mm Exposed Pad, Micro Lead Frame Package (MLF)

222

ATtiny2313/V

2543I–AVR–04/06

ATtiny2313/V

Errata

The revision in this section refers to the revision of the ATtiny2313 device.

ATtiny2313 Rev B

• Wrong values read after Erase Only operation

• Parallel Programming does not work

• Watchdog Timer Interrupt disabled

• EEPROM can not be written below 1.9 volts

1. Wrong values read after Erase Only operation

At supply voltages below 2.7 V, an EEPROM location that is erased by the Erase

Only operation may read as programmed (0x00).

Problem Fix/Workaround

If it is necessary to read an EEPROM location after Erase Only, use an Atomic Write

operation with 0xFF as data in order to erase a location. In any case, the Write Only

operation can be used as intended. Thus no special considerations are needed as

long as the erased location is not read before it is programmed.

2. Parallel Programming does not work

Parallel Programming is not functioning correctly. Because of this, reprogramming

of the device is impossible if one of the following modes are selected:

–

In-System Programming disabled (SPIEN unprogrammed)

Reset Disabled (RSTDISBL programmed)

Problem Fix/Workaround

Serial Programming is still working correctly. By avoiding the two modes above, the

device can be reprogrammed serially.

3. Watchdog Timer Interrupt disabled

If the watchdog timer interrupt flag is not cleared before a new timeout occurs, the

watchdog will be disabled, and the interrupt flag will automatically be cleared. This is

only applicable in interrupt only mode. If the Watchdog is configured to reset the

device in the watchdog time-out following an interrupt, the device works correctly.

Problem fix / Workaround

Make sure there is enough time to always service the first timeout event before a

new watchdog timeout occurs. This is done by selecting a long enough time-out

period.

4. EEPROM can not be written below 1.9 volts

Writing the EEPROM at V_CCbelow 1.9 volts might fail.

Problem fix / Workaround

Do not write the EEPROM when V_CCis below 1.9 volts.

ATtiny2313 Rev A

Revision A has not been sampled.

223

2543I–AVR–04/06

Datasheet Revision

History

Please note that the referring page numbers in this section are referred to this docu-

ment. The referring revision in this section are referring to the document revision.

Changes from Rev.

2514H-02/05 to Rev.

2514I-04/06

1.

2.

3

Updated typos.

Updated Figure 1 on page 2.

Added “Resources” on page 6.

4.

5.

6.

7.

Updated “Default Clock Source” on page 25.

Updated “128 kHz Internal Oscillator” on page 30.

Updated “Power Management and Sleep Modes” on page 33

Updated Table 3 on page 25,Table 13 on page 33, Table 14 on page 34,

Table 19 on page 45, Table 31 on page 63, Table 79 on page 180.

8.

9.

Updated “External Interrupts” on page 62.

Updated “Bit 7..0 – PCINT7..0: Pin Change Enable Mask 7..0” on page

65.

10.

Updated “Bit 6 – ACBG: Analog Comparator Bandgap Select” on page

153.

11.

12.

13.

14.

15.

Updated “Calibration Byte” on page 164.

Updated “DC Characteristics” on page 181.

Updated “Register Summary” on page 215.

Updated “Ordering Information” on page 219.

Changed occurences of OCnA to OCFnA, OCnB to OCFnB and OC1x to

OCF1x.

Changes from Rev.

2514G-10/04 to Rev.

2514H-02/05

1.

2.

3.

Updated Table 6 on page 27, Table 15 on page 37, Table 68 on page 164

and Table 80 on page 183.

Changed CKSEL default value in “Default Clock Source” on page 25 to

8 MHz.

Updated “Programming the Flash” on page 169, “Programming the

EEPROM” on page 171 and “Enter Programming Mode” on page 167.

4.

5.

Updated “DC Characteristics” on page 181.

MLF option updated to “Quad Flat No-Lead/Micro Lead Frame

(QFN/MLF)”

Changes from Rev.

2514F-08/04 to Rev.

2514G-10/04

1.

2.

3.

4.

5.

Updated “Features” on page 1.

Updated “Pinout ATtiny2313” on page 2.

Updated “Ordering Information” on page 219.

Updated “Packaging Information” on page 220.

Updated “Errata” on page 223.

Changes from Rev.

2514E-04/04 to Rev.

2514F-08/04

1.

2.

3.

Updated “Features” on page 1.

Updated “Alternate Functions of Port B” on page 56.

Updated “Calibration Byte” on page 164.

224

ATtiny2313/V

2543I–AVR–04/06

ATtiny2313/V

4.

Moved Table 69 on page 164 and Table 70 on page 165 to “Page Size”

on page 164.

5.

Updated “Enter Programming Mode” on page 167.

Updated “Serial Programming Algorithm” on page 177.

Updated Table 78 on page 178.

6.

7.

8.

Updated “DC Characteristics” on page 181.

9.

Updated “ATtiny2313 Typical Characteristics” on page 185.

10.

Changed occurences of PCINT15 to PCINT7, EEMWE to EEMPE and

EEWE to EEPE in the document.

Changes from Rev.

2514D-03/04 to Rev.

2514E-04/04

1.

Speed Grades changed

- 12MHz to 10MHz

- 24MHz to 20MHz

2.

3.

4.

5.

Updated Figure 1 on page 2.

Updated “Ordering Information” on page 219.

Updated “Maximum Speed vs. VCC” on page 184.

Updated “ATtiny2313 Typical Characteristics” on page 185.

Changes from Rev.

2514C-12/03 to Rev.

2514D-03/04

1.

2.

3.

4.

5.

6.

Updated Table 2 on page 25.

Replaced “Watchdog Timer” on page 42.

Added “Maximum Speed vs. VCC” on page 184.

“Serial Programming Algorithm” on page 177 updated.

Changed mA to µA in preliminary Figure 136 on page 211.

“Ordering Information” on page 219 updated.

MLF package option removed

7.

8.

9.

Package drawing “20P3” on page 220 updated.

Updated C-code examples.

Renamed instances of SPMEN to SELFPRGEN, Self Programming

Enable.

Changes from Rev.

2514B-09/03 to Rev.

2514C-12/03

1.

Updated “Calibrated Internal RC Oscillator” on page 27.

Changes from Rev.

2514A-09/03 to Rev.

2514B-09/03

1.

Fixed typo from UART to USART and updated Speed Grades and Power

Consumption Estimates in “Features” on page 1.

2.

3.

4.

5.

6.

7.

8.

9.

Updated “Pin Configurations” on page 2.

Updated Table 15 on page 37 and Table 80 on page 183.

Updated item 5 in “Serial Programming Algorithm” on page 177.

Updated “Electrical Characteristics” on page 181.

Updated Figure 82 on page 184 and added Figure 83 on page 184.

Changed SFIOR to GTCCR in “Register Summary” on page 215.

Updated “Ordering Information” on page 219.

Added new errata in “Errata” on page 223.

225

2543I–AVR–04/06

226

ATtiny2313/V

2543I–AVR–04/06

ATtiny2313

Table of Contents

Features................................................................................................ 1

Pin Configurations............................................................................... 2

Overview............................................................................................... 2

Block Diagram ...................................................................................................... 3

Pin Descriptions.................................................................................................... 5

Resources ............................................................................................ 6

About Code Examples......................................................................... 7

Disclaimer............................................................................................. 8

AVR CPU Core ..................................................................................... 9

Introduction........................................................................................................... 9

Architectural Overview.......................................................................................... 9

ALU – Arithmetic Logic Unit................................................................................ 10

Status Register ................................................................................................... 10

General Purpose Register File ........................................................................... 11

Stack Pointer ...................................................................................................... 13

Instruction Execution Timing............................................................................... 13

Reset and Interrupt Handling.............................................................................. 14

AVR ATtiny2313 Memories ............................................................... 16

In-System Reprogrammable Flash Program Memory ........................................ 16

SRAM Data Memory........................................................................................... 17

EEPROM Data Memory...................................................................................... 18

I/O Memory......................................................................................................... 23

System Clock and Clock Options .................................................... 24

Clock Systems and their Distribution.................................................................. 24

Clock Sources..................................................................................................... 25

Default Clock Source.......................................................................................... 25

Crystal Oscillator................................................................................................. 25

Calibrated Internal RC Oscillator ........................................................................ 27

External Clock..................................................................................................... 29

128 kHz Internal Oscillator.................................................................................. 30

System Clock Prescalar...................................................................................... 30

Power Management and Sleep Modes............................................. 33

Idle Mode............................................................................................................ 33

Power-down Mode.............................................................................................. 34

Standby Mode..................................................................................................... 34

Minimizing Power Consumption ......................................................................... 34

i

2543I–AVR–04/06

System Control and Reset................................................................ 36

Internal Voltage Reference................................................................................. 41

Watchdog Timer ................................................................................................. 42

Interrupts............................................................................................ 47

Interrupt Vectors in ATtiny2313 .......................................................................... 47

I/O-Ports.............................................................................................. 49

Introduction......................................................................................................... 49

Ports as General Digital I/O................................................................................ 50

Alternate Port Functions ..................................................................................... 54

Register Description for I/O-Ports....................................................................... 61

External Interrupts............................................................................. 62

Pin Change Interrupt Timing............................................................................... 62

8-bit Timer/Counter0 with PWM........................................................ 66

Overview............................................................................................................. 66

Timer/Counter Clock Sources............................................................................. 67

Counter Unit........................................................................................................ 67

Output Compare Unit.......................................................................................... 68

Compare Match Output Unit............................................................................... 69

Modes of Operation ............................................................................................ 70

Timer/Counter Timing Diagrams......................................................................... 75

8-bit Timer/Counter Register Description ........................................................... 77

Timer/Counter0 and Timer/Counter1 Prescalers............................ 84

16-bit Timer/Counter1........................................................................ 86

Overview............................................................................................................. 86

Accessing 16-bit Registers ................................................................................. 88

Timer/Counter Clock Sources............................................................................. 92

Counter Unit........................................................................................................ 92

Input Capture Unit............................................................................................... 93

Output Compare Units........................................................................................ 95

Compare Match Output Unit............................................................................... 97

Modes of Operation ............................................................................................ 98

Timer/Counter Timing Diagrams....................................................................... 106

16-bit Timer/Counter Register Description ....................................................... 108

USART .............................................................................................. 115

Overview........................................................................................................... 115

Clock Generation.............................................................................................. 116

Frame Formats ................................................................................................. 119

USART Initialization.......................................................................................... 120

Data Transmission – The USART Transmitter ................................................. 122

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ATtiny2313

Data Reception – The USART Receiver .......................................................... 125

Asynchronous Data Reception ......................................................................... 128

Multi-processor Communication Mode ............................................................. 132

USART Register Description ............................................................................ 133

Examples of Baud Rate Setting........................................................................ 138

Universal Serial Interface – USI...................................................... 142

Overview........................................................................................................... 142

Functional Descriptions .................................................................................... 143

Alternative USI Usage ...................................................................................... 148

USI Register Descriptions................................................................................. 148

Analog Comparator ......................................................................... 153

debugWIRE On-chip Debug System.............................................. 155

Features............................................................................................................ 155

Overview........................................................................................................... 155

Physical Interface ............................................................................................. 155

Software Break Points ...................................................................................... 156

Limitations of debugWIRE ................................................................................ 156

debugWIRE Related Register in I/O Memory................................................... 156

Self-Programming the Flash........................................................... 157

Addressing the Flash During Self-Programming .............................................. 158

Memory Programming..................................................................... 162

Program And Data Memory Lock Bits .............................................................. 162

Fuse Bits........................................................................................................... 163

Signature Bytes ................................................................................................ 164

Calibration Byte ................................................................................................ 164

Page Size ......................................................................................................... 164

Parallel Programming Parameters, Pin Mapping, and Commands .................. 165

Serial Programming Pin Mapping..................................................................... 167

Parallel Programming ....................................................................................... 167

Serial Downloading........................................................................................... 176

Electrical Characteristics................................................................ 181

Absolute Maximum Ratings*............................................................................. 181

DC Characteristics............................................................................................ 181

External Clock Drive Waveforms...................................................................... 183

External Clock Drive ......................................................................................... 183

Maximum Speed vs. V_{CC ........................................................................................................................ 184}

ATtiny2313 Typical Characteristics ............................................... 185

Register Summary........................................................................... 215

iii

2543I–AVR–04/06

Instruction Set Summary ................................................................ 217

Ordering Information....................................................................... 219

Packaging Information.................................................................... 220

20P3 ................................................................................................................. 220

20S ................................................................................................................... 221

20M1................................................................................................................. 222

Errata ................................................................................................ 223

ATtiny2313 Rev B............................................................................................. 223

ATtiny2313 Rev A............................................................................................. 223

Datasheet Revision History ............................................................ 224

Changes from Rev. 2514H-02/05 to Rev. 2514I-04/06 .................................... 224

Changes from Rev. 2514G-10/04 to Rev. 2514H-02/05................................... 224

Changes from Rev. 2514F-08/04 to Rev. 2514G-10/04................................... 224

Changes from Rev. 2514E-04/04 to Rev. 2514F-08/04 ................................... 224

Changes from Rev. 2514D-03/04 to Rev. 2514E-04/04................................... 225

Changes from Rev. 2514C-12/03 to Rev. 2514D-03/04................................... 225

Changes from Rev. 2514B-09/03 to Rev. 2514C-12/03................................... 225

Changes from Rev. 2514A-09/03 to Rev. 2514B-09/03 ................................... 225

Table of Contents ................................................................................. i

iv

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2543I–AVR–04/06

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2543I–AVR–04/06


型号：	ATTINY2313V-10MU-SL383
厂家：	ATMEL
描述：	Microcontroller 微控制器
文件：	总231页 (文件大小：2092K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ATTINY2313V-10MU-SL383 [ATMEL]

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