T6817_09 [ATMEL]
Dual Triple DMOS Output Driver with Serial Input Control; 带串行输入控制三双DMOS输出驱动器
| 型号： | T6817_09 |
| 厂家： | 
ATMEL |
| 描述： | Dual Triple DMOS Output Driver with Serial Input Control |
| 文件： | 总16页 (文件大小：377K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Three High-side and Three Low-side Drivers
• Outputs Freely Configurable as Switch, Half Bridge or H-bridge
• Capable of Switching All Kinds of Loads Such as DC Motors, Bulbs, Resistors,
Capacitors and Inductors
• 0.6A Continuous Current Per Switch
• Low-side: RDSon < 1.5Ω Versus Total Temperature Range
• High-side: RDSon < 2.0Ω Versus Total Temperature Range
• Very Low Quiescent Current IS < 20 µA in Standby Mode
• Outputs Short-circuit Protected
• Overtemperature Prewarning and Protection
• Undervoltage and Overvoltage Protection
• Various Diagnosis Functions Such as Shorted Output, Open Load, Overtemperature
and Power Supply Fail
Dual Triple
DMOS Output
Driver with
Serial Input
Control
• Serial Data Interface
• Daisy Chaining Possible
• SSO20 Package
1. Description
The T6817 is a fully protected driver interface designed in 0.8-µm BCDMOS technol-
ogy. It can be used to control up to 6 different loads by a microcontroller in automotive
and industrial applications.
T6817
Each of the 3 high-side and 3 low-side drivers is capable of driving currents up to
600 mA. The drivers are freely configurable and can be controlled separately from a
standard serial data interface. Therefore, all kinds of loads such as bulbs, resistors,
capacitors and inductors can be combined. The IC design is especially supportive of
H-bridges applications to drive DC motors.
Protection is guaranteed in terms of short-circuit conditions, overtemperature, under-
and overvoltage. Various diagnosis functions and a very low quiescent current in
standby mode open a wide range of applications. Meeting automotive qualifications in
the area of conducted interferences, EMC protection and 2 kV ESD protection provide
added value and enhanced quality for the exacting requirements of automotive
applications.
4670E–BCD–04/09
Figure 1-1. Block Diagram
HS3
HS2
HS1
12
14
16
Osc
VS
VS
Fault
detect
Fault
detect
Fault
detect
6
7
DI
V
S
2
4
OV
protection
-
S
C
T
O
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
S
R
R
n.
n. n. n. n. n.
CLK
L
S
I
u. u. u. u. u. u.
D
V
S
Vcc
VCC
Input register
Control
logic
UV
protection
-
CS
19
Serial interface
3
5
Output register
INH
n. n. n. n. n. n.
u. u. u. u. u. u.
P
S
F
I
N
H
S
C
D
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
T
P
GND
GND
Power-on
reset
1
DO
Vcc
10
18
GND
GND
GND
11
13
20
Fault
detect
Fault
detect
Fault
detect
Thermal
protection
8
15
17
LS3
LS2
LS1
2
T6817
4670E–BCD–04/09
T6817
2. Pin Configuration
Figure 2-1. Pinning SSO20
GND
DI
1
2
3
4
5
6
7
8
9
20 GND
19 VCC
18 DO
CS
CLK
INH
VS
17 LS1
16 HS1
15 LS2
14 HS2
13 GND
12 HS3
11 GND
VS
LS3
n.c.
GND 10
Table 2-1.
Pin Description
Pin
Symbol
Function
Ground; reference potential; internal connection to pin 10, 11, 13 and 20; cooling tab
1
GND
Serial data input; 5-V CMOS logic level input with internal pull-down; receives serial data from the control
device, DI expects a 16-bit control word with LSB being transferred first
2
3
4
DI
CS
Chip-select input; 5-V CMOS logic level input with internal pull-up;
low = serial communication is enabled, high = disabled
Serial clock input; 5-V CMOS logic level input with internal pull down;
controls serial data input interface and internal shift register (fmax = 2 MHz)
CLK
5
INH
VS
Inhibit input; 5-V logic input with internal pull-down; low = standby, high = normal operating
Power supply output stages HS1, HS2 and HS3
6, 7
Low-side driver output 3; power-MOS open drain with internal reverse diode: overvoltage protection by
active zenering; short-circuit protection; diagnosis for short and open load
8
LS3
9
n.c.
Not connected
10
11
GND
GND
Ground (see pin 1) be consistent
Ground (see pin 1)
High-side driver output 3; power-MOS open drain with internal reverse diode: overvoltage protection by
active zenering; short-circuit protection; diagnosis for short and open load
12
HS3
13
14
15
16
17
GND
HS2
LS2
HS1
LS1
Ground (see pin 1)
High-side driver output 2 (see pin 12) be consistent
Low-side driver output 2 (see pin 8)
High-side driver output 1 (see pin 12)
Low-side driver output 1 (see pin 8)
Serial data output; 5-V CMOS logic level tri-state output for output (status) register data; sends 16-bit
status information to the microcontroller (LSB is transferred first); output will remain tri-stated unless
device is selected by CS = low, therefore, several ICs can operate on only one data output line only.
18
DO
19
20
VCC
GND
Logic supply voltage (5V)
Ground (see pin 1)
3
4670E–BCD–04/09
3. Functional Description
3.1
Serial Interface
Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized
to CLK and are accepted on the falling edge of the CLK signal. LSB (bit 0, SRR) has to be trans-
ferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CS
is high, pin DO is in tri-state condition. This output is enabled on the falling edge of CS. Output
data will change their state with the rising edge of CLK and stay stable until the next rising edge
of CLK appears. LSB (bit 0, TP) is transferred first.
Figure 3-1. Data Transfer Input Data Protocol
CS
DI
SRR
0
LS1 HS1 LS2 HS2 LS3 HS3 n.u.
n.u.
n.u.
n.u.
10
n.u.
11
n.u.
12
OLD SCT SI
13 14 15
1
2
3
4
5
6
7
8
9
CLK
DO
TP
SLS1 SHS1 SLS2 SHS2 SLS3 SHS3 n.u.
n.u.
n.u.
n.u.
n.u.
n.u. SCD INH
PSF
Table 3-1.
Bit
Input Data Protocol
Input Register
Function
Status register reset (high = reset; the bits PSF, SCD and overtemperature
shutdown in the output data register are set to low)
0
SRR
1
2
LS1
HS1
LS2
HS2
LS3
HS3
n.u.
n.u.
n.u.
n.u.
n.u.
n.u.
OLD
Controls output LS1 (high = switch output LS1 on)
Controls output HS1 (high = switch output HS1 on)
3
See LS1
4
See HS1
5
See LS1
6
See HS1
7
Not used
8
Not used
9
Not used
10
11
12
13
Not used
Not used
Not used
Open load detection (low = on)
Programmable time delay for short circuit and overvoltage shutdown (short
circuit shutdown delay high/low = 100 ms/12.5 ms, overvoltage shutdown
delay high/low = 14 ms/3.5 ms
14
15
SCT
SI
Software inhibit; low = standby, high = normal operation
(data transfer is not affected by standby function because the digital part is
still powered)
4
T6817
4670E–BCD–04/09
T6817
Table 3-2.
Output Data Protocol
Output (Status)
Bit
Register
Function
Temperature prewarning: high = warning (overtemperature shut-down,
see remark below)
0
TP
Normal operation: high = output is on, low = output is off
1
2
Status LS1
Status HS1
Open-load detection: high = open load, low = no open load (correct
load condition is detected if the corresponding output is switched off)
Normal operation: high = output is on, low = output is off
Open-load detection: high = open load, low = no open load (correct
load condition is detected if the corresponding output is switched off)
3
4
Status LS2
Status HS2
Status LS3
Status HS3
n.u.
Description, see LS1
Description, see HS1
Description, see LS1
Description, see HS1
Not used
5
6
7
8
n.u.
Not used
9
n.u.
Not used
10
11
12
n.u.
Not used
n.u.
Not used
n.u.
Not used
Short circuit detected: set high, when at least one output is switched off
by a short circuit condition
13
SCD
Inhibit: this bit is controlled by software (bit SI in input register) and
hardware inhibit (pin 17). High = standby, low = normal operation
14
15
INH
PSF
Power supply fail: over- or undervoltage at pin VS detected
Note:
Bit 0 to 15 = high: overtemperature shutdown
Table 3-3.
Status of the Input Register after Power on Reset
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
(SI) (SCT) (OLD)
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 Bit 2 Bit 1
Bit 0
(HS3) (LS3) (HS2) (LS2) (HS1) (LS1) (SRR)
H
H
H
n.u.
n.u.
n.u.
n.u.
n.u.
n.u.
L
L
L
L
L
L
L
5
4670E–BCD–04/09
3.2
3.3
Power-supply Fail
In case of over- or undervoltage at pin VS, an internal timer is started. When the undervoltage
delay time (tdUV, tdOV) programmed by the SCT bit is reached, the power supply fail bit (PSF) in
the output register is set and all outputs are disabled. When normal voltage is present again, the
outputs are enabled immediately. The PSF bit remains high until it is reset by the SRR bit in the
input register.
Open-load Detection
If the open-load detection bit (OLD) is set to low, a pull-up current for each high-side switch and
a pull-down current for each low-side switch is turned on (open-load detection current IHS1-3
LS1-3). If VVS-VHS1-3 or VLS1-3 is lower than the open-load detection threshold (open-load condi-
,
I
tion), the corresponding bit of the output in the output register is set to high. Switching on an
output stage with the OLD bit set to low disables the open-load function for this output. If bit SI is
set to low, the open-load function is also switched off.
3.4
Overtemperature Protection
If the junction temperature exceeds the thermal prewarning threshold, TjPW set, the temperature
prewarning bit (TP) in the output register is set. When the temperature falls below the thermal
prewarning threshold, TjPW reset, the bit TP is reset. The TP bit can be read without transferring a
complete 16-bit data word: with CS = high to low, the state of TP appears at pin DO. After the
microcontroller has read this information, CS is set high and the data transfer is interrupted with-
out affecting the state of the input and output registers.
If the junction temperature exceeds the thermal shutdown threshold, Tj switch off, the outputs are
disabled and all bits in the output register are set high. The outputs can be enabled again when
the temperature falls below the thermal shutdown threshold, Tj switch on, and when a high has
been written to the SRR bit in the input register. Thermal prewarning and shutdown threshold
have hysteresis.
3.5
Short-circuit Protection
The output currents are limited by a current regulator. Current limitation takes place when the
overcurrent limitation and shutdown threshold (IHS1-3, ILS1-3) are reached. Simultaneously, an
internal timer is started. The shorted output is disabled when during a permanent short the delay
time (tdSd) programmed by the short-circuit timer bit (SCT) is reached. Additionally, the short-cir-
cuit detection bit (SCD) is set. If the temperature prewarning bit TP in the output register is set
during a short, the shorted output is disabled immediately and SCD bit is set. By writing a high to
the SRR bit in the input register, the SCD bit is reset and the disabled outputs are enabled.
3.6
Inhibit
There are two ways to inhibit the T6817:
1. Set bit SI in the input register to zero
2. Switch pin 5 (INH) to 0V
In both cases, all output stages are turned off but the serial interface stays active. The output
stages can be activated again by bit SI = 1 and by pin 5 (INH) switched back to 5V.
6
T6817
4670E–BCD–04/09
T6817
4. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
All values refer to GND pins.
Parameter
Pin
6, 7
6, 7
Symbol
Value
–0.3 to +40
–1
Unit
V
Supply voltage
VVS
Supply voltage t < 0.5s; IS > –2A
Supply voltage difference |VS_Pin6 – VS_Pin7
Supply current
VVS
V
|
ΔVVS
150
mV
A
6, 7
6, 7
19
IVS
IVS
1.4
Supply current t < 200 ms
Logic supply voltage
Input voltage
2.6
A
VVCC
–0.3 to 7
–0.3 to 17
–0.3 to VVCC +0.3
–0.3 to VVCC +0.3
–10 to +10
–10 to +10
V
5
VINH
V
Logic input voltage
Logic output voltage
Input current
2 to 4
18
VDI, VCLK, VCS
VDO
IINH, IDI, ICLK, ICS
IDO
LS1 to ILS3
V
V
5, 2 to 4
18
mA
mA
Output current
I
Internal limited, see
output specification
Output current
Output voltage
8, 12, 14 to 17
IHS1 to IHS3
HS1 to HS3
LS1 to LS3
12, 14, 16
8, 15, 17
–0.3 to +40
17
V
A
12, 14, 16
towards 6, 7
Reverse conducting current (tPulse = 150 µs)
IHS1 to IHS3
Junction temperature range
Storage temperature range
Tj
–40 to +150
–55 to +150
°C
°C
TSTG
5. Thermal Resistance
All values refer to GND pins
Parameter
Test Conditions
Measured to GND Pins 1, 10, 11, 13 and 20
Symbol
RthJP
RthJA
Value
25
65
Unit
K/W
K/W
Junction pin
Junction ambient
6. Operating Range
All values refer to GND pins
Parameter
Test Conditions
Pins 6, 7
Symbol
Min.
Typ.
Max.
40(2)
5.5
Unit
V
(1)
Supply voltage
VVS
VUV
4.5
Logic supply voltage
Pin 19
VVCC
5
V
Logic input voltage
Pin 2 to 4 and 5
Pin 4
VINH, VDI, VCLK, VCS
–0.3
VVCC
2
V
Serial interface clock frequency
Junction temperature range
fCLK
Tj
MHz
°C
–40
150
Notes: 1. Threshold for undervoltage detection
2. Outputs disabled for VVS > VOV (threshold for overvoltage detection)
7
4670E–BCD–04/09
7. Noise and Surge Immunity
Parameter
Test Conditions
Value
Level 4(1)
Level 5
2 kV
Conducted interferences
Interference Suppression
ESD (Human Body Model)
ESD (Machine Model)
ISO 7637–1
VDE 0879 Part 2
MIL-STM 5.1 – 1998
JEDEC EIA / JESD 22 – A115-A
150V
Note:
1. Test pulse 5: VSmax = 40V
8. Electrical Characteristics
7.5V < VVS < VOV; 4.5V < VVCC < 5.5V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins.
No.
1
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
Current Consumption
Quiescent current
(VS)
VVS < 16V, INH or
bit SI = low
1.1
1.2
6, 7
19
IVS
40
20
µA
µA
A
A
Quiescent current
(VCC)
4.5V < VVCC < 5.5V,
INH or bit SI = low
IVCC
VVS < 16V normal
1.3
1.4
Supply current (VS)
operating, all output
stages off,
6, 7
IVS
0.8
1.2
mA
A
VVS < 16V normal
operating, all output
stages on, no load
Supply current (VS)
Supply current (VCC)
6, 7
19
IVS
10
mA
µA
A
A
4.5V < VVCC < 5.5V,
normal operating pin
1.5
2
IVCC
150
Internal Oscillator Frequency
Frequency (time
base for delay timers)
2.1
3
fOSC
19
45
kHz
A
Over- and Undervoltage Detection, Power-on Reset
Power-on reset
19
3.1
VVCC
tdPor
VUV
3.4
30
3.9
95
4.4
160
7.0
V
µs
V
A
A
A
A
A
A
A
threshold
Power-on reset delay
time
After switching on
VVCC
3.2
3.3
3.4
3.6
3.7
3.8
19
Undervoltage
detection threshold
6, 7
6, 7
6, 7
6, 7
6, 7
5.5
Undervoltage
detection hysteresis
ΔVUV
tdUV
0.4
V
Undervoltage
detection delay
7
21
ms
V
Overvoltage
detection threshold
VOV
18.0
22.5
Overvoltage
detection hysteresis
ΔVOV
1
V
Input register
bit 14 (SCT) = high
bit 14 (SCT) = low
Undervoltage
detection delay
3.9
tdOV
tdOV
7
1.75
21
5.25
ms
ms
A
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Delay time between rising edge of CS after data transmission and switch on/off output stages to 90% of final level
8
T6817
4670E–BCD–04/09
T6817
8. Electrical Characteristics (Continued)
7.5V < VVS < VOV; 4.5V < VVCC < 5.5V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins.
No.
4
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
Thermal Prewarning and Shutdown
Thermal prewarning
4.1
4.2
TjPWset
125
105
145
125
165
145
°C
°C
A
A
Thermal prewarning
TjPWreset
Thermal prewarning
hysteresis
4.3
ΔTjPW
3
20
K
A
4.4
4.5
Thermal shutdown
Thermal shutdown
Tj switch off
Tj switch on
150
130
170
150
190
170
°C
°C
A
A
Thermal shutdown
hysteresis
4.6
ΔTj switch off
3
20
K
A
Ratio thermal
shutdown/thermal
prewarning
Tj switch off/
TjPW set
4.7
1.05
1.17
A
Ratio thermal
shutdown/thermal
prewarning
Tj switch on/
TjPW reset
4.8
1.05
1.2
A
5
Output Specification (LS1-LS6, HS1-HS6) 7.5V < VVS < VOV
8, 15,
17
5.1
On resistance
On resistance
IOut = 600 mA
IOut = –600 mA
RDS OnL
RDS OnH
VLS1-3
1.5
2.0
60
Ω
Ω
A
A
A
A
12, 14,
16
5.2
5.3
5.4
Output clamping
voltage
8, 15,
17
ILS1-3 = 50 mA
40
V
Output leakage
current
VLS1–3 = 40V
all output stages off
8, 15,
17
ILS1–3
10
µA
2, 3,
12, 13,
15, 28
Output leakage
current
VHS1-3 = 0V
all output stages off
5.5
5.7
IHS1–3
–10
µA
mJ
A
D
A
A
A
8, 12,
14 to
17
Inductive shutdown
energy
Woutx
15
8, 12,
14 to
17
Output voltage edge
steepness
dVLS1–3/dt
dVHS1–3/dt
5.8
50
650
200
950
400
mV/µs
mA
Overcurrentlimitation
and shutdown
threshold
8, 15,
17
5.9
ILS1–3
1250
–650
Overcurrentlimitation
and shutdown
threshold
12, 14,
16
5.10
IHS1–3
–1250
–950
100
mA
Input register
bit 14 (SCT) = high
bit 14 (SCT) = low
Overcurrent
shutdown delay time
5.11
5.12
tdSd
tdSd
70
8.75
140
17.5
ms
ms
A
A
Open load detection
current
Input register bit 13
(OLD) = low, output off
8, 15,
17
ILS1–3
60
200
µA
A
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note: 1. Delay time between rising edge of CS after data transmission and switch on/off output stages to 90% of final level
9
4670E–BCD–04/09
8. Electrical Characteristics (Continued)
7.5V < VVS < VOV; 4.5V < VVCC < 5.5V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins.
No.
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
Open load detection
current
Input register bit 13
(OLD) = low, output off
12, 14,
16
5.13
IHS1–3
–150
–30
µA
A
Open load detection
current ratio
ILS1–3/
IHS1–3
5.14
5.15
5.16
5.17
1.2
0.6
0.6
A
A
A
A
A
Open load detection
threshold
Input register bit 13
(OLD) = low, output off
8, 15,
17
VLS1–3
2
2
V
V
Open load detection
threshold
Input register bit 13
(OLD) = low, output off
12, 14,
16
VVS–
VHS1–3
Output switch on
delay(1)
RLoad = 1 kΩ
RLoad = 1 kΩ
tdon
tdoff
0.5
1
ms
ms
Output switch off
delay(1)
5.18
6
Inhibit Input
Input voltage low
level threshold
0.3 ×
VVCC
6.1
5
5
VIL
VIH
V
V
A
A
Input voltage high
level threshold
0.7 ×
VVCC
6.2
6.3
Hysteresis of input
voltage
5
5
ΔVI
100
10
700
80
mV
µA
A
A
6.4
Pull-down current
VINH = VVCC
IPD
7
Serial Interface – Logic Inputs DI, CLK, CS
Input voltage
low-level threshold
0.3 ×
VVCC
7.1
7.2
7.3
7.4
2-4
2-4
2-4
2, 4
3
VIL
VIH
V
V
A
A
A
A
A
Input voltage
high-level threshold
0.7 ×
VVCC
Hysteresis of input
voltage
ΔVI
50
2
500
50
mV
µA
µA
Pull-down current pin
VDI, VCLK = VVCC
DI, CLK
IPDSI
IPUSI
Pull-up current
VCS = 0V
7.5
8
–50
–2
pin CS
Serial Interface - Logic Output DO
Output voltage low
level
8.1
I
I
OL = 3 mA
18
18
18
VDOL
VDOH
IDO
0.5
V
V
A
A
A
Output voltage high
level
VVCC
–1V
8.2
8.3
OL = –2 mA
Leakage current
(tri-state)
VCS = VVCC,
0 V < VDO < VVCC
–10
10
µA
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Delay time between rising edge of CS after data transmission and switch on/off output stages to 90% of final level
10
T6817
4670E–BCD–04/09
T6817
9. Serial Interface - Timing
Timing
Parameters
Test Conditions
Chart No.
Symbol
tENDO
tDISDO
tDOf
Min.
Typ.
Max.
Unit
ns
DO enable after CS falling edge
DO disable after CS rising edge
DO fall time
CDO = 100 pF
CDO = 100 pF
CDO = 100 pF
CDO = 100 pF
CDO = 100 pF
1
2
200
200
100
100
200
ns
–
ns
DO rise time
–
tDOr
ns
DO valid time
10
4
tDOVal
tCSSethl
tCSSetlh
ns
CS setup time
225
225
ns
CS setup time
8
ns
Input register bit 14
(SCT) = high
CS high time
CS high time
9
9
tCSh
tCSh
140
ms
ms
Input register bit 14
(SCT) = low
17.5
CLK high time
CLK low time
CLK period time
CLK setup time
CLK setup time
DI setup time
DI hold time
5
6
tCLKh
tCLKl
225
225
500
225
225
40
ns
ns
ns
ns
ns
ns
ns
–
tCLKp
7
tCLKSethl
tCLKSetlh
tDIset
3
11
12
tDIHold
40
11
4670E–BCD–04/09
Figure 9-1. Serial Interface Timing with Chart Numbers
1
2
CS
DO
9
CS
4
7
CLK
5
3
6
8
DI
11
CLK
10
12
DO
Inputs DI, CLK, CS: High level = 0.7 VCC, low level = 0.3 VCC
Output DO: High level = 0.8 VCC, low level = 0.2 VCC
12
T6817
4670E–BCD–04/09
T6817
10. Application
Figure 10-1. Application Circuit
Vcc
Enable
U5021M
Watchdog
M
M
HS3
HS2
HS1
Vs
12
14
16
BYT41D
Osc
Fault
detect
Fault
detect
Fault
detect
VS
VS
6
7
V
Batt
13 V
+
+
DI
V
S
2
4
OV-
protection
S
O
H
S
3
L
S
3
H
S
2
L
S
2
H
L
S
1
S
R
R
n. n. n. n. n. n.
u. u. u. u. u. u.
CLK
C
T
L
S
S
I
D
1
Vcc
Vcc
19
V
S
VCC
Input register
Control
logic
5 V
UV-
CS
Serial interface
protection
3
5
Output register
μC
INH
n. n. n. n. n. n.
P
S
F
I
S
C
D
H
S
3
L
S
3
H
S
2
L
S
2
H
L
T
P
u. u. u. u. u. u.
N
H
S
S
GND
GND
Power-on
reset
1
1
1
DO
Vcc
10
18
GND
GND
GND
11
13
20
Fault
detect
Fault
detect
Fault
detect
Thermal
protection
8
15
17
LS3
LS2
LS1
10.1 Application Notes
It is strongly recommended that the blocking capacitors at VCC and VS be connected as close as
possible to the power supply and GND pins.
Recommended value for capacitors at VS:
Electrolythic capacitor C > 22 µF in parallel with a ceramic capacitor C = 100 nF. Value for elec-
trolytic capacitor depends on external loads, conducted interferences and reverse conducting
current IHSX (see: Absolute Maximum Ratings).
Recommended value for capacitors at VCC
:
Electrolythic capacitor C > 10 µF in parallel with a ceramic capacitor C = 100 nF.
To reduce thermal resistance it is recommended that cooling areas be placed on the PCB as
close as possible to GND pins.
13
4670E–BCD–04/09
11. Ordering Information
Extended Type Number
Package
Remarks
T6817-TKSY
SSO20
SSO20
Power package, tube, Pb-free
Power package, taped and reeled, Pb-free
T6817-TKQY
12. Package Information
5.4±0.2
4.4±0.1
6.75-0.25
6.45±0.15
0.25±0.05
0.65±0.05
5.85±0.05
20
11
Package: SSO20
Dimensions in mm
technical drawings
according to DIN
specifications
1
10
Drawing-No.: 6.543-5056.01-4
Issue: 1; 10.03.04
14
T6817
4670E–BCD–04/09
T6817
13. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision
mentioned, not to this document.
Revision No.
History
• Put datasheet in a new template
• Maximum Ratings table changed
4670E-BCD-04/09
• Put datasheet in a new template
4670D-BCD-04/07
• Pb-free logo on page 1 deleted
• Table 8 “Electrical Characteristics” number 5.11 on page 9 changed
• Pb-free logo on page 1 added
4670C-BCD-09/05
4670B-BCD-05/05
• Table “Ordering Information” on page 14 changed
• Put datasheet in a new template
• Table “Electrical Characteristics” rows 5.15 and 5.16 changed
15
4670E–BCD–04/09
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International
Atmel Corporation
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San Jose, CA 95131
USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
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78054
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Sales Contact
www.atmel.com
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4670E–BCD–04/09
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