TSX8308500GL_技术文档

Main Features

• 8-bit Resolution

• 500 Msps (min) Sampling Rate

• Power Consumption: 3.8W Typ

• 500 mVpp Differential or Single-ended Analog Inputs

• Differential or Single-ended 50Ω ECL Compatible Clock Inputs

• ECL or LVDS/HSTL Output Compatibility

• ADC Gain Adjust

• Data Ready Output with Asynchronous Reset

• Gray or Binary Selectable Output Data; NRZ Output Mode

• Enhanced CBGA Package with Ceramic Lid

• Evaluation Board: TSEV8308500GL (Detailed Specification on Request)

• Demultiplexer TS81102G0: Companion Device Available

ADC 8-bit

500 Msps

Performance

• 1.3 GHz Full Power Input Bandwidth

• Band Flatness: 0.5 dB up to 500 MHz

• SINAD = 45 dB (7.2 Effective Bits), SFDR = 54 dBc

at F_S= 500 Msps, F_IN= 20 MHz

TS8308500

• SINAD = 43 dB (7.1 Effective Bits), SFDR = 53 dBc

at F_S= 500 Msps, F_IN= 250 MHz

• SINAD = 42 dB (7.0 Effective Bits), SFDR = 52 dBc

at F_S= 500 Msps, F_IN= 500 MHz (-3 dB FS)

• 2-tone IMD: TBD (199.5 MHz, 200.5 MHz) at 500 Msps

• DNL = ±0.3 LSB INL = ±0.7 LSB

• Low Bit Error Rate (10^-13) at 500 Msps, Tj = 90°C

Applications

•

Digital Sampling Oscilloscopes

Satellite Receiver

Electronic Countermeasures/Electronic Warfare

Direct RF Down-conversion

Screening

•

Atmel Standard Screening Level

•

Temperature Range:

–

0°C < Tc; Tj < +90°C

-40°C < Tc ; Tj < + 110°C

Description

The TS8308500 is a monolithic 8-bit analog-to-digital converter, designed for digitizing

wide bandwidth analog signals at very high sampling rates of up to 500 Msps.

The TS8308500 is using an innovative architecture, including an on-chip Sample and

Hold (S/H), and is fabricated with an advanced high-speed bipolar process.

The on-chip S/H has a 1.3 GHz full power input bandwidth, providing excellent

dynamic performance in undersampling applications (High IF digitizing).

Rev. 2193A–BDC–046/03

1

Functional

Description

Block Diagram

Figure 1. Simplified Block Diagram

GAIN

Analog

Encoding

Block

V_INV_INB

,

4

Resistor

Chain

Interpolation

Stages

Master/Slave Track & Hold Amplifier

5

4

Regeneration

Latches

Error Correction &

Decode Logic

CLK, CLKB

Clock

Buffer

8

Output Latches &

Buffers

8

GORB

DATA, DATAB OR, ORB

DRRB DR, DRB

Functional

Description

The TS8308500 is an 8-bit 500 Msps ADC based on an advanced high-speed bipolar technol-

ogy featuring a cutoff frequency of 25 GHz.

The TS8308500 includes a front-end master/slave Track and Hold stage (S/H), followed by an

analog encoding stage and interpolation circuitry.

Successive banks of latches are regenerating the analog residues into logical data before

entering an error correction circuitry and a resynchronization stage followed by 75Ω differential

output buffers.

The TS8308500 works in fully differential mode from analog inputs up to digital outputs.

The TS8308500 features a full-power input bandwidth of 1.3 GHz.

Control pin GORB is provided to select either the Gray or Binary data output format.

The gain control pin is provided in order to adjust the ADC gain.

A Data Ready output asynchronous reset (DRRB) is available on TS8308500.

The TS8308500 uses only vertical isolated NPN transistors together with oxide isolated poly-

silicon resistors, which allow enhanced radiation tolerance (no performance drift measured at

150 kRad total dose).

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TS8308500

2193A–BDC–04/03

TS8308500

Specifications

Absolute

Maximum Ratings

Table 1. Absolute Maximum Ratings

Parameter

Symbol

V_CC

Comments

Value

Unit

V

Positive supply voltage

GND to 6

GND to -5.7

GND -0.3 to 2.8

GND to -6

0.3

Digital negative supply voltage

Digital positive supply voltage

Negative supply voltage

DV_EE

V

V_PLUSD

V_EE

V

Maximum difference between negative supply voltages

Analog input voltages

DV_EEto V_EE

V

_INor V_INB

-1 to 1

V

Maximum difference between V_INand V_INB

Digital input voltage

V_IN- V_INB

-2 to 2

V

V_D

V_O

GORB

DRRB

-0.3 to V_CC0.3

V_EE-0.3 to 0.9

V_PLUSD-3 to V_PLUSD-0.5

-3 to 1.5

V

Digital input voltage

V

Digital output voltage

V

Clock input voltage

V_CLKor V_CLKB

V

Maximum difference between V_CLKand V_CLKB

Maximum junction temperature

Storage temperature

V_CLK- V_CLKB

-2 to 2

V

T_j

135

°C

T_stg

T_leads

-65 to 150

300

Lead temperature (soldering 10s)

Note:

Absolute maximum ratings are limiting values (referenced to GND = 0V), to be applied individually, while other parameters are

within specified operating conditions. Long exposure to maximum ratings may affect device reliability. The use of a thermal heat

sink is mandatory (see Thermal characteristics).

Recommended

Conditions of Use

Table 2. Recommended Conditions of Use

Recommended Value

Parameter

Symbol

V_CC

Comments

Min

Typ

5

Max

Unit

V

Positive supply voltage

Positive digital supply voltage

Negative supply voltages

4.75

–

5.25

–

V_PLUSD

ECL output compatibility

LVDS output compatibility

GND

2.4

-5

V

1.4

2.6

V

_EE,DV_EE

_IN,V_INB

-5.25

-4.75

V

Differential analog input voltage

(full-scale)

V

50Ω differential or single-ended

50Ω single-ended clock input

±113

450

±125

500

±137

550

mV

V_IN- V_INB

mVpp

Clock input power level

P

_CLK,P_CLKB

3

4

10

dBm

Operating temperature range

Commercial grade: “C”

Industrial grade “V“

0 < Tc; Tj < 90

°C

T_J

-40 < Tc; Tj < 110

3

2193A–BDC–04/03

Electrical

V_EE= DV_EE= -5V; V_CC= +5V; V_IN-V_INB= 500 mVpp Full Scale differential input

Operating

Characteristics

50Ω differentially terminated digital outputs

Tj (typical) = 70°C

Table 3. Electrical Specifications

Value

Typ

Test

Level

Parameter

Power Requirements

Symbol

Min

Max

Unit

Note

Positive supply voltage

Analog

Digital (ECL)

Digital (LVDS)

V_CC

1

4

4.5

–

5

0

5.5

–

V

V_PLUSD

1.4

2.4

2.6

Positive supply current

Analog

Digital

I_CC

1

–

420

130

445

145

mA

I_PLUSD

Negative supply voltage

Negative supply current

V_EE

1

-5.5

-5

-4.5

V

Analog

Digital

AI_EE

DI_EE

1

–

185

160

200

180

mA

Nominal power dissipation

Power supply rejection ratio

Resolution

PD

PSRR

–

1

4

–

3.9

0.5

–

4.1

2

W

mW

bits

(2)

8

Analog Inputs

Full-scale input voltage range (differential mode)

(0V common mode voltage)

V_IN

4

–

-125

–

125

mV

V_INB

Full-scale input voltage range (single-ended input

option) ⁽¹⁴⁾

V_IN

4

–

-250

–

0

250

–

mV

V_INB

Analog input capacitance

Input bias current

C_IN

I_IN

4

–

3

3.5

20

–

pF

µA

10

1

Input Resistance

R_IN

0.5

–

MΩ

GHz

Full Power input Bandwidth (-3 dB)

Small signal input Bandwidth (10% full-scale)

Clock Inputs

FPBW

SSBW

1.8

1.7

–

Logic compatibility for clock inputs ⁽¹⁴⁾

ECL or specified clock input

power level in dBm

(8)

–

ECL Clock inputs voltages (V_CLKor V_CLKB):

Logic 0 voltage

–

V_IL

V_IH

I_IL

4

–

-1.5

–

V

–

Logic 1 voltage

-1.1

–

V

Logic 0 current

5

50

µA

–

Logic 1 current

I_IH

–

5

Clock input power level into 50Ω termination

dBm into 50Ω

4

TS8308500

2193A–BDC–04/03

TS8308500

Table 3. Electrical Specifications (Continued)

Value

Typ

4

Test

Level

Parameter

Clock input power level

Clock input capacitance

Digital Outputs

Symbol

–

Min

-2

Max

10

Unit

dBm

pF

Note

4

C_CLK

–

3

3.5

(1)(6)

Single-ended or differential input mode, 50% clock duty cycle (CLK, CLKB), binary output data format,

Tj (typical) = 70°C. Full temperature range: 0°C < Tc; Tj < +90°C or -40°C < Tc ; Tj < 110°C

Logic compatibility for digital outputs

–

4

ECL or LVDS

–

(14)

(Depending on the value of V_PLUSD

)

Differential output voltage swings

(assuming V_PLUSD= 0V):

–

75Ω open transmission lines (ECL levels)

75Ω differentially terminated

–

1.5

1.620

0.825

0.660

–

V

0.70

0.54

50Ω differentially terminated

Output levels (assuming V_PLUSD= 0V)

(6)

–

4

–

75Ω open transmission lines:

Logic 0 voltage

Logic 1 voltage

V_OL

V_OH

–

-1.62

-0.8

-1.54

–

V

-0.88

Output levels (assuming V_PLUSD= 0V)

–

4

–

75Ω differentially terminated:

Logic 0 voltage

Logic 1 voltage

V_OL

V_OH

–

-1.41

-1

-1.34

–

V

-1.07

Output levels (assuming V_PLUSD= 0V)

–

50Ω differentially terminated:

Logic 0 voltage

V_OL

V_OH

DOS

–

1, 2

4

–

-1.16

270

–

-1.40

-1.10

300

–

-1.32

–

V

Logic 1 voltage

Differential Output Swing

Output level drift with temperature

DC Accuracy

–

mV

4

1.6

mV/°C

Single-ended or differential input mode, 50% clock duty cycle (CLK, CLKB), Binary output data format

Tj (typical) = 70°C

(2)(3)

(3)

Differential non linearity

Integral non linearity

No missing codes

Gain

DNL-

DNL+

INL-

INL+

–

1

-0.6

–

-0.4

0.4

–

lsb/V

0.6

–

-1.2

–

-0.7

0.7

1.2

Guaranteed over specified temperature range

–

1, 2

90

98

-5

110

26

%/V

Input offset voltage

–

-26

mV/V

5

2193A–BDC–04/03

Table 3. Electrical Specifications (Continued)

Value

Typ

Test

Level

Parameter

Symbol

Min

Max

Unit

Note

Gain error drift

Offset error drift

–

4

100

40

125

50

150

60

ppm/°C

Transient Performance

Bit error rate

Error/

sample

(2)(4)

BER

4

–

1E-13

F_S= 500 Msps, F_IN= 62.5 MHz

ADC settling time

(2)

TS

4

–

0.5

1

ns

V_IN-V_INB= 400 mVpp

Overvoltage recovery time

TOR

AC Performance

Single-ended or differential input and clock mode, 50% clock duty cycle (CLK, CLKB), binary output data format,

Tj = 70°C, unless otherwise specified

(2)

Signal to noise and distortion ratio

F_S= 500 Msps, F_IN= 20 MHz

F_S= 500 Msps, F_IN= 500 MHz

F_S= 500 Msps, F_IN= 1000 MHz (-1 dBFS)

F_S= 50 Msps, F_IN= 25 MHz

Effective number of bits

SINAD

–

4

1

–

4

1

–

4

1

–

43

42

38

43

–

45

44

40

46

–

dB

–

ENOB

F_S= 500 Msps, F_IN= 20 MHz

F_S= 500 Msps, F_IN= 500 MHz

F_S= 500 Msps, F_IN= 1000 MHz (-1 dBFS)

F_S= 50 Msps, F_IN= 25 MHz

Signal to noise ratio

–

7.0

6.8

6.0

7.0

–

7.2

7.0

6.3

7.4

–

Bits

–

(2)

SNR

F_S= 500 Msps, F_IN= 20 MHz

F_S= 500 Msps, F_IN= 500 MHz

F_S= 500 Msps, F_IN= 1000 MHz (-1 dBFS)

F_S= 50 Msps, F_IN= 25 MHz

Total harmonic distortion

–

44

40

44

–

46

45

43

45

–

dB

–

(2)

|THD|

–

F_S= 500 Msps, F_IN= 20 MHz

4

50

53

–

dB

F_S= 500 Msps, F_IN= 500 MHz

F_S= 500 Msps, F_IN= 1000 MHz (-1 dBFS)

F_S= 50 Msps, F_IN= 25 MHz

–

4

1

48

38

44

50

40

54

–

dB

6

TS8308500

2193A–BDC–04/03

TS8308500

Table 3. Electrical Specifications (Continued)

Value

Typ

–

Test

Level

Parameter

Spurious free dynamic range

Symbol

Min

–

Max

–

Unit

–

Note

(2)

SFDR

–

4

1

4

F_S= 500 Msps, F_IN= 20 MHz

–

50

38

50

–

56

–

dBc

–

F_S= 500 Msps, F_IN= 500 MHz

F_S= 500 Msps, F_IN= 1000 MHz (-1 dBFS)

F_S= 50 Msps, F_IN= 25 MHz

53

–

40

–

55

–

(2)

Two-tone inter-modulation distortion

F_IN1= 199.5 MHz at F_S= 500 Msps,

IMD

–

-47

-52

–

dBc

F

_IN2= 200.5 MHz at F_S= 500 Msps

Switching Performance and Characteristics – See Figure 2 and Figure 3 on page 9

(12)

(13)

Maximum clock frequency

Minimum clock frequency

Minimum clock pulse width (high)

Minimum clock pulse width (low)

Aperture delay

F_S

–

4

500

10

–

700

50

Msps

ns

TC1

TC2

Ta

1.71

100

–

2

50

2

50

ns

(2)

+250

0.4

400

0.6

ps

(2)(5)

Aperture uncertainty

Jitter

ps (rms)

(2)(8)

Data output delay

TDO

4

1150

1360

1660

ps

(9)(10)

(9)

Output rise/fall time for data (20%-80%)

Output rise/fall time for data ready (20%-80%)

Data ready output delay

TR/TF

4

250

350

550

ps

(2)(8)

TDR

TRDR

4

1110

1320

720

40

1620

1000

80

ps

(9)(10)

Data ready reset delay

–

0

(7)(11)

(12)

Data to data ready – Clock low pulse width

(See “Timing Diagrams” on page 9)

TOD-TDR

Data to data ready output delay (50% duty cycle) at

1 Gsps (See “Timing Diagrams” on page 9)

(2)(13)

TD1

TPD

4

920

960

4

1000

ps

clock

cycles

Data pipeline delay

Notes: 1. Differential output buffers are internally loaded by 75Ω resistors. Buffer bias current = 11 mA

2. See “Definition of Terms” on page 46

3. Histogram testing based on sampling of a 10 MHz sinewave at 50 Msps

4. Output error amplitude < ±4 lsb around worst code

5. Maximum jitter value obtained for single-ended clock input on the die (chip on board): 200 fs

6. Digital output back termination options depicted in Application Notes

7. At 500 Msps, 50/50 clock duty cycle, TC2 = 2 ns (TC1). TDR - TOD = -100 ps (typ) does not depend on the sampling rate

8. Specified loading conditions for digital outputs:

- 50Ω or 75Ω controlled impedance traces properly 50/75Ω terminated, or unterminated 75Ω controlled impedance traces

- Controlled impedance traces far end loaded by 1 standard ECLinPS register from Motorola. (i.e.: 10E452) (Typical input

parasitic capacitance of 1.5 pF including package and ESD protections.)

9. Termination load parasitic capacitance derating values:

- 50Ω or 75Ω controlled impedance traces properly 50/75Ω terminated: 60 ps/pF or 75 ps per additionnal ECLinPS load

7

2193A–BDC–04/03

- Unterminated (source terminated) 75Ω controlled impedance lines: 100 ps/pF or 150 ps per additionnal ECLinPS termina-

tion load

10. Apply proper 50/75Ω impedance traces propagation time derating values: 6 ps/mm (155 ps/inch) for TSEV8308500GL Eval-

uation Board

11. Values for TOD and TDR track each other over temperature, (1% variation for TOD-TDR per 100°C temperature variation).

Therefore TOD-TDR variation over temperature is negligible. Moreover, the internal (on-chip) and package skews between

each Data TODs and TDR effect can be considered negligible. Consequently, minimum values for TOD and TDR are never

more than 100 ps apart. The same is true for the TOD and TDR maximum values (see Advanced Application Notes about

“TOD-TDR Variation Over Temperature” on page 22).

12. Min value guarantees performance. Max value guarantees functionality

13. Min value guarantees functionality. Max value guarantees performance

14. Refer to product Application Notes

8

TS8308500

2193A–BDC–04/03

TS8308500

Timing Diagrams

Figure 2. TS8308500 Timing Diagram (500 Msps Clock Rate), Data Ready Reset, Clock Held at LOW Level

TA = 250 ps

X

N+5

X

N+4

X

N+3

X

N+2

X

N+1

X

N

(V_IN,V_INB

)

X

N-1

TC = 1000 ps

TC1 TC2

(CLK, CLKB)

TOD = 1360 ps

TPD: 4.0 Clock periods

1360 ps

DIGITAL

OUTPUTS

1000 ps

DATA

N-5

DATA

N-4

DATA

N-3

DATA

N-2

DATA

N-1

DATA

N

DATA

N+1

TD1 = TC1+TDR-TOD

= TC1-40 ps = 460 ps

TDR = 1320 ps

Data Ready

(DR, DRB)

TD2 = TC2+TOD-TDR

= TC2+40 ps = 540 ps

TRDR = 720 ps

DRRB

1 ns (min)

Figure 3. TS8308500 Timing Diagram (500 Msps Clock Rate), Data Ready Reset, Clock Held at HIGH Level

TA = 250 ps

X

N+5

X

N+4

X

N+3

X

N+2

N+1

N

(V_IN, V_INB

)

X

N-1

TC = 1000 ps

TC1 TC2

(CLK, CLKB)

TPD: 4.0 Clock periods

TOD = 1360 ps

1360 ps

1000 ps

DIGITAL

OUTPUTS

DATA

N-5

DATA

N-4

DATA

N-3

DATA

N-2

DATA

N-1

DATA

N

DATA

N+1

TD1 = TC1+TDR-TOD

= TC1-40 ps = 460 ps

TDR = 1320 ps

Data Ready

(DR, DRB)

TD2 = TC2+TOD-TD

= TC2+40 ps = 540

TRDR = 720 ps

DRRB

1 ns (min)

9

2193A–BDC–04/03

Explanation of

Test Levels

Table 4. Explanation of Test Levels⁽³⁾

Num

Characteristics

1

100% production tested at +25°C⁽¹⁾(for “C” Temperature range⁽²⁾)

100% production tested at +25°C⁽¹⁾, and sample tested at specified temperatures

2

3

4

5

(for “V” Temperature range⁽²⁾)

Sample tested only at specified temperatures

Parameter is guaranteed by design and characterization testing (thermal steady-state

conditions at specified temperature)

Parameter is a typical value only

Note:

1. Unless otherwise specified, all tests are pulsed tests : therefore T_C= T_Awhere T_Cand T_Aare

case and ambient temperature.

2. Refer to “Ordering Information” on page 48.

3. Only min and max values are guaranteed (typical values are issued from characterization

results).

Functions

Description

Table 5. Functions Description

Name

V_CC

Function

Positive power supply

Analog negative power supply

Digital positive power supply

Ground

VPLUSD = +0V (ECL)

V_EE

VCC = +5V

VPLUSD = +2.4V (LVDS)

V_PLUSD

GND

V_IN

OR

V_IN, V_INB

CLK, CLKB

Differential analog inputs

Differential clock inputs

Differential output data port

V_INB

ORB

CLK

CLKB

GAIN

<D0:D7>

D0

16

D7

D7B

TS8308500

D0B

<D0B:D7B>

DR

DR, DRB

OR, ORB

GAIN

Differential data ready outputs

Out of range outputs

GORG

DRB

DIOD/

DRRB

ADC gain adjust

GORB

Gray or binary digital output select

Die junction temperature measurement/

asynchronous data ready reset

DVEE = -5V VEE = -5V

GND

DIOD/DRRB

10

TS8308500

2193A–BDC–04/03

TS8308500

Digital Output

Coding

NRZ (Non Return to Zero) mode, ideal coding: does not include gain, offset, and linearity volt-

age errors.

Table 6. Digital Output Coding

Digital Output

Binary

Gray

Differential

Analog Input

Out of

Range

Voltage Level

GORB = VCC or Floating

GORB = GND

> +251 mV

> Positive full-scale + 1/2 LSB

1 1 1 1 1 1 1 1

1 0 0 0 0 0 0 0

1

+251 mV

+249 mV

Positive full-scale + 1/2 LSB

Positive full-scale - 1/2 LSB

1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 0

1 0 0 0 0 0 0 0

1 0 0 0 0 0 0 1

0

+126 mV

+124 mV

Positive 1/2 scale + 1/2 LSB

Positive 1/2 scale - 1/2 LSB

1 1 0 0 0 0 0 0

1 0 1 1 1 1 1 1

1 0 1 0 0 0 0 0

1 1 1 0 0 0 0 0

0

+1 mV

-1 mV

Bipolar zero + 1/2 LSB

Bipolar zero - 1/2 LSB

1 0 0 0 0 0 0 0

0 1 1 1 1 1 1 1

1 1 0 0 0 0 0 0

0 1 0 0 0 0 0 0

0

-124 mV

-126 mV

Negative 1/2 scale + 1/2 LSB

Negative 1/2 scale - 1/2 LSB

0 1 0 0 0 0 0 0

0 0 1 1 1 1 1 1

0 1 1 0 0 0 0 0

0 0 1 0 0 0 0 0

0

-249 mV

-251 mV

Negative full-scale + 1/2 LSB

Negative full-scale - 1/2 LSB

0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0

0

< -251 mV

< Negative full-scale - 1/2

LSB

0 0 0 0 0 0 0 0

1

11

2193A–BDC–04/03

Typical

Characterization

Results

50/50 clock duty cycle, Binary output coding, Tj = 70°C, single-ended analog and clock inputs,

unless otherwise specified.

Static Linearity

F_S= 50 Msps/F_IN= 10 MHz

Figure 4. Integral Non-linearity

Note:

Clock frequency = 50 Msps; signal frequency = 10 MHz

Positive peak: -0.68 LSB; Negative peak: -0.69 LSB

Figure 5. Differential Non-linearity

Note:

Clock frequency = 50 Msps; signal frequency = 10 MHz;

Positive peak: 0.3 LSB; negative peak: -0.29 LSB

12

TS8308500

2193A–BDC–04/03

TS8308500

Effective Number

of Bits Versus

Power Supply

Variation

Figure 6. Effective Number of Bits = f (V_EEA); F_S= 500 Msps; F_IN= 100 MHz

8

7

6

5

4

3

2

1

0

-7

-6.5

-6

-5.5

-5

-4.5

-4

VEEA (V)

Figure 7. Effective Number of Bits = f (V_CC); F_S= 500 Msps; F_IN= 100 MHz

8

7

6

5

4

3

2

1

0

3

3.5

4

4.5

5

5.5

6

6.5

7

VCC (V)

Figure 8. Effective Number of Bits = f (V_EED); F_S= 500 Msps; F_IN= 100 MHz

8

7

6

5

4

3

2

1

0

-6

-5.5

-5

-4.5

-4

-3.5

-3

VEED (V)

13

2193A–BDC–04/03

Typical FFT

Results

Figure 9. Spectrum for F_S= 500 Msps, F_IN= 498 MHz (Full Scale Input)

Note:

Acquisition of 4096 points; THD = -49.67 dBc; F_s= 500 Msps; SINAD = 44.01 dB; F_IN= 498 MHz; SFDR = -54.31 dBc;

SFSR = -0.94 dB; ENOB = 7.13 bits; SNR = 45.39 dB

Figure 10. Reconstructed Signal for F_S= 500 Msps, F_IN= 498 MHz (Full Scale Input)

LSB

250

200

150

100

50

0

1

ns

Note:

Acquisition of 4096 samples; F_S= 500 Msps; Amplitude: 0.221V (114.5 LSB); F_IN= 498 MHz; Offset: 0V (122.5 LSB)

14

TS8308500

2193A–BDC–04/03

TS8308500

Figure 11. Spectrum for F_S= 500 Msps, F_IN= 250 MHz (Full Scale Input)

Figure 12. Reconstructed Signal for F_S= 500 Msps, F_IN= 250 MHz (Full Scale Input)

Lsb

250

200

150

100

50

0

1

2

3

ns

Note:

Acquisition of 4096 samples; F_S= 500 Msps ; Amplitude: 0.189V (113.5 LSB); F_IN= 250 MHz ; Offset: 0V (122.5 LSB)

15

2193A–BDC–04/03

Dynamic

Performance

Versus Analog

Input Frequency

Figure 13. SFDR: F_s= 500 Msps, F_IN= 20 MHz up to 1000 MHz, -1dB Full Scale Input, Tj = 70°C

SFDR

60

55

50

45

40

2

100

200

300

400

500

600

700

800

900

1000

Fin (MHz)

Figure 14. THD: Fs = 500 Msps, F_IN= 20 MHz up to 1000 MHz, -1dB Full Scale Input, Tj = 70°C

THD

-60

-50

-40

-30

-20

-10

0

2

100

200

300

400

500

600

700

800

900

1000

Fin (MHz)

Figure 15. SINAD and SNR: Fs = 500 Msps, F_IN= 20 MHz up to 1000 MHz, -1dB Full Scale Input, Tj = 70°C

SINAD

SNR

48

46

44

42

40

38

36

2

100

200

300

400

500

Fin (MHz)

600

700

800

900

1000

16

TS8308500

2193A–BDC–04/03

TS8308500

Figure 16. Fs = 500 Msps, F_IN= 20 MHz up to 1000 MHz, -1dB Full Scale Input, Tj = 70°C

ENOB

7,5

7

6,5

6

5,5

2

100

200

300

400

500

600

700

800

900

1000

Fin (MHz)

SFDR and THD

Versus Sampling Frequency

Figure 17. Analog Input Frequency: F_IN= 250 MHz and Fs = 200 Msps to 1400 Msps

SFDR

THD

-60

-50

-40

-30

-20

-10

200

400

600

800

1000

1200

1400

Fs (Msps)

Effective Number of Bits (ENOB)

Versus Sampling Frequency

Figure 18. Analog Input Frequency: F_IN= 250 MHz and Fs = 200 Msps to 1400 Msps

ENOB

8

7

6

5

4

3

2

1

200

400

600

800

1000

1200

1400

Fs Msps

17

2193A–BDC–04/03

Sinad and SNR

Versus Sampling Frequency

Figure 19. Analog Input Frequency: F_IN= 250 MHz and F_S= 200 Msps to 1400 Msps

SINAD

SNR

50

45

40

35

30

25

20

15

10

200

400

600

800

1000

1200

1400

Fs (Msps)

TS8308500 ADC Performances

Versus Junction Temperature

Figure 20. SFDR: F_S= 500 Msps, F_IN= 250 MHz, -1dB Full Scale Input, Tj = 0°C to 125°C

SFDR

53.0

52.5

52.0

51.5

51.0

50.5

50.0

25

0

50

75

100

125

Tj(°C)

18

TS8308500

2193A–BDC–04/03

TS8308500

Figure 21. THD: F_S= 500 Msps, F_IN= 250 MHz, -1dB Full Scale Input, Tj = 0°C to 125°C

THD

-60

-50

-40

-30

-20

-10

0

25

50

75

100

125

Tj (°C)

Figure 22. SINAD and SNR: F_S= 500 Msps, F_IN= 250 MHz, -1dB Full Scale Input, Tj = 0°C to 125°C

SINAD

SNR

46.5

46.0

45.5

45.0

44.5

44.0

43.5

0

25

50

75

100

125

Tj (°C)

Figure 23. ENOB: F_S= 500 Msps, F_IN= 250 MHz, -1dB Full Scale Input, Tj = 0°C to 125°C

ENOB

7.30

7.25

7.20

7.15

7.10

7.05

7.00

0

25

50

75

100

125

Tj (°C)

19

2193A–BDC–04/03

Figure 24. Power Consumption Versus Junction Temperature: F_S= 500 Msps; F_IN= 250 MHz; Duty cycle = 50%

5

4

3

2

1

0

-40

-20

0

20

40

60

80

100

120

140

160

Temperature (°C)

Typical Full Power

Input Bandwidth

Figure 25. Band Flatness at 1.3 GHz ; -3 dB (-2 dBm Full Power Input)

0

-1

-2

-3

-4

-5

-6

0

200

400

600

800

1000

1200

1400

1600

Frequency (MHz)

20

TS8308500

2193A–BDC–04/03

TS8308500

ADC Step

Response

Test pulse input characteristics: 20% to 80% input full scale and rise time ~ 200 ps.

Note: This step response was obtained with the TSEV8308500 chip on-board (device in die form).

Figure 26. Test Pulse Digitized with 20 GHz DSO

250

200

150

100

50

0

Vpp ~ 260 mV

Tr ~ 270 ps

50 mV/div

600 ps/div

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

Time (ns)

Figure 27. Same Test Pulse Digitized with TS8308500 ADC

200

150

Tr ~ 330 ps

50 codes/div (Vpp ~ 260 mV)

600 ps/div

100

50

0

0.6

1.2

1.8

2.4

3.0

3.6

4.2

4.8

5.4

6.0

Time (ns)

Note:

Ripples are due to the test setup (they are present on both measurements).

21

2193A–BDC–04/03

TS8308500

Main Features

Timing

Information

Timing Value for

TS8308500

Timing values as defined in Table 3 on page 4 are advanced data, issuing from electric simu-

lations and are the first characterization results fitted with measurements.

Timing values are given for CBGA68 package inputs/outputs, taking into account package

internal controlled impedance traces propagation delays, and specified termination loads.

Propagation delays in 50/75Ω impedance traces are NOT taken into account for TOD and

TDR.

Apply proper derating values corresponding to termination topology.

The min/max timing values are valid over the full temperature range in the following

conditions:

–

Specified termination load (differential output Data and Data Ready):

50Ω resistor in parallel with 1 standard ECLinPS register from Motorola, (i.e.:

10E452). (Typical ECLinPS inputs shows a typical input capacitance of 1.5 pF

(including package and ESD protections). If addressing an output Dmux, take care

if some Digital outputs do not have the same termination load and apply

corresponding derating value given below

–

Output Termination Load derating values for TOD and TDR:

~ 35 ps/pF or 50 ps per additional ECLinPS load

Propagation time delay derating values have also to be applied for TOD and TDR:

~ 6 ps/mm (155 ps/inch) for TSEV8308500 Evaluation Board

Apply proper time delay derating value if a different dielectric layer is used.

Propagation Time

Considerations

TOD and TDR timing values are given from pin to pin and DO NOT include the additional

propagation times between device pins and input/output termination loads. For the

TSEV8308500 Evaluation Board, the propagation time delay is 6 ps/mm (155 ps/inch) corre-

sponding to 3.4 (at 10 GHz) dielectric constant of the RO4003 used for the Board.

If a different dielectric layer is used (for instance Teflon), use appropriate propagation time

values.

TD does NOT depend on propagation times because it is a differential data.

(TD is the time difference between Data Ready output delay and digital Data output delay)

TD is also the most straightforward data to measure, again because it is differential: TD can be

measured directly onto termination loads, with matched oscilloscopes probes.

TOD-TDR Variation

Over Temperature

Values for TOD and TDR track each other over temperature (1% variation for TOD-TDR per

100°C temperature variation).

Therefore TOD-TDR variation over temperature is negligible. Moreover, the internal (on-chip)

and package skews between each Data TODs and TDR affect can be considered as

negligible.

22

TS8308500

2193A–BDC–04/03

TS8308500

Consequently, minimum values for TOD and TDR are never more than 100 ps apart. The

same is true for the TOD and TDR maximum values.

In other words:

–

If TOD is at 1150 ps, TDR will not be at 1620 ps (maximum time delay for TDR).

If TOD is at 1660 ps, TDR will not be at 1110 ps (minimum time delay for TDR).

However, external TOD-TDR values may be dictated by total digital data skews

between every TODs (each digital data) and TDR: MCM board , bonding wires and

output lines lengths differences, and output termination impedance mismatches.

The external (on board) skew effect has NOT been taken into account for the specification of

the minimum and maximum values for TOD-TDR.

Principle of Operation

The Analog input is sampled on the rising edge of the external clock input (CLK, CLKB) after

TA (aperture delay) of typically 250 ps .

The digitized data is available after 4 clock periods latency (pipeline delay (TPD), on clock ris-

ing edge, after 1360 ps typical propagation delay TOD.)

The Data Ready differential output signal frequency (DR, DRB) is half the external clock fre-

quency, that is it switches at the same rate as the digital outputs.

The Data Ready output signal (DR, DRB) switches on the external clock falling edge after a

propagation delay TDR of typically 1320 ps.

A Master Asynchronous Reset input command DRRB (ECL compatible single-ended input) is

available for initializing the differential Data Ready output signal (DR, DRB).

This feature is mandatory in certain applications using interleaved ADCs or using a single

ADC with demultiplexed outputs. Actually, without Data Ready signal initialization, it is impos-

sible to store the output digital data in a defined order.

Principle of Data

Ready Signal

Control by DRRB

Input Command

Data Ready Output

Signal Reset

The Data Ready signal is reset on the falling edge of the DRRB input command, on the ECL

logical low level (-1.8V). DRRB may also be tied to V_EE= -5V for Data Ready output signal

Master Reset. So long as DRRB remains at a logical low level, (or tied to V_EE= -5V), the Data

Ready output remains at logical zero and is independent of the external free running encoding

clock.

The Data Ready output signal (DR, DRB) is reset to logical zero after TRDR = 720 ps typical.

TRDR is measured between the -1.3V point of the falling edge of the DRRB input command

and the zero crossing point of the differential Data Ready output signal (DR, DRB).

The Data Ready Reset command may be a pulse of 1 ns minimum time width.

23

2193A–BDC–04/03

Data Ready Output

Signal Restart

The Data Ready output signal restarts on the DRRB command’s rising edge, ECL logical high

levels (-0.8V). DRRB may also be grounded, or is allowed to float, for a normal free running

Data Ready output signal.

The Data Ready signal restart sequence depends on the logical level of the external encoding

clock, at DRRB rising edge instant:

•

The DRRB rising edge occurs when the external encoding clock input (CLK,CLKB) is

LOW: The Data Ready output’s first rising edge occurs after half a clock period on the

clock falling edge, after a delay time TDR = 1320 ps already defined hereabove.

•

The DRRB rising edge occurs when external encoding clock input (CLK,CLKB) is HIGH:

The Data Ready output’s first rising edge occurs after one clock period on the clock falling

edge, and a delay TDR = 1320 ps.

Consequently, as the analog input is sampled on the clock’s rising edge, the first digitized data

corresponding to the first acquisition (N) after a Data Ready signal restart (rising edge) is

always strobed by the third rising edge of the Data Ready signal.

The time delay (TD1) is specified between the last point of a change in the differential output

data (zero crossing point) to the rising or falling edge of the differential Data Ready signal

(DR,DRB) (zero crossing point).

Note:

1. For normal initialization of the Data Ready output signal, the external encoding clock signal

frequency and level must be controlled. The minimum encoding clock sampling rate for the

ADC is 10 Msps and consequently the clock cannot be stopped.

2. One single pin is used for both the DRRB input command and die junction temperature

monitoring. Pin denomination will be DRRB/DIOD. (On former versions the denomination

was DIOD.). Temperature monitoring and Data Ready control by DRRB is not possible

simultaneously.

Analog Inputs (V_IN,

The analog input Full Scale range is 0.5V, or -2 dBm into the 50Ω termination resistor.

V_INB

)

In differential mode input configuration, that means 0.25V on each input, or ±125 mV around

0V. The input common mode is ground.

The typical input capacitance is 3 pF for TS8308500 in a CBGA package.

Differential Input

Voltage Span

Figure 28. Differential Input Voltage Span

[mV]

VIN

VINB

125

500 mV

Full Scale

250 mV

-250 mV

0V

analog input

-125

t

(VIN, VINB) = 250 mV = 500 mV diff

24

TS8308500

2193A–BDC–04/03

TS8308500

Differential Versus

Single-ended Analog

Input Operation

The TS8308500 can operate at full speed in either the differential or single-ended

configuration.

This is explained by the fact the ADC uses a high input impedance differential preamplifier

stage, (preceeding the sample and hold stage), which has been designed in order to be

entered either in differential mode or single-ended mode.

This is true so long as the out-of-phase analog input pin V_INBis 50Ω terminated very closely to

one of the neighboring shield ground pins (52, 53, 58, 59) which constitute the local ground

reference for the in-phase analog input pin (V_IN).

Thus the differential analog input preamplifier will fully reject the local ground noise (and any

capacitively and inductively coupled noise) as common mode effects.

In a typical single-ended configuration, enter on the (V_IN) input pin, with the inverted phase

input pin (V_INB) grounded through the 50Ω termination resistor.

In a single-ended input configuration, the in-phase input amplitude is 0.5V, centered on 0V (or

-2 dBm into 50Ω). The inverted phase input is at ground potential through the 50Ω termination

resistor.

However, dynamic performances can be somewhat improved by entering either analog or

clock inputs in differential mode.

Typical Single-ended

Analog Input

Configuration

Figure 29. Typical Single-ended Analog Input Configuration

[mV]

VIN or VINB double pad (pins 54, 55 or 56, 57)

VIN or VINB

V

IN

250

500 mV

Full Scale

VINB = 0V

1 MΩ

3 pF

50Ω

(on package)

analog input

VINB

-250

t

VIN = 250 mV = 500 mV diff

50Ω reverse termination

Clock Inputs (CLK,

CLKB)

The TS8308500 can be clocked at full speed without noticeable performance degradation in

either the differential or single-ended configuration.

This is explained by the fact the ADC uses a differential preamplifier stage for the clock buffer,

which has been designed in order to be entered either in differential or single-ended mode.

The recommended sinewave generator characteristics are typically -120 dBc/Hz phase noise

floor spectral density, at 1 kHz from carrier, assuming a single tone 4 dBm input for the clock

signal.

Single-ended Clock

Input (Ground

Common Mode)

Although the clock inputs were intended to be driven differentially with nominal -0.8V/-1.8V

ECL levels, the TS8308500 clock buffer can manage a single-ended sinewave clock signal

centered around 0V. This is the most convenient clock input configuration as it does not

require the use of a power splitter.

25

2193A–BDC–04/03

No performance degradation (i.e.: due to timing jitter) is observed in this particular single-

ended configuration up to 500 Msps Nyquist Conditions (F_IN= 250 MHz).

This is all the more so since the inverted phase clock input pin is 50Ω terminated on the pack-

age (that is very close to one of the neighboring shield ground pins, which constitutes the local

ground reference for the inphase clock input).

Thus the TS8308500 differential clock input buffer will fully reject the local ground noise (and

any capacitively and inductively coupled noise) as common mode effects. Moreover, a very

low phase noise sinewave generator must be used for enhanced jitter performance.

The typical in-phase clock input amplitude is 1V, centered on 0V (ground) common mode. This

corresponds to a typical clock input power level of 4 dBm into the 50Ω termination resistor. Do

not exceed 10 dBm to avoid saturation of the preamplifier input transistors.

Figure 30. Single-ended Clock Input (Ground Common Mode):

VCLK common mode = 0V; VCLKB = 0V; 4 dBm typical clock input power level (into 50Ω termination resistor)

CLK or CLKB double pad (pins 37, 38 or 39, 40)

[V]

VCLK

+0.5V

CLK or CLKB

1 MΩ

0.4 pF

50Ω

(on package)

VCLK = 0V

VCLK

-0.5V

t

50Ω reverse termination

Note:

Do not exceed 10 dBm into the 50Ω termination resistor for the single clock input power level.

Differential ECL Clock

Input

The clock inputs can be driven differentially with nominal -0.8V/-1.8V ECL levels.

In this mode, a low-phase noise sinewave generator can be used to drive the clock inputs, fol-

lowed by a power splitter (hybrid junction) in order to obtain 180° out of phase sinewave

signals. Biasing tees can be used for offseting the common mode voltage to ECL levels.

Note: As the biasing tees propagation times are not matching, a tunable delay line is required

in order to ensure the signals are 180° out of phase, especially at fast clock rates in the

500 Msps range.

Figure 31. Differential Clock Inputs (ECL Levels)

[mV]

CLK or CLKB double pad (pins 37, 38 or 39, 40)

CLK or CLKB

VCLK

-0.8V

VCLKB

1 MΩ

0.4 pF

Common mode = -1.3V

50Ω

(on package)

-2V

-1.8V

t

50Ω reverse termination

26

TS8308500

2193A–BDC–04/03

TS8308500

Single-ended ECL

Clock Input

In a single-ended configuration, enter at CLK (resp. CLKB) pin, with the inverted phase clock

input pin CLKB (respectively CLK) connected to -1.3V through the 50Ω termination resistor.

The in-phase input amplitude is 1V, centered on -1.3V common mode.

Figure 32. Single-ended Clock Input (ECL):

VCLK common mode = -1.3V; VCLKB = -1.3V

[V]

VCLK

-0.8V

VCLKB = -1.3V

-1.8V

t

Noise Immunity

Information

Circuit noise immunity performance begins at design level.

Efforts have been made to the design to make it as insensitive as possible to chip environment

perturbations resulting from the circuit itself or induced by external circuitry. (Cascode stage

isolation, internal damping resistors, clamps, internal (on-chip) decoupling capacitors.)

Furthermore, the fully differential operation from the analog input up to the digital outputs pro-

vides enhanced noise immunity with common mode noise rejection.

Common mode noise voltage induced on the differential analog and clock inputs will be can-

celed out by these balanced differential amplifiers.

Moreover, proper active signal shielding has been provided on the chip to reduce the amount

of coupled noise on the active inputs.

The analog inputs and clock inputs of the TS8308500 device have been surrounded by ground

pins, which must be directly connected to the external ground plane.

Digital Outputs

The TS8308500 differential output buffers are internally loaded with 75Ω. The 75Ω resistors

are connected to the digital ground pins through a -0.8V level shift diode (see Figure 33, Fig-

ure 34, Figure 35 on page 29).

The TS8308500 output buffers are designed for driving 75Ω (default) or 50Ω properly termi-

nated impedance lines or coaxial cables. An 11 mA bias current flowing alternately into one of

the 75Ω resistors when switching ensures a 0.825V voltage drop across the resistor (untermi-

nated outputs).

The V_PLUSDpositive supply voltage allows the adjustment of the output common mode level

from -1.2V (V_PLUSD= 0V for ECL output compatibility) to +1.2V (V_PLUSD= 2.4V for LVDS output

compatibility).

Therefore, the single-ended output voltages vary approximately between -0.8V and -1.625V,

(outputs unterminated), around -1.2V common mode voltage.

27

2193A–BDC–04/03

Three possible line driving and back-termination scenarios are proposed

(assuming V_PLUSD= 0V):

1. 75Ω impedance transmission lines, 75Ω differentially terminated (Figure 33):

Each output voltage varies between -1V and -1.42V (respectively +1.4V and +1V), leading

to ±0.41V = 0.825V in differential, around -1.21V (respectively +1.21V) common mode for

V_PLUSD= 0V (respectively 2.4V)

2. 50Ω impedance transmission lines, 50Ω differentially terminated (Figure 34):

Each output voltage varies between -1.02V and -1.35V (respectively +1.38V and +1.05V),

leading to ±0.33V = 660 mV in differential, around -1.18V (respectively +1.21V) common

mode for V_PLUSD= 0V (respectively 2.4V)

3. 75Ω impedance open transmission lines (Figure 35):

Each output voltage varies between -1.6V and -0.8V (respectively +0.8V and +1.6V),

which are true ECL levels, leading to ±0.8V = 1.6V in differential, around -1.2V (respec-

tively +1.2V) common mode for V_PLUSD= 0V (respectively 2.4V)

Therefore, it is possible to directly drive high input impedance storing registers, without

terminating the 75Ω transmission lines.

In the time domain, that means that the incident wave will reflect at the 75Ω transmission

line output and travel back to the generator (i.e.: the 75Ω data output buffer). As the buffer

output impedance is 75Ω, no back reflection will occur.

Note:

This is no longer true if a 50Ω transmission line is used, as the latter is not matching the buffer

75Ω output impedance.

Each differential output termination length must be kept identical.

It is recommended to decouple the midpoint of the differential termination with a 10 nF capaci-

tor to avoid common mode perturbation in case of slight mismatch in the differential output line

lengths.

Too large mismatches (keep < a few mm) in the differential line lengths will lead to switching

currents flowing into the decoupling capacitor leading to switching ground noise.

The differential output voltage levels (75Ω or 50Ω termination) are not ECL standard voltage

levels, however, it is possible to drive standard logic ECL circuitry like the ECLinPS logic line

from Motorola^®.

28

TS8308500

2193A–BDC–04/03

TS8308500

Differential Output Loading Configurations (Levels for ECL Compatibility)

Figure 33. Differential Output: 75Ω Terminated

VPLUSD = 0V

-0.8V

Out

-1V/-1.41V

75Ω

Differential output:

+0.41V = 0.825V

75Ω

Common mode level: -1.2V

(-1.2V below VPLUSD level)

75Ω

impedance

10 nF

+

-

OutB -1.41V/-1V

11 mA

DVEE

Figure 34. Differential Output: 50Ω Terminated

VPLUSD = 0V

-0.8V

Out

-1.02V/-1.35V

75Ω

50Ω

Differential output:

+0.33V = 0.660V

50Ω

Common mode level: -1.2V

(-1.2V below VPLUSD level)

50Ω

impedance

10 nF

+

-

OutB -1.35V/-1.02V

11 mA

DVEE

Figure 35. Differential Output: Open Loaded

VPLUSD = 0V

-0.8V

Out

-0.8V/-1.6V

75Ω

Differential output:

+0.8V = 1.6V

75Ω

Common mode level: -1.2V

(-1.2V below VPLUSD level)

75Ω

impedance

+

-

OutB -1.6V/-0.8V

11 mA

DVEE

29

2193A–BDC–04/03

Differential Output Loading Configurations (Levels for LVDS Compatibility)

Figure 36. Differential Output: 75Ω Terminated

VPLUSD = 2.4V

1.6V

Out

1.4V/0.99V

75Ω

Differential output:

+0.41V = 0.825V

75Ω

Common mode level: -1.2V

(-1.2V below VPLUSD level)

75Ω

impedance

10 nF

+

-

OutB 0.99V/1.4V

11 mA

DVEE

Figure 37. Differential Output: 50Ω Terminated

VPLUSD = 2.4V

1.6V

Out

1.38V/1.05V

75Ω

50Ω

Differential output:

+0.33V = 0.660V

50Ω

Common mode level: -1.2V

(-1.2V below VPLUSD level)

50Ω

impedance

10 nF

+

-

OutB 1.05V/1.38V

11 mA

DVEE

Figure 38. Differential Output: Open Loaded

VPLUSD = 2.4V

1.6V

Out

1.6V/0.8V

75Ω

Differential output:

+0.8V = 1.6V

75Ω

Common mode level: -1.2V

(-1.2V below VPLUSD level)

75Ω

impedance

+

-

OutB 0.8V/1.6V

11 mA

DVEE

30

TS8308500

2193A–BDC–04/03

TS8308500

Out of Range Bit

An Out of Range (OR, ORB) bit that goes to logical high state when the input exceeds the pos-

itive full scale or falls below the negative full scale is available.

When the analog input exceeds the positive full-scale, the digital output datas remain at a high

logical state, with (OR, ORB) at logical one.

When the analog input falls below the negative full-scale, the digital outputs remain at a logical

low state, with (OR, ORB) at logical one again.

Gray or Binary

Output Data

Format Select

The TS8308500 internal regeneration latches indecisions (for inputs very close to a latch

threshold) that can produce errors in the logic encoding circuitry and lead to large amplitude

output errors.

This is due to the fact that the latches are regenerating the internal analog residues into logical

states with a finite voltage gain value (Av) within a given positive amount of time (t):

Av = exp(∆(t)/τ), where τ is the positive feedback regeneration time constant.

The TS8308500 has been designed to reduce the probability of occurrence of such errors to

approximately 10^-13(targeted for the TS8308500 at 500 Msps).

A standard technique for reducing the amplitude of such errors down to ±1 LSB consists in

outputing the digital data in Gray code format. Though the TS8308500 has been designed to

feature a bit error rate of 10^-13with a binary output format, it is possible for the user to select

between the Binary or Gray output data format, in order to reduce the amplitude of such errors

when they occur, by storing Gray output codes.

Digital Data format selection:

•

BINARY output format if GORB is floating or V_CC

.

GRAY output format if GORB is connected to ground (0V).

Diode Pin K1

A single pin is used for both the DRRB input command and die junction monitoring. The pin

denomination is DRRB/DIOD. Temperature monitoring and Data Ready control by DRRB is

not possible simultaneously.

(See “Principle of Data Ready Signal Control by DRRB Input Command” on page 23 for Data

Ready Reset input command).

The operating die junction temperature must be kept below 145°C, therefore an adequate

cooling system has to be set up. The diode mounted transistor measured Vbe value versus

junction temperature is given below.

31

2193A–BDC–04/03

Figure 39. Diode Pin K1

1000

960

920

880

840

800

760

720

680

640

600

-55

-35

-15

5

25

45

65

85

105

125

Junction temperature (°C)

ADC Gain Control

Pin K6

The ADC gain is adjustable by means of the pin K6 (input impedance is 1 MΩ in parallel with 2

pF).

The gain adjust transfer function is given below:

Figure 40. ADC Gain Control Pin K6

1.20

1.15

1.10

1.05

1.00

0.95

0.90

0.85

0.80

-500

-400

-300

-200

-100

0

100

200

300

400

500

Vgain (command voltage) (mV)

32

TS8308500

2193A–BDC–04/03

TS8308500

Equivalent

Input/Output

Schematics

Figure 41. Equivalent Analog Input Circuit and ESD Protections

VCC = +5V

VCC

VCLAMP = +2.4V

-0.8V

-5.8V

GND

GND = 0V

-5.8V

+1.65V

50Ω

E21V

VEE

200Ω

VIN

VINB

Pad

capacitance

340 fF

Pad

capacitance

340 fF

5.8V

0.8V

-1.55V

0.8V

E21G

VEE = -5V

Note:

The ESD protection equivalent capacitance is 150 fF.

Figure 42. Equivalent Analog Clock Input Circuit and ESD Protections

VCC

VCC = +5V

+0.8V

-5.8V

-0.8V

-5.8V

GND = 0V

-5.8V

VEE

E31V

150Ω

CLK

CLKB

Pad

capacitance

340 fF

Pad

capacitance

340 fF

5.8V

0.8V

380 µA

0.8V

E21G

VEE = -5V

Note:

The ESD protection equivalent capacitance is 150 fF.

33

2193A–BDC–04/03

Figure 43. Equivalent Data Output Buffer Circuit and ESD Protections

VPLUSD = 0V to 2.4V

-5.8V

E01V

VEE

OUT

OUTB

5.8V

Pad

capacitance

180 fF

Pad

capacitance

180 fF

0.8V

DVEE = -5V

VEE = -5V

Note:

The ESD protection equivalent capacitance is 150 fF.

Figure 44. ADC Gain Adjust Equivalent Input Circuits and ESD Protections

VCC = +5V

GND

-0.8V

+0.8V

NP1032C2

-5.8V

E22V

1 kΩ

GA

Pad

capacitance

180 fF

0.8V

2 pF

0.8V

5.8V

GND

500 µA

E22GA

VEE

VEE = -5V

Note:

The ESD protection equivalent capacitance is 150 fF.

34

TS8308500

2193A–BDC–04/03

TS8308500

Figure 45. GORB Equivalent Input Schematic and ESD Protections

GORB: gray or binary select input; floating or tied to V_CC-> binary

VCC = +5V

-0.8V

-5.8V

1 kΩ

E21VA

VEE

5 kΩ

GORB

Pad

capacitance

180 fF

5.8V

250 µA

E31G

VEE = -5V

GND = 0V

Note:

The ESD protection equivalent capacitance is 150 fF.

Figure 46. DRRB Equivalent Input Schematic and ESD Protections

Actual protection range: 6.6V above V_EE, in fact stress above GND are clipped by the CB diode used for Tj monitoring

VCC = +5V

GND = 0V

NP1032C2

10 kΩ

200Ω

DRRB

-1.3V

Pad

capacitance

180 fF

-2.6V

5.8V

0.8V

E21G

VEE

VEE = -5V

Note:

The ESD protection equivalent capacitance is 150 fF.

35

2193A–BDC–04/03

TSEV8308500:

Device Evaluation Board

For complete specification, see the separate “TSEV8308500” document.

General

Description

The TSEV8308500 Evaluation Board (EB) is a board which has been designed in order to

facilitate the evaluation and the characterization of the TS8308500 device up to its 1.3 GHz full

power bandwidth at up to 500 Msps in the commercial temperature range.

The high speed of the TS8308500 requires careful attention to circuit design and layout to

achieve optimal performance.

This four metal layer board with internal ground plane has the adequate functions in order to

allow a quick and simple evaluation of the TS8308500 ADC performances over the tempera-

ture range.

The TSEV8308500 Evaluation Board is very straightforward as it only implements the

TS8308500 ADC, SMA connectors for input/output accesses and a 2.54 mm pitch connector

compatible with HP16500C high frequency probes.

The board also implements a de-embedding fixture in order to facilitate the evaluation of the

high frequency insertion loss of the input microstrip lines, and a die junction temperature mea-

surement setting.

The board is constituted by a sandwich of two dielectric layers, featuring low insertion loss and

enhanced thermal characteristics for operation in the high frequency domain and extended

temperature range.

The board dimensions are 130 mm x 130 mm.

The board set comes fully assembled and tested, with the TS8308500 and its heatsink

installed.

36

TS8308500

2193A–BDC–04/03

TS8308500

Package

Description

Table 7. TS8308500 Pad Description

Pad number

Chip Pad Name

Chip Pad Function

1

V_PLUSD

Positive digital supply (double pad)⁽²⁾

In-phase (+) digital output, bit 5

(D7 is the MSB; Bit 7, D0 is the LSB; Bit 0)

2

D5

3

D5B

D4

Inverted phase (-) digital output, bit 5

In-phase (+) digital output, bit 4

Inverted phase (-) digital output, bit 4

-5V digital supply (double pad)

In-phase (+) Data Ready

4

5

D4B

DV_EE

DR

6

7

8

DRB

D3

Inverted phase (-) Data Ready

In-phase (+) digital output, bit 3

Inverted phase (-) digital output, bit 3

Positive digital supply (double pad)⁽²⁾

In-phase (+) digital output, bit 2

Inverted phase (-) digital output, bit 2

In-phase (+) digital output, bit 1

Inverted phase (-) digital output, bit 1

In-phase (+) digital output, bit 0, Least Significant Bit

Inverted phase (-) digital output, bit 0, Least Significant Bit

Gray or Binary data output format select⁽¹⁾

+5V supply (double pad)

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

D3B

V_PLUSD

D2

D2B

D1

D1B

D0

D0B

GORG

V_CC

GND

V_CC

Analog ground (double pad)

+5V supply (double pad)

V_EE

-5V analog supply (double pad)

+5V supply (double pad)

V_CC

GND

CLK

GND

CLKB

GND

V_EE

Analog ground (double pad)

In-phase (+) clock input (double pad)

Analog ground

Inverted phase (-) clock input (double pad)

Analog ground (double pad)

-5V analog supply (double pad)

+5V supply (double pad)

V_CC

V_EE

-5V analog supply (double pad)

DIOD/DRRB

GND

Diode input for Tj monitoring/Input for asynchronous Data Ready Reset

Analog ground

37

2193A–BDC–04/03

Table 7. TS8308500 Pad Description (Continued)

Pad number

Chip Pad Name

Chip Pad Function

34

35

36

37

38

39

40

41

42

43

44

45

46

V_IN

GND

V_INB

GND

GAIN

V_CC

In-phase (+) analog input (double pad)

Analog ground

Inverted phase (-) analog input (double pad)

Analog ground (double pad)

ADC gain adjust input

+5V supply (double pad)

V_CC

+5V supply

OR

In-phase (+) Out of Range digital output

Inverted phase (-) Out of Range digital output

In-phase (+) digital output, bit 7, Most Significant Bit

Inverted phase (-) digital output bit 7

In-phase (+) digital output, bit 6

Inverted phase (-) digital output, bit 6

ORB

D7

D7B

D6

D6B

Notes: 1. GORB tied to V_CCor floating: Binary output data format. GORB tied to GND: Gray output data format.

2. The common mode level of the output buffers is 1.2V below the positive digital supply.

For ECL compatibility the positive digital supply must be set at 0V (ground).

For LVDS compatibility (output common mode at +1.2V) the positive digital supply must be set at 2.4V.If the subsequent

LVDS circuitry can withstand a lower level for input common mode, it is remmended to lower the positive digital supply level

in the name proportion in order to spare power dissipation.

38

TS8308500

2193A–BDC–04/03

TS8308500

Pin Description

(CBGA68 package)

Table 8. TS8308500 Pin Description

Symbol

Pin number

Function

GND

Ground pins, to be connected to external ground plane

A2, A5, B1, B5, B10, C2, D2, E1, E2, E11,

F1, F2, G11, K2, K3, K4, K5, K10, L2, L5

V_CC

V_EE

DV_EE

V_IN

A4, A6, B2, B4, B6, H1, H2, L6, L7

A3, B3, G1, G2, J1, J2

F10, F11

+5V positive supply

5V analog negative supply

-5V digital negative supply

In-phase (+) analog input signal of the Sample and Hold

differential preamplifier

L3

V_INB

CLK

L4

Inverted phase (-) of ECL clock input signal (CLK)

In-phase (+) ECL clock input signal. The analog input is

sampled and held on the rising edge of the CLK signal

C1

CLKB

D1

Inverted phase (-) of ECL clock input signal (CLK)

B0, B1, B2, B3, B4, B5,

B6, B7

In-phase (+) digital outputs. B0 is the LSB, B7 is the MSB

A8, A9, A10, D10, H11, J11, K9, K8

B0B, B1B, B2B, B3B,

B4B, B5B, B6B, B7B

Inverted phase (-) Digital outputs. B0B is the inverted LSB

B7B is the inverted MSB

B7, B8, B9, C11, G10, H10, L10, L9

K7

OR

In-phase (+) Out of Range bit. Out of Range is high on the

leading edge of code 0 and code 256

ORB

DR

L8

Inverted phase (+) of Out of Range bit (OR)

In-phase (+) output of Data Ready signal

E10

D11

DRB

GORB

Inverted phase (-) output of Data Ready signal (DR)

Gray or Binary select output format control pin

A7

K6

K1

– Binary output format if GORB is floating or V_CC

– Gray output format if GORB is connected at ground (0V)

GAIN

ADC gain adjust pin. The gain pin is grounded by default,

the ADC gain transfer fuction is nominally close to one

DIOD/DRRB

Die function temperature measurement pin and

asynchronous data ready reset active low, single ended

ECL input

V_PLUSD

NC

B11, C10, J10, K11

A1, A11, L1, L11

+ 2.4V for LVDS output levels otherwise to GND⁽¹⁾

Not connected

Note:

1. The common mode level of the output buffers is 1.2V below the positive digital supply

For ECL compatibility the positive digital supply must be set at 0V (ground )

For LVDS compatibility (output common mode at +1.2V) the positive digital supply must be set at 2.4V

If the subsequent LVDS circuitry can withstand a lower level for the input common mode, it is recommended to lower the

positive digital supply level in the same proportion in order to spare power dissipation

39

2193A–BDC–04/03

TS8308500GL

Pinout of CBGA68

Package

Figure 47. TS8308500 Pinout of CBGA68 Package

NC

B2

VPLUSD

GND

B2b

B3b

DRb

B3

GND

DR

DVEE

GND

B4b

B4

B5

VPLUSD

GND

B6

NC

B6b

11

10

9

VPLUSD

B5b

VPLUSD

B1

B7b

8

B0

B1b

B7

ORb

VCC

GND

VINB

7

Gorb

VCC

GND

VCC

B0b

OR

6

VCC

GND

VCC

GAIN

GND

5

4

3

VEE

GND

NC

VEE

VCC

GND

Diode

VIN

GND

NC

2

GND

CLK

GND

VEE

VCC

VEE

CLKB

1

Ball

A1 Index

other side

A

B

C

D

E

F

G

H

J

K

L

BOTTOM VIEW

40

TS8308500

2193A–BDC–04/03

TS8308500

Figure 48. TS8308500 Capacitors and Resistors Implant

Capacitors and

Resistors Implant

0.9 mm

GND

100 pF

DVEE

∅ 7.0 mm

0.9 mm

CLK

50Ω

VEE

100 pF

GND

VCC

100 pF

GND

VEE

100 pF

GND

CLKB

50Ω

0.9 mm

GND

0.9 mm

Only on-package marking

electrically isolated

Note:

R and C discrete components are 0603 size (1.6 x 0.8mm)

41

2193A–BDC–04/03

Outline Dimensions

Figure 49. Outline Dimensions - 68 Pins CBGA

CBGA 68 package.

AL203 substrate.

Package design.

Corner balls (x4) are not connected (mechanical ball).

Balls : 1.27 mm pitch on 11x11 grid.

Top side with

soldered R, C

devices

(using solder

Sn/Pb 63/37)

- T -

0.95 max

View balls side

1.27

Balls side

Balls

Sn/Pb 63/37

11

10

9

AI203 substrate

8

AI203 Ceramic

Cap. Glued and embedded

in substrate

7.84

7

6

5

4

3

2

1

Ball

A1 Index

other side

- B -

A

B

C

D

E

F

G

H

J

K

L

1.45 0.12

15.00 0.15 mm

68 x ∅ D = 0.80 0.10 mm

- A -

1.27 ref

(Position of array of balls/edges A and B)

(Position of balls within array)

0.40 T A B

0.15 T

Detail of

ball x2

0.63 0.10

All units in mm

42

TS8308500

2193A–BDC–04/03

TS8308500

Cross Section

Figure 50. Cross Section

- T -

Top side with soldered R, C devices

(using solder Sn/Pb 63/37)

0.95 max

Balls side

Balls

Sn/Pb 63/37

AI203 substrate

AI203 Ceramic Cap.

Glued on substrate

(0.400)

(0.20)

(2 x 0.20)

(0.25)

(0.20)

1.45 ꢀ0.1

All units in mm

43

2193A–BDC–04/03

Thermal And

Moisture

Characteristics

Thermal Resistance

from Junction to

Ambient: RTHJA

The following table lists the convection thermal performances parameters of the device itself,

with no external heatsink added.

Table 9. Thermal Resistance

Air Flow (m/s)

Estimated ja Thermal Resistance (°C/W)

0

0.5

1

45

35.8

30.8

27.4

24.9

23

50

40

30

20

10

0

1.5

2

2.5

3

21.5

19.3

17.7

0

1

2

5

3

4

Air Flow (m/s)

4

5

Thermal Resistance

from Junction to

Case: RTHJC

The typical value for Rthjc is given as 6.7°C/W (8°C/W max).

This value does not include thermal contact resistance between package and external compo-

nent (heatsink or PC Board).

As an example, 2.0°C/W can be taken for 50 µm of thermal grease.

CBGA68 Board

Assembly with

External Heatsink

It is recommended that an external heatsink or specifically designed PCB be used. Cooling

system efficiency can be monitored using the Temperature Sensing Diode, integrated in the

device.

Figure 51. CBGA68 Board Assembly

50.5

24.2 20.2

32.5

6.8

31

Board

Note:

Units = mm

44

TS8308500

2193A–BDC–04/03

TS8308500

Moisture

This device is sensitive to moisture (MSL3 according to JEDEC standard):

Characteristics

Shelf life in sealed bag: 12 months at <40°C and <90% relative humidity (RH).

After this bag is opened, devices that will be subjected to infrared reflow, vapor-phase reflow,

or equivalent processing (peak package body temperature 220°C) must be:

•

mounted within 198 hours at factory conditions of ≤30°C/60% RH, or

stored at ≤20% RH

Devices require baking, before mounting, if Humidity Indicator Card is >20% when read at

23°C ±5°C.

If baking is required, devices may be baked for:

•

192 hours at 40°C +5°C/-0°C and <5% RH for low-temperature device containers, or

24 hours at 125°C ±5°C for high temperature device containers

45

2193A–BDC–04/03

Definitions

Definition of Terms

(BER) Bit Error Rate

Probability to exceed a specified error threshold for a sample. An error code is a code that dif-

fers by more than ±4 LSB from the correct code.

(BW) Full-Power Input

Bandwidth

Analog input frequency at which the fundamental component in the digitally reconstructed out-

put has fallen by 3 dB with respect to its low frequency value (determined by FFT analysis) for

input at full-scale.

The peak gain variation (in percent) at five different DC levels for an AC signal of 20% Full-

Scale peak to peak amplitude. F_IN= 5 MHz (TBC).

(DG) Differential Gain

(DNL) Differential Non-

Linearity

The Differential Non-Linearity for an output code (i) is the difference between the measured

step size of code (i) and the ideal LSB step size. DNL (i) is expressed in LSBs. DNL is the

maximum value of all DNL (i). DNL error specification of less than 1 LSB guarantees that there

are no missing output codes and that the transfer function is monotonic.

(DP) Differential Phase

Peak Phase variation (in degrees) at five different DC levels for an AC signal of 20% Full-

Scale peak to peak amplitude. F_IN= 5 MHz (TBC).

(ENOB) Effective

Number of Bits

SINAD - 1.76 + 20 log (A/V/2)

ENOB =

6.02

Where A is the actual input amplitude and V is the full-scale range of the ADC under test.

(IMD) InterModulation

Distortion

The two tones intermodulation distortion (IMD) rejection is the ratio of either input tone to the

worst third order intermodulation products. The input tones levels are at -7 dB full-scale.

(INL) Integral Non-

Linearity

The Integral Non-Linearity for an output code (i) is the difference between the measured input

voltage at which the transition occurs and the ideal value of this transition.

INL (i) is expressed in LSBs, and is the maximum value of all |INL (i)|.

(JITTER) Aperture

Uncertainty

Sample to sample variation in aperture delay. The voltage error due to jitter depends on the

slew rate of the signal at the sampling point.

(NPR) Noise Power

Ratio

The NPR is measured to characterize the ADC performance in response to broad bandwidth

signals. When using a notch-filtered broadband white-noise generator as the input to the ADC

under test, the Noise Power Ratio is defined as the ratio of the average out-of-notch to the

average in-notch power spectral density magnitudes for the FFT spectrum of the ADC output

sample test.

(NRZ) Non-Return to

Zero

When the input signal is larger than the upper bound of the ADC input range, the output code

is identical to the maximum code and the Out of Range bit is set to logic one. When the input

signal is smaller than the lower bound of the ADC input range, the output code is identical to

the minimum code, and the Out of Range bit is set to logic one. (It is assumed that the input

signal amplitude remains within the absolute maximum ratings).

(ORT) Overvoltage

Recovery Time

Time to recover 0.2% accuracy at the output, after a 150% full-scale step applied on the input

is reduced to midscale.

46

TS8308500

2193A–BDC–04/03

TS8308500

(PSRR) Power Supply

Rejection Ratio

Ratio of input offset variation to a change in power supply voltage.

(SFDR) Spurious Free

Dynamic Range

Ratio expressed in dB of the RMS signal amplitude, set at 1 dB below full-scale, to the RMS

value of the next highest spectral component (peak spurious spectral component). SFDR is

the key parameter for selecting a converter to be used in a frequency domain application

(Radar systems, digital receiver, network analyzer, etc.). It may be reported in dBc (i.e.:

degrades as signal level is lowered), or in dBFS (i.e.: always related back to converter full

scale)

(SINAD) Signal to Noise

and Distortion Ratio

Ratio expressed in dB of the RMS signal amplitude, set to 1 dB below full-scale, to the RMS

sum of all other spectral components, including the harmonics except DC.

(SNR) Signal to Noise

Ratio

Ratio expressed in dB of the RMS signal amplitude, set to 1 dB below full-scale, to the RMS

sum of all other spectral components excluding the five first harmonics.

(TA) Aperture Delay

Delay between the rising edge of the differential clock inputs (CLK, CLKB) (zero crossing

point), and the time at which (V_IN, V_INB) is sampled.

(TC) Encoding Clock

Period

TC1 = Minimum clock pulse width (high) TC = TC1 + TC2

TC2 = Minimum clock pulse width (low)

(TD1) Time Delay from

Data to Data Ready

Time delay from Data transition to Data Ready.

(TD2) Time Delay from

Data Ready to Data

General expression is TD1 = TC1 + TDR - TOD with TC = TC1 + TC2 = 1 encoding clock

period.

(TF) Fall Time

Time delay for the output Data signals to fall from 80% to 20% of delta between low level and

high level.

(THD) Total Harmonic

Distorsion

Ratio expressed in dBc of the RMS sum of the first five harmonic components, to the RMS

value of the measured fundamental spectral component.

(TOD) Digital Data

Output Delay

Delay from the falling edge of the differential clock inputs (CLK, CLKB) (zero crossing point) to

the next point of change in the differential output data (zero crossing) with a specified load.

(TPD) Pipeline Delay

Number of clock cycles between the sampling edge of an input data and the associated output

data being made available, (not taking in account the TOD). For the TS8388BF the TPD is 4

clock periods.

(TR) Rise Time

Time delay for the output Data signals to rise from 20% to 80% of delta between low level and

high level.

(TRDR) Data Ready

Reset Delay

Delay between the falling edge of the Data Ready output asynchronous Reset signal (DDRB)

and the reset to digital zero transition of the Data Ready output signal (DR).

(TS) Settling Time

Time delay to achieve 0.2% accuracy at the converter output when a 80% full-scale step func-

tion is applied to the differential analog input.

47

2193A–BDC–04/03

Ordering

Information

Part Number

Package

Temperature Range

Screening

Prototype

Standard

Comments

TSX8308500GL

CBGA 68

Ambient

Prototype version

"C" grade

TS8308500CGL

CBGA 68

0°C < Tc ; Tj < 90°C

"V" grade

Standard

TS8308500VGL

-40°C < Tc ; Tj < 110°C

TSEV8308500GL

TSEV8308500GLZA2

CBGA 68

Ambient

Prototype

Evaluation Board (delivered with a heat sink)

Evaluation Board with digital output buffers

(delivered with a heat sink)

48

TS8308500

2193A–BDC–04/03

TS8308500

Datasheet

Status

Table 10. Datasheet Status

Description

Datasheet Status

Validity

This datasheet contains target and

goal specifications for discussion with

customer and application validation.

Before design phase

Objective specification

Target specification

This datasheet contains target or

goal specifications for product

development.

Valid during the design phase

This datasheet contains preliminary

data. Additional data may be

published later could include

simulation results.

Valid before characterization

phase

Preliminary specification

α-site

Preliminary specification

β-site

This datasheet also contains

characterization results.

Valid before the

industrialization phase

This datasheet contains final product

specification

Valid for production purposes

Product specification

Limiting Values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress

above one or more of the limiting values may cause permanent damage to the device. These are

stress ratings only and operation of the device at these or at any other conditions above those given in

the Characteristics sections of the specification is not implied. Exposure to limiting values for

extended periods may affect device reliability.

Application Information

Where application information is given, it is advisory and does not form part of the specification.

Life Support

Applications

These products are not designed for use in life support appliances, devices or systems where

malfunction of these products can reasonably be expected to result in personal injury. Atmel

customers using or selling these products for use in such applications do so at their own risk

and agree to fully indemnify Atmel for any damages resulting from such improper use or sale.

49

2193A–BDC–04/03

Atmel Corporation

Atmel Operations

2325 Orchard Parkway

San Jose, CA 95131

Tel: 1(408) 441-0311

Fax: 1(408) 487-2600

Memory

RF/Automotive

Theresienstrasse 2

Postfach 3535

74025 Heilbronn, Germany

Tel: (49) 71-31-67-0

Fax: (49) 71-31-67-2340

2325 Orchard Parkway

San Jose, CA 95131

Tel: 1(408) 441-0311

Fax: 1(408) 436-4314

Regional Headquarters

Microcontrollers

2325 Orchard Parkway

San Jose, CA 95131

Tel: 1(408) 441-0311

Fax: 1(408) 436-4314

1150 East Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

Tel: 1(719) 576-3300

Europe

Atmel Sarl

Route des Arsenaux 41

Case Postale 80

CH-1705 Fribourg

Switzerland

Tel: (41) 26-426-5555

Fax: (41) 26-426-5500

Fax: 1(719) 540-1759

Biometrics/Imaging/Hi-Rel MPU/

High Speed Converters/RF Datacom

Avenue de Rochepleine

La Chantrerie

BP 70602

44306 Nantes Cedex 3, France

Tel: (33) 2-40-18-18-18

Fax: (33) 2-40-18-19-60

BP 123

38521 Saint-Egreve Cedex, France

Tel: (33) 4-76-58-30-00

Fax: (33) 4-76-58-34-80

Asia

Room 1219

Chinachem Golden Plaza

77 Mody Road Tsimshatsui

East Kowloon

Hong Kong

Tel: (852) 2721-9778

Fax: (852) 2722-1369

ASIC/ASSP/Smart Cards

Zone Industrielle

13106 Rousset Cedex, France

Tel: (33) 4-42-53-60-00

Fax: (33) 4-42-53-60-01

1150 East Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

Tel: 1(719) 576-3300

Japan

9F, Tonetsu Shinkawa Bldg.

1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

Tel: (81) 3-3523-3551

Fax: (81) 3-3523-7581

Fax: 1(719) 540-1759

Scottish Enterprise Technology Park

Maxwell Building

East Kilbride G75 0QR, Scotland

Tel: (44) 1355-803-000

Fax: (44) 1355-242-743

e-mail

literature@atmel.com

Web Site

http://www.atmel.com

Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard

warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any

errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and

does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are

granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use

as critical components in life support devices or systems.

trademarks, of Atmel Corporation or its subsidiaries. Motorola^®is the registered trademark of Motorola Com-

pany. Other terms and product names may be the trademarks of others.

Printed on recycled paper.

2193A–BDC–04/03

0M


型号：	TSX8308500GL
厂家：	ATMEL
描述：	ADC 8-bit 500 Msps ADC的8位500 Msps的
文件：	总50页 (文件大小：489K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TSX8308500GL [ATMEL]

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