U2739M-BFT_技术文档

U2739M-B

DAB One-Chip Channel- and Source Decoder

Description

2

The U2739M-B is an integrated circuit in advanced Several standard interfaces, like I C/L3, I S, SPDIF or

CMOS technology for demodulation and decoding of a RDI are implemented to offer a flexible utilization.

DAB signal according to ETS 300 401. The channel

Moreover the U2739M-B includes a mechanism to

decoder part includes the main features OFDM

replace respectively extend certain software modules by

demodulation & decoding and time & frequency synchro-

using a special boot mode (so-called USE). For example,

nization algorithms, using the embedded OAK DSP core.

the time & frequency synchronization modules can be

replaced by down-loading the corresponding user

software algorithms to the OAK DSP core.

The source decoder consists of an audio and a data

decoder part. The audio source decoder supports

ISO MPEG 1,2 layer 2 and the data decoder offers Electrostatic sensitive device.

2 independent packet mode decoders.

Observe precautions for handling.

Block Diagram

RAM

U2739M–A

I2S

SLI, WAGC

DAC

Channel

decoder

Audio

decoder

Tuner

ADC

ROM

SPDIF

Data

decoder

V24/RS232

HSSO

MC

RDI

interface

RDI

SFCO

MCU

Figure 1. Block diagram

Ordering Information

Extended Type Number

U2739M-BFT

Package

Remarks

T–PQFP–G100

CQFP144

Tray

U2739M-BFC

Rev. A1, 22-May-01

1 (69)

U2739M-B

Table of Contents

1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5

1.1

1.2

1.3

1.4

1.5

General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Channel Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Audio Source Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Data Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5

6

2

3

4

5

6

Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Strap Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6

7

10

11

14

15

16

17

18

19

20

21

22

23

6.1

6.2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ADC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2.1

6.2.2

6.2.3

6.2.4

ADC Interface Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ADC Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ADC Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ADC Interface Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3

6.4

Tuner Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3.1

6.3.2

Tuner Interface Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Tuner Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.4.1

6.4.2

6.4.3

6.4.4

6.4.5

6.4.6

MC Interface Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

L3 Bus Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

L3 Bus Timing Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I2C Bus Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I2C Bus Timing Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.5

6.6

6.7

C-Bus / BOOT Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.5.1

6.5.2

6.5.3

6.5.4

C-Bus Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C-Bus / BOOT Bus Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BOOT Bus Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BOOT Bus Timing Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SRAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.6.1

6.6.2

6.6.3

6.6.4

SRAM Interface Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SRAM Interface Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SRAM Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SRAM Interface Timing Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

VCXO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.7.1

6.7.2

VCXO Interface Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

VCXO Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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U2739M-B

Table of Contents (continued)

6.8

Audio Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

24

6.8.1

6.8.2

6.8.3

6.8.4

6.8.5

6.8.6

6.8.7

6.8.8

I2S Interface Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I2S Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I2S Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I2S Interface Timing Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SP-DIF Interface Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SP-DIF Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SP-DIF Interface Timing Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SP-DIF Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

24

25

26

27

28

29

30

31

32

33

35

36

37

38

40

42

6.9

RDI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.9.1

6.9.2

6.9.3

6.9.4

RDI Interface Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RDI Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RDI Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RDI Interface Timing Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.10

SFCO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.10.1

6.10.2

6.10.3

6.10.4

6.10.5

SFCO Interface Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SFCO Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SFCO Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Detailed SFCO Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SFCO Interface Timing Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.11

6.12

RS232 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.11.1

6.11.2

6.11.3

6.11.4

RS232 Interface Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RS232 Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RS232 Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RS232 Interface Timing Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

HSSO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.12.1

6.12.2

6.12.3

6.12.4

HSSO Interface Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

HSSO Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

HSSO Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

HSSO Interface Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7

8

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1

7.2

7.3

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.1 ’Set System’ Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.1.1

8.1.2

8.1.3

8.1.4

8.1.5

8.1.6

8.1.7

8.1.8

Set DAB System Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Set ASD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Set DD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Set DD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Set CIF Counter and Occurrence Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Set Current SBCHID Long Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Set Next SBCHID Long Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Set Current SBCHID Short Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Rev. A1, 22-May-01

3 (69)

U2739M-B

Table of Contents (continued)

8.2

’Set Configuration’ Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

43

44

46

47

48

50

51

52

53

55

56

57

58

59

60

61

62

63

64

65

66

67

8.2.1

8.2.2

8.2.3

8.2.4

8.2.5

8.2.6

8.2.7

8.2.8

Set Global Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Set TS Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Set FS Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Set XO Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Set HSSO / RS232 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Set WAGC Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Set RCC Slot Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Set RFU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.3

8.4

’Read Status’ Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.3.1

8.3.2

8.3.3

Read Global Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Read Synchronization Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Read CIR Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

’Read Data’ Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.4.1

8.4.2

8.4.3

8.4.4

8.4.5

8.4.6

8.4.7

8.4.8

8.4.9

8.4.10

Read ASD Header Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Read X–PAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Read F–PAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Read AIC Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Read TII Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Read EFC Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Read FIC Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Read RCC Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Read Slot Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Read RFU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9

Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 (69)

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U2739M-B

1 Features

D Digital AGC with a wide gain control range

1.1 General

D Off-chip de-interleaver memory for full 1.8 Mbit/s

D Support of mode I, II, III and IV acc. to ETS 300 401

decoding data rate

D Time & frequency synchronization with a wide-range

D Time & frequency synchronization on DSP OAK core

parameter set

D Support of TII decoding and corresponding RDI

D Optional implementation of user-defined synchro-

insertion (set 2)

nization strategy by using USE boot mode

D Flexible software configuration:

set 1 – (temic kernel), set 2 – (user extension) concept

D Automatic mode detection (AMD)

1.3 Audio Source Decoder

D FIC on-chip memory, access via MC interface

D Generation of receiver status information

D Generation of tuner control signals

D Supports MPEG1 layer II streams according to ISO/

IEC 11172/3

D Supports MPEG2 layer II (half sampling rate) streams

according to ISO/IEC 13818–3

D Generation of pulse width modulated VCXO control

D Supports all bit rates defined in the ETS 300 401

signal

standard

D Power supply 3.3 V, master clock 24.576 MHz

D Plastic TQFP100 package or

2

D I S and SPDIF output interfaces

D Programmable fader

D Programmable DRC

D PAD extraction

D Ceramic QFP144 package for software development

1.2 Channel Decoder

D Demodulation and decoding of up to 64 UEP/EEP

1.4 Data Decoder

sub-channels

D 2 independent packet mode decoder

D Flexible configuration via MC commands

D Data group length limited to ~1 kbyte each

D Output via HSSO or V24

D Support of dynamic multiplex reconfiguration

(DMR) without mute state

D Digital Null-Symbol detection (FSYNCH generation)

D Channel filtering (48 dB)

D DD1 option: FIDC decoder

D Support of AIC decoding (set 2)

D Optional SAW filter equalization

D Digital AFC (freq. tolerance < 0.5 Hz for mode I)

Rev. A1, 22-May-01

5 (69)

U2739M-B

1_D.5_SourcI_en_dt_ee_cr_odf_ea_rc_oe_us_{tput interface: I S and SPDIF}

2

D 10-bit ADC interface:

D Data decoder output interface: V24 or HSSO

–

ADC sampling clock generation

D Channel decoder output interface: RDI and SFCO

ADC binary or 2’s complement format selection

2

D Microcontroller interface: I C/L3

support of several intermediate frequencies

D RDI:

D DSP OAK core bootstrap ROM interface

–

Extended high capacity mode

IEC 958 format

D Voltage controlled reference oscillator (VCXO)

interface

RDI control channel (RCC)

D SFCO simple full capacity output:

D Time de-interleaver SRAM (4 Mbit) interface

–

window-, serial sub-channel identifier (SbChId)-,

data-, error- and clock line

D High speed serial output HSSO (PAD, DD1, DD2,

–

3.072 MHz burst mode interface

CIR) interface, 3-line serial burst mode interface

2 Functional Block Diagram

SRAM

I2S

DAC

Audio

source

decoding

De-

IQ splitting

filtering

AFC

AGC

ADC

Decodeing

modulation

interleaving

SPDIF

FS_IN

SLI

TUNER

W_AGC

PAD

Time

FSYNC

extraction

TII decoding

(USE)

synchro–

generation

FSYNC

dF

nization

Source decoder

PWM

Frequency

synchro–

nization

Status

generation

AMD

Data

decoder 1

(FIDC)

V24/RS232

Channel

decoder

Data

decoder 2

(AIC (USE))

VCXO

tank

XO

UNIT

Data decoder

MC

memory

RDI_TX

RDI_RX

MC

BOOT

UNIT

RDI

controller

ROM

interface

MC interface

RDI interface

U2739M-B

SFCO

HSSO

MC

Figure 2. Functional block diagram

6 (69)

Rev. A1, 22-May-01

U2739M-B

3 Pin Description

QFP144

QFP100

Pin Name

Signal Description

Pad Type

PDO04T

Dir.

5 V Tol.

1

ADC_CLK

ADC sampling clock output 8.192 MHz

Test input 0 (pull down)

Test input 1 (pull down)

ADC data input, bit 9 (MSB)

ADC data input, bit 8

ADC data input, bit 7

ADC data input, bit 6

Test input 2 (pull down)

Ground

out

in

2

TIN0

PDDZ

x

3

TIN1

PDDZ

in

4

2

3

4

5

ADC_DATA9

ADC_DATA8

ADC_DATA7

ADC_DATA6

TIN2

PDIZ

in

5

PDIZ

in

6

PDIZ

in

7

PDIZ

in

8

PDDZ

in

9

DVSSE

PVSS1Z, PVSS2Z

PDIZ

gnd

in

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

6

7

8

9

ADC_DATA5

ADC_DATA4

ADC_DATA3

ADC_DATA2

TIN3

ADC data input, bit 5

ADC data input, bit 4

ADC data input, bit 3

ADC data input, bit 2

Test input 3 (pull down)

Test input 4 (pull down)

ADC data input, bit 1

ADC data input, bit 0 (LSB)

Digital ground

PDIZ

in

PDIZ

in

PDIZ

in

PDDZ

in

TIN4

PDDZ

in

10

11

12

13

14

15

16

ADC_DATA1

ADC_DATA0

DVSS1

PDIZ

in

PDIZ

in

PVSS1Z, PVSS2Z

PVSS3Z

PDX02

(PDX02)

PVDD3Z

PRO04T

PDIZ

gnd

osc

pwr

out

in

AVSS1

Analog ground

XIN

Oscillator input

XOUT

Oscillator output

AVDD1

Analog power supply

C-bus data read enable

Low active reset

/C_DR

17

18

/RS

x

PWM

Pulse width modulated control output

C-bus data write enable

Window AGC

PRO04T

PDUZ

out

in

/C_DW

19

20

W_AGC

SLI

Synchronization lock indicator

C-bus program read enable

HSSO window signal

C-bus program write enable

HSSO clock signal

/C_PR

21

22

HSSO_WIN

/C_PW

HSSO _CLK

/ABORT

HSSO _DAT

C_ADD0

C_ADD1

/BOOT_RE

C_ADD2

C_ADD3

C_ADD4

C_ADD5

C_ADD6

TOUT0

Low active ABORT signal (pull up)

HSSO data signal

x

23

24

25

26

27

28

29

30

31

PRO04T

PRO02T

PRO04T

out

C-bus address bit 0 (LSB)

C-bus address bit 1

BOOT read enable

C-bus address bit 2

C-bus address bit 3

C-bus address bit 4

C-bus address bit 5

C-bus address bit 6

Test output bit 0

32

C_ADD7

C-bus address bit 7

Rev. A1, 22-May-01

7 (69)

U2739M-B

QFP144

QFP100

Pin Name

C_ADD8

Signal Description

C-bus address bit 8

Pad Type

PRO04T

Dir.

5 V Tol.

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

33

34

35

36

37

38

39

out

C_ADD9

C-bus address bit 9

PRO04T

C_ADD10

C_ADD11

C_ADD12

DVDD1

C-bus address bit 10

PRO04T

out

C-bus address bit 11

PRO04T

out

C-bus address bit 12

PRO04T

out

Digital power supply

C-bus address bit 13

PVDD1Z, PVDD2Z

PRO04T

pwr

out

x

C_ADD13

C_ADD14

C_ADD15

C_DATA0/DBG

C_DATA1/BOOT

C_DATA8

C-bus address bit 14

PRO04T

out

C-bus address bit 15

PRO04T

out

40

41

C-bus data bit 0 (pull down)

C-bus data bit 1 (pull down)

C-bus data bit 8 (pull down)

C-bus data bit 9 (pull down)

Digital ground

PRD04TZ

PVSS1Z, PVSS2Z

PRD04TZ

PDDZ

inout

gnd

inout

in

x

C_DATA9

42

43

44

DVSS2

C_DATA2/URST

C_DATA3/XUSE

C_DATA10

C_DATA11

C_DATA4/PSPC

C_DATA5/RDI_VBIT

C_DATA12

C_DATA13

C_DATA6/XO12

C_DATA7/ADE

C_DATA14

C_DATA15

TEST_MODE/BYPP

MCM_TRIGGER

MC_MODE

MC_CLK

C-bus data bit 2 (pull down)

C-bus data bit 3 (pull down)

C-bus data bit 10 (pull down)

C-bus data bit 11 (pull down)

C-bus data bit 4 (pull down)

C-bus data bit 5 (pull down)

C-bus data bit 12 (pull down)

C-bus data bit 13 (pull down)

C-bus data bit 6 (pull down)

C-bus data bit 7 (pull down)

C-bus data bit 14 (pull down)

C-bus data bit 15 (pull down)

Test mode selection (pull down)

MCM trigger signal

45

46

47

48

49

50

51

52

53

PRO04T

out

Microcontroller mode signal

Microcontroller clock signal

Microcontroller data signal

Digital power supply

SPDIF output

PDIZ

in

x

PDIZ

in

MC_DAT

PRB04TZ

PVDD1Z, PVDD2Z

PRO04T

inout

pwr

out

DVDDE

54

55

56

57

SPDIF

RS232

RS232 output

PRO04T

out

I2S_CLK

I2S clock output

PRO04T

out

I2S_DAT

I2S data output

PRO04T

out

TOUT1

Test output bit 1

PRO02T

out

58

I2S_WIN

I2S win output

PRO04T

out

TOUT2

Test output bit 2

PRO02T

out

59

60

61

62

TOUT3

Test output bit 3

PRO02T

out

RDI_RX

RDI receive data

PDIZ

in

x

RDI_TX

RDI transmit data

PRO04T

out

DVSS3

Digital ground

PVSS1Z, PVSS2Z

PRO02T

gnd

out

TOUT4

Test output bit 4

8 (69)

Rev. A1, 22-May-01

U2739M-B

QFP144

QFP100

Pin Name

Signal Description

Test output bit 5

Pad Type

PRO02T

Dir.

5 V Tol.

89

TOUT5

out

90

63

64

65

SFCO_SID

SFCO_ERR

SFCO_DAT

TOUT6

SFCO sub-channel ID

SFCO errorflag

PRO04T

PRO02T

PRO04T

PRO02T

PVDD1Z, PVDD2Z

PRO02T

PRB04TZ

PRO02T

PRB04TZ

PRO02T

PRB04TZ

PRO02T

PRB04TZ

PDDZ

91

out

92

SFCO data

out

93

Test output bit 6

out

94

66

67

SFCO_CLK

SFCO_WIN

TOUT7

SFCO clock

out

95

SFCO window

out

96

Test output bit 7

out

97

68

69

DVDD2

Digital power supply

Test output bit 8

pwr

out

x

98

TOUT8

99

TOUT9

Test output bit 9

out

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

70

71

SRAM_D7

SRAM_D6

TOUT10

SRAM data bit 7

inout

out

x

SRAM data bit 6

Test output bit 10

SRAM data bit 5

72

73

SRAM_D5

SRAM_D4

TOUT11

inout

out

x

SRAM data bit 4

Test output bit 11

SRAM data bit 3

74

75

SRAM_D3

SRAM_D2

TOUT12

inout

out

x

SRAM data bit 2

Test output bit 12

SRAM data bit 1

76

77

SRAM_D1

SRAM_D0

TIN5

inout

in

x

SRAM data bit 0

Test input 5 (pull down)

SRAM write signal

SRAM output enable

SRAM address bit 18

Test input 6 (pull down)

SRAM address bit 17

SRAM address bit 16

Test output bit 13

SRAM address bit 15

SRAM address bit 14

Digital ground

78

79

80

SRAM_WR

SRAM_OE

SRAM_A18

TIN6

PRO04T

PDDZ

out

in

x

81

82

SRAM_A17

SRAM_A16

TOUT13

PRO04T

PRO02T

PRO04T

PVSS1Z, PVSS2Z

PDDZ

out

83

84

85

SRAM_A15

SRAM_A14

DVSS4

out

gnd

in

x

TIN7

Test input 7 (pull down)

SRAM address bit 13

SRAM address bit 12

Test output bit 14

SRAM address bit 11

SRAM address bit 10

Test output bit 15

SRAM address bit 9

SRAM address bit 8

86

87

SRAM_A13

SRAM_A12

TOUT14

PRO04T

PRO02T

PRO04T

PRO02T

PRO04T

out

88

89

SRAM_A11

SRAM_A10

TOUT15

out

90

91

SRAM_A9

SRAM_A8

out

Rev. A1, 22-May-01

9 (69)

U2739M-B

QFP144

131

132

133

134

135

136

137

138

139

140

141

142

143

144

QFP100

Pin Name

Signal Description

Test output bit 16

Pad Type

PRO02T

Dir.

out

pwr

out

in

5 V Tol.

TOUT16

92

93

94

SRAM_A7

SRAM_A6

DVDD3

SRAM address bit 7

PRO04T

PVDD1Z, PVDD2Z

PRO02T

PRO04T

PDDZ

SRAM address bit 6

Digital power supply

Test output bit 17

TOUT17

95

96

SRAM_A5

SRAM_A4

TMUX0

SRAM address bit 5

SRAM address bit 4

Test mux in bit 0 (LSB) (pull down)

SRAM address bit 3

x

97

98

SRAM_A3

SRAM_A2

TMUX1

PRO04T

PDDZ

out

in

SRAM address bit 2

Test mix in bit 1 (pull down)

SRAM address bit 1

99

SRAM_A1

SRAM_A0

TMUX2

PRO04T

PDDZ

out

in

100

SRAM address bit 0

Test mux in bit 2 (pull down)

4 Strap Pins

QFP144 QFP100

Pin Name

Signal Description

Pad Type

Dir

in

Comment

Strap pin OCSEL 1

Strap pin OCSEL 0

16

17

54

55

59

60

63

64

10

11

40

41

43

44

45

46

ADC_DATA1

ADC data input, bit 1 PDIZ

ADC data input, bit 0 PDIZ

ADC_DATA0

in

C_DATA0/DBG

C_DATA1/BOOT

C_DATA2/URST

C_DATA3/XUSE

C_DATA4/PSPC

C-bus data bit 0

C-bus data bit 1

C-bus data bit 2

C-bus data bit 3

C-bus data bit 4

C-bus data bit 5

PRD04TZ

inout Strap pin C_DATA0/DBG

inout Strap pin C_DATA1/BOOT

inout Strap pin C_DATA2/URST

inout Strap pin C_DATA3/XUSE

inout Strap pin C_DATA4/PSPC

PRD04TZ

C_DATA5/

RDI_VBIT

inout Strap pin C_DATA5/RDI_VBIT

0

1

RDI spec.: validity bit 1

IEC958 spec.: validity bit 0

67

68

71

73

47

48

49

51

C_DATA6/XO12

C_DATA7/ADE

C-bus data bit 6

PRD04TZ

PDDZ

inout Strap pin C_DATA6/XO12

0

1

external oscillator 24.576 MHz

external oscillator 12.288 MHz

C-bus data bit 7

ADC_DATA strap pin

function enable

inout Strap pin C_DATA7/ADE

0

1

ADC_DATA strap pin function disabled

ADC_DATA strap pin function enabled

TEST_MODE/BYPP Test mode selection

in

Strap pin TEST_MODE/BYPP

0

1

PLL activated

PLL bypassed

MC_MODE

Microcontroller mode PDIZ

signal

Strap pin I2C/L3

0

1

I2C

L3

10 (69)

Rev. A1, 22-May-01

U2739M-B

5 Pin Configuration

ADC_CLK

ADC_D9

ADC_D8

ADC_D7

ADC_D6

ADC_D5

ADC_D4

ADC_D3

ADC_D2

ADC_D1

ADC_D0

DVSS1

1

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

SRAM_D2

SRAM_D3

SRAM_D4

SRAM_D5

SRAM_D6

SRAM_D7

TOUT8

2

3

4

5

6

7

8

DVDD2

9

SFCO_WIN

SFCO_CLK

SFCO_DAT

SFCO_ERR

SFCO_SID

DVSS3

10

11

12

13

14

15

16

17

18

19

20

AVSS1

QFP100

XOUT

XIN

AVDD1

/RS

RDI_TX

RDI_RX

TOUT3

PWM

W_AGC

SLI

I2S_WIN

I2S_DAT

I2S_CLK

RS232

HSSO_WIN 21

HSSO_CLK 22

SPDIF

HSSO_DAT

C_ADD0

C_ADD1

23

24

25

MC_DAT

MC_CLK

MC_MODE

Figure 3. Production version QFP100

Rev. A1, 22-May-01

11 (69)

U2739M-B

signal. It is divided into twelve sections, which are related

to the different interfaces. An overview of all interfaces

is shown in the functional block diagram below. Several

standard output interfaces like I S or SPDIF are used to

offer a flexible usage of the U2739M-B.

6 Interface Description

6.1 Overview

The interface description explains the purpose, the

utilization and the meaning of every interface and every

2

SRAM

I2S

DAC

Audio

source

decoding

De-

IQ splitting

filtering

AFC

AGC

ADC

Decodeing

modulation

interleaving

SPDIF

FS_IN

SLI

TUNER

W_AGC

PAD

Time

FSYNC

extraction

TII decoding

(USE)

synchro–

generation

FSYNC

dF

nization

Source decoder

PWM

Frequency

synchro–

nization

Status

generation

AMD

Data

decoder 1

(FIDC)

V24/RS232

Channel

decoder

Data

decoder 2

(AIC (USE))

VCXO

tank

XO

UNIT

Data decoder

MC

memory

RDI_TX

RDI_RX

MC

BOOT

UNIT

RDI

controller

ROM

interface

MC interface

RDI interface

U2739M-B

SFCO

HSSO

MC

Figure 6. Functional block diagram

6.2 ADC Interface

6.2.1

ADC Interface Signal Description

QFP144 QFP100

Pin Name

Signal Description

Pad Type

Dir.

out

in

5 V Tol.

1

4

1

2

ADC_CLK

ADC sampling clock output 8.192 MHz PDO04T

ADC_DATA9 ADC data input, bit 9 (MSB)

ADC_DATA8 ADC data input, bit 8

ADC_DATA7 ADC data input, bit 7

ADC_DATA6 ADC data input, bit 6

ADC_DATA5 ADC data input, bit 5

ADC_DATA4 ADC data input, bit 4

ADC_DATA3 ADC data input, bit 3

ADC_DATA2 ADC data input, bit 2

ADC_DATA1 ADC data input, bit 1

ADC_DATA0 ADC data input, bit 0 (LSB)

PDIZ

x

5

3

in

6

4

in

7

5

in

10

11

12

13

16

17

6

in

7

in

8

in

9

in

10

11

in

14 (69)

Rev. A1, 22-May-01

U2739M-B

6.2.2

ADC Interface Description

The ADC interface as shown in figure 6 consists of the typical output delay (td3 in figure 7) of the AD converter

ADC data input signal ADC_DATA(9:0) and the ADC related to the falling edge of the sampling clock CLK8192

sampling clock output signal ADC_CLK. The should be 20 ns. The generated 8.192 MHz output clock

U2739M-B can be connected to every standard AD with take over the ADC_DATA with his rising edge of

either binary or 2’s complement output format. The ADC_CLK. The format ‘binary offset’ or ‘2’s

sampling frequency is 8.192 MHz and a bandwidth of complement’ of the A/D converter can be selected by the

2 MHz is necessary. The possible IF’s, which are parameter ADCF. This parameter is also defined by the

supported in conjunction with the IF input signal mode ‘set global configuration’ MC command [Atmel Wireless

(parameter IFM) are given by the formula.

& Microcontrollers U2739M documentation set –

“U2739M_MC_Command_set_vxxx.pdf”].

f = 2.048 MHz + n 4.096 MHz, with n = 0, 1, 2, 3 ....

if

Furthermore, the sampling clock generation is performed

Thus possible IFs are 2.048 MHz, 6.144 MHz, ... by the U2739M-B. The input data appearing at the

38.912 MHz. The parameter IFM is defined by the ADC_DATA port are assumed to be generated by an A/D

MC command ‘set global configuration’ [Atmel Wireless converter. The effective resolution of this converter

& Microcontrollers U2739M documentation set – should be greater than 9 bit in order to use the full

“U2739M_MC_Command_set_vxxx.pdf”]. The analog dynamic range implemented in the U2739M-B. The

input bandwidth of the A/D converter must be chosen sampling clock required for the external A/D converter is

accordingly. The ADC_DATA input is 10 bit wide. The derived inside U2739M-B. It has to be 8.192 MHz.

6.2.3

ADC Interface Timing Diagram

tclk

tH

tL

XIN

tc8

td1

tc8H

tc8L

ADC_CLK

ADC_D[9:0]

ts1

Figure 7. ADC interface timing diagram

6.2.4

ADC Interface Timing Parameters

Parameter

Symbol

tclk

tH

Min.

Typ.

Max.

Unit

ns

XIN clock period

40.7

XIN clock high

15.0

20.35

25.0

ns

XIN clock low

tL

20.35

ns

ADC_CLK clock period

ADC_CLK clock high

ADC_CLK clock low

Setup time ADC_D(9:0)

Output delay of ADC_CLK

tc8

3 × 40.7

1 × 40.7

2 × 40.7

ns

tc8H

tc8L

ts1

ns

5.0

ns

td1

12.0

20.0

28.0

ns

Rev. A1, 22-May-01

15 (69)

U2739M-B

6.3 Tuner Interface

6.3.1

Tuner Interface Signal Description

QFP144 QFP100

Pin Name

Signal Description

Window AGC

Pad Type

Dir.

5 V Tol.

27

19

W_AGC

PRO04T

out

0 during COFDM symbols

1 during the NULL symbol

28

20

SLI

Synchronization lock indicator

PRO04T

out

0

1

receiver synchronization not locked

receiver synchronization locked

6.3.2

Tuner Interface Description

In order to implement a flexible AGC concept of a DAB the set WAGC configuration MC command. The WAGC

receiver the signals W_AGC and SLI can be used to signal does not follow the moving FFT window. The

control the tuner IC U2731B. The influence of W_AGC rising and falling edge can be adjusted by the MC. The

and SLI to the RF AGC voltage generation block is MC can use the differential dT, which correspond to the

described in the U2731B preliminary datasheet.

FFT window shift, from the read synchronization status

command to adjust the WAGC rising and falling edge.

The WAGC signal must be controlled by the MC by using

6.4 MC Interface

6.4.1

MC Interface Signal Description

QFP144 QFP100

Pin Name

MCM_TRIGGER

MC_MODE

Signal Description

MCM trigger signal

Pad Type

PRO04T

PDIZ

Dir.

out

in

5 V Tol.

72

73

50

51

Microcontroller mode signal

0 I2C bus protocol

x

1 L3 bus protocol

74

75

52

53

MC_CLK

MC_DAT

Microcontroller clock signal

Microcontroller data signal

PDIZ

in

x

PRB04TZ

inout

6.4.2

MC Interface Description

The MC interface is used for data transmission between The external MCU is able to communicate with the

the U2739M-B (slave) and an external microcontroller U2739M-B during LOW phases of MCM_TRIGGER

(master). It can be configured for L3- or I2C protocol only !

depending on the status of the MC_MODE line during

Further the MCM trigger signal indicates the synchro-

reset (/RS = LOW):

nization status. If the MCM trigger has period of 8 ms,

MC_MODE = HIGH

MC_MODE = LOW

V

L3 bus selected

I2C bus selected

then the U2739M-B is not locked. In the synchronized

(‘locked’) state the MCM trigger period correspond to the

CIF frame, which is provided every 24 ms. The complete

The MCM_TRIGGER line indicates the status of the FIC is processed at the beginning of the transmission

internal interface controller.

frame.

16 (69)

Rev. A1, 22-May-01

U2739M-B

6.4.3

L3 Bus Interface Timing Diagram

Address mode

1

ts2

th2

MC_MODE

MC_CLK

MC_DAT

tLC

tHC

0

1

6

7

ts1 th1

Data mode

2

ts2

th2

MC_MODE

tLC

tHC

MC_CLK

MC_DAT

0

1

6

7

(MCU

U2739M)

ts

th1

MC_DAT

0

1

6

7

(U2739M

MCU)

td1

Halt mode

3

tL

MC_MODE

th2

ts2

MC_CLK

MC_DAT

td3

td2

high Z

(U2739M

MCU)

Figure 8. MC L3 bus interface timing diagram

Rev. A1, 22-May-01

17 (69)

U2739M-B

6.4.4

L3 Bus Timing Parameter

Parameter

Symbol

tLC

tHC

ts1

Min.

61

Typ.

Max.

Unit

ns

MC_CLK low phase

MC_CLK high phase

61

ns

MC_DAT input setup time

MC_DAT input hold time

MC_MODE hold time

61

ns

th1

61

ns

th2

61

ns

MC_MODE setup time

ts2

61

ns

MC_CLK(h/l) / MC_DAT delay

MC_MODE(l/h) / MC_DAT (output driven)

MC_CLK(l/h) / MC_DAT(high Z)

td1

20

100

130

160

ns

td2

110

120

ns

td3

ns

6.4.5

I2C Bus Interface Timing Diagram

tBF

thS

tsS

thS

tsS

MC_DATA

7

0

7

0

tsD

thD

tLC

tHC

MC_CLK

r

S

t

S

p

S

t

S

p

Figure 9. MC I2C bus timing diagram

6.4.6

I2C Bus Timing Parameter

Parameter

Symbol

Min.

Typ.

Max.

Unit

Bus free time between STOP and START

condition

tBF

400

ns

Hold time (repeated) START condition

Setup time data

thS

tsD

thD

tLC

tHC

tsS

200

120

320

300

200

240

ns

Hold time data

Low period clock

High period clock

Setup time:

repeated START condition, STOP condition

18 (69)

Rev. A1, 22-May-01

U2739M-B

6.5 C-Bus / BOOT Bus Interface

6.5.1

C-Bus Signal Description

QFP144 QFP100

Pin Name

/C_DR

Signal Description

C-bus data read enable

C-bus data write enable

C-bus program read enable

C-bus program write enable

C-bus address bit 0 (LSB)

C-bus address bit 1

Pad Type

PRO04T

PRD04TZ

Dir.

out

5 V Tol.

23

26

29

31

/C_DW

out

/C_PR

out

/C_PW

out

35

36

37

38

39

40

41

42

44

45

46

47

48

49

51

52

53

54

55

56

57

59

60

61

62

63

64

65

66

67

68

69

70

24

25

26

27

28

29

30

31

32

33

34

35

36

37

39

C_ADD0

out

C_ADD1

out

/BOOT_RE

C_ADD2

BOOT read enable

out

C-bus address bit 2

out

C_ADD3

C-bus address bit 3

out

C_ADD4

C-bus address bit 4

out

C_ADD5

C-bus address bit 5

out

C_ADD6

C-bus address bit 6

out

C_ADD7

C-bus address bit 7

out

C_ADD8

C-bus address bit 8

out

C_ADD9

C-bus address bit 9

out

C_ADD10

C_ADD11

C_ADD12

C_ADD13

C_ADD14

C_ADD15

C_DATA0/DBG

C_DATA1/BOOT

C_DATA8

C_DATA9

C_DATA2/URST

C_DATA3/XUSE

C_DATA10

C_DATA11

C_DATA4/PSPC

C-bus address bit 10

out

C-bus address bit 11

out

C-bus address bit 12

out

C-bus address bit 13

out

C-bus address bit 14

out

C-bus address bit 15

out

40

41

C-bus data bit 0 (pull down)

C-bus data bit 1 (pull down)

C-bus data bit 8 (pull down)

C-bus data bit 9 (pull down)

C-bus data bit 2 (pull down)

C-bus data bit 3 (pull down)

C-bus data bit 10 (pull down)

C-bus data bit 11 (pull down)

C-bus data bit 4 (pull down)

inout

x

43

44

45

46

C_DATA5/RDI_VBIT C-bus data bit 5 (pull down)

C_DATA12

C-bus data bit 12 (pull down)

C-bus data bit 13 (pull down)

C-bus data bit 6 (pull down)

C-bus data bit 7 (pull down)

C-bus data bit 14 (pull down)

C–-bus data bit 15 (pull down)

C_DATA13

47

48

C_DATA6/XO12

C_DATA7/BYPP

C_DATA14

C_DATA15

Rev. A1, 22-May-01

19 (69)

U2739M-B

6.5.2

C-Bus / BOOT Bus Interface Description

The C-Bus is a multiplexed program as well as data bus Atmel Wireless & Microcontrollers firmware. The

system to communicate with external components. The BOOT bus is a standard ROM interface (address/ data

complete bus system is available only in the QFP144 buses, read enable line) and the read access is always with

package version and needed for debugging the internal 16 wait states (referring the OAK internal 49.152 MHz

OAK DSP core.

clock) to support slow devices.

The BOOT bus covers a subset of the C-Bus signals. The

user is able to download his own so-called ’User Software The BOOT bus is available in both package versions. The

Extensions’ using this bus system to replace or extend the timing diagram refers to the BOOT bus signals only.

6.5.3

BOOT Bus Timing Diagram

/BOOT_RE

valid address

C_ADD (13..0)

C_DATA (7..0)

valid data

tacc

Figure 10. C-bus interface timing diagram

6.5.4

BOOT Bus Timing Parameter

Parameter

Symbol

tacc

Min.

Typ.

Max.

120

Unit

ns

BOOT ROM access time

20 (69)

Rev. A1, 22-May-01

U2739M-B

6.6 SRAM Interface

6.6.1

SRAM Interface Signal Description

QFP144 QFP100

Pin Name

SRAM_D7

Signal Description

SRAM data bit 7

Pad Type

PRB04TZ

PRO04T

Dir.

inout

out

5 V Tol.

100

101

103

104

106

107

109

110

112

113

114

116

117

119

120

123

124

126

127

129

130

132

133

136

137

139

140

142

143

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

86

87

88

89

90

91

92

93

95

96

97

98

99

100

x

SRAM_D6

SRAM_D5

SRAM_D4

SRAM_D3

SRAM_D2

SRAM_D1

SRAM_D0

SRAM_WR

SRAM_OE

SRAM_A18

SRAM_A17

SRAM_A16

SRAM_A15

SRAM_A14

SRAM_A13

SRAM_A12

SRAM_A11

SRAM_A10

SRAM_A9

SRAM_A8

SRAM_A7

SRAM_A6

SRAM_A5

SRAM_A4

SRAM_A3

SRAM_A2

SRAM_A1

SRAM_A0

SRAM data bit 6

SRAM data bit 5

SRAM data bit 4

SRAM data bit 3

SRAM data bit 2

SRAM data bit 1

SRAM data bit 0

SRAM write signal

SRAM output enable

SRAM address bit 18

SRAM address bit 17

SRAM address bit 16

SRAM address bit 15

SRAM address bit 14

SRAM address bit 13

SRAM address bit 12

SRAM address bit 11

SRAM address bit 10

SRAM address bit 9

SRAM address bit 8

SRAM address bit 7

SRAM address bit 6

SRAM address bit 5

SRAM address bit 4

SRAM address bit 3

SRAM address bit 2

SRAM address bit 1

SRAM address bit 0

out

6.6.2

SRAM Interface Descriptions

For time de-interleaving and further task an external Due to the high data rates a fast SRAM with a access time

static random access memory of 4 MB is necessary. The of 18 ns or below is necessary.

organization of the SRAM is 512 k × 8 bit.

Rev. A1, 22-May-01

21 (69)

U2739M-B

6.6.3

SRAM Interface Timing Diagram

READ CYCLE

XIN

td1

td2

tavav

valid address

SRAM_A(18:0)

SRAM_WR

td3

SRAM_OE

HIGH–Z

SRAM_D(7:0)

data valid

tsdata

WRITE CYCLE

XIN

tavav

td1

valid address

SRAM_A(18:0)

SRAM_WR

td2

twleh

td3

SRAM_OE

SRAM_D(7:0)

data valid

tdvwh

tddata

Figure 11. SRAM interface timing diagram

22 (69)

Rev. A1, 22-May-01

U2739M-B

6.6.4

SRAM Interface Timing Parameter

Parameter

Symbol

Min.

Typ.

40.7

25.0

20.0

24.0

Max.

Unit

ns

Read/ write cycle time

tavav

td1

Output delay SRAM_A(18:0)

Output delay SRAM_WR

Output delay SRAM_OE

Setup time SRAM_D(7:0)

Write pulse with

15.0

12.0

16.0

2.0

35.0

28.0

32.0

ns

td2

ns

td3

ns

tsdata

twleh

tddata

tdvwh

ns

33.0

15.0

33.0

40.7

23.0

40.7

48.0

31.0

48.0

ns

Output delay SRAM_D(7:0)

Data valid to end of write

ns

6.7 VCXO Interface

6.7.1

VCXO Interface Signal Description

QFP144 QFP100

Pin Name

AVSS1

Signal Description

Analog ground

Pad Type

Dir.

5 V Tol.

19

20

21

22

25

13

14

15

16

18

PVSS3Z

PDX02

gnd

osc

pwr

out

x

XIN

Oscillator input

XOUT

AVDD1

PWM

Oscillator output

(PDX02)

PVDD3Z

PRO04T

Analog power supply

Pulse width modulated control output

6.7.2

VCXO Interface Description

U2739M-B

PLL

49.192 MHz

PWM

PAD

XIN

PAD

XOUT

PAD

VCXO 24.576 MHz

n

f

= f

/ 2

PWM

clk2457

n = 11 –> f

= 12 kHz

PWM

Figure 12. VCXO application circuit

The U2739M-B master clock should be derived from a voltage-controlled reference oscillator. The pulse width modu-

lated output signal PWM of the U2739M-B can be used to control the VCXO frequency of 24.576 MHz.

Rev. A1, 22-May-01

23 (69)

U2739M-B

6.8 Audio Interfaces

6.8.1

I2S Interface Signal Description

QFP144 QFP100

Pin Name

I2S_CLK

Signal Description

I2S clock line

Pad Type

PRO04T

Dir.

out

5 V Tol.

79

80

82

56

57

58

I2S_DAT

I2S_WIN

I2S data line

I2S window line

6.8.2

I2S Interface Description

The I2S interface is a standard continuous audio interface As in the DAB system the I2S_WIN clock is fixed as

consisting of bit clock (_CLK), word select (_WIN) and 48 kHz (MPEG1) or 24 kHz (MPEG2) the bit clock

data (_DAT) lines. The word select line indicates the depends on the data word length. The standard word

transmitted channel: LOW for left, HIGH for right. Please length is 16 bit, hence the bit clock is fixed at 1.536 MHz

be aware of the 1 cycle delay of the data word MSB resp. 768 kHz.

corresponding to the I2S_WIN edge !

6.8.3

I2S Interface Timing Diagram

tclk

tH

tL

I2S_CLK

I2S_WIN

I2S_DAT

td1

0

15

14

13

12

3

2

1

0

15

14

13

12

3

2

1

0

15

14

13

12

td2

left sample

right sample

Figure 13. I2S interface timing diagram

6.8.4

I2S Interface Timing Parameter

Parameter

Symbol

tclk

tH

Min.

Typ.

16.28

14.28

0.0

Max.

Unit

us

I2S clock period

I2S clock high

us

I2S clock low

tL

us

I2S_WIN output delay

I2S_DAT output delay

td1

–5.0

5.0

ns

td2

0.0

ns

6.8.5

SP-DIF Interface Signal Description

QFP144 QFP100

Pin Name

SPDIF

Signal Description

SPDIF output

Pad Type

Dir.

out

5 V Tol.

77

54

PRO04T

24 (69)

Rev. A1, 22-May-01

U2739M-B

Complete frames (left and right sample according to

64 2 bit due to bi-phase coding) are transmitted at the

audio sampling rate (48 resp. 24 kHz).

6.8.6

SP-DIF Interface Description

The SP-DIF format is frame based, which means one

frame represents one audio sampling period. Every frame

comprises 2 subframes a 32 bit referring to the left and

right sample. The data is transmitted in bi-phase coded

format. The frame synchronization pattern are based on

biphase violations and indicate whether a left or right

subframe follows.

6.8.7

SP-DIF Interface Timing

Parameter

The last 4 bi-phase coded bits of each subframe represent

the V (validity flag), U (user channel data), C (channel The SP-DIF interface was designed according the digital

status data) and P (parity) information as described in the audio interface IEC958 specification [CEI/ISO 958

SP-DIF specification.

Digital Audio Interface Standard].

6.8.8

SP-DIF Interface Timing Diagram

S3

S2

S1

SPDIF

A0

A1

A2

A14

A15

V

U

C

P

Frame sync. pattern

8

Zero’s (bi–phase coded)

Audio data bits (bi–phase coded)

Flag bits (bi–phase coded)

SP–DIF subframe (left or right audio sample)

Figure 14. SP-DIF interface timing diagram

6.9 RDI Interface

6.9.1

RDI Interface Signal Description

QFP144 QFP100

Pin Name

Signal Description

Pad Type

PRD04TZ

PDIZ

Dir.

inout

in

5 V Tol.

64

85

86

46

60

61

C_DATA5/RDI_VBIT C–bus data bit 5 (pull down)

x

RDI_RX

RDI_TX

RDI receive data

RDI transmit data

PRO04T

out

6.9.2

RDI Interface Description

The RDI interface is designed according to the ‘Digital data is provided in the extended format of the high

Audio Broadcasting System: Specification of the capacity mode. Further the RDI Control Channel (RCC)

Receiver Data Interface (RDI)’ [Digital Audio can be implemented according to the preliminary specifi-

Broadcasting System: Specification of the Receiver Data cation [Digital Audio Broadcasting System: Preliminary

Interface (RDI), Issue 1.4]. The RDI frames are Specification of the RDI Control Channel], [Proposal of

embedded into the IEC 958 interface. The RDI output DAB Command Set for Receiver (DCSR)].

6.9.3

RDI Interface Timing Diagram

tH

tL

2 * tH

2 * tL

3 * tH

3 * tL

RDI_TX/RX

Figure 15. RDI interface timing diagram

Rev. A1, 22-May-01

25 (69)

U2739M-B

6.9.4

RDI Interface Timing Parameter

The RDI interface is realized according to the digital audio interface IEC958 specification [CEI/ISO 958 Digital Audio

Interface Standard].

Parameter

Symbol

TH

Min.

Typ.

160

Max.

Unit

ns

Data high period

Data low period

TL

ns

6.10 SFCO Interface

6.10.1 SFCO Interface Signal Description

QFP144 QFP100

Pin Name

SFCO_SID

SFCO_ERR

SFCO_DAT

SFCO_CLK

SFCO_WIN

Signal Description

SFCO sub-channel ID

Pad Type

Dir.

5 V Tol.

90

91

92

94

95

63

64

65

66

67

PRO04T

out

SFCO error flag

SFCO data

SFCO clock

SFCO window

6.10.2 SFCO Interface Description

The simple full capacity output interface (SFCO) is a decoder. The window line can be used to distinguish

3.072 MHz burst mode interface. It consists of a window, between FIC and MSC data. Via the MC interface the

data, errorflag and clock line. Furthermore, a serial sub- provided sub-channel can be selected. Only these

channel identifier information is provided. The interface selected sub-channels are processed by the channel

carries fast information channel (FIC) and main service decoder.

information (MSC) at the output of the COFDM channel

26 (69)

Rev. A1, 22-May-01

U2739M-B

6.10.3 SFCO Interface Timing Diagram

2 * 32 * clk

48*clk

FIC

32*clk

SFCO_win

SFCO_clk

32 * clk

3 * 32 * clk

16*clk 80*clk

20*clk

12*clk

16 *clk

FIB1

12

FIB1

CRC

FIB2

FIBn

12

FIBn

CRC

SFCO_data

1

SFCO_SubChId

0

SFCO_ErrFl

MSC

32*clk

1*clk

SFCO_win

SFCO_clk

32*clk

22*clk

10 *clk

MSC

SFCO_data

n

1

n – 1

6*clk

SFCO_SubChId

ID

SFCO_ErrFl

Figure 16. SFCO interface timing diagram

Rev. A1, 22-May-01

27 (69)

U2739M-B

6.10.4 Detailed SFCO Interface Timing Diagram

FIC

td1

td2

SFCO_win

tHC

tLC

SFCO_clk

SFCO_data

0

1

n

ts

th

SFCO_SubChId

SFCO_ErrFl

0

MSC

tHW

th

SFCO_win

SFCO_clk

SFCO_data

tHC

tLC

0

1

5

6

0

n

ts

th

SFCO_SubChId

SFCO_ErrFl

6

Figure 17. Detailed SFCO interface timing diagram

28 (69)

Rev. A1, 22-May-01

U2739M-B

6.10.5 SFCO Interface Timing Parameter

Parameter

Clock high period

Symbol

tHC

tLC

ts

Min.

Typ.

160

Max.

Unit

ns

160

ns

Clock low period

160

ns

Data setup time

th

160

ns

Data hold time

tHW

td1

10.56

10.24

us

Window MSC high period

Delay data valid

us

td2

us

Delay window FIC low

6.11 RS232 Interface

6.11.1 RS232 Interface Signal Description

QFP144 QFP100

78 55

Pin Name

RS232

Signal Description

RS232 output

Pad Type

PRO04T

Dir.

out

5 V Tol.

6.11.2 RS232 Interface Description

The RS232 interface is an standard serial output used for D Data decoder 2

transferring data directly to a PC COM port. One of 3

applications can be given out:

D Programme Associated Data (PAD)

Each RS232 burst consists of a header word followed by

n data words (as indicated in the header):

D Data decoder 1

RS232-ID

Length

(Burst Identifier)

(Number of Transmitted Data Words n Without Header Word)

bit 15

14

0

13

0

12

1

11

10

9

8

7

6

5

4

3

2

1

0

DD1

DD2

PAD

0

Number of DD1 words

Number of DD2 words

Number of PAD words

0

1

0

1

The RS232 output can be configured using the ’set HSSO/ out and the baud rate.

RS232 configuration’ MC command [Atmel Wireless &

Please notice the byte order: first the high byte is trans-

mitted followed by the low byte (LSB first both).

Microcontrollers U2739M documentation set

“U2739M_MC_Command_set_vxxx.pdf”]. Using this

–

command the user can select the application to be given

6.11.3 RS232 Interface Timing Diagram

RS232

8

9

10

14

15

0

1

2

6

7

8

9

10

11

12

Figure 18. RS232 interface timing diagram

6.11.4 RS232 Interface Timing Parameter

The RS232 timing is related to the defined baud rate of the interface.

Rev. A1, 22-May-01

29 (69)

U2739M-B

6.12 HSSO Interface

6.12.1 HSSO Interface Signal Description

QFP144 QFP100

Pin Name

HSSO_WIN

HSSO _CLK

HSSO _DAT

Signal Description

HSSO window signal

Pad Type

PRO04T

Dir.

out

5 V Tol.

30

32

34

21

22

23

HSSO clock signal

HSSO data signal

6.12.2 HSSO Interface Description

The High Speed Serial Output (HSSO) is a standard 3-line D Data decoder 2

output interface implemented to give out data bursts in a

multiplexed way. Up to 4 applications can be given out

simultaneously:

D Programme Associated Data (PAD)

The HSSO can be configured using the ’set HSSO / RS232

configuration’ MC command (see section 8). Each HSSO

burst consists of a header word followed by n data words

(as indicated in the header).

D Channel Impulse Response (CIR)

D Data decoder 1

HSSO-ID

Length

(Burst Identifier)

(Number of Transmitted Data Words n Without Header Word)

bit 15

14

0

13

0

12

0

11

10

9

8

7

6

5

4

3

2

1

0

CIR

0

Number of CIR words

Number of DD1 words

Number of DD2 words

Number of PAD words

DD1

DD2

PAD

0

1

0

1

0

1

6.12.3 HSSO Interface Timing Diagram

tclk

tH

tL

HSSO_CLK

HSSO_WIN

HSSO_DAT

td1

15

14

13

1

0

15

14

13

1

0

15

0

15

14

1

0

td2

header

Data

0

Data n–1

Figure 19. HSSO interface timing diagram

6.12.4 HSSO Interface Timing Parameters

Parameter

Symbol

Min.

Typ.

Max.

Unit

us

HSSO clock period

HSSO clock high

HSSO clock low

tclk

tH

4.07

2.035

0.0

us

tL

us

HSSO_WIN output delay

HSSO_DAT output delay

td1

td2

–5.0

5.0

ns

0.0

ns

30 (69)

Rev. A1, 22-May-01

U2739M-B

7 Electrical Characteristics

7.1 Absolute Maximum Ratings

Parameter

Symbol

VDD

Min.

–0.5

–65

Max.

VDD + 0.5

125

Unit

V

Supply voltage

Input / output voltage

Storage temperature

Vin/Vout

Tstg

V

°C

7.2 Operating Range

Parameter

Symbol

VDD

Min.

Typ.

Max.

3.6

Unit

V

Supply voltage

3.0

0

3.3

Input / output voltage

Ambient temperature

Power dissipation

Vin/Vout

Tamb

VDD

+85

V

–40

°C

Pstat

20

mW

Power dissipation

Pdyn

860

7.3 DC Characteristics

Parameter

Input HIGH voltage

Input LOW voltage

Threshold

Test Conditions

Pad Type Symbol

Min.

Typ.

Max.

Unit

VIH

VIL

VT

2.0

V

0.8

1.4

Output HIGH voltage IOH= –2 mA

IOH= –4 mA

VOH

Pxx02x

Pxx04x

Pxx02x

Pxx04x

2.4

VDD

0.4

Output LOW voltage IOL= 2 mA

IOL= 4 mA

VOL

0.2

0.4

Rev. A1, 22-May-01

31 (69)

U2739M-B

8 MC Command Set

8.1 ’Set System’ Commands

8.1.1

Set DAB System Mode

Command Settings Overview:

D Set system mode

D Set FSLI control loops

Command

sequence:

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

0

DAB

U2739M-B

Write Command

$6E

$00

Data Mode

7

6

5

4

3

2

1

0

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

0

DAB

U2739M-B

Write Command

Data Mode

$6C

7

6

5

4

3

2

1

0

SMODE

NSM

0

$XX

Command Parameters:

Parameter

Meaning

Description

SMODE(1..0)

New DAB system mode

00:

01:

10:

11:

DAB system mode 4

DAB system mode 1

DAB system mode 2

DAB system mode 3

NSM

New system mode valid

0:

1:

SMODE not valid

SMODE indicates new system mode

32 (69)

Rev. A1, 22-May-01

U2739M-B

8.1.2

Set ASD

Command Settings Overview:

D Set ASD on/off

D Set ASD dynamic range control fixed value

D Set ASD mute state

D Set ASD ScF–CRC on/off

D Set ASD dual channel configuration

D Set ASD fader value

D Set ASD sub–channel ID

D Set ASD dynamic range control on/off

Command

sequence:

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

0

DAB

U2739M-B

Write Command

$6E

$10

Data Mode

7

6

5

4

3

2

1

0

1

0

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

0

DAB

U2739M-B

Write Command

$6C

Data Mode

7

6

5

4

3

2

1

0

ASDE MUTE

FADD

IDV

DCCV FADV DRCON DRCFIX SCFON

$XX

SBCHID

DRCFV

DCC

Rev. A1, 22-May-01

33 (69)

U2739M-B

Command Parameters:

Parameter

Meaning

ASD enable

Description

ASDE

0:

1:

ASD disabled

ASD enabled

MUTE

IDV

ASD mute state

0:

1:

ASD output active

ASD output muted

ASD SBCHID valid

DCC setting valid

Fader setting valid

DRC on/off switch

0:

1:

Last set ASD SBCHID remains valid

Following ASD SBCHID valid

DCCV

FADV

DRCON

DRCFIX

SCFON

FAD

0:

1:

Last set DCC remains valid

Following DCC valid

0:

1:

Last set FAD remains valid

Following FAD valid

0:

1:

DRC off

DRC on

DRC additional fixed gain 0:

value valid

DRC additional fixed gain + 6 dB (default)

DRC additional fixed gain according to DRCFV

1:

ScF–CRC on/off switch

0:

1:

ScF–CRC off

ScF–CRC on

Fader value

00:

01:

10:

11:

Fade In / Fade out over 0 frames each

Fade In / Fade out over 30 frames each

Fade In / Fade out over 60 frames each

Fade In / Fade out over 90 frames each

SBCHID(5..0)

DCC(1..0)

Sub–channel identifier

n:

ASD sub–channel ID

Dual channel

configuration

00/10: Left channel on both ASD output channels

01:

11:

Right channel on both ASD output channels

Both channels on ASD output

DRCFV(5..0)

DRC additional fixed gain 000000:

value 000001:

Fixed gain 0 dB

Fixed gain + 0.25 dB

... (continuous steps of +0.25 dB)

111111:

fixed gain + 15.75 dB

34 (69)

Rev. A1, 22-May-01

U2739M-B

8.1.3

Set DD1

DD configuration for transmission in packet mode

Command Settings Overview:

D Set DD1 on/off

D Set DD1 sub–channel ID

D Set DD1 packet address

Command

sequence:

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

0

DAB

U2739M-B

Write Command

$6E

Data Mode

7

6

5

4

3

2

1

0

1

0

1

$11

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

0

DAB

U2739M-B

Write Command

Data Mode

$6C

7

6

5

4

3

2

1

0

DD1E

FIDC

PA1V

ID1V

0

PA(9/8)

$XX

PA(7..0)

0

SBCHID

Command Parameters:

Parameter

Meaning

Description

DD1E

DD1 enable

0:

1:

DD1 disabled

DD1 enabled

FIDC

PA1V

ID1V

FIDC decoding switch

PA valid

0:

1:

DD1 decodes MSC

DD1 decodes FIDC

1)

0:

1:

Last set DD1 PA remains valid

Following DD1 PA valid

DD1 SBCHID valid

0:

1:

Last set DD1 SBCHID remains valid

Following DD1 SBCHID valid

PA(9..0)

Packet address

n:

DD1 packet address

SBCHID(5..0)

Sub–channel identifier

DD1 sub–channel ID

1)

in this case PA and SBCHID parameters are ignored (regardless of whether PA1V/ID1V have been set or not)

Rev. A1, 22-May-01

35 (69)

U2739M-B

8.1.4

Set DD2

DD configuration for transmission in packet mode

Command Settings Overview:

D Set DD2 on/off

D Set DD2 sub–channel ID

D Set DD2 packet address

D Set DD2 AIC on/off

Command

sequence:

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

0

DAB

U2739M-B

Write Command

$6E

$12

Data Mode

7

6

5

4

3

2

1

0

1

0

1

0

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

0

DAB

U2739M-B

Write Command

Data Mode

$6C

7

6

5

4

3

2

1

0

DD2E

AIC

PA2V

ID2V

0

PA(9/8)

$0X

$XX

PA(7..0)

0

SBCHID

Command Parameters:

Parameter

Meaning

Description

DD2E

DD2 enable

0:

1:

DD2 disabled

DD2 enabled

AIC

AIC decoding switch

DD2 PA valid

0:

1:

DD2 decodes MSC

DD2 decodes AIC

2)

PA2V

ID2V

0:

1:

Last set DD2 PA remains valid

Following DD2 PA valid

DD2 SBCHID valid

0:

1:

Last set DD2 SBCHID remains valid

Following DD2 SBCHID valid

PA(9..0)

Packet address

n:

DD2 packet address

SBCHID(5..0)

Sub–channel identifier

DD2 sub–channel ID

1)

in this case PA and SBCHID parameters are ignored (regardless of whether PA2V/ID2V have been set or not)

and the default values for AIC decoding (PA = 1023, SBCHID = 63) are used instead

36 (69)

Rev. A1, 22-May-01

U2739M-B

8.1.5

Set CIF Counter and Occurrence Change

Command Settings Overview:

D Set channel decoder CIF counter

D Set channel decoder occurrence change

Command

sequence:

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

0

DAB

U2739M-B

Write Command

$6E

Data Mode

7

6

5

4

3

2

1

0

1

0

1

$13

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

0

DAB

U2739M-B

Write Command

$6C

Data Mode

7

6

5

4

3

2

1

0

CF

AF

CIFCH(4..0)

$XX

CIFCL(7..0)

OC(7..0)

Command Parameters:

Parameter

Meaning

Description

CF(1..0)

Change flags

00:

01:

10:

11:

No change

Sub–channel organization change

Service organization change

Sub–channel & service organization change

AF

Alarm flag

0:

1:

Alarm messages not accessible

Alarm messages accessible

CIFCH(4..0)

CIFCL(7..0)

OC(7..0)

CIF counter (higher part)

CIF counter (lower part)

Occurrence change

n:

CIF counter higher part (modulo 20)

CIF counter lower part (modulo 250)

Value for CIFCL, from which the new

configuration is valid

Rev. A1, 22-May-01

37 (69)

U2739M-B

8.1.6

Set Current SBCHID Long Form

Command Settings Overview:

D Set current sub–channel parameters (long form)

Command

sequence:

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

0

DAB

U2739M-B

Write Command

$6E

$14

Data Mode

7

6

5

4

3

2

1

0

1

0

1

0

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

0

DAB

U2739M-B

Write Command

$6C

Data Mode

7

6

5

4

3

2

1

0

ON

SCEFC

SBCHID

$XX

SCU(9..2)

EPPAR

CU(7..0)

SCU(1..0)

EP

CU(9..8)

38 (69)

Rev. A1, 22-May-01

U2739M-B

Command Parameters:

Parameter

Meaning

Description

Switch sub–channel off

ON

Sub–channel on/off switch 0:

1:

Switch sub–channel on

SCEFC

Single sub–channel for

EFC

0:

1:

Single sub–channel for EFC remains unchanged

Set SBCHID as single sub–channel for EFC

SBCHID(5..0)

SCU(9..0)

EP

sub–channel identifier

Start CU for SBCHID

Error Protection

n:

Sub–channel ID

Start CU address (0..863)

0:

1:

UEP

EEP

EPPAR(2..0)

Error Protection

parameters

If EP = 0 (UEP):

000: Protection level P 1

001: Protection level P 2

010: Protection level P 3

011: Protection level P 4

100: Protection level P 5

If EP = 1 (EEP):

0xx: EEP long form option 0 (protection level xx–A)

00:

01:

10:

11:

Protection level 1–A (code rate 2/8)

Protection level 2–A (code rate 3/8)

Protection level 3–A (code rate 4/8)

Protection level 4–A (code rate 6/8)

1xx: EEP long form option 1 (protection level xx–B)

00:

01:

10:

11:

Protection level 1–B (code rate 4/9)

Protection level 2–B (code rate 4/7)

Protection level 3–B (code rate 4/6)

Protection level 4–B (code rate 4/5)

CU(9..0)

Sub–channel size

(number of CU’s)

n:

Sub–channel size in CU’s (4..864)

Rev. A1, 22-May-01

39 (69)

U2739M-B

8.1.7

Set Next SBCHID Long Form

Command Settings Overview:

D Set next sub–channel parameters

Command

sequence:

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

0

DAB

U2739M-B

Write Command

$6E

$15

Data Mode

7

6

5

4

3

2

1

0

1

0

1

0

1

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

0

DAB

U2739M-B

Write Command

$6C

Data Mode

7

6

5

4

3

2

1

0

ON

SCEFC

SBCHID

$XX

SCU(9..2)

EPPAR

CU(7..0)

SCU(1..0)

EP

CU(9..8)

40 (69)

Rev. A1, 22-May-01

U2739M-B

Command Parameters:

Parameter

Meaning

Description

Switch sub–channel off

ON

Sub–channel on/off switch 0:

1:

Switch sub–channel on

SCEFC

Single sub–channel for

EFC

0:

1:

Single sub–channel for EFC remains unchanged

Set SBCHID as single sub–channel for EFC

SBCHID(5..0)

SCU(9..0)

EP

Sub–channel identifier

Start CU for SBCHID

Error Protection

n:

Sub–channel ID

Start CU address (0..863)

0:

1:

UEP

EEP

EPPAR(2..0)

Error Protection

parameters

If EP = 0 (UEP):

000: Protection level P 1

001: Protection level P 2

010: Protection level P 3

011: Protection level P 4

100: Protection level P 5

If EP = 1 (EEP):

0xx: EEP long form option 0 (protection level xx–A)

00:

01:

10:

11:

Protection level 1–A (code rate 2/8)

Protection level 2–A (code rate 3/8)

Protection level 3–A (code rate 4/8)

Protection level 4–A (code rate 6/8)

1xx: EEP long form option 1 (protection level xx–B)

00:

01:

10:

11:

Protection level 1–B (code rate 4/9)

Protection level 2–B (code rate 4/7)

Protection level 3–B (code rate 4/6)

Protection level 4–B (code rate 4/5)

CU(9..0)

Sub–channel size

(number of CU’s)

n:

Sub–channel size in CU’s (4..864)

Rev. A1, 22-May-01

41 (69)

U2739M-B

8.1.8

Set Current SBCHID Short Form

Command Settings Overview:

D Set current sub–channel parameters (short form)

Command

sequence:

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

0

DAB

U2739M-B

Write Command

$6E

$16

Data Mode

7

6

5

4

3

2

1

0

1

0

1

0

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

0

DAB

U2739M-B

Write Command

$6C

Data Mode

7

6

5

4

3

2

1

0

ON

SCEFC

SBCHID

$XX

Command Parameters:

Parameter

Meaning

Description

ON

Sub–channel on/off switch 0:

Switch sub–channel off

Switch sub–channel on

1:

SCEFC

Single sub–channel for

EFC

0:

1:

Single sub–channel for EFC remains unchanged

Set SBCHID as single sub–channel for EFC

SBCHID(5..0)

Sub–channel identifier

n:

Sub–channel ID

42 (69)

Rev. A1, 22-May-01

U2739M-B

8.2 ’Set Configuration’ Commands

D Set channel decoder AGC values

D Set channel decoder global parameters

8.2.1

Set Global Configuration

Command Settings Overview:

Command

sequence:

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

0

DAB

U2739M-B

Write Command

Data Mode

$6G

$00

7

6

5

4

3

2

1

0

1

0

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

0

DAB

U2739M-B

Write Command

$6C

Data Mode

7

6

5

4

3

2

1

0

AGCV

0

dB3

DSC

PSC(10..8)

$XX

PSC(7..0)

CDPV

IFM

FSYS

SAW

ADCF

0

Command Parameters:

Parameter

Meaning

AGC values valid

Description

Defaults

AGCV

0:

1:

Following DSC/PSC values ignored

Following DSC/PSC values valid

DSC(1..0)

PSC(10..0)

CDPV

Input data scale

Programmable (I)FFT scale

n:

Scale value

Channel decoder parameters valid

0:

1:

Following global parameters ignored

Following global parameters valid

IFM

IF input signal mode

0:

1:

Common IF representation

Reverse IF representation

1

FSYS

Frame synchronization sensitivity

level

00:

01:

10:

11:

Very high

High

Low

01

Very low

SAW

SAW filter equalization switch

ADC format

0:

1:

Equalization off

Equalization on

1

0

ADCF

0:

1:

Binary ADC input format

2’s complement ADC input format

Rev. A1, 22-May-01

43 (69)

U2739M-B

8.2.2

Set TS Configuration

Command Settings Overview:

D Set TS post processing parameters

Command

sequence:

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

0

DAB

U2739M-B

Write Command

$6E

$21

Data Mode

7

6

5

4

3

2

1

0

1

0

1

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

0

DAB

U2739M-B

Write Command

$6C

Data Mode

7

6

5

4

3

2

1

0

PARV

COV

PKS

ISPCnt

$XX

TMIN

CIRTH

NSTH

GFCH

GFCL

44 (69)

Rev. A1, 22-May-01

U2739M-B

Command Parameters:

Parameter

Meaning

Description

De-

faults

PARV

COV

PKS

CIR post processing parameters valid

(PKS / AVG / CIRTH / NSTH / TMIN) 1:

0:

Parameters not valid

Following parameters valid

CIR post processing filter coefficients

valid

0:

1:

Coefficients not valid

following coefficients valid

n

Number of peaks required for ’CIR

correct’ indication

2 :

Required peaks

0

ISPCnt

CIR post processing average

CIR minimum dT output

n:

CIR output average over n+1 values

0

TMIN(7..0)

Minimum dT output after CIR post

processing (* 488 ns)

CIRTH(7..0) CIR threshold

n.n: – Threshold value for CIR peak

detection (format: 4.4 bit)

– Will be multiplied by ?

(standard deviation)

3.0

NSTH(7..0)

B0(15..0)

Noise threshold

n:

– Noise threshold value

(8 bit unsigned)

– Will be multiplied by 32

st

0

IIR filter coefficients

Coefficients for 1 order IIR filter used for

CIR post processing (Q15 format required)

0.5

0

Rev. A1, 22-May-01

45 (69)

U2739M-B

8.2.3

Set FS Configuration

Command Settings Overview:

D Set FS post processing parameters

Command

sequence:

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

0

DAB

U2739M-B

Write Command

$6E

$22

Data Mode

7

6

5

4

3

2

1

0

1

0

1

0

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

0

DAB

U2739M-B

Write Command

$6C

Data Mode

7

6

5

4

3

2

1

0

GA

THA

GB

$XX

THB

GC

F2FT

Command Parameters:

Parameter

Meaning

Description

Defaults

0.03125

0.125

0.25

GA(7..0)

THA(7..0)

GB(7..0)

Area A gradient

Area A threshold

Area B gradient

Area B threshold

Area C gradient

n:

Fractional part

n:

THB(7..0)

GC(7..0)

0.5

F2FT(7..0)

Max. frame–to–frame tolerance n:

Maximum frequency shift in carriers

(format: 3.5 bit)

1.0

46 (69)

Rev. A1, 22-May-01

U2739M-B

8.2.4

Set XO Configuration

Command Settings Overview:

D Set XO control parameters

Command

sequence:

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

0

DAB

U2739M-B

Write Command

$6E

Data Mode

7

6

5

4

3

2

1

0

1

0

1

$23

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

0

DAB

U2739M-B

Write Command

$6C

Data Mode

7

6

5

4

3

2

1

0

XO_Rough line

XO_Fine line

$XX

XOAVG

0

Command Parameters:

Parameter

Meaning

Description

Defaults

nd

XO_B0(15..0)

XO_B1(15..0)

XO_B2(15..0)

XO_A1(15..0)

XO_A2(15..0)

IIR filter coefficients

Coefficients for 2 order IIR filter used for XO

control

0.25

0.5

0.25

0

XOAVG(4..0)

XO control average

n:

XO control average over n+1 values

0

Rev. A1, 22-May-01

47 (69)

U2739M-B

8.2.5

Set HSSO / RS232 Configuration

Command Settings Overview:

D Set HSSO parameters

D Set RS232 parameters

Command

sequence:

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

0

DAB

U2739M-B

Write Command

$6E

$00

Data Mode

7

6

5

4

3

2

1

0

1

0

1

0

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

0

DAB

U2739M-B

Write Command

Data Mode

$6C

7

6

5

4

3

2

1

0

HCLK

RSBAUD

HCIRL

HPAD

HDD2 HDD1

HCIR

$XX

0

RSSEL

Command Parameters:

Parameter

Meaning

HSSO bit clock

Description

HCLK(1..0)

00: 0.768 MHz

01: 1.536 MHz

10: 3.072 MHz

11: 6.144 MHz

HCIRL(1..0)

HSSO CIR output length

00: N values (DAB system mode dependent)

01: N/2

1x: N/4

HPAD

HSSO PAD output switch

HSSO DD2 output switch

HSSO DD1 output switch

HSSO CIR output switch

RS232 baud rate

0: No PAD output via HSSO

1: PAD output

HDD2

0: No DD2 output via HSSO

1: DD2 output

HDD1

0: No DD1 output via HSSO

1: DD1 output

HCIR

0: No CIR output via HSSO

1: CIR output

RSBAUD(1..0)

RSSEL(1..0)

00: 19200 baud

01: 38400 baud

10: 57600 baud

11: 115200 baud

RS232 output selection

00: no output

01: DD1

10: DD2

11: PAD

48 (69)

Rev. A1, 22-May-01

U2739M-B

Command Parameters:

Parameter

Meaning

USE FS module

Description

UFS

0:

1:

Internal set2 XTFPR module used

External USE module used

UFSP

USE FS post processing module

USE TS post processing module

USE XO control module

USE DD1 module

0:

1:

Internal set2 module used

External USE module used

UTSP

0:

1:

Internal set2 module used

External USE module used

UXOC

UDD1

0:

1:

Internal set2 module used

External USE module used

0:

1:

Internal set2 module used

External USE module used

UDD2

USE DD2 module

0:

1:

Internal set2 module used

External USE module used

UPAD

USE PAD extraction module

USE TII module

0:

1:

Internal set2 module used

External USE module used

UTII

0:

1:

Internal set2 module used

External USE module used

UAMD ... UNMI

Reserved

Rev. A1, 22-May-01

49 (69)

U2739M-B

8.2.6

Set WAGC Configuration

Command Settings Overview:

D Set WAGC rising edge / falling edge parameters

Command

sequence:

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

0

DAB

U2739M-B

Write Command

$6E

$26

Data Mode

7

6

5

4

3

2

1

0

1

0

1

0

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

0

DAB

U2739M-B

Write Command

$6C

Data Mode

7

6

5

4

3

2

1

0

WRISE(3..0)

WS

0

WV

$XX

WRISE(11..4)

WRISE(17..12)

WFALL(9..2)

WFALL(1..0)

WFALL(17..10)

Command Parameters:

Parameter

Meaning

WAGC values valid

Description

WV

0:

1:

use default WAGC values

use following WAGC values

WRISE(17..0)

WFALL(17..0)

WAGC rising edge time marker

WAGC falling edge time marker

n:

value for WAGC rising edge

value for WAGC falling edge

50 (69)

Rev. A1, 22-May-01

U2739M-B

8.2.7

Set RCC Slot Configuration

Command Settings Overview:

D Set RCC slot data

Command

sequence:

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

0

DAB

U2739M-B

Write Command

$6E

Data Mode

7

6

5

4

3

2

1

0

1

0

1

$27

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

0

DAB

U2739M-B

Write Command

$6C

Data Mode

7

6

5

4

3

2

1

0

RCC(7..0)

$XX

RCC(15..8)

RCC(23..16)

RCC(31..24)

RCC(39..32)

RCC(47..40)

RCC(55..48)

RCC(63..56)

Command Parameters:

Parameter

Meaning

Description

RCC(63..0)

RCC slot data

Rev. A1, 22-May-01

51 (69)

U2739M-B

8.2.8

Set RFU

Command Settings Overview:

D Set RFU parameters

Command

sequence:

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

0

DAB

U2739M-B

Write Command

$6E

$30

Data Mode

7

6

5

4

3

2

1

0

1

0

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

0

DAB

U2739M-B

Write Command

$6C

Data Mode

7

6

5

4

3

2

1

0

(reserved)

$XX

(reserved)

RFU4

RFU5

RFU6

...

RFU42

RFU43

RFU44

Command Parameters:

Parameter

Meaning

Description

(reserved)

Reserved for internal use (Atmel Wireless &

Microcontrollers will deliver default values, if necessary)

RFU4..44

52 (69)

Reserved for future use

Rev. A1, 22-May-01

U2739M-B

8.3 ’Read Status’ Commands

8.3.1

Read Global Status

Command Overview:

D Get DAB system mode

D Get synchronization status

D Get OAK core operating mode

D Get AGC information

Command

sequence:

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

DAB

U2739M-B

Write Command

$6F

$40

Data Mode

7

6

5

4

3

2

1

0

1

0

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

0

1

DAB

U2739M-B

Write Command

Data Mode

$6D

7

6

5

4

3

2

1

0

DABMODE

OAKMODE

CIRS

PSLI

MV

FSLI

SLI

WDSP

$XX

0

CCIR

CAFC

P(8)

0

IDSL

P(7..0)

Rev. A1, 22-May-01

53 (69)

U2739M-B

Command Parameters:

Parameter

Meaning

Description

DAB system mode 4

DAB system mode 1

DAB system mode 2

DAB system mode 3

DABMODE(1..0)

DAB system mode

00:

01:

10:

11:

OAKMODE(1..0)

OAK operating mode

00:

01:

10:

11:

Normal stand–alone

USE boot mode

XUSE boot mode

HOST boot mode

MV

MODE_VALID line status

FSLI line status

SLI line status

FSLI

SLI

CIRS

CIR status

0:

1:

No CIR detected

CIR correct

CCIR(1..0)

CAFC(1..0)

Coded CIR status

Coded AFC status

00:

01:

10:

11:

|average| ? N/64

N/64 < |average| ? N/8

|average| > N/4

rfu.

00:

01:

10:

11:

|dF

| ? TA

FRAME

TA < |dF

TB < |dF

| ? TB

|< 16 kHz

FRAME

|dF

| ? 16 kHz

FRAME

PSLI(3..0)

IDSL(1..0)

Precise signal level infor- 0000: Very weak signal

mation

...

1111: Very strong signal

Input data signal level

00:

01:

10:

11:

Weak input signal

Typical input signal

Strong input signal

rfu.

P(8..0)

WDSP

Calculated in–band power

Watchdog DSP

Toggels every 24 ms from 0 to 1

54 (69)

Rev. A1, 22-May-01

U2739M-B

8.3.2

Read Synchronization Status

Command Overview:

D Get TS control value

D Get FS control value

Command

sequence:

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

DAB

U2739M-B

Write Command

$6F

Data Mode

7

6

5

4

3

2

1

0

1

0

1

$41

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

0

1

DAB

U2739M-B

Write Command

$6D

Data Mode

7

6

5

4

3

2

1

0

DT(9..2)

$XX

DT(1..0)

0

DF(19..16)

DF(15..8)

DF(7..0)

Command Parameters:

Parameter

DT(9..0)

Meaning

Description

Cycle count (signed, @2.048 MHz)

Deviation in carriers (signed, Q11 format)

1)

Detected time deviation

n:

DF(19..0)

Detected channel

frequency deviation

1)

Signed values refers to virtual zero at T

/2

guard

Rev. A1, 22-May-01

55 (69)

U2739M-B

8.3.3

Read CIR Status

Command Overview:

1)

D Get CIR post processing results

Command

sequence:

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

DAB

U2739M-B

Write Command

$6F

$42

Data Mode

7

6

5

4

3

2

1

0

1

0

1

0

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

0

1

DAB

U2739M-B

Write Command

$6D

Data Mode

7

6

5

4

3

2

1

0

P_FIRST(15..8)

P_FIRST(7..0)

P_AGV(15..8)

P_AGV(7..0)

$XX

P_LAST(15..8)

P_LAST(7..0)

Command Parameters:

Parameter

P_FIRST(15..0)

P_AVG(15..0)

P_LAST(15..0)

Meaning

Description

st

2)

Index of 1 CIR peak above CIR threshold

Index of CIR average value

n:

Cycle count (signed, @2.048 MHz)

Index of last CIR peak above CIR threshold n:

1)

2)

If time synchronization has lost all values are set to $8000 !

Signed values refers to zero at T /2

guard

56 (69)

Rev. A1, 22-May-01

U2739M-B

8.4 ’Read Data’ Commands

8.4.1

Read ASD Header Data

Command Overview:

D Get MPEG audio header

Command

sequence:

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

DAB

U2739M-B

Write Command

$6F

Data Mode

7

6

5

4

3

2

1

0

1

0

1

0

$50

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

0

1

DAB

U2739M-B

Write Command

$6D

Data Mode

7

6

5

4

3

2

1

0

MPG_HW1(15..8)

MPG_HW1(7..0)

MPG_HW2(15..8)

MPG_HW2(7..0)

$XX

Command Parameters:

Parameter

MPG_HW1(15..0)

MPG_HW2(15..0)

Meaning

Description

st

1 MPEG header word

Sync. word ($FFFx) expected

MPEG stream signature

nd

2

MPEG header word

Rev. A1, 22-May-01

57 (69)

U2739M-B

8.4.2

Read X–PAD

Command Overview:

D Get MPEG ancillary data (X–PAD)

Command

sequence:

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

DAB

U2739M-B

Write Command

$6F

Data Mode

7

6

5

4

3

2

1

0

1

0

1

0

XPNUM

$5X

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

0

1

DAB

U2739M-B

Write Command

$6D

Data Mode

7

6

5

4

3

2

1

0

X–PAD0

...

X–PAD31

$XX

Command Parameters:

Parameter

Meaning

Description

XPNUM

X–PAD block number n The maximum X–PAD capacity supported by the U2739M-B is 64kbit/s.

(n from 1..5)

The access is splitted into 6 blocks (numbered 1..5) of 32 bytes.

The blocks are time aligned, that means block 1 is the first block in an

MPEG frame after audio samples.

X–PADm

X–PAD byte m

Byte 0 is the first byte of block n, byte 31 the last one. It is followed by

the first one of block n+1.

Read RFU

Use MC command “RFU” to read block 6

58 (69)

Rev. A1, 22-May-01

U2739M-B

8.4.3

Read F–PAD

Command Overview:

D Get MPEG ancillary data (F–PAD)

Command

sequence:

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

DAB

U2739M-B

Write Command

$6F

Data Mode

7

6

5

4

3

2

1

0

1

0

1

0

$58

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

0

1

DAB

U2739M-B

Write Command

$6D

Data Mode

7

6

5

4

3

2

1

0

F–PAD0

F–PAD1

$XX

Command Parameters:

Parameter

F–PAD0

Meaning

Description

F–PAD byte 0

F–PAD byte 1

F–PAD1

Rev. A1, 22-May-01

59 (69)

U2739M-B

8.4.4

Read AIC Data

Command Overview:

D Get AIC data

Command

sequence:

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

DAB

U2739M-B

Write Command

$6F

Data Mode

7

6

5

4

3

2

1

0

1

0

AICNUM

$6X

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

0

1

DAB

U2739M-B

Write Command

$6D

Data Mode

7

6

5

4

3

2

1

0

AIC0

...

$XX

AIC31

Command Parameters:

Parameter

Meaning

Description

AICNUM

AIC block number n The maximum AIC capacity is 512 bytes.

The access is splitted into 16 blocks (numbered 0..15) of 32 bytes.

The blocks are time aligned, that means block 0 is the first filled block.

AICm

AIC byte m

Byte 0 is the first byte of block n, byte 31 the last one. It is followed by

the first one of block n+1.

60 (69)

Rev. A1, 22-May-01

U2739M-B

8.4.5

Read TII Data

Command Overview:

D Get TII data

Command

sequence:

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

DAB

U2739M-B

Write Command

$6F

Data Mode

7

6

5

4

3

2

1

0

1

0

TIINUM

$7X

$6D

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

0

1

DAB

U2739M-B

Write Command

Data Mode

7

6

5

4

3

2

1

0

TII0

...

$XX

TII31

Command Parameters:

Parameter

Meaning

Description

TIINUM

TII block number n The maximum TII capacity is 128 bytes.

The access is splitted into 4 blocks (numbered 0..3) of 32 bytes.

The blocks are time aligned, that means block 0 is the first filled block.

TIIm

TII byte m

Byte 0 is the first byte of block n, byte 31 the last one. It is followed by

the first one of block n+1.

Rev. A1, 22-May-01

61 (69)

U2739M-B

8.4.6

Read EFC Data

Command Overview:

D Get EFC data

Command

sequence:

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

DAB

U2739M-B

Write Command

$6F

Data Mode

7

6

5

4

3

2

1

EFCSEL

0

1

0

$8X

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

0

1

DAB

U2739M-B

Write Command

$6D

Data Mode

7

6

5

4

3

2

1

0

EFC(7..0)

EFC(15..8)

$XX

Command Parameters:

Parameter

Meaning

Description

EFCSEL

EFC selection

00:

01:

EFC of FIC

EFC of all MSC applications

EFC(15..0)

EFC value for chosen

application

n:

EFC value summarized over...

... 12 FIB’s

... 3 FIB’s

... 4 FIB’s

... 6 FIB’s

(DAB mode 1)

(DAB mode 2)

(DAB mode 3)

(DAB mode 4)

62 (69)

Rev. A1, 22-May-01

U2739M-B

8.4.7

Read FIC Data

Command Overview:

D Get FIB bytes

Command

sequence:

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

DAB

U2739M-B

Write Command

$6F

Data Mode

7

6

5

4

3

2

1

0

1

0

1

FIBNUM

$9X

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

0

1

DAB

U2739M-B

Write Command

$6D

Data Mode

7

6

5

4

3

2

1

0

FIB0

...

$XX

FIB31

$XX

Command Parameters:

Parameter

Meaning

Description

FIBNUM

FIB number n Possible FIB numbers DAB mode dependent:

0..11 (DAB mode 1)

0..2 (DAB mode 2)

0..3 (DAB mode 3)

0..5 (DAB mode 4)

FIBm

FIB byte m

Each FIB consists of 32 bytes. The order of the FIB bytes and bits corresponds

to the serial FIC processing. That means:

(1) Byte order:

The first 8 output bits after FIC processing represent FIB byte 0 of FIB num-

ber 0, the next ones FIB byte 1 of FIB number 0 and so on.

(2) Bit order:

The FIB bytes are given out MSB first. The first outgoing bit represents bit 7

of the corresponding byte, the next one bit 6 and so on. The FIB bits are num-

bered from bit 0 (MSB of FIB0) up to bit 255 (LSB of FIB31).

NOTE:

The last 2 bytes of an FIB represent the result of the U2739M internal CRC

check. That means, if these bytes are $00 both, the internal CRC check was

successful and the FIB data bytes are correct.

Rev. A1, 22-May-01

63 (69)

U2739M-B

8.4.8

Read RCC Slot

Command Overview:

D Get RCC slot data

Command

sequence:

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

DAB

U2739M-B

Write Command

$6F

Data Mode

7

6

5

4

3

2

1

0

1

0

1

0

$A0

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

0

1

DAB

U2739M-B

Write Command

$6D

Data Mode

7

6

5

4

3

2

1

0

RCC(7..0)

$XX

RCC(15..8)

RCC(23..16)

RCC(31..24)

RCC(39..32)

RCC(47..40)

RCC(55..48)

RCC(3..56)

Command Parameters:

Parameter

Meaning

Description

RCC(63..0)

RCC slot data

64 (69)

Rev. A1, 22-May-01

U2739M-B

8.4.9

Read Slot Pointer

Command Overview:

D Get RCC RX/TX slot pointer

Command

sequence:

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

DAB

U2739M-B

Write Command

$6F

Data Mode

7

6

5

4

3

2

1

0

1

0

1

0

1

$A1

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

0

1

DAB

U2739M-B

Write Command

$6D

Data Mode

7

6

5

4

3

2

1

0

TXPTR

RXPTR

$XX

Command Parameters:

Parameter

RXPTR(3..0)

Meaning

Description

RCC RX slot pointer

RCC TX slot pointer

TXPTR(3..0)

Rev. A1, 22-May-01

65 (69)

U2739M-B

8.4.10 Read RFU

Command Overview:

D Get RFU data

Command

sequence:

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

DAB

U2739M-B

Write Command

$6F

Data Mode

7

6

5

4

3

2

1

0

1

0

1

0

$9X

Address Mode

7

6

1

5

4

3

2

1

0

1

0

1

0

1

DAB

U2739M-B

Write Command

$6D

Data Mode

7

6

5

4

3

2

1

0

RFU0

...

$XX

RFU43

Command Parameters:

Parameter

XPAD0..31

Meaning

Description

XPAD block 6

See: read XPAD command

Reserved for future use

RFU0..11

66 (69)

Rev. A1, 22-May-01

U2739M-B

9 Package Information

Rev. A1, 22-May-01

67 (69)

U2739M-B

68 (69)

Rev. A1, 22-May-01

U2739M-B

Ozone Depleting Substances Policy Statement

It is the policy of Atmel Germany GmbH to

1. Meet all present and future national and international statutory requirements.

2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems

with respect to their impact on the health and safety of our employees and the public, as well as their impact on

the environment.

It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as

ozone depleting substances (ODSs).

The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid

their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these

substances.

Atmel Germany GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed

in the following documents.

1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively

2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental

Protection Agency (EPA) in the USA

3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively.

Atmel Germany GmbH can certify that our semiconductors are not manufactured with ozone depleting substances

and do not contain such substances.

We reserve the right to make changes to improve technical design and may do so without further notice.

Parameters can vary in different applications. All operating parameters must be validated for each customer

application by the customer. Should the buyer use Atmel Wireless & Microcontrollers products for any unintended

or unauthorized application, the buyer shall indemnify Atmel Wireless & Microcontrollers against all claims,

costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death

associated with such unintended or unauthorized use.

Data sheets can also be retrieved from the Internet:

http://www.atmel–wm.com

Atmel Germany GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany

Telephone: 49 (0)7131 67 2594, Fax number: 49 (0)7131 67 2423

Rev. A1, 22-May-01

69 (69)


型号：	U2739M-BFT
厂家：	ATMEL
描述：	DAB One-Chip Channel- and Source Decoder 民建联单芯片通道和信源解码器解码器消费电路商用集成电路异步传输模式 ATM
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