U2794B-MFSG3 [ATMEL]
1000 MHZ QUADRATURE DEMODULATOR; 1000兆赫正交解调器
| 型号： | U2794B-MFSG3 |
| 厂家： | 
ATMEL |
| 描述： | 1000 MHZ QUADRATURE DEMODULATOR |
| 文件： | 总15页 (文件大小：281K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Supply Voltage 5 V
• Very Low Power Consumption 125 mW
• Very Good Image Rejection By Means of Phase Control Loop for Precise 90° Phase
Shifting
• Duty-cycle Regeneration for Single-ended LO Input Signal
• Low LO Input Level -10 dBm
• LO Frequency from 70 MHz to 1 GHz
• Power-down Mode
• 25 dB Gain Control
• Very Low I/Q Output DC Offset Voltage Typically < 5 mV
1000-MHz
Quadrature
Demodulator
Benefits
• Low Current Consumption
• Easy to Implement
• Perfect Performance for Large Variety of Wireless Applications
U2794B
Electrostatic sensitive device.
Observe precautions for handling.
Description
The silicon monolithic integrated circuit U2794B is a quadrature demodulator manu-
factured using Atmel’s advanced UHF technology. This demodulator features a
frequency range from 70 MHz to 1000 MHz, low current consumption, selectable gain,
power-down mode and adjustment-free handling. The IC is suitable for direct conver-
sion and image rejection applications in digital radio systems up to 1 GHz such as
cellular radios, cordless telephones, cable TV and satellite TV systems.
Rev. 4653C–CELL–06/03
Figure 1. Block Diagram
VS
IIX
II
PU
5,6 14
4
3
IX
Power
down
1
2
OUTPUT
I
0°
15
90°Control
loop
Frequency
doubler
Duty cycle
regenerator
7
8
LO
RFin
90°
17
13
PC
PCX
12
19
20
Q
OUTPUT
QX
10
9
11
16,18
GND
GC
QQ
QQX
Pin Configuration
Figure 2. Pinning SSO20
1
2
20
19
18
17
16
15
14
13
12
11
IX
QX
Q
I
3
II
GND
4
IIX
LOin
5
V
S
GND
6
LOXin
V
S
7
RFin
PU
RFXin
8
PC
9
PCX
GC
QQ
10
QQX
2
U2794B
4653C–CELL–06/03
U2794B
Pin Description
Pin
Symbol
Function
1
IX
IX output
2
I
I output
3
II
II lowpass filter I
IIX lowpass filter I
Supply voltage
Supply voltage
RF input
4
IIX
5
VS
6
VS
7
RFin
RFXin
QQ
QQX
GC
PCX
PC
8
RFX input
9
QQ lowpass filter Q
QQX lowpass filter Q
GC gain control
PCX phase control
PC phase control
PU power up
LOX input
10
11
12
13
14
15
16
17
18
19
20
PU
LOXin
GND
LOin
GND
Q
Ground
LO input
Ground
Q output
QX
QX output
3
4653C–CELL–06/03
Absolute Maximum Ratings
Parameters
Symbol
Value
6
Unit
V
Supply voltage
VS
Vi
Input voltage
0 to VS
+125
V
Junction temperature
Storage-temperature range
Tj
LC
LC
Tstg
-40 to +125
Thermal Resistance
Parameters
Symbol
Value
Unit
Junction ambient SSO20
RthJA
140
K/W
Operating Range
Parameters
Symbol
VS
Value
Unit
V
Supply-voltage range
Ambient-temperature range
4.75 to 5.25
-40 to +85
Tamb
LC
Electrical Characteristics
Test conditions (unless otherwise specified); VS = 5 V, Tamb = 25°C, referred to test circuit
System impedance ZO = 50 ꢀ, fiLO = 950 MHz, PiLO = -10 dBm
No.
1.1
1.2
2
Parameters
Test Conditions
Pin
5, 6
5, 6
Symbol
Min.
4.75
22
Typ.
Max.
5.25
35
Unit
Type*
Supply-voltage range
Supply current
VS
IS
V
A
A
30
mA
Power-down Mode
2.1
“OFF” mode supply
current
VPU ? 0.5 V
14, 5
6
ISPU
? 1
20
µA
µA
B
D
VPU = 1.0 V
(1)
3
Switch Voltage
3.1
“Power ON”
14
VPON
4
V
D
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes: 1. During power-down status a load circuitry with DC-isolation to GND is assumed, otherwise a current of I Wꢀ(VS -0.8 V)/RI
has to be added to the above power-down current for each output I, IX, Q, QX.
2. The required LO-Level is a function of the LO frequency (see Figure 8).
3. Measured with input matching. For 950 MHz, the optional transmission line T3 at the RF input may be used for this pur-
pose. Noise figure measurements without using the differential output signal result in a worse noise figure.
4. Using Pins 7 and 8 as a symmetric RF input, the second-order IIP can be improved.
5. Due to test board parasitics, this bandwidth may be reduced and not be equal for I, IX, Q, QX. If symmetry and full band-
width is required, the lowpass Pins 3, 4 and 9, 10 should be isolated from the board. the bandwidth of the I/Q outputs can
be increased further by using a resistor between Pins 3, 4, 9 and 10. These resistors shunt the internal loads of
RI ~ 5.4 kꢁ. The decrease in gain here has to be considered.
6. The internal current of the output emitter followers is 0.6 mA. This reduces the undistorted output voltage swing at a 50 ꢁ
load to approsimately 30 mV. For low signal distortion the load impedance should be RI O 5 kꢁ.
7. Referred to the level of the output vector I2 + Q2
8. The low-gain status is achieved with an open or high-ohmic Pin 11. A recommended application circuit for switching
between high and low gain status is hown in Figure 3.
4
U2794B
4653C–CELL–06/03
U2794B
Electrical Characteristics (Continued)
Test conditions (unless otherwise specified); VS = 5 V, Tamb = 25°C, referred to test circuit
System impedance ZO = 50 ꢀ, fiLO = 950 MHz, PiLO = -10 dBm
No.
3.2
4
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
“Power DOWN”
LO Input, LOin
Frequency range
Input level
14
VPOFF
1
V
D
4.1
4.2
4.3
4.4
17
17
17
17
fiLO
PiLO
70
1000
-5
MHz
dBm
ꢁ
D
D
D
D
(2)
-12
-10
50
Input impedance
See Figure 12
See Figure 5
ZiLO
Voltage standing
wave ratio
VSWRLO
1.2
2
4.5
5
Duty-cycle range
17
DCRLO
0.4
40
0.6
D
D
RF Input, RFin
5.1
Noise figure (DSB)
symmetrical output
at 950 MHz (3)
at 100 MHz
7, 8
NF
fiRF
12
10
dB
5.2
5.3
Frequency range
fiRF = FiLO ±ꢀBWYQ
7, 8
7, 8
1030
MHz
dBm
D
D
-1 dB input
compression point
High gain
Low gain
(4)
P1dBHG
P1dBLG
-8
+3.5
5.4
5.5
Second order IIP
Third order IIP
7, 8
7, 8
IIP2HG
35
dBm
dBm
D
D
High gain
Low gain
IIP3HG
IIP3LG
+3
+13
5.6
LO leakage
Symmetric input
Asymmetric input
7, 8
LOL
? -60
? -55
dBm
D
D
5.7
6
Input impedance
see Figure 12
7, 8
ZiRF
500II0.8
ꢁIIpF
I/Q Outputs (I, IX, Q, QX) Emitter Follower I = 0.6 mA
6.1
3–dB bandwidth
w/o external C
1, 2, 19,
20
BWI/Q
Ae
O 30
-0.5
-3
MHz
dB
D
B
B
6.2
6.3
I/Q amplitude error
1, 2, 19,
20
? M0.2
? M1.5
+0.5
+3
I/Q phase error
1, 2, 19,
20
Pe
Deg
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes: 1. During power-down status a load circuitry with DC-isolation to GND is assumed, otherwise a current of I Wꢀ(VS -0.8 V)/RI
has to be added to the above power-down current for each output I, IX, Q, QX.
2. The required LO-Level is a function of the LO frequency (see Figure 8).
3. Measured with input matching. For 950 MHz, the optional transmission line T3 at the RF input may be used for this pur-
pose. Noise figure measurements without using the differential output signal result in a worse noise figure.
4. Using Pins 7 and 8 as a symmetric RF input, the second-order IIP can be improved.
5. Due to test board parasitics, this bandwidth may be reduced and not be equal for I, IX, Q, QX. If symmetry and full band-
width is required, the lowpass Pins 3, 4 and 9, 10 should be isolated from the board. the bandwidth of the I/Q outputs can
be increased further by using a resistor between Pins 3, 4, 9 and 10. These resistors shunt the internal loads of
RI ~ 5.4 kꢁ. The decrease in gain here has to be considered.
6. The internal current of the output emitter followers is 0.6 mA. This reduces the undistorted output voltage swing at a 50 ꢁ
load to approsimately 30 mV. For low signal distortion the load impedance should be RI O 5 kꢁ.
7. Referred to the level of the output vector I2 + Q2
8. The low-gain status is achieved with an open or high-ohmic Pin 11. A recommended application circuit for switching
between high and low gain status is hown in Figure 3.
5
4653C–CELL–06/03
Electrical Characteristics (Continued)
Test conditions (unless otherwise specified); VS = 5 V, Tamb = 25°C, referred to test circuit
System impedance ZO = 50 ꢀ, fiLO = 950 MHz, PiLO = -10 dBm
No.
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
6.4
I/Q maximum output
swing
Symm. output
RL > 5 kꢁ
1, 2, 19,
20
VPP
2
D
6.5
6.6
DC output voltage
1, 2, 19,
20
VOUT
Voffset
2.5
2.8
< 5
3.1
V
A
(6)
DC output offset
voltage
1, 2, 19,
20
mV
Test
Spec.
6.7
Output impedance
see Figure 12
1, 2, 19,
20
Zout
50
ꢁ
D
7
Gain Control, GC
(7)
7.1
Control range power
Gain high
11
GCR
GH
25
23
-2
dB
D
B
D
dBm
dBm
Gain low
GL
7.2
7.3
7.4
7.5
7.6
7.7
Switch Voltage
“Gain high”
11
1
V
(8)
“Gain low”
11 < open
Settling Time, ST
Power “OFF” - “ON”
Power “ON” - “OFF”
TSON
< 4
< 4
µs
µs
D
D
TSOFF
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes: 1. During power-down status a load circuitry with DC-isolation to GND is assumed, otherwise a current of I Wꢀ(VS -0.8 V)/RI
has to be added to the above power-down current for each output I, IX, Q, QX.
2. The required LO-Level is a function of the LO frequency (see Figure 8).
3. Measured with input matching. For 950 MHz, the optional transmission line T3 at the RF input may be used for this pur-
pose. Noise figure measurements without using the differential output signal result in a worse noise figure.
4. Using Pins 7 and 8 as a symmetric RF input, the second-order IIP can be improved.
5. Due to test board parasitics, this bandwidth may be reduced and not be equal for I, IX, Q, QX. If symmetry and full band-
width is required, the lowpass Pins 3, 4 and 9, 10 should be isolated from the board. the bandwidth of the I/Q outputs can
be increased further by using a resistor between Pins 3, 4, 9 and 10. These resistors shunt the internal loads of
RI ~ 5.4 kꢁ. The decrease in gain here has to be considered.
6. The internal current of the output emitter followers is 0.6 mA. This reduces the undistorted output voltage swing at a 50 ꢁ
load to approsimately 30 mV. For low signal distortion the load impedance should be RI O 5 kꢁ.
7. Referred to the level of the output vector I2 + Q2
8. The low-gain status is achieved with an open or high-ohmic Pin 11. A recommended application circuit for switching
between high and low gain status is hown in Figure 3.
6
U2794B
4653C–CELL–06/03
U2794B
Figure 3. Test Circuit
PU
* optional for single-ended tests (notice 3 dB bandwidth of AD620)
T1, T2 = transmission line ZO = 50 ꢀꢁ
If no GC function is required, connect Pin 11 to GND.
For high and low gain status GC´ is to be switched to GND respectively to VS.
Figure 4. I and Q phase for fRF > fLO. For fRF < fLO the phase is inverted.
1.5
1.0
Q
I
0.5
0.0
0
5
10
15
20
25
30
-0.5
-1.0
-1.5
time (arbitrary units)
7
4653C–CELL–06/03
Figure 5. Typical VSWR Frequency Response of the LO Input
6
5
4
3
2
1
1050
50
250
450
650
850
LO Frequency ( MHz )
Figure 6. Noise Figure versus LO Frequency; o: Value at 950 MHz with RF Input
Matching with T3
18
16
14
12
10
8
0
200
400
600
800
1000
LO Frequency (MHz)
Figure 7. Typical Suitable LO Power Range versus Frequency
0
PLOmax
-10
-20
-30
-40
-50
PLOmin
30
40
50
60
70
80
90
LO Frequency (MHz)
8
U2794B
4653C–CELL–06/03
U2794B
Figure 8. Gain versus LO Frequency; x: Value at 950 MHz with RF Input Matching with
T3
30
26
22
18
14
10
0
200
400
600
800
1000
LO Frequency (MHz)
Figure 9. Typical Output Signal versus LO Frequency for PRF = -15 dBm and
PLO = -15 dBm
1600
1500
1400
1300
1200
1100
1000
900
800
0
200
400
600
800
1000
LO Frequency (MHz)
Figure 10. Typical Suitable LO Power Range versus Frequency
10
0
-10
-20
-30
-40
-50
0
200
400
600
800
1000
LO Frequency (MHz)
9
4653C–CELL–06/03
Figure 11. Typical Output Voltage (single ended) versus PRF at Tamb = 25°C and
PLO = -15 dBm
1800
1600
1400
1200
1000
800
600
400
200
0
-40
-35
-30
-25
-20
-15
-10
PRF (dBm)
Figure 12. Typical S11 Frequency Response
j
0.5j
2j
0.2j
5j
c
a
0
0.2
0.5
1
2
5
1
b
-0.2j
-5j
-0.5j
-2j
-j
a: LO input, LO frequency from 100 MHz to 1100 MHz, marker: 950 MHz
b: RF input, RF frequency from 100 MHz to 1100 MHz, marker: 950 MHz
c: I/Q Outputs, Baseband Frequency from 5 MHz to 55 MHz, marker: 25 MHz
10
U2794B
4653C–CELL–06/03
U2794B
Figure 13. Evaluation Board Layout
Figure 14. Evaluation Board
11
4653C–CELL–06/03
External Components
CUCC
CRFX
CLO
100 nF
1 nF
100 pF
1 nF
CNLO
CRF
100 pF
CII, CQQ
T3
optional external lowpass filters
transmission line for RF-input matching, to connect
optionally
CI, CIX
CQ, CQX
CPDN
CGC
optional for AC-coupling at
baseband outputs
not connected
100 pF
100 pF
100 pF
100 pF
CPC
not connected
not connected
gain switch
CNPC
GSW
Calibration Part
CO, CS, CL 100 pF
RL 50 ꢀ
Conversion to Single
Ended Output
(see data sheet of AD620)
OP1, OP2
RG1, RG2
AD620
prog. gain, see datasheet, for 5.6 kꢀ a gain of 1 at
50 ꢀ is achieved together with RD1 and RD2.
RD1, RD2
CS1, CS2
CS3, CS4
450 ꢀ
100 nF
100 nF
12
U2794B
4653C–CELL–06/03
U2794B
Description of the
Evaluation Board
Board material: epoxy; ꢂr = 4.8, thickness = 0.5 mm, transmission lines: ZO = 50 ꢀ
The board offers the following functions:
•
Test circuit for the U2794B:
–
The supply voltage and the control inputs GC, PC and PU are connected via
a plug strip. The control input voltages can be generated via external
potentiometers; then the inputs should be AC-grounded (time requirements
in burst mode for power up have to be considered).
–
The outputs I, IX, Q, QX are DC coupled via an plug strip or can be AC-
connected via SMB plugs for high frequency tests e.g. noise figure or s-
parameter measurement. The Pins II, IIX, QQ, QQX allow user-definable
filtering with 2 external capacitors CII, CQQ.
–
–
The offsets of both channels can be adjusted with two potentimeters or
resistors.
The LO- and the RF-inputs are AC-coupled and connected via SMB plugs. If
transmission line T3 is connected to the RF-input and AC-grounded at the
other end, gain and noise performance can be improved (input matching to
50 ꢀ).
–
The complementary RF-input is AC-coupled to GND (CRFX = 1 nF), the
same appears to the complementary LO input (CNLO = 1 nF).
•
•
A calibration part which allows to calibrate an s-parameter analyzer directly to the in-
and output- signal ports of the U2794B.
For single-ended measurements at the demodulator outputs, two OPs (e.g., AD620
or other) can be con-figured with programmable gain; together with an output-
divider network RD = 450 ꢀ to RL = 50 ꢀ, direct measurements with 50 ꢀ load
impedances are possible at frequencies t < 100 kHz.
13
4653C–CELL–06/03
Ordering Information
Extended Type Number
Package
SSO20
SSO20
Remarks
U2794B-MFS
Tube, MOQ 830 pcs
Taped and reeled, MOQ 4000 pcs
U2794B-MFSG3
Package Information
5.7
5.3
Package SSO20
Dimensions in mm
6.75
6.50
4.5
4.3
1.30
0.15
0.15
0.05
0.25
0.65
6.6
6.3
5.85
20
11
technical drawings
according to DIN
specifications
1
10
14
U2794B
4653C–CELL–06/03
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© Atmel Corporation 2003.
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which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
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Printed on recycled paper.
4653C–CELL–06/03
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