AFCT-57D5ATPZ [AVAGO]
16GFC SFP Digital Diagnostic SFP, 850 nm, 16G/8G/4G Low Voltage (3.3 V) Fibre Channel Optical Transceiver;
| 型号： | AFCT-57D5ATPZ |
| 厂家： | 
AVAGO TECHNOLOGIES LIMITED |
| 描述： | 16GFC SFP Digital Diagnostic SFP, 850 nm, 16G/8G/4G Low Voltage (3.3 V) Fibre Channel Optical Transceiver |
| 文件： | 总22页 (文件大小：669K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AFBR-57F5MZ
16GFC SFP+ Digital Diagnostic SFP, 850 nm, 16G/8G/4G
Low Voltage (3.3 V) Fibre Channel Optical Transceiver
Data Sheet
Description
Features
• Compliant to RoHS directives
• 850 nm Vertical Cavity Surface Emitting Laser (VCSEL)
• Class 1 eye safe per IEC60825-1 and CDRH
• Wide temperature range (0 °C to 70 °C)
• LC duplex connector optical interface conforming to
ANSI TIA/EIA604-10 (FOCIS 10A)
• Diagnostic features per SFF-8472 “Diagnostic Monitor-
ing Interface for Optical Transceivers”
Avago Technologies’ AFBR-57F5MZ optical transceiver
supports high speed serial links over multi-mode opti-
cal fiber at signalling rates up to 14.025 Gb/s (the serial
line rate of 16GFC). The product is compliant with Small
Form Pluggable industry agreements SFP and SFP+ for
mechanical and low speed electrical specifications. High
speed electrical and optical specifications are compliant
with ANSI Fibre Channel FC-PI-5.
The AFBR-57F5MZ is a multi-rate 850nm transceiver
which ensures compliance with FC-PI-5 16GFC, 8GFC and
4GFC specifications. Per the requirements of 16GFC, inter-
nal clock and data recovery circuits (CDRs) are present on
both electrical input and electrical output of this trans-
ceiver. These CDRs will lock at 14.025 Gb/s (16GFC) but
must be bypassed for operation at 8.5 Gb/s (8GFC) and
4.25 Gb/s (4GFC), accomplished by using two Rate Select
inputs to configure transmit and receive sides. Transmitter
and receiver can operate at different data rates, as is often
seen during Fibre Channel speed negotiation.
• Enhanced operational features including EWRAP,
OWRAP and variable electrical EQ/emphasis settings
• Real time monitoring of:
- Transmitter average optical power
- Received average optical power
- Laser bias current
- Temperature
- Supply Voltage
• SFP+ mechanical specifications per SFF-8432
• SFP+ compliant low speed interface
• Fibre Channel FC-PI-5 compliant high speed interface
- 1600-SN-M6-S, 800-SN-M6-S, 400-SN-M6-I
- 1600-SN-M5-S, 800-SN-M5-S, 400-SN-M5-I
- 1600-SN-M5E-I, 800-SN-M5E-I, 400-SN-M5E-I
- 1600-SN-M5F-I, 800-SN-M5F-I, 400-SN-M5F-I
• Fibre Channel FC-PI-5 compliant optical link distances
Digital diagnostic monitoring information (DMI) is present
in the AFBR-57F5MZ per the requirements of SFF-8472,
providing real time monitoring information of transceiver
laser, receiver and environment conditions over a SFF-
8431 2-wire serial interface.
Related Products
• AFBR-57D7APZ: 850 nm SFP for 8G/4G/2G Fibre Channel
• AFCT-57D5ATPZ: 1310 nm SFP for 8G/4G/2G Fibre Channel
• AFCT-57D5ANPZ: 1310 nm SFP for 8G/4G/2G Fibre Channel
• AFBR-57R5APZ: 850 nm SFP for 4G/2G/1G Fibre Channel
• AFCT-57R5APZ: 1310 nm SFP for 4G/2G/1G Fibre Channel
• AFCT-57R5ATPZ: 1310 nm SFP for 4G/2G/1G Fibre Channel
• AFCT-57R5ANPZ: 1310 nm SFP for 4G/2G/1G Fibre Channel
Applications
• Fibre Channel switches (director, stand alone, blade)
• Fibre Channel Host Bus Adapters
• Fibre Channel RAID controllers
• Fibre Channel tape drive
• Port side connections
• Inter-switch or inter-chassis aggregated links
Patent - www.avagotech.com/patents
Installation
Compliance Prediction
The AFBR-57F5MZ can be installed in any SFF-8074i com-
pliant Small Form Pluggable (SFP) port regardless of host
equipment operating status. The AFBR-57F5MZ is hot-
pluggable, allowing the module to be installed while the
host system is operating and on-line. Upon insertion, the
transceiver housing makes initial contact with the host
board SFP cage, mitigating potential damage due to Elec-
tro-Static Discharge (ESD).
Compliance prediction is the ability to determine if an
optical transceiver is operating within its operating and
environmental requirements. AFBR-57F5MZ devices pro-
vide real-time access to transceiver internal supply volt-
age and temperature, allowing a host to identify potential
component compliance issues. Received optical power is
also available to assess compliance of a cable plant and
remote transmitter. When operating out of requirements,
the link cannot guarantee error free transmission.
Digital Diagnostic Interface and Serial Identification
Fault Isolation
The 2-wire serial interface is based on ATMEL AT24C01A
series EEPROM protocol and signaling detail. Conven-
tional EEPROM memory, bytes 0-255 at memory address
0xA0, is organized in compliance with SFF-8074i. New
digital diagnostic information, bytes 0-255 at memory ad-
dress 0xA2, is compliant to SFF-8472. The new diagnostic
information provides the opportunity for Predictive Fail-
ure Identification, Compliance Prediction, Fault Isolation
and Component Monitoring.
The fault isolation feature allows a host to quickly pin-
point the location of a link failure, minimizing downtime.
For optical links, the ability to identify a fault at a local de-
vice, remote device or cable plant is crucial to speeding
service of an installation. AFBR-57F5MZ real-time moni-
tors of Tx_Bias, Tx_Power, Vcc, Temperature and Rx_Power
can be used to assess local transceiver current operating
conditions. In addition, status flags Tx_Disable and Rx Loss
of Signal (LOS) are mirrored in memory and available via
the two-wire serial interface.
Predictive Failure Identification
The AFBR-57F5MZ predictive failure feature allows a host
to identify potential link problems before system perfor-
mance is impacted. Prior identification of link problems
enables a host to service an application via “fail over” to
a redundant link or replace a suspect device, maintaining
system uptime in the process. For applications where ul-
tra-high system uptime is required, a digital SFP provides
a means to monitor two real-time laser metrics associated
with observing laser degradation and predicting failure:
average laser bias current (Tx_Bias) and average laser op-
tical power (Tx_Power).
Component Monitoring
Component evaluation is a more casual use of the AFBR-
57F5MZ real-time monitors of Tx_Bias, Tx_Power, Vcc,
Temperature and Rx_Power. Potential uses are as debug-
ging aids for system installation and design, and transceiv-
er parametric evaluation for factory or field qualification.
For example, temperature per module can be observed in
high density applications to facilitate thermal evaluation
of blades, PCI cards and systems.
2
OPTICAL INTERFACE
LIGHT FROM FIBER
ELECTRICAL INTERFACE
RD+ (RECEIVE DATA)
RECEIVER
RD- (RECEIVE DATA)
Rx LOSS OF SIGNAL
Rx RATE SELECT RS(0)
Rx Vout &
Emphasis
Rx
CDR
AMPLIFICATION
& QUANTIZATION
PHOTO-DETECTOR
MOD-DEF2 (SDA)
µController
MOD-DEF1 (SCL)
MOD-DEF0
TRANSMITTER
TX_DISABLE
TD+ (TRANSMIT DATA)
LASER
DRIVER &
SAFETY
Tx
CDR
Tx
TD- (TRANSMIT DATA)
TX_FAULT
LIGHT TO FIBER
VCSEL
Equalization
CIRCUITRY
Tx RATE SELECT RS(1)
Figure 1. Transceiver functional diagram.
Transmitter Section
The transmitter section includes a Transmitter Optical
SubAssembly (TOSA), laser driver circuit, Clock and Data
Recovery circuit (CDR) and an electrical input stage with
variable equalization controls and electrical eye mea-
surement capability. The TOSA contains a 850 nm Vertical
Cavity Surface Emitting Laser (VCSEL) light source with
integral light monitoring function and imaging optics to
assure efficient optical coupling to the LC connector in-
terface. The TOSA is driven by a laser driver IC, which uses
the differential output from an integral Tx CDR stage to
modulate and regulate VCSEL optical power. As mandated
by FC-PI-5, the integral CDR cleans up any incoming jit-
ter accumulated from the host ASIC, PCB traces and SFP
electrical connector. Between the SFP electrical connector
tween successive assertions of this control signal. Tx_Dis-
able can also be asserted via the two-wire serial interface
(address A2h, byte 110, bit 6) and monitored (address
A2h, byte 110, bit 7).
The contents of A2h, byte 110, bit 6 are logic OR’d with
hardware Tx_Disable (pin 3) to control transmitter opera-
tion.
Transmit Fault (Tx_Fault)
A catastrophic laser fault will activate the transmitter sig-
nal, TX_FAULT, and disable the laser. This signal is an open
collector output (pull-up required on the host board). A
low signal indicates normal laser operation and a high
signal indicates a fault. The TX_FAULT will be latched high
when a laser fault occurs and is cleared by toggling the
TX_DISABLE input or power cycling the transceiver. The
transmitter fault condition can also be monitored via the
two-wire serial interface (address A2, byte 110, bit 2).
2
and Tx CDR is a variable, I C-bus controlled, equalization
circuit to optimize SFP performance with non-ideal in-
coming electrical waveforms. Note the Tx CDR is engaged
only with Tx_RATE=high (16GFC) and bypassed with Tx_
RATE=low (8G/4G).
Eye Safety Circuit
Transmit Disable (Tx_Disable)
The AFBR-57F5MZ provides Class 1 (single fault tolerant)
eye safety by design and has been tested for compliance
with the requirements listed in Table 1. The eye safety
circuit continuously monitors the optical output power
level and will disable the transmitter upon detecting an
unsafe condition beyond the scope of Class 1 certification.
Such unsafe conditions can be due to inputs from the host
board (Vcc fluctuation, unbalanced code) or a fault within
the transceiver.
The AFBR-57F5MZ accepts a TTL and CMOS compatible
transmit disable control signal input (pin 3) which shuts
down the transmitter optical output. A high signal im-
plements this function while a low signal allows normal
transceiver operation. In the event of a fault (e.g. eye safe-
ty circuit activated), cycling this control signal resets the
module as depicted in Figure 4. An internal pull up resistor
disables the transceiver transmitter until the host pulls the
input low. Host systems should allow a 10 ms interval be-
3
Receiver Section
Application Support
The receiver section includes a Receiver Optical SubAs-
sembly (ROSA), pre-amplification and post-amplification
circuit, Clock and Data Recovery Circuit and an electrical
output stage with variable emphasis controls. The ROSA,
containing a high speed PIN detector, pre-amplifier and
imaging optics efficiently couple light from the LC con-
nector interface and perform an optical to electrical con-
version. The resulting differential electrical signal passes
through a post amplification circuit and into a Clock and
Data Recovery circuit (CDR) for cleaning up accumulated
jitter. The resulting signal is passed to a high speed output
An Evaluation Kit and Reference Designs are available to
assist in evaluation of the AFBR-57F5MZ. Please contact
your local Field Sales representative for availability and
ordering details.
Caution
There are no user serviceable parts nor maintenance re-
quirements for the AFBR-57F5MZ. All mechanical adjust-
ments are made at the factory prior to shipment. Tamper-
ing with, modifying, misusing or improperly handling the
AFBR-57F5MZ will void the product warranty. It may also
result in improper operation and possibly overstress the
laser source. Performance degradation or device failure
may result. Connection of the AFBR-57F5MZ to a light
source not compliant with ANSI FC-PI specifications, oper-
ating above maximum operating conditions or in a man-
ner inconsistent with it’s design and function may result in
exposure to hazardous light radiation and may constitute
an act of modifying or manufacturing a laser product. Per-
sons performing such an act are required by law to re-cer-
tify and re-identify the laser product under the provisions
of U.S. 21 CFR (Subchapter J) and TUV.
2
line driver stage with variable, I C-bus controlled, empha-
sis settings allowing the host to optimize signal character-
istics between the SFP and host ASIC. Note the Rx CDR is
engaged only with Rx_RATE=high (16GFC) and bypassed
with Rx_RATE=low (8G/4G).
Receiver Loss of Signal (Rx_LOS)
The post-amplification IC also includes transition detec-
tion circuitry which monitors the ac level of incoming op-
tical signals and provides a TTL/CMOS compatible status
signal to the host (pin 8). An adequate optical input results
in a low Rx_LOS output while a high Rx_LOS output in-
dicates an unusable optical input. The Rx_LOS thresholds
are factory set so that a high output indicates a definite
optical fault has occurred. Rx_LOS can also be monitored
via the two-wire serial interface (address A2h, byte 110,
bit 1).
Ordering Information
Please contact your local field sales engineer or one of
Avago Technologies franchised distributors for ordering
information. For technical information, please visit Avago
Technologies’ WEB page at www.avagotech.com or contact
Avago Technologies Semiconductor Products Customer
Response Center at 1-800-235-0312. For information re-
lated to SFF Committee documentation visit www.sffcom-
mittee.org.
Functional Data I/O
The AFBR-57F5MZ interfaces with the host circuit board
through twenty I/O pins (SFP electrical connector) identi-
fied by function in Table 2. The board layout for this inter-
face is depicted in Figure 6.
Regulatory Compliance
The AFBR-57F5MZ complies with all applicable laws and
regulations as detailed in Table 1. Certification level is de-
pendent on the overall configuration of the host equip-
ment. The transceiver performance is offered as a figure of
merit to assist the designer.
The AFBR-57F5MZ high speed transmit and receive inter-
faces require SFP MSA compliant signal lines on the host
board. To simplify board requirements, biasing resistors
and ac coupling capacitors are incorporated into the SFP
transceiver module (per SFF-8074i) and hence are not re-
quired on the host board. The Tx_Disable, Tx_Fault, and
Rx_LOS lines require TTL lines on the host board (per SFF-
8074i) if used. If an application chooses not to take advan-
tage of the functionality of these pins, care must be taken
to ground Tx_Disable (for normal operation).
Figure 2 depicts the recommended interface circuit to link
the AFBR-57F5MZ to supporting physical layer ICs. Tim-
ing for MSA compliant control signals implemented in the
transceiver are listed in Figure 4.
4
Electrostatic Discharge (ESD)
Electromagnetic Interference (EMI)
The AFBR-57F5MZ is compatible with ESD levels found in
typical manufacturing and operating environments as de-
scribed in Table 1. In the normal handling and operation
of optical transceivers, ESD is of concern in two circum-
stances.
Equipment incorporating gigabit transceivers is typically
subject to regulation by the FCC in the United States,
CENELEC EN55022 (CISPR 22) in Europe and VCCI in Japan.
The AFBR-57F5MZ’s compliance to these standards is de-
tailed in Table 1. The metal housing and shielded design
of the AFBR-57F5MZ minimizes the EMI challenge facing
the equipment designer.
The first case is during handling of the transceiver prior to
insertion into an SFP compliant cage. To protect the de-
vice, it’s important to use normal ESD handling pre-cau-
tions. These include use of grounded wrist straps, work-
benches and floor wherever a transceiver is handled.
EMI Immunity (Susceptibility)
Due to its shielded design, the EMI immunity of the AFBR-
57F5MZ exceeds typical industry standards.
The second case to consider is static discharges to the
exterior of the host equipment chassis after installation.
If the optical interface is exposed to the exterior of host
equipment cabinet, the transceiver may be subject to sys-
tem level ESD requirements.
Flammability
The AFBR-57F5MZ optical transceiver is made of metal
and high strength, heat resistant, chemical resistant and
UL 94V-0 flame retardant plastic.
Table 1. Regulatory Compliance
Feature
Test Method
Performance
Electrostatic Discharge (ESD)
to the Electrical Pins
MIL-STD-883C
Method 3015.4
Class 1 (> 2000 Volts)
Electrostatic Discharge (ESD)
to the Duplex LC Receptacle
Variation of IEC 61000-4-2
Typically, no damage occurs with 25 kV when
the duplex LC connector receptacle is
contacted by a Human Body Model probe.
GR1089
10 contacts of 8 kV on the electrical faceplate
with device inserted into a panel.
Electrostatic Discharge (ESD)
to the Optical Connector
Variation of IEC 801-2
FCC Class B
CENELEC EN55022 Class B
(CISPR 22A)
Air discharge of 15kV (min.) contact to
connector without damage.
Electromagnetic Interference
(EMI)
System margins are dependent on customer
board and chassis design.
VCCI Class 1
Immunity
Variation of IEC 61000-4-3
Typically shows no measurable effect from a
10 V/m field swept from 10 MHz to 1 GHz.
Laser Eye Safety and
Equipment Type Testing
US FDA CDRH AEL Class 1
US21 CFR, Subchapter J per
Paragraphs 1002.10
and 1002.12
CDRH certification 9720151-111
TUV file 72102056
BAUART
GEPRUFT
¬
(IEC) EN60825-1: 1994 + A11 + A2
(IEC) EN60825-2: 1994 + A1
(IEC) EN60950: 1992 + A1 + A2 +
A3 + A4 + A11
¬
TUV
TYPE
APPROVED
Rheinland
Product Safety
Component Recognition
Underwriters Laboratories and
Canadian Standards Association
Joint Component Recognition
for Information Technology
Equipment including Electrical
Business Equipment
UL file 8543036783
RoHS Compliance
Less than 1000 ppm of cadmium, lead, mercury,
hexavalent chromium, polybrominated biphenyls,
and polybrominated biphenyl ethers.
5
Special Operation Functions:
Pre
Amp
Pre
Amp
Post
Amp
Rx Vout &
Emphasis
Post
Amp
Rx Vout &
Emphasis
Rx
CDR
Rx
CDR
µcontroller
µcontroller
Laser
Driver
Tx EQ
Laser
Driver
Tx EQ
Tx
CDR
Tx
CDR
2
2
Figure 2a. OWRAP Functionality (I C-bus controlled)
Figure 2b. EWRAP Functionality (I C-bus controlled)
Electrical and optical high speed data “wrap” functions are enabled to assist with local host or remote diagnostic and
optimization sequences. Optical data wrap (OWRAP) takes a received optical signal through a CDR jitter cleanup and
retransmits it optically out. Electrical data wrap (EWRAP) takes an incoming electrical signal through a CDR jitter cleanup
and retransmits it electrically out. An optional pass-through function is available to transmit outbound the wrapped
2
information, controlled through I C-bus commands.
Pre
Amp
Pre
Amp
Post
Amp
Rx Vout &
Emphasis
Post
Amp
Rx Vout &
Emphasis
Rx
CDR
Rx
CDR
µcontroller
µcontroller
i2c setting
i2c setting
Laser
Driver
Tx EQ
Laser
Driver
Tx EQ
Tx
CDR
Tx
CDR
2
2
Figure 2c. SFP Tx Variable Input Electrical EQ (I C-bus controlled)
Figure 2d. SFP Rx Variable Output Electrical Emphasis (I C-bus controlled)
The electrical SFP input stage (TD +/-) has been enhanced with features to allow host control and optimization of the
transceiver’s input equalization settings. The host can then select, in situ, the most appropriate SFP setting for a given
interconnect scenario.
The SFP electrical output stage (RD+/-) has been enhanced with variable output emphasis features to allow host control
and optimization of the receiver’s output settings. The host can then select, in situ, the most appropriate SFP setting for
a given interconnect scenario. To assist with optimizing the receiver output setting, the user can have data transmitted
by the SFP to a host ASIC by using EWRAP to loop back host generated traffic or can use a remotely generated optical
signal as a data source for SFP and interconnect training.
Table 2. Rate Select Function
Function
State
Explanation
Rx Rate Select
RS(0)
High
Receive Rate Select HIGH engages the internal Rx CDR. The CDR will look for valid 16GFC traffic and
lock within 500us when found. Due to differences in coding, this CDR will not be able to lock on valid
8GFC or 4GFC traffic.
Low
Receive Rate Select LOW bypasses the internal Rx CDR. This is intended for use only with 8GFC and
4GFC traffic. When set low, the SFP behaves like a legacy SFP.
Tx Rate Select
RS(1)
High
Transmit Rate Select HIGH engages the internal Tx CDR. The CDR will look for valid 16GFC traffic and
lock within 500us when found. Due to differences in coding, this CDR will not be able to lock on valid
8GFC or 4GFC traffic.
Low
Transmit Rate Select LOW bypasses the internal Tx CDR. This is intended for use only with 8GFC and
4GFC traffic. When set low, the SFP behaves like a legacy SFP.
Note: During Fibre Channel Link Speed Negotiation sequences, the host will control Tx Rate and Rx Rate inputs separately to accomplish link initial-
ization. Once speed negotiation is complete, it is expected both Tx Rate and Rx Rate will be placed in the same state by the host.
6
V
CC
,T
Tx Rate Select
RS (1)
40 kΩ
10 kΩ
Tx DIS
Tx_DISABLE
Tx_FAULT
Tx FAULT
0.1 µF
0.1 µF
TD+
TD-
100Ω
Tx CDR
LASER DRIVER
4.7 k to 10 kΩ
4.7 µH
0.1 µF
4.7 µH
0.1 µF
V
,T
CC
22 µF
0.1 µF
0.1 µF
3.3 V
V
,R
V
SERDES IC
CC
PROTOCOL IC
V
CC
,R
,R
CC
22 µF
50 Ω
4.7 k to
50 Ω
10 kΩ
0.1 µF
RD+
RD-
100 Ω
0.1 µF
Rx LOS
RS (0)
LOSS OF SIGNAL
Rx Rate Select
Rx CDR
POST AMPLIFIER
40 kΩ
3.3 V
GND,R
4.7 k to 10 kΩ
4.7 k to 10 kΩ
MOD_DEF0
MOD_DEF1 MOD_DEF2
4.7 k to 10 kΩ
MODULE DETECT
SCL
SDA
Figure 3. Typical application configuration
4.7 µH
V
T
CC
0.1 µF
0.1 µF
22 µF
22 µF
0.1 µF
3.3 V
4.7 µH
V
R
CC
0.1 µF
HOST BOARD
SFP MODULE
NOTE: INDUCTORS MUST HAVE LESS THAN 1Ω SERIES RESISTANCE TO LIMIT VOLTAGE DROP TO THE SFP MODULE.
Figure 4. Recommended power supply filter
7
Table 3. Pin Description
Pin
Name
Function/Description
Notes
1
VeeT
Transmitter Ground
2
TX_FAULT
TX_DISABLE
MOD-DEF2
MOD-DEF1
MOD-DEF0
Rx Rate Select RS(0)
RX_LOS
Tx Rate Select RS(1)
VeeR
Transmitter Fault Indication – High indicates a fault condition
Transmitter Disable – Module electrical input disables on high or open
Module Definition 2 – Two wire serial ID interface data line (SDA)
Module Definition 1 – Two wire serial ID interface clock line (SCL)
Module Definition 0 – Grounded in module (module present indicator)
Receiver rate select. Logic High = 14.025 Gb/s, Logic Low = 8.5 Gb/s and 4.25 Gb/s
Loss of Signal – High indicates loss of received optical signal
Note 1
Note 2
Note 3
Note 3
Note 3
Note 8
Note 4
3
4
5
6
7
8
9
Transmitter rate select. Logic High = 14.025 Gb/s, Logic Low = 8.5 Gb/s and 4.25 Gb/s Note 8
10
11
12
13
14
15
16
17
18
19
Receiver Ground
Receiver Ground
VeeR
RD-
Inverse Received Data Out
Received Data Out
Note 5
Note 5
RD+
VeeR
Receiver Ground
VccR
Receiver Power + 3.3 V
Transmitter Power + 3.3 V
Transmitter Ground
Note 6
Note 6
VccT
VeeT
TD+
Transmitter Data In
Note 7
Note 7
TD-
Inverse Transmitter Data In
Transmitter Ground
20
VeeT
Notes:
1. TX_FAULT is an open collector/drain output, which must be pulled up with a 4.7k – 10kΩ resistor on the host board. When high, this output indi-
cates a laser fault of some kind. Low indicates normal operation. In the low state, the output will be pulled to < 0.8V.
2. TX_DISABLE is an input that is used to shut down the transmitter optical output. It is internally pulled up (within the transceiver) with a 6.8kΩ
resistor.
Low (0 – 0.8V):
Between (0.8V and 2.0V):
Transmitter on
Undefined
High (2.0 – Vcc max) or OPEN: Transmitter Disabled
3. The signals Mod-Def 0, 1, 2 designate the two wire serial interface pins. They must be pulled up with a 4.7k – 10kΩ resistor on the host board.
Mod-Def 0 is grounded by the module to indicate the module is present
Mod-Def 1 is serial clock line (SCL) of two wire serial interface
Mod-Def 2 is serial data line (SDA) of two wire serial interface
4. RX_LOS (Rx Loss of Signal) is an open collector/drain output that must be pulled up with a 4.7k – 10kΩ resistor on the host board. When high, this
output indicates the received optical power is below the worst case receiver sensitivity (as defined by the standard in use). Low indicates normal
operation. In the low state, the output will be pulled to < 0.8V.
5. RD-/+ designate the differential receiver outputs. They are AC coupled 100Ω differential lines which should be terminated with 100Ω differential
at the host SERDES input. AC coupling is done inside the transceiver and is not required on the host board. The voltage swing on these lines will
be between 370 and 850 mV differential (185 – 425 mV single ended) when properly terminated.
6. VccR and VccT are the receiver and transmitter power supplies. They are defined at the SFP connector pin. The maximum supply current is 300 mA
and the associated in-rush current will typically be no more than 30 mA above steady state after 2 microseconds.
7. TD-/+ designate the differential transmitter inputs. They are AC coupled differential lines with 100 Ω differential termination inside the module.
The AC coupling is done inside the module and is not required on the host board. The inputs will accept differential swings of 180 – 1200 mV (90
– 600mV single ended)
8. Rate_Select is an input that is used to control transmit and receive high speed parametric optimizaton. It is internally pulled down (within the
transceiver) with a 40kOhm resistor.
Low (0 - 0.8V) or Open:
Between (0.8V and 2.0V)
High (2.0 - Vcc max):
Rate is set to 8.5Gb/s and below optimization. The CDR is bypassed.
Undefined
Rate is set to 14.025Gb/s optimization. The CDR is engaged.
8
Table 4. Absolute Maximum Ratings
Parameter
Symbol
TS
Minimum
-40
Maximum
85
Unit
C
Notes
Storage Temperature
Case Operating Temperature
Relative Humidity
Note 1, 2
Note 1, 2
Note 1
TC
-40
85
C
RH
5
95
%
V
Supply Voltage
VccT, R
VIN
-0.5
-0.5
3.8
Note 1, 2, 3
Note 1
Low Speed Input Voltage
Vcc+0.5
V
Notes;
1. Absolute Maximum Ratings are those values beyond which damage to the device may occur if these limits are exceeded for other than a short
period of time. See Reliability Data Sheet for specific reliability performance.
2. Between Absolute Maximum Ratings and the Recommended Operating Conditions functional performance is not intended, device reliability is
not implied, and damage to the device may occur over an extended period of time.
3. The module supply voltages, V T and V R must not differ by more than 0.5 V or damage to the device may occur.
CC
CC
Table 5. Recommended Operating Conditions
Parameter
Symbol
Minimum
0
Maximum
70
Unit
°C
Notes
Case Operating Temperature
Supply Voltage
TC
Note 1, 2
Note 2
Note 2
VccT, R
3.135
4.25
3.465
14.025
V
Data Rate
Gb/s
Notes:
1. The Ambient Operating Temperature limitations are based on the Case Operating Temperature limitations and are subject to the host system
thermal design.
2. Recommended Operating Conditions are those values for which functional performance and device reliability is implied.
Table 6. Transceiver Electrical Characteristics
(T = 0 °C to 70 °C, V T, V R = 3.3V 5%)
C
cc
cc
Parameter
Symbol
Minimum
Typical
Maximum
Unit Notes
AC Electrical Characteristics
Power Supply Noise Rejection (peak-peak)
DC Electrical Characteristics
Module Supply Current
PSNR
100
mV
Note 1
ICC
300
mA
V
Low Speed Outputs:
VOH
VOL
2.0
VccT,R+0.3
0.8
Note 2
Note 3
Transmit Fault (TX_FAULT), Loss of Signal
(RX_LOS), MOD-DEF 2
V
Low Speed Inputs:
VIH
VIL
2.0
0
Vcc
0.8
V
V
Transmit Disable (TX_DIS), MOD-DEF 1,
MOD-DEF2, RS(0), RS(1)
Notes:
1. Filter per SFP specification is required on host board to remove 10 Hz to 2 MHz content.
2. Pulled up externally with a 4.7k – 10kΩ resistor on the host board to 3.3 V.
3. Mod-Def1 and Mod-Def2 must be pulled up externally with a 4.7k – 10kΩ resistor on the host board to 3.3V.
9
Table 7. Transmitter and Receiver Electrical Characteristics
(T = 0 °C to 70 °C, V T, V R = 3.3V 5%)
C
cc
cc
Parameter
Symbol
Min
Typ
Max
Unit
Notes
High Speed Data Input
VI
180
1200
mV
Note 1
Transmitter Differential Input Voltage (TD+/-)
High Speed Data Output
Vo
370
850
mV
Note 2
Receiver Differential Output Voltage (RD+/-)
Receiver Total Jitter (14.025 Gb/s)
TJ
0.36
0.71
0.26
0.22
0.42
0.10
UI
UI
UI
UI
UI
UI
Note 3, Rx_Rate = high
Note 4, Rx_Rate = low
Note 4, Rx_Rate = low
Note 3, Rx_Rate = high
Note 4, Rx_Rate = low
Note 4, Rx_Rate = low
Receiver Total Jitter (8.5 Gb/s)
TJ
Receiver Contributed Total Jitter (4.25 Gb/s)
Receiver Deterministic Jitter (14.025 Gb/s)
Receiver Deterministic Jitter (8.5 Gb/s)
TJ
DJ
DJ
DJ
Receiver Contributed Deterministic Jitter
(4.25 Gb/s)
Receiver Data Dependent Pulse Width Shrinkage
(14.025 Gb/s)
DDPWS
DDPWS
0.14
0.36
UI
UI
Note 3, Rx_Rate = high
Note 4, Rx_Rate = low
Receiver Data Dependent Pulse Width Shrinkage
(8.5 Gb/s)
Notes:
1. Internally ac coupled and terminated (100Ω differential).
2. Internally ac coupled but requires an external load termination (100Ω differential).
3. CDR is engaged with Rx_Rate = high. Received output jitter for 14.025 Gb/s.
4. CDR is not engaged with Rx_Rate = low (ie. Bypassed). Receiver output jitter for 8.5 Gb/s and 4.25Gb/s.
Table 8. Transmitter Optical Characteristics
(T = 0 °C to 70 °C, V T, V R = 3.3V 5%)
C
cc
cc
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Modulated Optical Output Power (OMA)
(Peak to Peak) 14.025Gb/s
Tx,OMA
331
µW
µW
µW
Modulated Optical Output Power (OMA)
(Peak to Peak) 8.5Gb/s
Tx,OMA
Tx,OMA
302
247
Modulated Optical Output Power (OMA)
(Peak to Peak) 4.25Gb/s
Average Optical Output Power
Center Wavelength
Pout
lc
-7.8
840
dBm
nm
nm
ps
Note 1
860
Spectral Width – rms
qrms
tr, tf
RIN
0.59
Optical Rise Time (20%-80%)
RIN12 (OMA)
30
-128
2.56
4.3
dB/Hz
dB
Vertical Eye Closure Penalty, 14.025Gb/s
VECP
Note 2
Note 3
Note 2
Note 3
Note 3
Transmitter Waveform Distortion Penalty, 8.5Gb/s TWDP
dB
Transmitter Uncorrelated Jitter, 14.025Gb/s
Transmitter Uncorrelated Jitter, 8.5Gb/s
Transmitter Contributed Jitter, 4.25Gb/s
Pout Tx_DISABLE Asserted
UJ
UJ
TJ
0.03
0.03
0.25
-35
UI
UI
UI
Poff
dBm
Notes:
1. Max P is the lesser of Class 1 safety limits (CDRH and EN 60825) or received power, max.
out
2. CDR is engaged with Tx_Rate = high. Transmitter output jitter for 14.025 Gb/s.
3. CDR is not engaged with Tx_Rate = low (ie. Bypassed). Transmitter output jitter for 8.5 Gb/s and 4.25 Gb/s.
10
Table 9. Receiver Optical and Electrical Characteristics
(T = 0 °C to 70 °C, V T, V R = 3.3V 5%)
C
cc
cc
Parameter
Symbol Min
Typ
Max
Unit
Notes
Optical Input Power
PIN
0
dBm,avg
µW,OMA
Input Optical Modulation Amplitude,
14.025Gb/s
OMA
89
Note 1
(Peak to Peak) [Unstressed Sensitivity]
Input Optical Modulation Amplitude, 8.5Gb/s
(Peak to Peak) [Unstressed Sensitivity]
OMA
76
61
Note 1
Note 1
µW,OMA
µW,OMA
Input Optical Modulation Amplitude, 4.25Gb/s OMA
(Peak to Peak) [Unstressed Sensitivity]
Stressed Receiver Sensitivity (OMA) 14.025Gb/s
Stressed Receiver Sensitivity (OMA) 8.5Gb/s
Stressed Receiver Sensitivity (OMA) 4.25Gb/s
170
151
Note 2, all fiber types
Note 3, all fiber types
µW,OMA
µW,OMA
µW,OMA
148
138
126
OM1 62.5µm fiber
OM2 50µm fiber, Note 4
OM3 50µm fiber
Return Loss
12
dB
Loss of Signal – Assert
Loss of Signal – De-asserted
Loss of Signal – Hysteresis
Notes:
Pa
-30
dBm,avg
dBm,avg
dB
PD
-14
PA – PD 0.5
1. Input Optical Modulation Amplitude (commonly known as sensitivity] requires a valid Fibre Channel encoded input.
2. 14.025 Gb/s stressed received vertical eye closure penalty (ISI) min is 2.5 dB for all fiber types.
3. 8.5 Gb/s stressed received vertical eye closure penalty (ISI) min is 3.1 dB for all fiber types.
4. 4.25 Gb/s stressed received vertical eye closure penalty (ISI) min is 0.75 dB for OM3 fiber, 1.67 dB for OM2 fiber and 2.14 dB for OM1 fiber..
11
Table 10. Transceiver SOFT DIAGNOSTIC Timing Characteristics
(T = 0 °C to 70 °C, V T, V R = 3.3V 5%)
C
cc
cc
Parameter
Symbol
Minimum
Maximum
Unit
µs
Notes
Hardware TX_DISABLE Assert Time
Hardware TX_DISABLE Negate Time
Time to initialize, including reset of TX_FAULT
Hardware TX_FAULT Assert Time
Hardware TX_DISABLE to Reset
Hardware RX_LOS Deassert Time
Hardware RX_LOS Assert Time
Hardware RATE_SELECT Assert Time
Hardware RATE_SELECT Deassert Time
Software TX_DISABLE Assert Time
Software TX_DISABLE Negate Time
Software Tx_FAULT Assert Time
Software Rx_LOS Assert Time
Software Rx_LOS Deassert Time
Software Rate_Select Assert Time
Software Rate_Select Deassert Time
Analog parameter data ready
Serial bus hardware ready
t_off
10
Note 1
Note 2
Note 3
Note 4
Note 5
Note 6
Note 7
Note 17
Note 17
Note 8
Note 9
Note 10
Note 11
Note 12
Note 18
Note 19
Note 13
Note 14
Note 16
Note 15
t_on
1
ms
ms
µs
t_init
300
100
t_fault
t_reset
10
µs
t_loss_on
t_loss_off
t_rate_high
t_rate_low
t_off_soft
t_on_soft
t_fault_soft
t_loss_on_soft
t_loss_off_soft
t_rate_on_soft
t_rate_off_soft
t_data
100
100
1
µs
µs
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
µs
1
100
100
100
100
100
100
100
1000
300
t_serial
Serial bus buffer time
t_buf
20
Write Cycle Time
t_write
40
ms
kHz
Serial ID Clock Rate
f_serial_clock
400
Notes:
1. Time from rising edge of TX_DISABLE to when the optical output falls below 10% of nominal.
2. Time from falling edge of TX_DISABLE to when the modulated optical output rises above 90% of nominal.
3. Time from power on or falling edge of Tx_Disable to when the modulated optical output rises above 90% of nominal.
4. From power on or negation of TX_FAULT using TX_DISABLE.
5. Time TX_DISABLE must be held high to reset the laser fault shutdown circuitry.
6. Time from loss of optical signal to Rx_LOS Assertion.
7. Time from valid optical signal to Rx_LOS De-Assertion.
8. Time from two-wire interface assertion of TX_DISABLE (A2h, byte 110, bit 6) to when the optical output falls below 10% of nominal. Measured
from falling clock edge after stop bit of write transaction.
9. Time from two-wire interface de-assertion of TX_DISABLE (A2h, byte 110, bit 6) to when the modulated optical output rises above 90% of nomi-
nal.
10. Time from fault to two-wire interface TX_FAULT (A2h, byte 110, bit 2) asserted.
11. Time for two-wire interface assertion of Rx_LOS (A2h, byte 110, bit 1) from loss of optical signal.
12. Time for two-wire interface de-assertion of Rx_LOS (A2h, byte 110, bit 1) from presence of valid optical signal.
13. From power on to data ready bit asserted (A2h, byte 110, bit 0). Data ready indicates analog monitoring circuitry is functional.
14. Time from power on until module is ready for data transmission over the serial bus (reads or writes over A0h and A2h).
15. Time from stop bit to completion of a 1 – 4 byte write command. Write cycle time is 80 ms max. for a 5 – 8 byte write.
16. Time between STOP and START commands.
17. Time from rising or falling edge of Rate_Select input until transceiver is successfully passing traffic as designated by RS(0) and RS(1). For Rate_
Select going high, the internal CDR will lock on valid 64b/66b encoded 14.025 Gb/s data within the specified time. For Rate_Select going low,
the internal CDR will be bypassed within the specified time for transmission of valid 8b/10b encoded 8.5 Gb/s or 4.25 Gb/s data.
18. Time from two-wire interface Assertion of Rate_Select (either RS(0) in A2h, byte 110, bit 3 or RS(1) in A2h, byte 118, bit 3) to when the respective
CDR is engaged at 14.025 Gb/s data rate.
19. Time from two-wire interface Deassertion of Rate_Select (either RS(0) in A2h, byte 110, bit 3 or RS(1) in A2h, byte 118, bit 3) to when the respec-
tive CDR is bypassed for low speed 8.5 Gb/s or 4.25 Gb/s operation.
12
Table 11. Transceiver Digital Diagnostic Monitor (Real Time Sense) Characteristics
(T = 0 °C to 70 °C, V T, V R = 3.3V 5%)
C
cc
cc
Parameter
Symbol
Min.
Units Notes
Transceiver Internal Temperature
Accuracy
TINT
3.0
°C
Temperature is measured internal to the transceiver.
Valid from = 0 °C to 70 °C case temperature.
Transceiver Internal Supply
Voltage Accuracy
VINT
0.1
V
Supply voltage is measured internal to the transceiver
and can, with less accuracy, be correlated to
voltage at the SFP Vcc pin. Valid over 3.3 V 10%.
Transmitter Laser DC Bias Current
Accuracy
IINT
PT
10
%
IINT is better than 10% of the nominal value.
Transmitted Average Optical
Output Power Accuracy
3.0
3.0
dB
dB
Coupled into 50/125 µm multi-mode fiber. Valid from
100 µW to 500 µW, avg.
Received Average Optical Input
Power Accuracy
PR
Coupled from 50/125 µm multi-mode fiber. Valid from
31 µW to 500 µW, avg.
V
T,R > 2.97 V
V
T,R > 2.97 V
CC
CC
TX_FAULT
TX_FAULT
TX_DISABLE
TX_DISABLE
TRANSMITTED SIGNAL
TRANSMITTED SIGNAL
t_init
t_init
t-init: TX DISABLE NEGATED
t-init: TX DISABLE ASSERTED
V
T,R > 2.97 V
TX_FAULT
TX_DISABLE
CC
TX_FAULT
TX_DISABLE
TRANSMITTED SIGNAL
TRANSMITTED SIGNAL
t_off
t_on
t_init
INSERTION
t-init: TX DISABLE NEGATED, MODULE HOT PLUGGED
t-off & t-on: TX DISABLE ASSERTED THEN NEGATED
OCCURANCE OF FAULT
OCCURANCE OF FAULT
TX_FAULT
TX_FAULT
TX_DISABLE
TX_DISABLE
TRANSMITTED SIGNAL
TRANSMITTED SIGNAL
t_fault
t_reset
* SFP SHALL CLEAR TX_FAULT IN
t_init*
< t_init IF THE FAILURE IS TRANSIENT
t-fault: TX FAULT ASSERTED, TX SIGNAL NOT RECOVERED
OCCURANCE OF FAULT
t-reset: TX DISABLE ASSERTED THEN NEGATED, TX SIGNAL RECOVERED
TX_FAULT
OCCURANCE
OF LOSS
OPTICAL SIGNAL
LOS
TX_DISABLE
TRANSMITTED SIGNAL
t_fault
t_loss_on
t_loss_off
t_reset
* SFP SHALL CLEAR TX_FAULT IN
< t_init IF THE FAILURE IS TRANSIENT
t_init*
t-fault: TX DISABLE ASSERTED THEN NEGATED, TX SIGNAL NOT RECOVERED
t-loss-on & t-loss-off
Figure 5. Transceiver timing diagrams (module installed except where noted)
13
Table 12. EEPROM Serial ID Memory Contents – Address A0h
Byte #
Byte #
Decimal Hex Description
Decimal Hex Description
0
1
2
3
4
5
6
7
03
04
07
00
00
00
00
60
40
0C
70
06
8C
SFP physical device
SFP function defined by serial ID only
LC optical connector
37
38
39
40
41
42
43
00
17
6A
41
46
42
52
2D
35
37
46
35
4D
5A
20
20
20
20
20
20
20
20
20
03
52
00
Hex Byte of Vendor OUI [4]
Hex Byte of Vendor OUI [4]
Hex Byte of Vendor OUI [4]
“A” - Vendor Name ASCII Character
“F” - Vendor Name ASCII Character
“B” - Vendor Name ASCII Character
“R” - Vendor Name ASCII Character
“-” - Vendor Name ASCII Character
“5” - Vendor Name ASCII Character
“7” - Vendor Name ASCII Character
“F” - Vendor Name ASCII Character
“5” - Vendor Name ASCII Character
“M” - Vendor Name ASCII Character
“Z” - Vendor Name ASCII Character
“ ” - Vendor Name ASCII Character
“ ” - Vendor Name ASCII Character
“ ” - Vendor Name ASCII Character
“ ” - Vendor Name ASCII Character
“ ” - Vendor Name ASCII Character
“ ” - Vendor Name ASCII Character
“ ” - Vendor Name ASCII Character
“ ” - Vendor Name ASCII Character
“ ” - Vendor Name ASCII Character
Hex Byte of Laser Wavelength [5]
Hex Byte of Laser Wavelength [5]
Short and Intermediate link distance (per FC-PI-5) 44
Shortwave laser without OFC (open fiber control) 45
8
9
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
Multi-mode 50 µm and 62.5 µm and optical media
400, 800 and 1600 MByte/s FC-PI-5 speed [1]
64B/66B data at 14.025G & 8B/10B at 8.5G/4.25G
14.025 Mbit/s nominal bit rate (14.025 Gb/s)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
0A 16/8/4G Independent Tx and Rx Rate Selects
00
00
04
02
00
35m of OM2 50/125um fiber at 14.025 Gb/s [2]
15m of OM1 62.5/125um fiber at 14.025 Gb/s [3]
0A 100m of OM3 50/125um fiber at 14.025 Gb/s [9]
41
56
41
47
4F
20
20
20
20
“A” - Vendor Name ASCII Character
“V” - Vendor Name ASCII Character
“A” - Vendor Name ASCII Character
“G” - Vendor Name ASCII Character
“O” - Vendor Name ASCII Character
“ ” - Vendor Name ASCII Character
“ ” - Vendor Name ASCII Character
“ ” - Vendor Name ASCII Character
“ ” - Vendor Name ASCII Character
Checksum for Bytes 0-62 [6]
Receiver limiting output. 1W power class
Hardware Tx_Disable, Tx_Fault, Rx_LOS,
Rate_Select
00
3A
29
30
31
32
33
34
20
20
20
20
20
20
“ ” - Vendor Name ASCII Character
“ ” - Vendor Name ASCII Character
“ ” - Vendor Name ASCII Character
“ ” - Vendor Name ASCII Character
“ ” - Vendor Name ASCII Character
“ ” - Vendor Name ASCII Character
66
67
68 - 83
84 - 91
92
00
00
Vendor Serial Number ASCII characters [7]
Vendor Date Code ASCII characters [8]
Digital diagnostics, Internal Cal, Rx Pwr Avg
Alarms/Warnings, Software Tx_Disable,
Tx-Fault, Rx_LOS, Rate_Select
68
FA
93
35
36
20
00
“ ” - Vendor Name ASCII Character
94
95
05
SFF-8472 compliance to revision 11.0
Checksum for Bytes 62-94 [6]
96 – 255 00
Notes:
1. FC-PI-5 speed 1600 MByte/s is a serial bit rate of 14.025 Gb/s. 800 MByte/s is a serial bit rate of 8.5 Gb/s. 400 MByte/s is a serial bit rate of 4.25
Gb/s.
2. Link distance with OM2 50/125 µm cable at 8.5 Gb/s is 50 m. Link distance at 4.25 Gb/s is 150 m.
3. Link distance with OM1 62.5/125 µm cable at 8.5 Gb/s is 25 m. Link distance at 4.25 Gb/s is 70 m.
4. The IEEE Organizationally Unique Identified (OUI) assigned to Avago Technologies is 00-17-64 (3 bytes of Hex).
5. Laser Wavelength is represented in 16 unsigned bits. The Hex representation of 850 nm is 0352.
6. Addresses 63 and 95 are checksums calculated (per SFF-8472 and SFF-8074) and stored before product shipment.
7. Address 68-83 specify the AFBR-57F5MZ ASCII serial number and will vary on a per unit basis.
8. Address 84-91 specify the AFBR-57F5MZ ASCII data code and will vary on a per date code basis.
9. Link distance with OM3 50/125 µm cable at 8.5 Gb/s is 150 m. Link distance at 4.25 Gb/s is 380 m.
14
Table 13. EEPROM Serial ID Memory Contents – Enhanced Feature Set Memory (Address A2h)
Byte #
Decimal Notes
Byte #
Decimal Notes
Byte #
Decimal Notes
0
Temp H Alarm MSB[1]
26
Tx Pwr L Alarm MSB[4]
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
Real Time Rx Pwr MSB[5]
1
Temp H Alarm LSB[1]
Temp L Alarm MSB[1]
Temp L Alarm LSB[1]
Temp H Warning MSB[1]
Temp H Warning LSB[1]
Temp L Warning MSB[1]
Temp L Warning LSB[1]
Vcc H Alarm MSB[2]
27
Tx Pwr L Alarm LSB[4]
Real Time Rx Pwr LSB[5]
Reserved
2
28
Tx Pwr H Warning MSB[4]
Tx Pwr H Warning LSB[4]
Tx Pwr L Warning MSB[4]
Tx Pwr L Warning LSB[4]
Rx Pwr H Alarm MSB[5]
Rx Pwr H Alarm LSB[5]
3
29
Reserved
4
30
Reserved
5
31
Reserved
6
32
Status/Control - See Table 14
Status/Control - See Table 15
Flag Bits - See Table 16
Flag Bits - See Table 16
Reserved
7
33
8
34
Rx Pwr L Alarm MSB[5]
9
Vcc H Alarm LSB[2]
35
Rx Pwr L Alarm LSB[5]
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Notes:
Vcc L Alarm MSB[2]
36
Rx Pwr H Warning MSB[5]
Rx Pwr H Warning LSB[5]
Rx Pwr L Warning MSB[5]
Rx Pwr L Warning LSB[5]
Control Settings - See Table 18
External Calibration Constants[6]
Checksum for Bytes 0-94[7]
Real Time Temperature MSB[1]
Real Time Temperature LSB[1]
Real Time Vcc MSB[2]
Vcc L Alarm LSB[2]
37
Reserved
Vcc H Warning MSB[2]
Vcc H Warning LSB[2]
Vcc L Warning MSB[2]
Vcc L Warning LSB[2]
Tx Bias H Alarm MSB[3]
Tx Bias H Alarm LSB[3]
Tx Bias L Alarm MSB[3]
Tx Bias L Alarm LSB[3]
Tx Bias H Warning MSB[3]
Tx Bias H Warning LSB[3]
Tx Bias L Warning MSB[3]
Tx Bias L Warning LSB[3]
Tx Pwr H Alarm MSB[4]
Tx Pwr H Alarm LSB[4]
38
Flag Bits - See Table 16
Flag Bits - See Table 16
Status/Control - See Table 17
39
40-55
56-94
95
119-127 Reserved
128-247 Customer Writeable
248-255 Vendor Specific
96
97
98
99
Real Time Vcc LS[2]
100
101
102
103
Real Time Tx Bias MSB[3]
Real Time Tx Bias LSB[3]
Real Time Tx Power MSB[4]
Real Time Tx Power LSB[4]
1. Temperature (Temp) is decoded as a 16 bit signed twos compliment integer in increments of 1/256 °C.
2. Supply Voltage (Vcc) is decoded as a 16 bit unsigned integer in increments of 100 µV.
3. Laser bias current (Tx Bias) is decoded as a 16 bit unsigned integer in increments of 2 µA.
4. Transmitted average optical power (Tx Pwr) is decoded as a 16 bit unsigned integer in increments of 0.1 µW.
5. Received average optical power (Rx Pwr) is decoded as a 16 bit unsigned integer in increments of 0.1 µW.
6. Bytes 56-94 are not intended for use with AFBR-57F5MZ, but have been set to default values per SFF-8472.
7. Byte 95 is a checksum calculated (per SFF-8472) and stored before product shipment.
15
Table 14. EEPROM Serial ID Memory Contents – Soft Commands (Address A2h, Byte 110)
Bit #
7
Status/Control Name
TX_DISABLE State
Soft TX_DISABLE Control
RS(1) State
Description
Notes
Digital state of TX_DISABLE Input Pin (1 = TX_DISABLE asserted)
Read/write bit for changing digital state of TX_DISABLE function
Digital state of TX Rate_Select Input Pin RS(1) (1 = Rate High asserted)
Digital state of RX Rate_Select Input Pin RS(0) (1 = Rate High asserted)
Read/write bit for changing digital state of Rx Rate_Select RS(0) function
Digital state of TX_FAULT Output Pin (1 = TX_FAULT asserted)
Digital state of SFP RX_LOS Output Pin (1 = RX_LOS asserted)
Note 1
Note 1, 2
6
5
4
RS(0) State
3
Soft RS(0) Control
TX_FAULT State
RX_LOS State
Note 3
Note 1
Note 1
2
1
0
Data Ready (Bar)
Indicates transceiver is powered and real time sense data is ready
(0 = Data Ready)
Notes:
1. The response time for soft commands of the AFBR-57F5MZ is 100msec as specified by MSA SFF-8472.
2. Bit 6 is logic OR’d with the SFP TX_DISABLE input pin 3 …. either asserted will disable the SFP transmitter.
3. Bit 3 is logic OR’d with the SFP RS(0) RX Rate_Select input pin 7 …. either asserted will set receiver to Rate = High.
Table 15. EEPROM Serial ID Memory Contents – Soft Commands (Address A2h, Byte 111)
Bit #
4-7
3
Status/Control Name
Description
Notes
Reserved
OWRAP FORWARD
Control Bit
Logic Low = FORWARD disabled. Logic High = FORWARD enabled. When
used in combination with OWRAP enable, FORWARD routes incoming SFP
Rx optical data to both the Tx optical output and the Rx electrical output.
Enabling sets bit 2 and clears all other bits in byte 111.
2
1
OWRAP
Control Bit
Logic Low = OWRAP disabled. Logic High = OWRAP enabled. When
enabled, OWRAP routes incoming SFP Rx optical data to the Tx optical
output. Enabling clears all other bits in byte 111.
EWRAP FORWARD
Control Bit
Logic Low = FORWARD disabled. Logic High = FORWARD enabled. When
used in combination with EWRAP enable, FORWARD routes incoming
SFP Tx electrical data to both Rx electrical output and Tx optical output.
Enabling sets bit 0 and clears all other bits in byte 111.
0
EWRAP
Control Bit
Logic Low = EWRAP disabled. Logic High = EWRAP enabled. When en-
abled, EWRAP routes incoming SFP Tx electrical data to the Rx electrical
output. Enabling clears all other bits in byte 111.
16
Table 16. EEPROM Serial ID Memory Contents – Alarms and Warnings (Address A2h, Bytes 112, 113, 116, 117)
Byte
112
Bit
7
Flag Bit Name Description
Temp High Alarm
Temp Low Alarm
Set when transceiver internal temperature exceeds high alarm threshold
Set when transceiver internal temperature exceeds low alarm threshold
Set when transceiver internal supply voltage exceeds high alarm threshold
Set when transceiver internal supply voltage exceeds low alarm threshold
Set when transceiver laser bias current exceeds high alarm threshold
Set when transceiver laser bias current exceeds low alarm threshold
Set when transmitted average optical power exceeds high alarm threshold
Set when transmitted average optical power exceeds low alarm threshold
Set when received average optical power exceeds high alarm threshold
Set when received average optical power exceeds low alarm threshold
6
5
Vcc High Alarm
4
Vcc Low Alarm
3
Tx Bias High Alarm
Tx Bias Low Alarm
Tx Power High Alarm
Tx Power Low Alarm
Rx Power High Alarm
Rx Power Low Alarm
Reserved
2
1
0
113
116
7
6
0-5
7
Temp High Warning
Temp Low Warning
Vcc High Warning
Vcc Low Warning
Set when transceiver internal temperature exceeds high warning threshold
Set when transceiver internal temperature exceeds low warning threshold
Set when transceiver internal supply voltage exceeds high warning threshold
Set when transceiver internal supply voltage exceeds low warning threshold
Set when transceiver laser bias current exceeds high warning threshold
Set when transceiver laser bias current exceeds low warning threshold
Set when transmitted average optical power exceeds high warning threshold
Set when transmitted average optical power exceeds low warning threshold
Set when received average optical power exceeds high warning threshold
Set when received average optical power exceeds low warning threshold
6
5
4
3
Tx Bias High Warning
Tx Bias Low Warning
Tx Power High Warning
Tx Power Low Warning
Rx Power High Warning
Rx Power Low Warning
Reserved
2
1
0
117
7
6
0-5
17
Table 17. EEPROM Serial ID Memory Contents – Soft Commands (Address A2h, Byte 118)
Bit #
4-7
3
Status/Control Name
Reserved
Description
Notes
Soft RS(1) Control
Reserved
Read/write bit for changing digital state of Tx Rate_Select RS(1) function
Note 1
2
1
Power Level State
Always set to zero. Value of zero indicates Power Level 1 operation (1 Watt
max)
0
Power Level Select
Unused. This device supports power level zero (1 Watt max) only.
Notes:
1. Bit 3 is logic OR’d with the SFP RS(1) TX Rate_Select input pin 9 …. either asserted will set transmitter to Rate = High.
Table. 18. Signal Integrity Feature Configuration Bytes (2-Wire Address A2h)
Byte
Name
Description
40
Tx Input EQ Setting for
RS(1) = High
Defines SFP incoming electrical Tx equalization setting for Tx_Rate = High [ie. RS(1)=High]
The SFP transceiver will support two EQ settings based on LSB. With LSB = 0, the Tx input
EQ is set to 0 dB (no EQ). With LSB = 1, the Tx input EQ is set to 6 dB gain at 7 GHz.
Writing FFh to this byte resets to factory settings, EQ = 0 dB.
41
42
Tx Input EQ Setting for
RS(1) = Low
Defines SFP incoming electrical Tx equalization setting for Tx_Rate = Low [ie. RS(1)=Low]
The SFP transceiver will support two EQ settings based on LSB. With LSB = 0, the Tx input
EQ is set to 0 dB (no EQ). With LSB = 1, the Tx input EQ is set to 6 dB gain at 7 GHz.
Writing FFh to this byte resets to factory settings, EQ = 0 dB.
Rx Output Pre Emphasis
Setting for RS(0) = High
Defines SFP output electrical Rx pre-emphasis setting for Rx_Rate = High [ie. RS(0)=High]
The SFP transceiver will support 8 Pre Emphasis amplitude settings in the lower 3 bits of
this byte. Emphasis can be varied from 0 dB to 6 dB in eight non-linear steps. A value of 0
results in 0 dB emphasis.
Writing FFh to this byte resets to factory settings, EMPH = 0 dB.
43
Rx Output Pre Emphasis
Setting for RS(0) = Low
Defines SFP output electrical Rx pre-emphasis setting for Rx_Rate = Low [ie. RS(0)=Low]
The SFP transceiver will support 8 Pre Emphasis amplitude settings in the lower 3 bits of
this byte. Emphasis can be varied from 0 dB to 6 dB in eight non-linear steps. A value of 0
results in 0 dB emphasis.
Writing FFh to this byte resets to factory settings, EMPH = 0 dB.
44-55
Unallocated
Contents 00h.
Note: Checksum at address A2h byte 95 will be updated within 100 ms of a value change in these bytes.
18
47.5
8.9
13.9
0.64 UNCOMPRESSED
8.55
6.25
1.63
13.6
13.44
Figure 6. Module drawing
Figure 7. Module Label
19
X
Y
34.5
10
3x
7.2
7.1
10x ˇ 1.05 ± 0.01
ˇ
∅
0.1 L X A S
2.5
ˇ
0.85 ± 0.05
∅
ˇ 0.1 S X Y
16.25
MIN. PITCH
1
2.5
B
A
1
PCB
EDGE
3.68
5.68
20
PIN 1
8.58
8.48
2x 1.7
11.08
14.25
11.93
16.25
REF.
9.6
4.8
11
10
SEE DETAIL 1
9x 0.95 ± 0.05
2.0
11x
∅
ˇ
0.1 L X A S
11x 2.0
5
26.8
2
10
3x
3
41.3
42.3
5
3.2
20x 0.5 ± 0.03
0.9
0.06
L A S B S
LEGEND
20
PIN 1
10.53
10.93
1. PADS AND VIAS ARE CHASSIS GROUND
2. THROUGH HOLES, PLATING OPTIONAL
11.93
9.6
0.8
TYP.
11
10
3. HATCHED AREA DENOTES COMPONENT
AND TRACE KEEPOUT (EXCEPT
CHASSIS GROUND)
4
4. AREA DENOTES COMPONENT
KEEPOUT (TRACES ALLOWED)
2 ± 0.005 TYP.
0.06 A S B S
2x 1.55 ± 0.05
0.1 L A S B S
L
∅
ˇ
DIMENSIONS ARE IN MILLIMETERS
DETAIL 1
Figure 8. SFP host board mechanical layout
20
1.7 ꢀ.ꢂ
Tcase REFERENCE POINT
3.ꢁ ꢀ.3
41.78 ꢀ.ꢁ
1ꢁ MAX.
ꢂ.8 MAX.
16.2ꢁ ꢀ.1
1ꢀ
1ꢁ.2ꢁ ꢀ.1
Figure 9. SFP Assembly drawing
Customer Manufacturing Processes
This module is pluggable and is not designed for aqueous wash, IR reflow, or wave soldering processes.
21
Appendix I. Rate Select Control
RX and TX rates can be independently controlled by either hardware input pins or via register writes. Module electrical
input pins 7 and 9 are used to select RX and TX rate respectively. Status of each logic level is reflected to register byte
110 bit 4 and 5 on address A2h as shown in the diagram below. RX and TX rates can also be controlled by register writes
to byte 110 bit 3 and 118 bit 3. Power on default of these bits are logic low. Hardware and software control inputs are
OR’d to allow flexible control.
RS0 RX Rate Select control flow
RS1 TX Rate Select control flow
Hardware
Input
Software
Input
Hardware
Input
Software
Input
RS1 (PIN9) Voltage
"1"...V>2.0
"0"...V<0.8
RS0 (PIN7) Voltage
"1"...V>2.0
"0"...V<0.8
A2h, byte 118
Bit 3
A2h, byte 110
Bit 3
A2h, byte 110
Bit 5
A2h, byte 110
Bit 4
OR
OR
RX Rate
Control
TX Rate
Control
RS0 Control Input
RS1 Control Input
Hardware
Software
RX Operation
Hardware
Software
TX Operation
0
0
1
1
0
1
0
1
4/8G FC
16G FC
16G FC
16G FC
RX CDR bypassed
RX CDR enabled
0
0
1
1
0
1
0
1
4/8G FC
16G FC
16G FC
16G FC
TX CDR bypassed
TX CDR enabled
For product information and a complete list of distributors, please go to our website: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2013 Avago Technologies. All rights reserved. Obsoletes AV02-2898EN.
AV02-3165EN - May 16, 2013
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