HCPL-7710-560E [AVAGO]
40 ns Propagation Delay, CMOS Optocoupler; 40 ns的传播延迟， CMOS光电耦合器
| 型号： | HCPL-7710-560E |
| 厂家： | 
AVAGO TECHNOLOGIES LIMITED |
| 描述： | 40 ns Propagation Delay, CMOS Optocoupler |
| 文件： | 总18页 (文件大小：305K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HCPL-7710/0710
40 ns Propagation Delay, CMOS Optocoupler
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
Available in either an 8-pin DIP or SO-8 package style
respectively, the HCPL-7710 or HCPL-0710 optocouplers
utilizethelatestCMOSICtechnologytoachieveoutstand-
ing performance with very low power consumption. The
HCPL-x710requireonlytwobypasscapacitorsforcomplete
CMOS compatibility.
• +5 V CMOS compatibility
• 8 ns maximum pulse width distortion
• 20 ns maximum prop. delay skew
• High speed: 12 Mbd
• 40 ns maximum prop. delay
• 10 kV/µs minimum common mode rejection
• -40°C to 100°C temperature range
• Safety and regulatory approvals
UL Recognized
3750 V rms for 1 min. per UL 1577
5000 V rms for 1 min. per UL 1577 (for HCPL-7710
option 020)
Basic building blocks of the HCPL-x710 are a CMOS LED
driver IC, a high speed LED and a CMOS detector IC. A
CMOS logic input signal controls the LED driver IC which
supplies current to the LED. The detector IC incorporates
an integrated photodiode, a high-speed transimped-
ance amplifier, and a voltage comparator with an output
driver.
CSA Component Acceptance Notice #5
IEC/EN/DIN EN 60747-5-2
Functional Diagram
– VIORM = 630 Vpeak for HCPL-7710 Option 060
– VIORM = 560 Vpeak for HCPL-0710 Option 060
1
2
8
7
**V
V
**
DD2
DD1
Applications
NC*
V
I
• Digital fieldbus isolation: DeviceNet, SDS, Profibus
• AC plasma display panel level shifting
• Multiplexed data transmission
• Computer peripheral interface
• Microprocessor system interface
I
O
3
4
6
5
NC*
V
O
LED1
GND
GND
2
1
SHIELD
* Pin 3 is the anode of the internal LED and must be left
unconnected for guaranteed data sheet performance.
Pin 7 is not connected internally.
** A 0.1 µF bypass capacitor must be connected
between pins 1 and 4, and 5 and 8.
TRUTH TABLE
(POSITIVE LOGIC)
V , INPUT
I
LED1 V , OUTPUT
O
H
L
OFF
ON
H
L
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Selection Guide
8-Pin DIP
(300 Mil)
Small Outline
SO-8
HCPL-7710
HCPL-0710
Ordering Information
HCPL-0710 and HCPL-7710 are UL Recognized with 3750 Vrms for 1 minute per UL1577.
Option
UL 5000
Part
number
RoHS
Non RoHS
Surface
Mount
Gull
Wing
Tape
Vrms/
1
IEC/EN/DIN
Compliant Compliant Package
& Reel Minute rating EN 60747-5-2 Quantity
-000E
-300E
-500E
-020E
-320E
-520E
-060E
-360E
-560E
-000E
-500E
-060E
-560E
No option
#300
50 per tube
50 per tube
X
X
X
X
#500
X
X
1000 per reel
50 per tube
50 per tube
1000 per reel
50 per tube
50 per tube
1000 per reel
100 per tube
1500 per reel
100 per tube
1500 per reel
-020
X
X
X
300mil
DIP-8
HCPL-7710
HCPL-0710
-320
X
X
X
X
-520
#060
X
X
X
#360
X
X
X
X
X
X
X
X
#560
X
X
X
No option
#500
SO-8
#060
X
X
#560
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
HCPL-7710-560E to order product of Gull Wing Surface Mount package in Tape and Reel packaging with IEC/EN/
DIN EN 60747-5-2 Safety Approval in RoHS compliant.
Example 2:
HCPL-0710 to order product of Small Outline SO-8 package in tube packaging and non RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since 15th July 2001 and
RoHS compliant option will use ‘-XXXE‘.
2
Package Outline Drawing
HCPL-7710 8-Pin DIP Package
7.62 ꢀ.25
(ꢀ.3ꢀꢀ ꢀ.ꢀ1ꢀ)
9.65 ꢀ.25
(ꢀ.38ꢀ ꢀ.ꢀ1ꢀ)
8
1
7
6
5
TYPE NUMBER
6.35 ꢀ.25
(ꢀ.25ꢀ ꢀ.ꢀ1ꢀ)
DATE CODE
A XXXX
YYWW
2
3
4
1.78 (ꢀ.ꢀ7ꢀ) MAX.
1.19 (ꢀ.ꢀ47) MAX.
+ ꢀ.ꢀ76
- ꢀ.ꢀ51
ꢀ.254
5° TYP.
+ ꢀ.ꢀꢀ3)
- ꢀ.ꢀꢀ2)
(ꢀ.ꢀ1ꢀ
4.7ꢀ (ꢀ.185) MAX.
ꢀ.51 (ꢀ.ꢀ2ꢀ) MIN.
2.92 (ꢀ.115) MIN.
DIMENSIONS IN MILLIMETERS AND (INCHES).
*MARKING CODE LETTER FOR OPTION NUMBERS
"L" = OPTION ꢀ2ꢀ
1.ꢀ8ꢀ ꢀ.32ꢀ
(ꢀ.ꢀ43 ꢀ.ꢀ13)
ꢀ.65 (ꢀ.ꢀ25) MAX.
"V" = OPTION ꢀ6ꢀ
2.54 ꢀ.25
(ꢀ.1ꢀꢀ ꢀ.ꢀ1ꢀ)
OPTION NUMBERS 3ꢀꢀ AND 5ꢀꢀ NOT MARKED.
Package Outline Drawing
HCPL-7710 Package with Gull Wing Surface Mount Option 300
PAD LOCATION (FOR REFERENCE ONLY)
9.65 ꢀ.25
(ꢀ.38ꢀ ꢀ.ꢀ1ꢀ)
1.ꢀ16 (ꢀ.ꢀ4ꢀ)
1.194 (ꢀ.ꢀ47)
6
5
8
1
7
4.826
(ꢀ.19ꢀ)
TYP.
6.35ꢀ ꢀ.25
(ꢀ.25ꢀ ꢀ.ꢀ1ꢀ)
9.398 (ꢀ.37ꢀ)
9.9ꢀ6 (ꢀ.39ꢀ)
2
3
4
ꢀ.381 (ꢀ.ꢀ15)
ꢀ.635 (ꢀ.ꢀ25)
1.194 (ꢀ.ꢀ47)
1.778 (ꢀ.ꢀ7ꢀ)
9.65 ꢀ.25
1.78ꢀ
(ꢀ.ꢀ7ꢀ)
MAX.
(ꢀ.38ꢀ ꢀ.ꢀ1ꢀ)
1.19
(ꢀ.ꢀ47)
MAX.
7.62 ꢀ.25
(ꢀ.3ꢀꢀ ꢀ.ꢀ1ꢀ)
+ ꢀ.ꢀ76
ꢀ.254
- ꢀ.ꢀ51
4.19
+ ꢀ.ꢀꢀ3)
- ꢀ.ꢀꢀ2)
MAX.
(ꢀ.165)
(ꢀ.ꢀ1ꢀ
1.ꢀ8ꢀ ꢀ.32ꢀ
(ꢀ.ꢀ43 ꢀ.ꢀ13)
ꢀ.635 ꢀ.25
(ꢀ.ꢀ25 ꢀ.ꢀ1ꢀ)
12° NOM.
ꢀ.635 ꢀ.13ꢀ
(ꢀ.ꢀ25 ꢀ.ꢀꢀ5)
2.54
(ꢀ.1ꢀꢀ)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = ꢀ.1ꢀ mm (ꢀ.ꢀꢀ4 INCHES).
Outline (8-pin DIP - Option 300)
3
Package Outline Drawing
HCPL-0710 Outline Drawing (Small Outline SO-8 Package)
LAND PATTERN RECOMMENDATION
8
1
7
2
6
5
4
5.994 ꢀ.2ꢀ3
(ꢀ.236 ꢀ.ꢀꢀ8)
XXXV
YWW
3.937 ꢀ.127
(ꢀ.155 ꢀ.ꢀꢀ5)
TYPE NUMBER
(LAST 3 DIGITS)
7.49 (ꢀ.295)
DATE CODE
3
PIN ONE
1.9 (ꢀ.ꢀ75)
ꢀ.4ꢀ6 ꢀ.ꢀ76
(ꢀ.ꢀ16 ꢀ.ꢀꢀ3)
1.27ꢀ
(ꢀ.ꢀ5ꢀ)
BSC
ꢀ.64 (ꢀ.ꢀ25)
ꢀ.432
(ꢀ.ꢀ17)
*
7°
5.ꢀ8ꢀ ꢀ.127
(ꢀ.2ꢀꢀ ꢀ.ꢀꢀ5)
45° X
3.175 ꢀ.127
(ꢀ.125 ꢀ.ꢀꢀ5)
ꢀ ~ 7°
ꢀ.228 ꢀ.ꢀ25
(ꢀ.ꢀꢀ9 ꢀ.ꢀꢀ1)
1.524
(ꢀ.ꢀ6ꢀ)
ꢀ.2ꢀ3 ꢀ.1ꢀ2
(ꢀ.ꢀꢀ8 ꢀ.ꢀꢀ4)
TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH)
5.2ꢀ7 ꢀ.254 (ꢀ.2ꢀ5 ꢀ.ꢀ1ꢀ)
*
ꢀ.3ꢀ5
(ꢀ.ꢀ12)
MIN.
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = ꢀ.1ꢀ mm (ꢀ.ꢀꢀ4 INCHES) MAX.
OPTION NUMBER 5ꢀꢀ NOT MARKED.
NOTE: FLOATING LEAD PROTRUSION IS ꢀ.15 mm (6 mils) MAX.
Solder Reflow Thermal Profile
300
PREHEATING RATE 3°C + 1°C/- 0.5°C/SEC.
REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC.
PEAK
TEMP.
245°C
PEAK
TEMP.
240°C
PEAK
TEMP.
230°C
200
100
0
2.5°C ± 0.5°C/SEC.
SOLDERING
TIME
200°C
30
160°C
150°C
140°C
SEC.
30
SEC.
3°C + 1°C/- 0.5°C
PREHEATING TIME
150°C, 90 + 30 SEC.
50 SEC.
TIGHT
TYPICAL
LOOSE
ROOM
TEMPERATURE
0
50
100
150
200
250
TIME (SECONDS)
Note: Non-halide flux should be used.
4
Recommended Pb-Free IR Profile
TIMEWITHIN 5 °C of ACTUAL
PEAKTEMPERATURE
t
p
2ꢀ-4ꢀ SEC.
26ꢀ +ꢀ/-5 °C
T
T
p
217 °C
L
RAMP-UP
3 °C/SEC. MAX.
15ꢀ - 2ꢀꢀ °C
RAMP-DOWN
6 °C/SEC. MAX.
T
smax
T
smin
t
s
t
L
6ꢀ to 15ꢀ SEC.
PREHEAT
6ꢀ to 18ꢀ SEC.
25
t 25 °C to PEAK
TIME
NOTES:
THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX.
= 2ꢀꢀ °C, T = 15ꢀ °C
T
smax
smin
Note: Non-halide flux should be used.
Regulatory Information
The HCPL-x710 have been approved by the following organizations:
IEC/EN/DIN EN 60747-5-2
UL
Approved under:
Recognized under UL 1577, component recognition
program, File E55361.
IEC 60747-5-2:1997 + A1:2002
EN 60747-5-2:2001 + A1:2002
DIN EN 60747-5-2 (VDE 0884
Teil 2):2003-01.
CSA
Approved under CSA Component Acceptance Notice
#5, File CA 88324.
(Option 060 only)
Insulation and Safety Related Specifications
Value
Parameter
Symbol
7710
0710
Units
Conditions
Minimum External Air
Gap (Clearance)
L(I01)
7.1
4.9
mm
Measured from input terminals to output
terminals, shortest distance through air.
Minimum External
Tracking (Creepage)
Minimum Internal Plastic
Gap (Internal Clearance)
L(I02)
CTI
7.4
4.8
mm
mm
Measured from input terminals to output
terminals, shortest distance path along body.
Insulation thickness between emitter and
detector; also known as distance through
insulation.
0.08
0.08
Tracking Resistance
(Comparative Tracking Index)
Isolation Group
≥175
IIIa
≥175 Volts DIN IEC 112/VDE 0303 Part 1
IIIa Material Group (DIN VDE 0110, 1/89, Table 1)
surfaceofaprintedcircuitboardbetweenthesolderfillets
of the input and output leads must be considered. There
are recommended techniques such as grooves and ribs
which may be used on a printed circuit board to achieve
desiredcreepageandclearances.Creepageandclearance
distances will also change depending on factors such as
pollution degree and insulation level.
All Avago data sheets report the creepage and clearance
inherent to the optocoupler component itself. These
dimensions are needed as a starting point for the equip-
ment designer when determining the circuit insulation
requirements.However,oncemountedonaprintedcircuit
board, minimum creepage and clearance requirements
must be met as specified for individual equipment stan-
dards. For creepage, the shortest distance path along the
5
IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics (Option 060)
Description
HCPL-7710
Option 060
HCPL-0710
Option 060
Symbol
Units
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤150 V rms
I-IV
I-IV
I-III
I-IV
I-III
for rated mains voltage ≤300 V rms
for rated mains voltage ≤450 V rms
Climatic Classification
55/100/21
55/100/21
Pollution Degree (DIN VDE 0110/1.89)
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b†
VIORM x 1.875 = VPR, 100% Production
Test with tm = 1 sec, Partial Discharge < 5 pC
2
2
V
VPR
630
1181
560
1050
V peak
V peak
IORM
Input to Output Test Voltage, Method a†
VIORM x 1.5 = VPR, Type and Sample Test,
tm = 60 sec, Partial Discharge < 5 pC
Highest Allowable Overvoltage†
(Transient Overvoltage, tini = 10 sec)
VPR
945
840
V peak
V peak
VIOTM
6000
4000
Safety Limiting Values
(Maximum values allowed in the event of a failure,
also see Thermal Derating curve, Figure 11.)
Case Temperature
TS
175
230
600
150
150
600
°C
mA
mW
Input Current
IS,INPUT
Output Power
PS,OUTPUT
Insulation Resistance at TS, V10 = 500 V
RIO
≥109
≥109
Ω
†Refer to the front of the optocoupler section of the Isolation and Control Component Designer’s Catalog, under Product Safety Regulations sec-
tion IEC/EN/DIN EN 60747-5-2, for a detailed description.
Note: These optocouplers are suitable for “safe electrical isolation”only within the safety limit data. Maintenance of the safety data shall be
ensured by means of protective circuits.
Note: The surface mount classification is Class A in accordance with CECC 00802.
Absolute Maximum Ratings
Parameter
Symbol
TS
Min.
–55
–40
0
Max.
Units
°C
Storage Temperature
Ambient Operating Temperature
Supply Voltages
125
TA
+100
6.0
°C
VDD1, VDD2
Volts
Volts
Volts
mA
mA
Input Voltage
V
I
–0.5
–0.5
–10
VDD1 +0.5
VDD2 +0.5
+10
Output Voltage
VO
II
Input Current
Average Output Current
Lead Solder Temperature
Solder Reflow Temperature Profile
IO
10
260°C for 10 sec., 1.6 mm below seating plane
See Solder Reflow Temperature Profile Section
Recommended Operating Conditions
Parameter
Symbol
TA
Min.
–40
4.5
2.0
0.0
Max.
+100
5.5
Units
°C
V
Ambient Operating Temperature
Supply Voltages
VDD1, VDD2
Logic High Input Voltage
Logic Low Input Voltage
Input Signal Rise and Fall Times
V
IH
VDD1
0.8
V
V
IL
V
tr, tf
1.0
ms
6
Electrical Specifications
Test conditions that are not specified can be anywhere within the recommended operating range.
All typical specifications are at TA = +25°C, VDD1 = VDD2 = +5 V.
DC Specifications
Parameter
Symbol
Min.
Typ.
Max.
Units
Test Conditions
Logic Low Input
Supply Current [1]
IDD1L
6.0
10.0
mA
VI = 0 V
Logic High Input
Supply Current
IDD1H
1.5
5.5
3.0
mA
VI = VDDI
Input Supply Current
Output Supply Current
Input Current
IDD1
IDD2
II
13.0
11.0
10
mA
mA
µA
V
-10
Logic High Output
Voltage
VOH
4.4
4.0
5.0
4.8
IO = -20 µA, VI = VIH
IO = -4 mA, VI = VIH
Logic Low Output
Voltage
VOL
0
0.5
0.1
1.0
V
IO = -20 µA, VI = VIL
IO = -4 mA, VI = VIL
Switching Specifications
Parameter
Symbol
Min.
Typ.
Max.
Units
Test Conditions
Propagation Delay Time
to Logic Low Output [2]
tPHL
20
40
ns
CL = 15 pF
CMOS Signal Levels
Propagation Delay Time
to Logic Low Output [2]
tPHL
tPLH
PW
20
23
40
40
ns
CL = 15 pF
CMOS Signal Levels
Propagation Delay Time
to Logic High Output
Pulse Width [3]
ns
CL = 15 pF
CMOS Signal Levels
80
ns
CL = 15 pF
CMOS Signal Levels
Data Rate [3]
12.5
8
MBd
ns
CL = 15 pF
CMOS Signal Levels
Pulse Width Distortion [4]
PWD
3
CL = 15 pF
|tPHL - tPLH
|
CMOS Signal Levels
Propagation Delay Skew [5]
tPSK
tR
20
ns
ns
CL = 15 pF
Output Rise Time
(10 - 90%)
9
CL = 15 pF
CMOS Signal Levels
Output Fall Time
(90 - 10%)
tF
8
ns
CL = 15 pF
CMOS Signal Levels
Common Mode
|CMH|
10
10
20
kV/µs
VI = VDD1, VO >
0.8 VDD1,
VCM = 1000 V
Transient Immunity at
Logic High Output [6]
Common Mode
|CML|
20
kV/µs
VI = 0 V, VO > 0.8 V,
VCM = 1000 V
Transient Immunity at
Logic Low Output [6]
Input Dynamic Power
CPD1
CPD2
60
10
pF
pF
Dissipation Capacitance [7]
Output Dynamic Power
Dissipation Capacitance [7]
7
Package Characteristics
Parameter
Symbol Min.
Typ.
Max.
Units
Test Conditions
Input-Output Momentary
Withstand Voltage [8, 9, 10]
0710
VISO
3750
3750
5000
Vrms RH = 50%,
t = 1 min.,
7710
TA = 25°C
Option 020
Resistance
RI-O
CI-O
1012
0.6
W
VI-O = 500 Vdc
f = 1 MHz
(Input-Output) [8]
Capacitance
pF
(Input-Output) [8]
Input Capacitance [11]
CI
3.0
Input IC Junction-to-Case
Thermal Resistance
-7710
-0710
-7710
-0710
qjci
145
160
140
135
°C/W Thermocouple
located at center
underside of package
Output IC Junction-to-Case
Thermal Resistance
qjco
Package Power Dissipation
PPD
150
mW
Notes:
1. The LED is ON when VI is low and OFF when VI is high.
2. tPHL propagation delay is measured from the 50% level on the falling edge of the VI signal to the 50% level of the falling edge of the VO signal.
tPLH propagation delay is measured from the 50% level on the rising edge of the VI signal to the 50% level of the rising edge of the VO signal.
3. Mimimum Pulse Width is the shortest pulse width at which 10% maximum, Pulse Width Distortion can be guaranteed. Maximum Data Rate is
the inverse of Minimum Pulse Width. Operating the HCPL-x710 at data rates above 12.5 MBd is possible provided PWD and data dependent
jitter increases and relaxed noise margins are tolerable within the application. For instance, if the maximum allowable variation of bit width is
30%, the maximum data rate becomes 37.5 MBd. Please note that HCPL-x710 performances above 12.5MBd are not guaranteed by Hewlett-
Packard.
4. PWD is defined as |tPHL - tPLH|. %PWD(percent pulse width distortion) is equal to the PWD divided by pulse width.
5. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within
the recommended operating conditions.
6. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common
mode voltage slew rate that can be sustained while maintaining VO < 0.8V. The common mode voltage slew rates apply to both rising and
falling common mode voltage edges.
7. Unloaded dynamic power dissipation is calculated as follows: CPD * VDD2 * f + IDD * VDD, where f is switching frequency in MHz.
8. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together.
9. In accordance with UL1577, each HCPL-0710 is proof tested by applying an insulation test voltage ≥4500 VRMS for 1 second (leakage detec-
tion current limit, II-O ≤5 µA). Each HCPL-7710 is proof tested by applying an insulation test voltage ≥ 4500 V rms for 1 second (leakage detec-
tion current limit, II-O ≤ 5 µA).
10. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to your equipment level safety specification or Avago Application Note 1074 entitled
“Optocoupler Input-Output Endurance Voltage.”
11. CI is the capacitance measured at pin 2 (VI).
2.2
29
5
4
3
2
1
ꢀ
ꢀ °C
25 °C
85 °C
2.1
2.ꢀ
1.9
27
25
23
ꢀ °C
25 °C
85 °C
T
T
PLH
PHL
21
19
17
15
1.8
1.7
1.6
ꢀ
1
2
3
4
5
4.5
4.75
5
5.25
5.5
ꢀ
1ꢀ 2ꢀ 3ꢀ 4ꢀ 5ꢀ 6ꢀ 7ꢀ 8ꢀ
(C)
V (V)
V
(V)
DD1
T
I
A
Figure 1. Typical output voltage vs. input voltage.
Figure 2. Typical input voltage switching threshold vs.
input supply voltage.
Figure 3. Typical propagation delays vs. temperature.
8
4
3
2
15
14
7
6
5
4
3
2
13
12
1
ꢀ
ꢀ
2ꢀ
4ꢀ
6ꢀ
8ꢀ
ꢀ
2ꢀ
4ꢀ
6ꢀ
8ꢀ
ꢀ
2ꢀ
4ꢀ
6ꢀ
8ꢀ
T
(C)
T
(C)
T (C)
A
A
A
Figure 4. Typical pulse width distortion vs. tempera-
ture.
Figure 5. Typical rise time vs. temperature.
Figure 6. Typical fall time vs. temperature.
25
23
21
19
17
15
13
11
9
6
5
4
3
29
27
25
T
PHL
23
21
19
17
15
T
PLH
2
1
0
7
5
ꢀ
5
1ꢀ 15 2ꢀ 25 3ꢀ 35
15 20
25
30
35
40
45
50
15 20 25 30 35 40 45 50
C (pF)
I
C (pF)
C (pF)
I
I
Figure 7. Typical propagation delays vs. output load
capacitance.
Figure 8. Typical pulse width distortion vs. output load
capacitance.
Figure 9. Typical rise time vs. load capacitance.
STANDARD 8 PIN DIP PRODUCT
800
SURFACE MOUNT SO8 PRODUCT
800
1ꢀ
9
8
7
6
5
4
3
2
1
ꢀ
P
(mW)
P
I
(mW)
S
S
700
600
500
400
300
700
600
500
400
300
I
(mA)
(mA)
S
S
(230)
200
200
(150)
100
100
0
0
ꢀ
5
1ꢀ 15 2ꢀ 25 3ꢀ 35
C (pF)
0
25 50 75 100 125 150 175 200
- CASE TEMPERATURE - o C
0
25 50 75 100 125 150 175 200
- CASE TEMPERATURE - o C
I
T
T
A
A
Figure 11. Thermal derating curve, dependence of Safety Limiting Value with case temperature per IEC/EN/DIN EN
60747-5-2.
Figure 10. Typical fall time vs. load capacitance.
9
Application Information
Bypassing and PC Board Layout
The HCPL-x710 optocouplers are extremely easy to
use. No external interface circuitry is required because
the HCPL-x710 use high-speed CMOS IC technology
allowing CMOS logic to be connected directly to the
inputs and outputs.
required for proper operation are two bypass capacitors.
Capacitor values should be between 0.01 µF and 0.1 µF.
For each capacitor, the total lead length between both
ends of the capacitor and the power-supply pins should
not exceed 20 mm. Figure 13 illustrates the recommend-
ed printed circuit board layout for the HPCL-x710.
As shown in Figure 12, the only external components
V
8
7
6
5
V
V
DD1
1
2
3
4
DD2
C1
C2
V
I
NC
NC
O
GND
GND
1
2
C1, C2 = ꢀ.ꢀ1 µF TO ꢀ.1 µF
Figure 12. Recommended Printed Circuit Board layout.
V
DD1
V
V
DD2
V
I
C1
C2
O
GND
GND
2
1
C1, C2 = ꢀ.ꢀ1 µF TO ꢀ.1 µF
Figure 13. Recommended Printed Circuit Board layout.
Propagation Delay, Pulse-Width Distortion and Propagation Delay
Skew
Propagation Delay is a figure of merit which describes
how quickly a logic signal propagates through a
from low to high. Similarly, the propagation delay from
high to low (tPHL) is the amount of time required for the
input signal to propagate to the output, causing the
output to change from high to low. See Figure14.
system. The propagation delay from low to high (tPLH
)
is the amount of time required for an input signal to
propagate to the output, causing the output to change
INPUT
5 V CMOS
ꢀ V
V
5ꢀ%
I
t
t
PHL
PLH
V
OH
2.5 V CMOS
OUTPUT
9ꢀ%
9ꢀ%
V
1ꢀ%
1ꢀ%
O
V
OL
Figure 14.
10
Pulse-width distortion (PWD) is the difference between
tPHL and tPLH and often determines the maximum data
rate capability of a transmission system. PWD can be
expressed in percent by dividing the PWD (in ns) by
the minimum pulse width (in ns) being transmitted.
Typically, PWD on the order of 20 - 30% of the minimum
pulse width is tolerable. The PWD specification for the
HCPL-x710 is 8 ns (10%) maximum across recommend-
ed operating conditions. 10% maximum is dictated
by the most stringent of the three fieldbus standards,
PROFIBUS.
Propagation delay skew is defined as the differ-
ence between the minimum and maximum propa-
gation delays, either tPLH or tPHL, for any given group
of optocouplers which are operating under the same
conditions (i.e., the same drive current, supply voltage,
output load, and operating temperature). As illustrated
in Figure 15, if the inputs of a group of optocouplers
are switched either ON or OFF at the same time, tPSK is
the difference between the shortest propagation delay,
either tPLH or tPHL, and the longest propagation delay,
either tPLH or tPHL
.
Propagation delay skew, tPSK, is an important parameter
to consider in parallel data applications where synchro-
nization of signals on parallel data lines is a concern. If
the parallel data is being sent through a group of op-
tocouplers, differences in propagation delays will cause
the data to arrive at the outputs of the optocouplers at
different times. If this difference in propagation delay
is large enough it will determine the maximum rate at
which parallel data can be sent through the optocou-
plers.
As mentioned earlier, tPSK can determine the maximum
parallel data transmission rate. Figure 16 is the timing
diagram of a typical parallel data application with both
the clock and data lines being sent through the opto-
couplers. The figure shows data and clock signals at the
inputs and outputs of the optocouplers. In this case the
data is assumed to be clocked off of the rising edge of
the clock.
DATA
V
I
5ꢀ%
INPUTS
CLOCK
2.5 V,
CMOS
V
O
t
PSK
DATA
V
5ꢀ%
I
OUTPUTS
t
PSK
CLOCK
2.5 V,
CMOS
V
O
t
PSK
Figure 15. Propagation delay skew waveform.
Figure 16. Parallel data transmission example.
Propagation delay skew represents the uncertainty of
where an edge might be after being sent through an
optocoupler. Figure16 shows that there will be uncer-
tainty in both the data and clock lines. It is important
that these two areas of uncertainty not overlap,
otherwise the clock signal might arrive before all of
the data outputs have settled, or some of the data
outputs may start to change before the clock signal
has arrived. From these considerations, the absolute
minimum pulse width that can be sent through op-
tocouplers in a parallel application is twice tPSK.
A cautious design should use a slightly longer pulse
width to ensure that any additional uncertainty in the
rest of the circuit does not cause a problem.
The HCPL-x710 optocouplers offer the advantage of
guaranteed specifications for propagation delays, pulse-
width distortion, and propagation delay skew over the
recommended temperature and power supply ranges.
11
Digital Field Bus Communication Networks
To date, despite its many drawbacks, the 4 - 20 mA
analog current loop has been the most widely accepted
standard for implementing process control systems.
In today’s manufacturing environment, however,
automated systems are expected to help manage
the process, not merely monitor it. With the advent
of digital field bus communication networks such as
DeviceNet, PROFIBUS, and Smart Distributed Systems
(SDS), gone are the days of constrained information.
Controllers can now receive multiple readings from field
devices (sensors, actuators, etc.) in addition to diagnos-
tic information.
The physical model for each of these digital field bus
communication networks is very similar as shown in
Figure 17. Each includes one or more buses, an interface
unit, optical isolation, transceiver, and sensing and/or
actuating devices.
CONTROLLER
BUS
INTERFACE
OPTICAL
ISOLATION
TRANSCEIVER
FIELD BUS
TRANSCEIVER
TRANSCEIVER
TRANSCEIVER
TRANSCEIVER
OPTICAL
ISOLATION
OPTICAL
ISOLATION
OPTICAL
ISOLATION
OPTICAL
ISOLATION
BUS
INTERFACE
BUS
INTERFACE
BUS
INTERFACE
BUS
INTERFACE
XXXXXX
YYY
SENSOR
DEVICE
CONFIGURATION
MOTOR
CONTROLLER
MOTOR
STARTER
Figure 17. Typical field bus communication physical model.
Optical Isolation for Field Bus Networks
These components could include such things as devices
with serial ports, parallel ports, RS232 and RS485 type
ports. As shown in Figure 18, power from the network is
used only for the transceiver and input (network) side of
the optocouplers.
To recognize the full benefits of these networks, each
recommends providing galvanic isolation using Avago
optocouplers. Since network communication is bi-direc-
tional (involving receiving data from and transmitting
data onto the network), two Avago optocouplers are
needed. By providing galvanic isolation, data integrity is
retained via noise reduction and the elimination of false
signals. In addition, the network receives maximum pro-
tection from power system faults and ground loops.
Isolation of nodes connected to any of the three types of
digital field bus networks is best achieved by using the
HCPL-x710 optocouplers. For each network, the HCPL-
x710 satisify the critical propagation delay and pulse
width distortion requirements over the temperature
range of 0°C to +85°C, and power supply voltage range
of 4.5 V to5.5V.
Within an isolated node, such as the DeviceNet Node
shown in Figure 18, some of the node’s components are
referenced to a ground other than V- of the network.
12
AC LINE
NODE/APP SPECIFIC
uP/CAN
LOCAL
NODE
SUPPLY
GALVANIC
ISOLATION
BOUNDARY
HCPL
x71ꢀ
HCPL
x71ꢀ
5 V REG.
TRANSCEIVER
DRAIN/SHIELD
SIGNAL
V+ (SIGNAL)
V– (SIGNAL)
V+ (POWER)
V– (POWER)
POWER
NETWORK
POWER
SUPPLY
Figure 18. Typical DeviceNet node.
Implementing DeviceNet and SDS with the HCPL-x710
Isolated Node Powered by the Network
With transmission rates up to 1 Mbit/s, both DeviceNet
and SDS are based upon the same broadcast-oriented,
This type of node is very flexible and as can be seen in
Figure 19, is regarded as “isolated” because not all of its
components have the same ground reference. Yet, all
components are still powered by the network. This node
contains two regulators: one is isolated and powers the
CAN controller, node-specific application and isolated
(node) side of the two optocouplers while the other is
non-isolated. The non-isolated regulator supplies the
transceiver and the non-isolated (network) half of the
two optocouplers.
communications protocol
— the Controller Area
Network (CAN). Three types of isolated nodes are rec-
ommended for use on these networks: Isolated Node
Powered by the Network (Figure 19), Isolated Node
with Transceiver Powered by the Network (Figure 20),
and Isolated Node Providing Power to the Network
(Figure21).
NODE/APP SPECIFIC
uP/CAN
ISOLATED
GALVANIC
SWITCHING
ISOLATION
POWER
HCPL
x71ꢀ
HCPL
x71ꢀ
BOUNDARY
SUPPLY
REG.
TRANSCEIVER
DRAIN/SHIELD
SIGNAL
V+ (SIGNAL)
V– (SIGNAL)
V+ (POWER)
V– (POWER)
POWER
NETWORK
POWER
SUPPLY
Figure 19. Isolated node powered by the network.
13
Isolated Node with Transceiver Powered by the Network
*Bus V+ Sensing
It is suggested that the Bus V+ sense block shown in
Figure 20 be implemented. A locally powered node with
an un-powered isolated Physical Layer will accumulate
errors and become bus-off if it attempts to transmit. The
Bus V+ sense signal would be used to change the BOI
attribute of the DeviceNet Object to the “auto-reset”
(01) value. Refer to Volume 1, Section 5.5.3. This would
cause the node to continually reset until bus power was
detected. Once power was detected, the BOI attribute
would be returned to the “hold in bus-off” (00) value.
The BOI attribute should not be left in the “auto-reset”
(01) value since this defeats the jabber protection ca-
pability of the CAN error confinement. Any inexpensive
low frequency optical isolator can be used to implement
this feature.
Figure20 shows a node powered by both the network
and another source. In this case, the transceiver and
isolated (network) side of the two optocouplers are
powered by the network. The rest of the node is
powered by the AC line which is very beneficial when
an application requires a significant amount of power.
This method is also desirable as it does not heavily load
the network.
More importantly, the unique “dual-inverting” design
of the HCPL-x710 ensure the network will not “lock-up”
if either AC line power to the node is lost or the node
powered-off. Specifically, when input power (VDD1) to
the HCPL-x710 located in the transmit path is eliminat-
ed, a RECESSIVE bus state is ensured as the HCPL-x710
output voltage (VO) go HIGH.
AC LINE
NON ISO
5 V
NODE/APP SPECIFIC
uP/CAN
GALVANIC
ISOLATION
BOUNDARY
HCPL
ꢀ71ꢀ
HCPL
ꢀ71ꢀ
HCPL
ꢀ71ꢀ
REG.
TRANSCEIVER
DRAIN/SHIELD
SIGNAL
V+ (SIGNAL)
V– (SIGNAL)
V+ (POWER)
V– (POWER)
POWER
NETWORK
POWER
SUPPLY
* OPTIONAL FOR BUS V + SENSE
Figure 20. Isolated node with transceiver powered by the network.
14
Isolated Node Providing Power to the Network
More importantly, the unique “dual-inverting” design
of the HCPL-x710 ensure the network will not “lock-up”
if either AC line power to the node is lost or the node
powered-off. Specifically, when input power (VDD1) to
the HCPL-x710 located in the transmit path is eliminat-
ed, a RECESSIVE bus state is ensured as the HCPL-x710
output voltage (VO) go HIGH.
Figure 21 shows a node providing power to the
network. The AC line powers a regulator which provides
five (5) volts locally. The AC line also powers a 24 volt
isolated supply, which powers the network, and another
five-volt regulator, which, in turn, powers the transceiv-
er and isolated (network) side of the two optocouplers.
This method is recommended when there are a limited
number of devices on the network that don’t require
much power, thus eliminating the need for separate
power supplies.
AC LINE
DEVICENET NODE
NODE/APP SPECIFIC
uP/CAN
5 V REG.
ISOLATED
SWITCHING
POWER
GALVANIC
ISOLATION
BOUNDARY
HCPL
ꢀ71ꢀ
HCPL
ꢀ71ꢀ
SUPPLY
5 V REG.
TRANSCEIVER
DRAIN/SHIELD
SIGNAL
V+ (SIGNAL)
V– (SIGNAL)
V+ (POWER)
V– (POWER)
POWER
Figure 21. Isolated node providing power to the network.
15
Power Supplies and Bypassing
the input and output power-supply pins of the HCPL-
x710. For each capacitor, the total lead length between
both ends of the capacitor and the power supply pins
should not exceed 20 mm. The bypass capacitors are
required because of the high-speed digital nature of the
signals inside the optocoupler.
The recommended DeviceNet application circuit is
shown in Figure 22. Since the HCPL-x710 are fully com-
patible with CMOS logic level signals, the optocoupler is
connected directly to the CAN transceiver. Two bypass
capacitors (with values between 0.01 and 0.1 µF) are
required and should be located as close as possible to
GALVANIC
ISOLATION
BOUNDARY
ISO 5 V
5 V
LINEAR OR
SWITCHING
REGULATOR
V
V
V
DD2
1
2
8
7
DD1
+
+
ꢀ.ꢀ1
µF
TXꢀ
IN
HCPL-ꢀ71ꢀ
V
CC
5 V+
TxD
Rs
V
O
ꢀ.ꢀ1 µF
3
4
6
5
CANH
4 CAN+
3 SHIELD
2 CAN–
1 V–
82C25ꢀ
GND
GND
GND
+
1
2
2
C4
ꢀ.ꢀ1 µF
CANL
REF
GND
VREF
RXD
GND
GND
5
6
4
3
1
C1
ꢀ.ꢀ1 µF
5ꢀꢀ V
ꢀ.ꢀ1
µF
D1
3ꢀ V
R1
1 M
RXꢀ
V
O
HCPL-ꢀ71ꢀ
V
ꢀ.ꢀ1 µF
7
8
2
1
IN
V
V
DD1
DD2
ISO 5 V
5 V
Figure 22. Recommended DeviceNet application circuit.
Implementing PROFIBUS with the HCPL-x710
PROFIBUS USER:
CONTROL STATION
An acronym for Process Fieldbus, PROFIBUS is essen-
tially a twisted-pair serial link very similar to RS-485
capable of achieving high-speed communication up to
12MBd. As shown in Figure 23, a PROFIBUS Controller
(PBC) establishes the connection of a field automation
unit (control or central processing station) or a field
device to the transmission medium. The PBC consists
of the line transceiver, optical isolation, frame character
transmitter/receiver (UART), and the FDL/APP processor
with the interface to the PROFIBUS user.
(CENTRAL PROCESSING)
OR FIELD DEVICE
USER INTERFACE
FDL/APP
PROCESSOR
UART
PBC
OPTICAL ISOLATION
TRANSCEIVER
MEDIUM
Figure 23. PROFIBUS Controller (PBC).
16
Power Supplies and Bypassing
The recommended PROFIBUS application circuit is
shown in Figure 24. Since the HCPL-x710 are fully com-
patible with CMOS logic level signals, the optocoup-
ler is connected directly to the transceiver. Two bypass
capacitors (with values between 0.01 and 0.1 µF) are
required and should be located as close as possible to
the input and output power-supply pins of the HCPL-
x710. For each capacitor, the total lead length between
both ends of the capacitor and the power supply pins
should not exceed 20 mm. The bypass capacitors are
required because of the high-speed digital nature of the
signals inside the optocoupler.
Being very similar to multi-station RS485 systems, the
HCPL-061N optocoupler provides a transmit disable
function which is necessary to make the bus free after
each master/slave transmission cycle. Specifically, the
HCPL-061N disables the transmitter of the line driver
by putting it into a high state mode. In addition, the
HCPL-061N switches the RX/TX driver IC into the listen
mode. The HCPL-061N offers HCMOS compatibility and
the high CMR performance (1 kV/µs at VCM = 1000 V)
essential in industrial communication interfaces.
GALVANIC
ISOLATION
BOUNDARY
5 V
ISO 5 V
V
V
V
DD1
8
7
1
2
ISO 5 V
8
DD2
V
ꢀ.ꢀ1 µF
IN
HCPL-x71ꢀ
V
CC
ꢀ.ꢀ1
µF
1
R
6
5
3
4
Rx
O
6
7
+
A
B
ꢀ.ꢀ1
µF
RT
SHIELD
–
SN75176B
GND
GND
1
2
4
3
2
D
DE
RE
5 V
ISO 5 V
GND
5
V
V
DD2
1
2
8
7
DD1
ꢀ.ꢀ1
µF
1 M
ꢀ.ꢀ1 µF
V
Tx
IN
HCPL-x71ꢀ
V
O
3
4
6
5
ꢀ.ꢀ1 µF
GND
GND
2
1
ISO 5 V
V
1
2
8
7
CC
5 V
V
E
ANODE
68ꢀ Ω
ꢀ.ꢀ1
µF
1, ꢀ kΩ
V
3
4
CATHODE
6
5
Tx ENABLE
O
GND
HCPL-ꢀ61N
HCPL-ꢀ71ꢀ fig 23
Figure 24. Recommended PROFIBUS application circuit.
17
For product information and a complete list of distributors, please go to our website: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries.
Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved. Obsoletes AV01-0564EN
AV02-0641EN - January 4, 2008
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