ADS1605 [BB]
16 BIT 5MSPS ANALOG TO DIGITAL CONVERTER; 16位5MSPS模数转换器
| 型号： | ADS1605 |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | 16 BIT 5MSPS ANALOG TO DIGITAL CONVERTER |
| 文件： | 总32页 (文件大小：425K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢋ ꢑꢉ ꢀꢁ ꢗꢇ
ꢋ ꢑꢉ ꢀꢁ ꢗꢁ
SBAS274E − MARCH 2003 − REVISED JUNE 2004
ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢉ ꢊꢉ
ꢋ ꢌ ꢍꢎ ꢏꢐꢂ ꢅ ꢏꢂ ꢑ ꢄ ꢐꢄ ꢅꢍ ꢎ ꢒꢓ ꢏꢌꢔ ꢕ ꢖ ꢅꢕ ꢖ
FEATURES
DESCRIPTION
The ADS1605 and ADS1606 are high-speed, high-precision,
delta-sigma analog-to-digital converters (ADCs) with 16-bit
resolution. The data rate is 5 mega-samples per second
(MSPS), the bandwidth (−3dB) is 2.45MHz, and passband
ripple is less than 0.0025dB (to 2.2MHz). Both devices offer
the same outstanding performance at these speeds with a
signal-to-noise ratio up to 88dB, total harmonic distortion
down to −99dB, and a spurious-free dynamic range up to
101dB. For even higher-speed operation, the data rate can
be doubled to 10MSPS in 2X mode. The ADS1606 includes
an adjustable first-in first-out buffer (FIFO) for the output data.
D
D
D
D
D
D
D
D
D
Data Rate: 5MSPS (10MSPS in 2X Mode)
Signal-to-Noise Ratio: 88dB
Total Harmonic Distortion: −99dB
Spurious-Free Dynamic Range: 101dB
Linear Phase with 2.45 MHz Bandwidth
Passband Ripple: 0.0025dB
Selectable On-Chip Reference
Directly Connects to TMS320C6000 DSPs
Easily Upgradable to 18 Bits with the
ADS1625 and ADS1626
The input signal is measured against a voltage reference that
can be generated on-chip or supplied externally. The digital
output data is provided over a simple parallel interface that
easily connects to digital signal processors (DSPs). An
out-of-range monitor reports when the input range has been
exceeded. The ADS1605/6 operate from a +5V analog
supply (AVDD) and +3V digital supply (DVDD). The digital
I/O supply (IOVDD) operates from +2.7 to +5.25V, enabling
the digital interface to support a range of logic families. The
analog power dissipation is set by an external resistor and
can be reduced when operating at slower speeds. A power
down mode, activated by a digital I/O pin, shuts down all
circuitry. The ADS1605/6 are offered in a TQFP-64 package
using TI PowerPAD technology.
D
D
D
Adjustable Power Dissipation: 315 to 570mW
Power Down Mode
Supplies: Analog
Digital
+5V
+3V
Digital I/O +2.7 to +5.25V
APPLICATIONS
D
D
D
D
D
Scientific Instruments
Automated Test Equipment
Data Acquisition
Medical Imaging
Vibration Analysis
The ADS1605 and ADS1606, along with their 18-bit
counterparts, the ADS1625 and ADS1626, are well suited
for the demanding measurement requirements of scientific
instrumentation, automated test equipment, data acquisi-
tion, and medical imaging.
VREFP VREFN VMID RBIAS VCAP
AVDD DVDD IOVDD
PD
Reference and Bias Circuits
REFEN
RESET
CLK
CS
I/O
2XMODE
AINP
AINN
DS
Digital
Filter
Interface
RD
Modulator
DRDY
OTR
ADS1606 Only
FIFO
DOUT[15:0]
ADS1605
ADS1606
FIFO_LEV[2:0]
AGND
DGND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
ꢊꢘ ꢙ ꢑꢚ ꢓ ꢛꢜ ꢙꢝ ꢑ ꢋꢛꢋ ꢄꢌ ꢞꢏ ꢖ ꢟꢍ ꢅꢄꢏꢌ ꢄꢠ ꢡꢢ ꢖ ꢖ ꢕꢌꢅ ꢍꢠ ꢏꢞ ꢣꢢꢤ ꢎꢄꢡ ꢍꢅꢄ ꢏꢌ ꢥꢍ ꢅꢕꢦ ꢊꢖ ꢏꢥꢢ ꢡꢅꢠ
ꢡ ꢏꢌ ꢞꢏꢖ ꢟ ꢅꢏ ꢠ ꢣꢕ ꢡ ꢄ ꢞꢄ ꢡ ꢍ ꢅꢄ ꢏꢌꢠ ꢣ ꢕꢖ ꢅꢧꢕ ꢅꢕ ꢖ ꢟꢠ ꢏꢞ ꢛꢕꢨ ꢍꢠ ꢜꢌꢠ ꢅꢖ ꢢꢟ ꢕꢌꢅ ꢠ ꢠꢅ ꢍꢌꢥ ꢍꢖ ꢥ ꢩ ꢍꢖ ꢖ ꢍ ꢌꢅꢪꢦ
ꢊꢖ ꢏ ꢥꢢꢡ ꢅ ꢄꢏ ꢌ ꢣꢖ ꢏ ꢡ ꢕ ꢠ ꢠ ꢄꢌ ꢐ ꢥꢏ ꢕ ꢠ ꢌꢏꢅ ꢌꢕ ꢡꢕ ꢠꢠ ꢍꢖ ꢄꢎ ꢪ ꢄꢌꢡ ꢎꢢꢥ ꢕ ꢅꢕ ꢠꢅꢄ ꢌꢐ ꢏꢞ ꢍꢎ ꢎ ꢣꢍ ꢖ ꢍꢟ ꢕꢅꢕ ꢖ ꢠꢦ
Copyright 2003−2004, Texas Instruments Incorporated
www.ti.com
ꢋꢑ ꢉꢀ ꢁ ꢗ ꢇ
ꢋꢑ ꢉꢀ ꢁ ꢗ ꢁ
www.ti.com
SBAS274E − MARCH 2003 − REVISED JUNE 2004
ORDERING INFORMATION
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE−LEAD
(1)
ADS1605IPAPT
ADS1605IPAPR
ADS1606IPAPT
ADS1606IPAPR
Tape and Reel, 250
Tape and Reel, 1000
Tape and Reel, 250
Tape and Reel, 1000
TQFP−64
PowerPAD
ADS1605
ADS1606
PAP
PAP
−40°C to +85°C
−40°C to +85°C
ADS1605I
ADS1606I
TQFP−64
PowerPAD
(1)
For the most current specification and package information, refer to our web site at www.ti.com.
PRODUCT FAMILY
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range unless otherwise noted
PRODUCT
ADS1605
ADS1606
ADS1625
ADS1626
RESOLUTION
16 Bits
DATA RATE
FIFO?
No
ADS1605, ADS1606
−0.3 to +6
UNIT
5.0MSPS
5.0MSPS
1.25MSPS
1.25MSPS
AVDD to AGND
V
V
V
V
16 Bits
18 Bits
18 Bits
Yes
No
DVDD to DGND
−0.3 to +3.6
IOVDD to DGND
−0.3 to +6
Yes
AGND to DGND
−0.3 to +0.3
Input Current
100mA, Momentary
10mA, Continuous
−0.3 to AVDD + 0.3
−0.3 to IOVDD + 0.3
+150
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handledwith appropriate precautions. Failure to observe
Input Current
Analog I/O to AGND
Digital I/O to DGND
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature (soldering, 10s)
V
V
proper handling and installation procedures can cause damage.
°C
°C
°C
°C
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
−40 to +105
−60 to +150
+260
(1)
Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not implied.
2
ꢋ ꢑꢉ ꢀꢁ ꢗꢇ
ꢋ ꢑꢉ ꢀꢁ ꢗꢁ
www.ti.com
SBAS274E − MARCH 2003 − REVISED JUNE 2004
ELECTRICAL CHARACTERISTICS
All specifications at −40°C to +85°C, AVDD = 5V, DVDD = IOVDD = 3V, f
= 40MHz, External V
REF
= +3V, 2XMODE = low, V
CM
= 2.0V,
CLK
FIFO disabled, and R
= 37kΩ, unless otherwise noted.
BIAS
PARAMETER TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analog Input
0dBFS
1.545V
1.227V
0.774V
0.155V
V
V
V
V
REF
REF
REF
REF
−2dBFS
−6dBFS
−20dBFS
Differential input voltage (V
(AINP − AINN)
)
IN
Common-mode input voltage (V
(AINP + AINN) / 2
)
CM
2.0
V
0dBFS
−0.1
0.1
4.7
4.2
V
V
Absolute input voltage
(AINP or AINN with respect to AGND)
−2dBFS input and smaller
Dynamic Specifications
f
CLK
Data rate
MSPS
5.0ǒ Ǔ
40MHz
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
= 100kHz, −2dBFS
= 100kHz, −6dBFS
= 100kHz, −20dBFS
= 500kHz, −2dBFS
= 500kHz, −6dBFS
= 500kHz, −20dBFS
= 2MHz, −2dBFS
= 2MHz, −6dBFS
= 2MHz, −20dBFS
= 100kHz, −2dBFS
= 100kHz, −6dBFS
= 100kHz, −20dBFS
= 500kHz, −2dBFS
= 500kHz, −6dBFS
= 500kHz, −20dBFS
= 2MHz, −2dBFS
= 2MHz, −6dBFS
= 2MHz, −20dBFS
= 100kHz, −2dBFS
= 100kHz, −6dBFS
= 100kHz, −20dBFS
= 500kHz, −2dBFS
= 500kHz, −6dBFS
= 500kHz, −20dBFS
= 2MHz, −2dBFS
= 2MHz, −6dBFS
= 2MHz, −20dBFS
88
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
84
62
70
86
83
Signal−to−noise ratio (SNR)
69
84
82
69
−93
−99
−94
−94
−97
−93
−98
−101
−92
86
−85
Total harmonic distortion (THD)
84
62
70
86
83
Signal−to−noise and distortion (SINAD)
69
84
82
69
3
ꢋꢑ ꢉꢀ ꢁ ꢗ ꢇ
ꢋꢑ ꢉꢀ ꢁ ꢗ ꢁ
www.ti.com
SBAS274E − MARCH 2003 − REVISED JUNE 2004
ELECTRICAL CHARACTERISTICS (continued)
All specifications at −40°C to +85°C, AVDD = 5V, DVDD = IOVDD = 3V, f
= 40MHz, External V
REF
= +3V, 2XMODE = low, V
CM
= 2.0V,
CLK
FIFO disabled, and R
= 37kΩ, unless otherwise noted.
BIAS
PARAMETER
TEST CONDITIONS
= 100kHz, −2dBFS
MIN
TYP
96
MAX
UNIT
dB
dB
dB
dB
dB
dB
dB
dB
dB
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
= 100kHz, −6dBFS
= 100kHz, −20dBFS
= 500kHz, −2dBFS
= 500kHz, −6dBFS
= 500kHz, −20dBFS
= 2MHz, −2dBFS
= 2MHz, −6dBFS
= 2MHz, −20dBFS
101
96
85
95
100
95
Spurious free dynamic range (SFDR)
102
105
96
f
1
f
2
= 1.99MHz, −6dBFS
= 2.00MHz, −6dBFS
Intermodulation distortion (IMD)
−94
4
dB
ns
Aperture delay
Digital Filter Characteristics
f
CLK
Pass band
0
MHz
2.2ǒ Ǔ
40MHz
Pass band ripple
0.0025
dB
f
CLK
−0.1dB attenuation
−3.0dB attenuation
MHz
2.3ǒ Ǔ
40MHz
Pass band transition
f
CLK
MHz
2.45ǒ Ǔ
40MHz
f
f
CLK
CLK
Stop band
MHz
dB
37.2ǒ Ǔ
2.8ǒ Ǔ
40MHz
40MHz
Stop band attenuation
Group delay
72
40MHz
µs
5.2ǒ Ǔ
f
CLK
40MHz
Settling time
To 0.001%
µs
9.4ǒ Ǔ
f
CLK
Static Specifications
Resolution
16
Bits
Bits
No missing codes
Input referred noise
Integral nonlinearity
Differential nonlinearity
Offset error
16
1.0
0.75
0.25
0.05
1
LSB, rms
LSB
−1.5dBFS signal
LSB
%FSR
ppmFSR/°C
%
Offset error drift
Gain error
0.25
10
Gain error drift
Excluding reference drift
ppm/°C
dB
Common-mode rejection
Power-supply rejection
At dc
At dc
75
65
dB
4
ꢋ ꢑꢉ ꢀꢁ ꢗꢇ
ꢋ ꢑꢉ ꢀꢁ ꢗꢁ
www.ti.com
SBAS274E − MARCH 2003 − REVISED JUNE 2004
ELECTRICAL CHARACTERISTICS (continued)
All specifications at −40°C to +85°C, AVDD = 5V, DVDD = IOVDD = 3V, f
= 40MHz, External V
REF
= +3V, 2XMODE = low, V
CM
= 2.0V,
CLK
FIFO disabled, and R
= 37kΩ, unless otherwise noted.
BIAS
PARAMETER
(1)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Voltage Reference
= (VREFP − VREFN)
V
REF
2.5
3.75
0.75
2.3
3.0
4.0
1.0
2.5
50
3.2
4.25
1.25
2.8
V
VREFP
VREFN
VMID
V
V
V
V
REF
drift
Internal reference (REFEN = low)
Internal reference (REFEN = low)
ppm/°C
ms
Startup time
Clock Input
Frequency (f
Duty Cycle
15
)
40
50
55
MHz
%
CLK
f
= 40MHz
45
CLK
Digital Input/Output
V
V
V
V
0.7 IOVDD
DGND
IOVDD
V
V
IH
0.3 IOVDD
IL
I
I
= 50µA
= 50µA
IOVDD − 0.5
V
OH
OL
OH
DGND +0.5
10
V
OL
Input leakage
DGND < V
DIGIN
< IOVDD
µA
Power-Supply Requirements
AVDD
DVDD
IOVDD
4.75
2.7
5.25
3.3
5.25
135
105
55
V
V
2.7
V
REFEN = low
REFEN = high
110
85
45
4
mA
mA
mA
mA
AVDD current (I
DVDD current (I
)
AVDD
)
DVDD
IOVDD current (I
)
IOVDD = 3V
6
IOVDD
AVDD = 5V, DVDD = 3V, IOVDD = 3V,
REFEN = high
570
5
710
mW
mW
Power dissipation
PD = low, CLK disabled
Temperature Range
Specified
−40
−40
−60
+85
+105
+150
°C
°C
Operating
Storage
°C
Thermal Resistance, θ
25
°C/W
°C/W
JA
PowerPAD soldered to PCB with 2oz.
trace and copper pad.
θ
0.5
JC
(1)
The specification limits for VREF, VREFP, VREFN, and VMID apply when using the internal or an external reference. The internal reference
voltages are bounded by the limits shown. When using an external reference, the limits indicate the allowable voltages that can be applied to
the reference pins.
5
ꢋꢑ ꢉꢀ ꢁ ꢗ ꢇ
ꢋꢑ ꢉꢀ ꢁ ꢗ ꢁ
www.ti.com
SBAS274E − MARCH 2003 − REVISED JUNE 2004
DEFINITIONS
Absolute Input Voltage
Intermodulation Distortion (IMD)
Absolute input voltage, given in volts, is the voltage of each
analog input (AINN or AINP) with respect to AGND.
IMD, given in dB, is measured while applying two input
signals of the same magnitude, but with slightly different
frequencies. It is calculated as the difference between the
rms amplitude of the input signal to the rms amplitude of
the peak spurious signal.
Aperture Delay
Aperture delay is the delay between the rising edge of CLK
and the sampling of the input signal.
Offset Error
Common-Mode Input Voltage
Offset Error, given in % of FSR, is the output reading when
the differential input is zero.
Common-mode input voltage (VCM) is the average voltage
of the analog inputs:
Offset Error Drift
(AINP ) AINN)
Offset error drift, given in ppm of FSR/_C, is the drift over
temperature of the offset error. The offset error is specified
as the larger of the drift from ambient (T = 25_C) to the
minimum or maximum operating temperatures.
2
Differential Input Voltage
Differential input voltage (VIN) is the voltage difference
between the analog inputs: (AINP−AINN).
Signal-to-Noise Ratio (SNR)
Differential Nonlinearity (DNL)
SNR, given in dB, is the ratio of the rms value of the input
signal to the sum of all the frequency components below
fCLK/2 (the Nyquist frequency) excluding the first six
harmonics of the input signal and the dc component.
DNL, given in least-significant bits of the output code
(LSB), is the maximum deviation of the output code step
sizes from the ideal value of 1LSB.
Signal-to-Noise and Distortion (SINAD)
Full-Scale Range (FSR)
SINAD, given in dB, is the ratio of the rms value of the input
signal to the sum of all the frequency components below
FSR is the difference between the maximum and minimum
measurable input signals. FSR = 2 × 1.545VREF
.
f
CLK/2 (the Nyquist frequency) including the harmonics of
Gain Error
the input signal but excluding the dc component.
Gain error, given in %, is the error of the full-scale input
signal with respect to the ideal value.
Spurious Free Dynamic Range (SFDR)
SFDR, given in dB, is the difference between the rms
amplitude of the input signal to the rms amplitude of the
peak spurious signal.
Gain Error Drift
Gain error drift, given in ppm/_C, is the drift over
temperature of the gain error. The gain error is specified as
the larger of the drift from ambient (T = 25_C) to the
minimum or maximum operating temperatures.
Total Harmonic Distortion (THD)
THD, given in dB, is the ratio of the sum of the rms value
of the first six harmonics of the input signal to the rms value
of the input signal.
Integral Nonlinearity (INL)
INL, given in least-significant bits of the output code (LSB),
is the maximum deviation of the output codes from a best
fit line.
6
ꢋ ꢑꢉ ꢀꢁ ꢗꢇ
ꢋ ꢑꢉ ꢀꢁ ꢗꢁ
www.ti.com
SBAS274E − MARCH 2003 − REVISED JUNE 2004
PIN ASSIGNMENTS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
AGND
AVDD
AGND
AINN
1
2
3
4
5
6
7
8
9
48 FIFO_LEV[2] (ADS1606 Only)
ADS1605
ADS1606
47
46
FIFO_LEV[1] (ADS1606 Only)
FIFO_LEV[0] (ADS1606 Only)
45 NC
AINP
44 DOUT[15]
43
42
AGND
AVDD
RBIAS
AGND
DOUT[14]
DOUT[13]
TQFP PACKAGE
(TOP VIEW)
41 DOUT[12]
40 DOUT[11]
39 DOUT[10]
PowerPADTM
AVDD 10
11
12
38
37
AGND
AVDD
DOUT[9]
DOUT[8]
REFEN 13
NC 14
36 DOUT[7]
35 DOUT[6]
15
16
34
33
2XMODE
NC
DOUT[5]
DOUT[4]
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Terminal Functions
TERMINAL
TYPE
DESCRIPTION
NAME
AGND
AVDD
AINN
NO.
1, 3, 6, 9, 11, 55, 57
Analog
Analog
Analog ground
2, 7, 10, 12, 58
Analog supply
4
Analog input
Analog input
Analog
Negative analog input
Positive analog input
AINP
5
RBIAS
REFEN
NC
8
13
Terminal for external analog bias setting resistor
Digital input: active low
Not connected
Internal reference enable. Internal pull-down resistor of 170kΩ to DGND.
14,16, 27, 28, 45, 50
These terminals are not connected within the ADS1605/6 and must be left
unconnected.
2XMODE
PD
15
Digital input
Digital input: active low
Digital
Digital filter decimation rate. Internal pull-down resistor of 170kΩ to DGND.
17
18, 26, 52
19, 25, 51, 54
20
Power down all circuitry. Internal pull-up resistor of 170kΩ to DGND.
DVDD
DGND
RESET
CS
Digital supply
Digital
Digital ground
Digital input: active low
Digital input: active low
Digital input: active low
Digital output
Reset digital filter
21
Chip select
RD
22
Read enable
OTR
23
Analog inputs out of range
Data ready on falling edge
Data output. DOUT[15] is the MSB and DOUT[0] is the LSB.
DRDY
DOUT [15:0]
FIFO_LEV[2:0]
24
Digital output: active low
Digital output
29−44
46−48
Digital input
FIFO level (for the ADS1606 only). FIFO_LEV[2] is MSB.
NOTE: These terminals must be left disconnected on the ADS1605.
IOVDD
CLK
53
56
Digital
Digital input
Analog
Digital I/O supply
Clock input
VCAP
VREFN
VMID
59
Terminal for external bypass capacitor connection to internal bias voltage
Negative reference voltage
60, 61
62
Analog
Analog
Midpoint voltage
VREFP
63, 64
Analog
Positive reference voltage
7
ꢋꢑ ꢉꢀ ꢁ ꢗ ꢇ
ꢋꢑ ꢉꢀ ꢁ ꢗ ꢁ
www.ti.com
SBAS274E − MARCH 2003 − REVISED JUNE 2004
PARAMETER MEASUREMENT INFORMATION
t2
t1
CLK
t2
t3
t4
t4
DRDY
t6
t5
DOUT[15:0]
Data N
Data N + 1
Data N + 2
NOTE: CS and RD tied low.
Figure 1. Data Retrieval Timing (ADS1605, ADS1606 with FIFO Disabled)
RD, CS
t7
t8
DOUT[15:0]
Figure 2. DOUT Inactive/Active Timing (ADS1605, ADS1606 with FIFO Disabled)
TIMING REQUIREMENTS FOR FIGURES 1 AND 2
SYMBOL
DESCRIPTION
MIN
20
1
TYP
25
MAX
1000
50
UNIT
t
1
ns
MHz
ns
CLK period (1/f
)
CLK
1/t
1
40
f
CLK
t
2
10
CLK pulse width, high or low
t
3
10
ns
Rising edge of CLK to DRDY low
t
4
4 t
1
ns
DRDY pulse width high or low
t
10
15
15
15
ns
Falling edge of DRDY to data invalid
5
t
6
ns
Falling edge of DRDY to data valid
t
7
ns
Rising edge of RD and/or CS inactive (high) to DOUT high impedance
Falling edge of RD and/or CS active (low) to DOUT active.
t
8
ns
NOTE: DOUT[15:0] and DRDY load = 10pF.
8
ꢋ ꢑꢉ ꢀꢁ ꢗꢇ
ꢋ ꢑꢉ ꢀꢁ ꢗꢁ
www.ti.com
SBAS274E − MARCH 2003 − REVISED JUNE 2004
CLK
t11
t9
RESET
DRDY
t12
t10
t3
Settled
Data
DOUT[15:0]
NOTE: CS and RD tied low.
Figure 3. Reset TIming (ADS1605, ADS1606 with FIFO Disabled)
TIMING REQUIREMENTS FOR FIGURE 3
SYMBOL
DESCRIPTION
MIN
50
TYP
MAX
UNIT
ns
t
3
10
Rising edge of CLK to DRDY low
t
9
ns
RESET pulse width
t
9
ns
Delay from RESET active (low) to DRDY forced high and DOUT forced low
RESET rising edge to falling edge of CLK
10
t
−5
10
ns
11
DRDY
Cycles
t
12
47
Delay from DOUT active to valid DOUT (settling to 0.001%)
NOTE: DOUT[15:0] and DRDY load = 10pF.
9
ꢋꢑ ꢉꢀ ꢁ ꢗ ꢇ
ꢋꢑ ꢉꢀ ꢁ ꢗ ꢁ
www.ti.com
SBAS274E − MARCH 2003 − REVISED JUNE 2004
t1
t2
CLK
t2
t13
t14
DRDY
t15
t16
CS(1
)
t21
t17
t20
R
D
t18
t19
DOUT[15:0]
D1
D2
DL(2)
(1) CS may be tied low.
(2) The number of data readings (DL) is set by the FIFO level.
Figure 4. Data Retrieval Timing (ADS1606 with FIFO Enabled)
RD, CS
t7
t8
DOUT[15:0]
Figure 5. DOUT Inactive/Active Timing (ADS1606 with FIFO Enabled)
TIMING REQUIREMENTS FOR FIGURE 4 AND FIGURE 5
SYMBOL
DESCRIPTION
MIN
20
TYP
MAX
UNIT
t
1
25
1000
ns
ns
ns
CLK period (1/f
)
CLK
t
2
10
CLK pulse width, high or low
t
7
7
7
15
15
Rising edge of RD and/or CS inactive (high) to DOUT high impedance
t
8
ns
ns
Falling edge of RD and/or CS active (low) to DOUT active.
Rising edge of CLK to DRDY high
t
13
12
CLK
Cycles
(1)
t
14
8 × FIFO Level
DRDY period
CLK
Cycles
t
15
1
DRDY positive pulse width
t
0
0
ns
ns
ns
ns
RD high hold time after DRDY goes low
CS low before RD goes low
RD negative pulse width
16
t
17
t
18
10
10
t
19
t
20
t
21
RD positive pulse width
CLK
Cycles
2
0
RD high before DRDY toggles
RD high before CS goes high
ns
NOTE: DOUT[15:0] and DRDY load = 10pF.
(1)
See FIFO section for more details.
10
ꢋ ꢑꢉ ꢀꢁ ꢗꢇ
ꢋ ꢑꢉ ꢀꢁ ꢗꢁ
www.ti.com
SBAS274E − MARCH 2003 − REVISED JUNE 2004
CLK
t11
t9
RESET
t26
t25
DRDY
t23
t24
R
D
Figure 6. Reset Timing (ADS1606 with FIFO Enabled)
TIMING REQUIREMENTS FOR FIGURE 6
SYMBOL
DESCRIPTION
MIN
50
TYP
MAX
UNIT
ns
t
9
RESET pulse width
t
11
−5
10
ns
RESET rising edge to falling edge of CLK
CLK
Cycles
t
8
8
RD pulse low after RESET goes high
23
CLK
Cycles
t
24
RD pulse high before first DRDY pulse after RESET goes high
DRDY low after RESET goes low
CLK
Cycles
t
25
8 × (FIFO level + 1)
DRDY
Cycles
See Table 4
t
26
Delay from RESET high to valid DOUT (settling to 0.001%)
11
ꢋꢑ ꢉꢀ ꢁ ꢗ ꢇ
ꢋꢑ ꢉꢀ ꢁ ꢗ ꢁ
www.ti.com
SBAS274E − MARCH 2003 − REVISED JUNE 2004
TYPICAL CHARACTERISTICS
All specifications at T = 25°C, AVDD = 5V, DVDD = IOVDD = 3V, f
CLK
BIAS
= 40MHz, External V
REF
= +3V, 2XMODE = low, V
CM
= 2.0V, and
A
R
= 37kΩ, unless otherwise noted.
SPECTRAL RESPONSE
SPECTRAL RESPONSE
0
20
40
60
80
0
−
fIN = 100kHz, 6dBFS
SNR = 84dB
−
−
−
−
−
−
−
−
20
40
60
80
−
THD = 99dB
SFDR = 101dB
−
−
−
−
−
−
−
−
100
120
140
160
100
120
140
160
0
0
0
0.5
1.0
1.5
2.0
2.5
0
0
0
0.5
1.0
1.5
2.0
2.5
Frequency (MHz)
Frequency (MHz)
SPECTRAL RESPONSE
SPECTRAL RESPONSE
0
0
−
fIN = 500kHz, 2dBFS
SNR = 86dB
THD = 97dB
SFDR = 97dB
−
−
−
−
−
−
−
−
20
40
60
80
20
40
60
80
−
−
−
−
−
−
−
−
−
100
120
140
160
100
120
140
160
0.5
1.0
1.5
2.0
2.5
0.5
1.0
1.5
2.0
2.5
Frequency (MHz)
Frequency (MHz)
SPECTRAL RESPONSE
SPECTRAL RESPONSE
0
0
−
−
−
−
−
−
−
−
20
40
60
80
20
40
60
80
−
−
−
−
−
−
−
−
100
120
140
160
100
120
140
160
0.5
1.0
1.5
2.0
2.5
0.5
1.0
1.5
2.0
2.5
Frequency (MHz)
Frequency (MHz)
12
ꢋ ꢑꢉ ꢀꢁ ꢗꢇ
ꢋ ꢑꢉ ꢀꢁ ꢗꢁ
www.ti.com
SBAS274E − MARCH 2003 − REVISED JUNE 2004
TYPICAL CHARACTERISTICS (continued)
All specifications at T = 25°C, AVDD = 5V, DVDD = IOVDD = 3V, f
CLK
BIAS
= 40MHz, External V
REF
= +3V, 2XMODE = low, V = 2.0V, and
CM
A
R
= 37kΩ, unless otherwise noted.
INTERMODULATION RESPONSE
NOISE HISTOGRAM
0
18k
16k
14k
12k
10k
8k
fIN1 = 1.99MHz
fIN2 = 2.00MHz
VIN = 0V
−
−
−
−
20
40
60
80
−
IMD = 94dB
−
−
−
−
100
120
140
160
6k
4k
2k
0
−
−
−
−
−
1.95 1.96 1.97 1.98 1.99 2.00 2.01 2.02 2.03 2.04 2.05
5
4
3
2
1
0
1
2
3
4
5
Output Code (LSB)
Frequency (MHz)
SIGNAL−TO−NOISE RATIO,
TOTAL HARMONIC DISTORTION,
AND SPURIOUS−FREE DYNAMIC RANGE
vs INPUT SIGNALAMPLITUDE
SIGNAL−TO−NOISE RATIO
vs INPUT FREQUENCY
110
100
90
80
70
60
50
40
30
20
10
90
−
= 2dBFS
VIN
85
80
75
70
65
60
−
= 6dBFS
VIN
SFDR
−
= 20dBFS
VIN
THD
SNR
fIN = 100kHz
−
−
−
−
−
−
−
10
70
60
50
40
30
20
0
0.001
0.01
0.1
1
10
Input Signal Amplitude, VIN (dB)
Input Frequency, fIN (MHz)
TOTAL HARMONIC DISTORTION
vs INPUT FREQUENCY
SPURIOUS−FREE DYNAMIC RANGE
vs INPUT FREQUENCY
−
−
−
85
90
95
110
108
106
104
102
100
98
−
VIN
=
6dBFS
−
= 20dBFS
VIN
−
= 2dBFS
VIN
−
2dBFS
VIN
=
−
100
−
105
−
110
−
= 20dBFS
VIN
96
−
VIN
=
6dBFS
0.1
94
92
90
0.001
0.01
1
10
0.001
0.01
0.1
Input Frequency, fIN (MHz)
1
10
Input Frequency, fIN (MHz)
13
ꢋꢑ ꢉꢀ ꢁ ꢗ ꢇ
ꢋꢑ ꢉꢀ ꢁ ꢗ ꢁ
www.ti.com
SBAS274E − MARCH 2003 − REVISED JUNE 2004
TYPICAL CHARACTERISTICS (continued)
All specifications at T = 25°C, AVDD = 5V, DVDD = IOVDD = 3V, f
CLK
BIAS
= 40MHz, External V
REF
= +3V, 2XMODE = low, V
CM
= 2.0V, and
A
R
= 37kΩ, unless otherwise noted.
SIGNAL−TO−NOISE RATIO
vs INPUT COMMON−MODE VOLTAGE
TOTAL HARMONIC DISTORTION
vs INPUT COMMON−MODE VOLTAGE
−
−
−
−
89
87
85
83
81
79
77
75
65
75
85
95
−
VIN
=
=
2dBFS
6dBFS
−
= 2dBFS
VIN
VIN
−
VIN
−
=
6dBFS
−
105
−
115
125
135
−
−
fIN = 100kHz
1.7
fIN = 100kHz
1.7
1.5
1.9
2.1
2.3
2.5
1.5
1.9
2.1
2.3
2.5
Input Common−Mode Voltage, VCM (V)
Input Common−Mode Voltage, VCM (V)
SPURIOUS−FREE DYNAMIC RANGE
vs INPUT COMMON−MODE VOLTAGE
SIGNAL−TO−NOISE RATIO
vs CLK FREQUENCY
105
100
95
90
85
80
75
70
65
60
55
50
45
40
Ω
BIAS = 30k
R
−
= 6dBFS
VIN
−
= 2dBFS
VIN
Ω
R
BIAS = 37k
BIAS = 45k
RBIAS = 50k
90
Ω
R
85
Ω
80
Ω
BIAS = 60k
R
75
fIN = 100kHz, 6dBFS
70
fIN = 100kHz
1.7
65
1.5
1.9
2.1
2.3
2.5
10
20
30
40
50
60
Input Common−Mode Voltage, VCM (V)
CLK Frequency, fCLK (MHz)
TOTAL HARMONIC DISTORTION
vs CLK FREQUENCY
SPURIOUS−FREE DYNAMIC RANGE
vs CLK FREQUENCY
−
−
−
−
−
−
−
65
110
−
fIN = 100kHz, 6dBFS
−
fIN = 100kHz, 6dBFS
70
75
80
85
90
95
105
100
95
Ω
RBIAS = 60k
Ω
R
BIAS = 30k
Ω
BIAS = 50k
R
Ω
RBIAS = 37k
Ω
RBIAS = 45k
Ω
R
BIAS = 45k
RBIAS = 50k
RBIAS = 60k
90
Ω
85
Ω
Ω
RBIAS = 37k
80
−
−
100
105
Ω
RBIAS = 30k
75
10
20
30
40
50
60
10
20
30
40
50
60
CLK Frequency, fCLK (MHz)
CLK Frequency, fCLK (MHz)
14
ꢋ ꢑꢉ ꢀꢁ ꢗꢇ
ꢋ ꢑꢉ ꢀꢁ ꢗꢁ
www.ti.com
SBAS274E − MARCH 2003 − REVISED JUNE 2004
TYPICAL CHARACTERISTICS (continued)
All specifications at T = 25°C, AVDD = 5V, DVDD = IOVDD = 3V, f
CLK
BIAS
= 40MHz, External V
REF
= +3V, 2XMODE = low, V
CM
= 2.0V, and
A
R
= 37kΩ, unless otherwise noted.
SIGNAL−TO−NOISE RATIO
vs TEMPERATURE
TOTAL HARMONIC DISTORTION
vs TEMPERATURE
−
−
−
100
90
80
70
60
50
85
90
95
−
−
VIN
VIN
=
=
2dBFS
6dBFS
−
−
−
VIN
VIN
VIN
=
=
=
20dBFS
2dBFS
6dBFS
−
100
−
105
−
110
−
VIN
=
20dBFS
fIN = 100kHz
fIN = 100kHz
−
−
15
40
10
35
60
85
−
−
15
40
10
35
60
85
_
_
Temperature ( C)
Temperature ( C)
SPURIOUS−FREE DYNAMIC RANGE
vs TEMPERATURE
POWER−SUPPLY CURRENT
vs TEMPERATURE
110
105
100
95
130
120
110
100
90
IAVDD (REFEN = low)
−
= 6dBFS
VIN
IAVDD (REFEN = high)
−
= 20dBFS
VIN
80
70
60
−
= 2dBFS
VIN
IDVDD + IIOVDD
90
50
40
fIN = 100kHz
Ω
DVDD = IOVDD = 3V
60 85
RBIAS = 37k , fCLK = 40MHz
85
30
−
−
−
−
15
40
15
10
35
60
85
40
10
35
_
_
Temperature ( C)
Temperature ( C)
ANALOG SUPPLY CURRENT vs RBIAS
SUPPLY CURRENT vs CLK FREQUENCY
140
130
120
110
100
90
100
80
60
40
20
0
Ω
IAVDD (RBIAS = 37k )
Ω
AVDD (RBIAS = 60k )
I
REFEN = low
REFEN = high
80
IDVDD + IIOVDD
70
60
AVDD = 5V, DVDD = IOVDD = 3V, REFEN = High
50
30
35
40
45
50
55
60
10
20
30
40
50
Ω
RBIAS (k )
CLK Frequency, fCLK (MHz)
15
ꢋꢑ ꢉꢀ ꢁ ꢗ ꢇ
ꢋꢑ ꢉꢀ ꢁ ꢗ ꢁ
www.ti.com
SBAS274E − MARCH 2003 − REVISED JUNE 2004
TYPICAL CHARACTERISTICS (continued)
All specifications at T = 25°C, AVDD = 5V, DVDD = IOVDD = 3V, f
CLK
BIAS
= 40MHz, External V
REF
= +3V, 2XMODE = low, V
CM
= 2.0V, and
A
R
= 37kΩ, unless otherwise noted.
INTEGRAL NONLINEARITY
DIFFERENTIAL NONLINEARITY
0.5
1.0
0.8
0.6
0.4
0.2
0
−
fIN = 100Hz, 1.5dBFS
−
fIN = 100Hz, 1.5dBFS
0.4
0.3
0.2
0.1
0
−
0.1
0.2
0.3
0.4
0.5
−
0.2
0.4
0.6
0.8
1.0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
25k 20k 15k 10k 5k
0
5k 10k 15k 20k 25k
25k 20k 15k 10k 5k
0
5k 10k 15k 20k 25k
Output Code (LSB)
Output Code (LSB)
16
ꢋ ꢑꢉ ꢀꢁ ꢗꢇ
ꢋ ꢑꢉ ꢀꢁ ꢗꢁ
www.ti.com
SBAS274E − MARCH 2003 − REVISED JUNE 2004
output code of 7FFFh. Likewise, the most negative
measurable differential input is –1.545VREF, which produces
the most negative digital output code of 8000h.
OVERVIEW
The ADS1605 and ADS1606 are high-performance
delta-sigma ADCs with a default oversampling ratio of 8. The
modulator uses an inherently stable 2-1-1 pipelined
delta-sigma modulator architecture incorporating proprietary
circuitry that allows for very linear high-speed operation. The
modulator samples the input signal at 40MSPS (when
fCLK = 40MHz). A low-ripple linear phase digital filter
decimates the modulator output to provide data output word
rates of 5MSPS with a signal passband out to 2.45MHz. The
2X mode, enabled by a digital I/O pin, doubles the data rate
to 10MSPS by reducing the oversampling ratio to 4. See the
2X Mode section for more details.
The ADS1605/6 supports a very wide range of input signals.
For VREF = 3V, the full scale input voltages are 4.6V. Having
such a wide input range makes out-of-range signals unlikely.
However, should an out-of-range signal occur, the digital
output OTR will go high.
To achieve the highest analog performance, it is
recommended that the inputs be limited to 1.227VREF
(−2dBFS). For VREF = 3V, the corresponding recommended
input range is 3.68V.
The analog inputs must be driven with a differential signal to
achieve optimum performance. The recommended
Conceptually, the modulator and digital filter measure the dif-
ferential input signal, VIN = (AINP – AINN), against the scaled
differential reference, VREF = (VREFP – VREFN), as shown
in Figure 7. The voltage reference can either be generated
internally or supplied externally. An 16-bit parallel data bus,
designed for direct connection to DSPs, outputs the data. A
separate power supply for the I/O allows flexibility for interfac-
ing to different logic families. Out-of-range conditions are indi-
cated with a dedicated digital output pin. Analog power dis-
sipation is controlled using an external resistor. This allows
reduced dissipation when operating at slower speeds. When
not in use, power consumption can be dramatically reduced
using the PD pin.
common-mode
voltage
of
the
input
signal,
AINP ) AINN
VCM
+
, is 2.0V. For signals larger than
2
−2dBFS, the input common-mode voltage needs to be raised
in order to meet the absolute input voltage specifications. The
typical characteristics show how performance varies with
input common-mode voltage.
In addition to the differential and common-mode input
voltages, the absolute input voltage is also important. This is
the voltage on either input (AINP or AINN) with respect to
AGND. The range for this voltage is:
* 0.1V t (AINN or AINP) t 4.6V
The ADS1606 incorporates an adjustable FIFO buffer for the
output data. The level of the FIFO is set by the
FIFO_LEV[2:0] pins. Other than the FIFO buffer, the
ADS1605 and ADS1606 are identical, and are referred to to-
gether in this data sheet as the ADS1605/6.
If either input is taken below –0.1V, ESD protection diodes on
the inputs will turn on. Exceeding 4.6V on either input will
result in degradation in the linearity performance. ESD
protection diodes will also turn on if the inputs are taken
above AVDD (+5V).
ANALOG INPUTS (AINP, AINN)
For signals below –2dBFS, the recommended absolute input
voltage is:
The ADS1605/6 measures the differential signal,
VIN = (AINP − AINN), against the differential reference,
VREF = (VREFP – VREFN). The reference is scaled
internally so that the full-scale differential input voltage is
1.545VREF. That is, the most positive measurable differential
input is 1.545VREF, which produces the most positive digital
* 0.1V t (AINN or AINP) t 4.2V
Keeping the inputs within this range provides for optimum
performance.
VREFP VREFN
IOVDD
Σ
VREF
1.545
OTR
1.545VREF
Digital
ADS1606 Only
Parallel
Interface
DOUT[15:0]
FIFO
VIN
AINP
AINN
Σ∆
Modulator
Filter
Σ
FIFO_LEV[2:0]
2XMODE
Figure 7. Conceptual Block Diagram
17
ꢋꢑ ꢉꢀ ꢁ ꢗ ꢇ
ꢋꢑ ꢉꢀ ꢁ ꢗ ꢁ
www.ti.com
SBAS274E − MARCH 2003 − REVISED JUNE 2004
external capacitors, between the inputs and from each
input to AGND, improve linearity and should be placed as
close to the pins as possible. Place the drivers close to the
inputs and use good capacitor bypass techniques on their
supplies; usually a smaller high-quality ceramic capacitor
in parallel with a larger capacitor. Keep the resistances
used in the driver circuits low—thermal noise in the driver
circuits degrades the overall noise performance. When the
signal can be ac-coupled to the ADS1605/6 inputs, a
simple RC filter can set the input common mode voltage.
The ADS1605/6 is a high-speed, high−performance ADC.
Special care must be taken when selecting the test
equipment and setup used with this device. Pay particular
attention to the signal sources to ensure they do not limit
performance when measuring the ADS1605/6.
INPUT CIRCUITRY
The ADS1605/6 uses switched-capacitor circuitry to
measure the input voltage. Internal capacitors are charged
by the inputs and then discharged internally with this cycle
repeating at the frequency of CLK. Figure 8 shows a
conceptual diagram of these circuits. Switches S2 represent
the net effect of the modulator circuitry in discharging the
sampling capacitors, the actual implementation is different.
The timing for switches S1 and S2 is shown in Figure 9.
ADS1605
ADS1606
S1
AINP
AINN
S2
10pF
8pF
Ω
392
VMID
40pF
Ω
Ω
392
392
S1
V
IN
−
2
µ
0.01
1k
F
S2
Ω
49.9
10pF
8pF
AINP
OPA2822
(2)
(1)
V
CM
100pF
Ω
Ω
µ
F
VMID
392
1
AGND
(2)
Ω
392
ADS1605
ADS1606
(1)
(3)
V
100pF
CM
(2)
40pF
Ω
392
V
Ω
1k
IN
Figure 8. Conceptual Diagram of Internal
Circuitry Connected to the Analog Inputs
2
µ
0.01
F
Ω
49.9
AINN
OPA2822
Ω
392
(2)
(1)
CM
V
100pF
Ω
µ
F
392
1
tSAMPLE = 1/fCLK
AGND
On
Off
S1
S2
(1) Recommended VCM = 2.0V.
(2) Optional ac−coupling circuit provides common−mode input voltage.
≤
(3) Increase to 390pF when fIN 100kHz for improved SNR and THD.
On
Off
Figure 10. Recommended Driver Circuit Using the
OPA2822
Figure 9. Timing for the Switches in Figure 2
DRIVING THE INPUTS
22pF
Ω
Ω
24.9
24.9
AINP
Ω
392
100pF
100pF
Ω
Ω
392
392
The external circuits driving the ADS1605/6 inputs must be
able to handle the load presented by the switching capacitors
within the ADS1605/6. The input switches S1 in Figure 5 are
−
VIN
ADS1605
ADS1606
VCM
THS4503
+VIN
closed approximately one half of the sampling period, tsample
,
Ω
392
allowing only ≈12ns for the internal capacitors to be charged
by the inputs, when fCLK = 40MHz.
AINN
100pF
Figure 10 and Figure 11 show the recommended circuits
when using single-ended or differential op amps,
respectively. The analog inputs must be driven
differentially to achieve optimum performance. The
22pF
Figure 11. Recommended Driver Circuits Using
the THS4503 Differential Amplifier
18
ꢋ ꢑꢉ ꢀꢁ ꢗꢇ
ꢋ ꢑꢉ ꢀꢁ ꢗꢁ
www.ti.com
SBAS274E − MARCH 2003 − REVISED JUNE 2004
Characteristics table. Typically VREFP = 4V, VMID = 2.5V
and VREFN = 1V. The external circuitry must be capable
of providing both a dc and a transient current. Figure 13
shows a simplified diagram of the internal circuitry of the
reference when the internal reference is disabled. As with
the input circuitry, switches S1 and S2 open and close as
shown in Figure 9.
REFERENCE INPUTS (VREFN, VREFP, VMID)
The ADS1605/6 can operate from an internal or external
voltage reference. In either case, the reference voltage VREF
is set by the differential voltage between VREFN and
VREFP: VREF = (VREFP – VREFN). VREFP and VREFN
each use two pins, which should be shorted together. VMID
equals approximately 2.5V and is used by the modulator.
VCAP connects to an internal node and must also be
bypassed with an external capacitor. For the best analog
performance, it is recommended that an external reference
voltage (VREF) of 3.0V be used.
ADS1605
ADS1606
S1
VREFP
VREFP
S2
INTERNAL REFERENCE (REFEN = LOW)
Ω
300
50pF
To use the internal reference, set the REFEN pin low. This
activates the internal circuitry that generates the reference
voltages. The internal reference voltages are applied to
the pins. Good bypassing of the reference pins is critical
to achieve optimum performance and is done by placing
the bypass capacitors as close to the pins as possible.
Figure 12 shows the recommended bypass capacitor
values. Use high quality ceramic capacitors for the smaller
values. Avoid loading the internal reference with external
circuitry. If the ADS1605/6 internal reference is to be used
by other circuitry, buffer the reference voltages to prevent
directly loading the reference pins.
VREFN
VREFN
S1
Figure 13. Conceptual Internal Circuitry for the
Reference When REFEN = High
Figure 14 shows the recommended circuitry for driving
these reference inputs. Keep the resistances used in the
buffer circuits low to prevent excessive thermal noise from
degrading performance. Layout of these circuits is critical,
make sure to follow good high-speed layout practices.
Place the buffers and especially the bypass capacitors as
close to the pins as possible. VCAP is unaffected by the
setting on REFEN and must be bypassed when using the
internal or an external reference.
ADS1605
ADS1606
VREFP
µ
µ
0.1 F
VREFP
10 F
Ω
392
µ
0.001
F
µ
22 F
ADS1605
ADS1606
VMID
µ
22 F
µ
0.1 F
VREFP
VREFP
OPA2822
µ
µ
0.1 F
10 F
µ
10
F
4V
0.1µF
Ω
392
µ
22 F
µ
0.1
F
VREFN
VREFN
µ
0.001
F
µ
22 F
µ
22
F
µ
µ
0.1 F
10 F
VMID
OPA2822
µ
10
F
2.5V
VCAP
µ
0.1
F
µ
0.1 F
Ω
392
µ
0.001
F
AGND
22µF
VREFN
VREFN
OPA2822
Figure 12. Reference Bypassing When Using the
Internal Reference
1V
µ
µ
µ
10
F
0.1
0.1
F
F
EXTERNAL REFERENCE (REFEN = HIGH)
VCAP
To use an external reference, set the REFEN pin high. This
deactivates the internal generators for VREFP, VREFN
and VMID, and saves approximately 25mA of current on
the analog supply (AVDD). The voltages applied to these
pins must be within the values specified in the Electrical
AGND
Figure 14. Recommended Buffer Circuit When
Using an External Reference
19
ꢋꢑ ꢉꢀ ꢁ ꢗ ꢇ
ꢋꢑ ꢉꢀ ꢁ ꢗ ꢁ
www.ti.com
SBAS274E − MARCH 2003 − REVISED JUNE 2004
Likewise, when the input is negative out-of-range by going
below the negative full-scale value of –1.545VREF, the output
clips to 8000h and the OTR output goes high. The OTR
remains high while the input signal is out-of-range.
CLOCK INPUT (CLK)
The ADS1605/6 requires an external clock signal to be
applied to the CLK input pin. The sampling of the
modulator is controlled by this clock signal. As with any
high-speed data converter, a high quality clock is essential
for optimum performance. Crystal clock oscillators are the
recommended CLK source; other sources, such as
frequency synthesizers are usually not adequate. Make
sure to avoid excess ringing on the CLK input; keeping the
trace as short as possible will help.
Table 2. Output Code Versus Input Signal
INPUT SIGNAL
(INP – INN)
IDEAL OUTPUT
(1)
CODE
OTR
≥+1.545V
(> 0dB)
7FFF
1
0
0
REF
H
H
1.545V
(0dB)
7FFF
0001
REF
Measuring high frequency, large amplitude signals
requires tight control of clock jitter. The uncertainty during
sampling of the input from clock jitter limits the maximum
achievable SNR. This effect becomes more pronounced
with higher frequency and larger magnitude inputs.
Fortunately, the ADS1605/6 oversampling topology
reduces clock jitter sensitivity over that of Nyquist rate
converters like pipeline and successive approximation
+1.545VREF
H
2
15 * 1
0
0000
0
0
H
FFFF
−1.545VREF
H
2
15 * 1
8000
0
1
215
H
ǒ
Ǔ
−1.545VREF
Ǹ
215 * 1
converters by a factor of 8.
8000
215
215 * 1
H
In order to not limit the ADS1605/6 SNR performance,
keep the jitter on the clock source below the values shown
in Table 1. When measuring lower frequency and lower
amplitude inputs, more CLK jitter can be tolerated. In
determining the allowable clock source jitter, select the
worst-case input (highest frequency, largest amplitude)
that will be seen in the application.
ǒ
Ǔ
v −1.545VREF
(1)
Excludes effects of noise, INL, offset and gain errors.
OUT-OF-RANGE INDICATION (OTR)
If the output code on DOUT[15:0] exceeds the positive or
negative full-scale, the out-of-range digital output OTR will
go high on the falling edge of DRDY. When the output code
returns within the full-scale range, OTR returns low on the
falling edge of DRDY.
Table 1. Maximum Allowable Clock Source Jitter
for Different Input Signal Frequencies and
Amplitude
MAXIMUM
ALLOWABLE
CLOCK SOURCE
JITTER
INPUT SIGNAL
DATA RETRIEVAL
Data retrieval is controlled through a simple parallel
interface. The falling edge of the DRDY output indicates
new data is available. To activate the output bus, both CS
and RD must be low, as shown in Table 3. Make sure the
DOUT bus does not drive heavy loads (> 20pF), as this will
degrade performance. Use an external buffer when driving
an edge connector or cables.
MAXIMUM
MAXIMUM
FREQUENCY
AMPLITUDE
2MHz
2MHz
−2dB
−20dB
−2dB
1.9ps
14ps
3.8ps
28ps
7.6ps
57ps
38ps
285ps
1MHz
1MHz
−20dB
−2dB
500kHz
500kHz
100kHz
100kHz
Table 3. Truth Table for CS and RD
−20dB
−2dB
CS
0
RD
0
DOUT[15:0]
Active
−20dB
0
1
High impedance
High impedance
High impedance
1
0
DATA FORMAT
1
1
The 16-bit output data is in binary two’s complement format
as shown in Table 2. When the input is positive out-of-range,
exceeding the positive full-scale value of 1.545VREF, the
output clips to all 7FFFh and the OTR output goes high.
20
ꢋ ꢑꢉ ꢀꢁ ꢗꢇ
ꢋ ꢑꢉ ꢀꢁ ꢗꢁ
www.ti.com
SBAS274E − MARCH 2003 − REVISED JUNE 2004
RESETTING THE ADS1605
RESETTING THE ADS1606
The ADS1605 and ADS1606 with FIFO disabled are
asynchronously reset when the RESET pin is taken low.
During reset, all of the digital circuits are cleared,
DOUT[15:0] are forced low, and DRDY forced high. It is
recommended that the RESET pin be released on the
falling edge of CLK. Afterwards, DRDY goes low on the
second rising edge of CLK. Allow 47 DRDY cycles for the
digital filter to settle before retrieving data. See Figure 3 for
the timing specifications.
The ADS1606 with the FIFO enabled requires a different
reset sequence than the ADS1605, as shown in Figure 16.
Ignore any DRDY toggles that occur while RESET is low.
Release RESET on the rising edge of CLK, then
afterwards toggle RD to complete the reset sequence.
CLK
Reset can be used to synchronize multiple ADS1605s. All
devices to be synchronized must use a common CLK
input. With the CLK inputs running, pulse RESET on the
falling edge of CLK, as shown in Figure 15. Afterwards, the
converters will be converting synchronously with the
RESET
Ignore
t26
DRDY
DRDY
outputs
updating
simultaneously.
After
synchronization, allow 47 DRDY cycles (t12) for output
data to fully settle.
R
D
Toggle RD to complete reset sequence
ADS16051
Figure 16. Resetting the ADS1606 with the FIFO
Enabled
RESET
Clock
RESET
CLK
DRDY
DRDY1
DOUT[15:0]
DOUT[15:0]1
After resetting, the settling time for the ADS1606 is 47 CLK
cycles, regardless of the FIFO level. Therefore, for higher
FIFO levels, it takes fewer DRDY cycles to settle because
the DRDY period is longer. Table 4 shows the number of
DRDY cycles required to settle for each FIFO level.
ADS16052
RESET
CLK
DRDY
DRDY2
DOUT[15:0]
DOUT[15:0]2
Table 4. ADS1606 Reset Settling
CLK
FILTER SETTLING TIME AFTER RESET
(t in units of DRDY cycles )
26
FIFO LEVEL
2
4
24
12
8
RESET
t12
DRDY1
6
8
6
Settled
Data
DOUT[15:0]1
10
12
14
5
4
4
DRDY2
Settled
Data
DOUT[15:0]2
Synchronized
Figure 15. Synchronizing Multiple Converters
21
ꢋꢑ ꢉꢀ ꢁ ꢗ ꢇ
ꢋꢑ ꢉꢀ ꢁ ꢗ ꢁ
www.ti.com
SBAS274E − MARCH 2003 − REVISED JUNE 2004
SETTLING TIME
IMPULSE RESPONSE
The settling time is an important consideration when
measuring signals with large steps or when using a
multiplexer in front of the analog inputs. The ADS1605/6
digital filter requires time for an instantaneous change in
signal level to propagate to the output.
Figure 18 plots the normalized response for an input applied
at t = 0 with 2XMODE = low. The X-axis units of time are
DRDY cycles (for the ADS1605 or the ADS1606 with FIFO
disabled). As shown in Figure 18, the peak of the impulse
takes 26 DRDY cycles to propagate to the output. For fCLK
= 40MHz, a DRDY cycle is 0.2µs in duration and the
propagation time (or group delay) is 26 × 0.2µs = 5.2µs.
Be sure to allow the filter time to settle after applying a large
step in the input signal, switching the channel on a
multiplexer placed in front of the inputs, resetting the
ADS1605/6, or exiting the power-down mode,
1.0
0.8
0.6
0.4
0.2
0
Figure 17 shows the settling error as a function of time for a
full-scale signal step applied at t = 0 with 2XMODE = low. This
figure uses DRDY cycles (for the ADS1605 or the ADS1606
with FIFO disabled) for the time scale (X-axis). After 47 DRDY
cycles, the settling error drops below 0.001%. For
f
= 40MHz, this corresponds to a settling time of 9.4µs.
CLK
101
100
−
−
0.2
0.4
0
5
10
15
20
25
30
35
40
45 50
10−1
10−2
10−3
10−4
Time (DRDY cycles)
Figure 18. Impulse Response
25
30
35
40
45
50
Settling Time (DRDY cycles)
Figure 17. Settling Time
22
ꢋ ꢑꢉ ꢀꢁ ꢗꢇ
ꢋ ꢑꢉ ꢀꢁ ꢗꢁ
www.ti.com
SBAS274E − MARCH 2003 − REVISED JUNE 2004
FREQUENCY RESPONSE
0.0025
0.0020
0.0015
0.0010
0.0005
0
The linear phase FIR digital filter sets the overall frequency
response. The decimation rate is set to 8 (2XMODE = low)
for all the figures shown in this section. Figure 19 shows
the frequency response from dc to 20MHz for
fCLK = 40MHz
f
CLK = 40MHz. The frequency response of the ADS1605/6
filter scales directly with CLK frequency. For example, if
the CLK frequency is decreased by half (to 20MHz), the
values on the X-axis in Figure 19 would need to be scaled
by half, with the span becoming dc to 10MHz.
−
−
−
−
0.0005
0.0010
0.0015
0.0020
Figure 20 shows the passband ripple from dc to 2.2MHz
(fCLK = 40MHz). Figure 21 shows a closer view of the
passband transition by plotting the response from 2.0MHz
to 2.5MHz (fCLK = 40MHz).
0
0.5
1.0
1.5
2.0
2.5
Frequency (MHz)
The overall frequency response repeats at multiples of the
CLK frequency. To help illustrate this, Figure 22 shows the
response out to 120MHz (fCLK = 40MHz). Notice how the
passband response repeats at 40MHz, 80MHz and
120MHz; it is important to consider this when there is
high-frequency noise present with the signal. The
modulator bandwidth extends to 100MHz. High-frequency
noise around 40MHz and 80MHz will not be attenuated by
either the modulator or the digital filter. This noise will alias
back in-band and reduce the overall SNR performance
unless it is filtered out prior to the ADS1605/6. To prevent
this, place an anti-alias filter in front of the ADS1605/6 that
rolls off before 37MHz.
Figure 20. Passband Ripple
1
0
−
−
−
−
−
−
−
1
2
3
4
5
6
7
fCLK = 40MHz
20
0
2.0 2.05 2.1 2.15 2.2 2.25 2.3 2.35 2.4 2.45 2.5
Frequency (MHz)
−
−
−
−
20
40
60
80
Figure 21. Passband Transition
−
−
100
120
20
0
fCLK = 40MHz
0
2
4
6
8
10
12 14
16 18
20
Frequency (MHz)
−
−
−
−
20
40
60
80
Figure 19. Frequency Response.
−
100
0
20
40
60
80
100
120
Frequency (MHz)
Figure 22. Frequency Response Out to 120MHz
23
ꢋꢑ ꢉꢀ ꢁ ꢗ ꢇ
ꢋꢑ ꢉꢀ ꢁ ꢗ ꢁ
www.ti.com
SBAS274E − MARCH 2003 − REVISED JUNE 2004
take RD low. The first, or oldest, data will be presented on
the data output pins. After reading this data, advance to the
next data reading by toggling RD. On the next falling edge
of RD, the second data is present on the data output pins.
Continue this way until all the data have been read from the
FIFO, making sure to take RD high when complete.
Afterwards, wait until DRDY toggles and repeat the
readback cycle. Figure 23 shows an example readback
when FIFO_LEV[2:0] = 010 (level = 4).
FIFO (ADS1606 ONLY)
The ADS1606 includes an adjustable level first-in first-out
buffer (FIFO) for the output data. The FIFO allows data to
be temporarily stored within the ADS1606 to provide more
flexibility for the host controller when retrieving data. Pins
FIFO_LEV[2:0] set the level or depth of the FIFO. Note that
these pins must be left unconnected on the ADS1605. The
FIFO is enabled by setting at least one of the FIFO_LEV
inputs high. Table 5 shows the corresponding FIFO level
and DRDY period for the different combinations of
FIFO_LEV[2:0] settings. For the best performance when
using the FIFO, it is recommended to:
Readback considerations
The exact number of data readings set by the FIFO level
must be read back each time DRDY toggles. The one
exception is that readback can be skipped entirely. In this
case, the DRDY period increases to 128 CLK period.
Figure 24 shows an example when readback is skipped
with the FIFO level = 4. Do not read back more or less
readings from the FIFO than set by the level. This
interrupts the FIFO operation and can cause DRDY to stay
low indefinitely. If this occurs, the RESET pin must be
toggled followed by a RD pulse. This resets the ADS1606
FIFO and also the digital filter, which then must settle
afterwards before valid data is ready. See the section,
Resetting the ADS1606, for more details.
1. Set IOVDD = 3V.
2. Synchronize data retrieval with CLK.
3. Minimize loading on outputs DOUT[15:0].
4. Ensure rise and fall times on CLK and RD are 1ns
or longer.
Table 5. FIFO Buffer Level Settings for the
ADS1606
FIFO_LEV[2:0]
FIFO BUFFER LEVEL
DRDY PERIOD
8/f
000
0: disabled,
CLK
Setting the FIFO Level
operates like ADS1605
The FIFO level setting is usually a static selection that is
set when power is first applied to the ADS1606. If the FIFO
level needs to be changed after powerup, there are two
options. One is to asynchronously set the new value on pin
FIFO_LEV[2:0] then toggle RESET. Remember that the
ADS1606 will need to settle after resetting. See the
section, Resetting the ADS1606, for more details. The
other option avoids requiring a reset, but needs
synchronization of the FIFO level change with the
readback. The FIFO_LEV[2:0] pins have to be changed
after RD goes high after reading the first data, but before
RD goes low to read the last data from the FIFO. The new
FIFO level becomes active immediately and the DRDY
period adjusts accordingly. When decreasing the FIFO
level this way, make sure to give adequate time for
readback of the data before setting the new, smaller level.
Figure 25 shows an example of a synchronized FIFO level
change from 4 to 8.
001
010
011
100
101
110
111
2
4
16/f
32/f
48/f
64/f
80/f
96/f
CLK
CLK
CLK
CLK
CLK
CLK
6
8
10
12
14
112/f
CLK
FIFO Operation
The ADS1606 FIFO collects the number of output
readings set by the level corresponding to the
FIFO_LEV[2:0] setting. When the specified level is
reached, DRDY is pulsed high, indicating the data in the
FIFO is ready to be read. The DRDY period is a function
of the FIFO level, as shown in Table 5. To read the data,
make sure CS is low (it is acceptable to tie it low) and then
DRDY
CS(1)
RD
(2)
Data1
Data2
Data3
Data4
DOUT[15:0]
(1) CS can be tied low.
(2) Data1 is the oldest data and Data4 is the most recent.
Figure 23. Example of FIFO Readback when FIFO Level = 4
24
ꢋ ꢑꢉ ꢀꢁ ꢗꢇ
ꢋ ꢑꢉ ꢀꢁ ꢗꢁ
www.ti.com
SBAS274E − MARCH 2003 − REVISED JUNE 2004
32/fCLK
128/fCLK
DRDY
RD
Figure 24. Example of Skipping Readback when FIFO Level = 4
32/fCLK
64/fCLK
DRDY
RD
FIFO_LEV[2:0]
010 (Level = 4)
100 (Level = 8)
Change FIFO_LEV[2:0] here
Figure 25. Example of Synchronized Change of FIFO Level from 4 to 8
ANALOG POWER DISSIPATION
Table 6. Recommended R
Resistor Values for
BIAS
Different CLK Frequencies
An external resistor connected between the RBIAS pin and
the analog ground sets the analog current level, as shown in
Figure 26. The current is inversely proportional to the resistor
value. Table 6 shows the recommended values of RBIAS for
different CLK frequencies. Notice that the analog current can
be reduced when using a slower frequency CLK input
because the modulator has more time to settle. Avoid adding
any capacitance in parallel to RBIAS , since this will interfere
with the internal circuitry used to set the biasing.
TYPICAL POWER
DISSIPATION WITH REFEN
HIGH
DATA
RATE
f
R
BIAS
CLK
16MHz
24MHz
32MHz
40MHz
2MHz
3MHz
4MHz
5MHz
60kΩ
50kΩ
45kΩ
37kΩ
315mW
400mW
475mW
570mW
POWER DOWN (PD)
ADS1605
ADS1606
When not in use, the ADS1605/6 can be powered down by
taking the PD pin low. All circuitry will be shutdown,
including the voltage reference. To minimize the digital
current during power down, stop the clock signal supplied
to the CLK input. There is an internal pull-up resistor of
170kΩ on the PD pin, but it is recommended that this pin
be connected to IOVDD if not used. If using the ADS1606
with the FIFO enabled, issue a reset after exiting
power-down mode. Make sure to allow time for the
reference to start up after exiting power-down mode. The
internal reference typically requires 15ms. After the
reference has stabilized, allow at least 100 DRDY cycles
for the modulator and digital filter to settle before retrieving
data.
RBIAS
RBIAS
AGND
Figure 26. External Resistor Used to Set Analog
Power Dissipation
25
ꢋꢑ ꢉꢀ ꢁ ꢗ ꢇ
ꢋꢑ ꢉꢀ ꢁ ꢗ ꢁ
www.ti.com
SBAS274E − MARCH 2003 − REVISED JUNE 2004
associated ground, as shown in Figure 27. Each main
supply bus should also be bypassed with a bank of
capacitors from 47µF to 0.1µF, as shown.
The IO and digital supplies (IOVDD and DVDD) can be
connected together when using the same voltage. In this
case, only one bank of 47µF to 0.1µF capacitors is needed
on the main supply bus, though each supply pin must still
be bypassed with a 1µF and 0.1µF ceramic capacitor.
POWER SUPPLIES
Three supplies are used on the ADS1605/6: analog
(AVDD), digital (DVDD) and digital I/O (IOVDD). Each
supply must be suitably bypassed to achieve the best
performance. It is recommended that a 1µF and 0.1µF
ceramic capacitor be placed as close to each supply pin as
possible. Connect each supply-pin bypass capacitor to the
DVDD
µ
µ
µ
1 F
µ
0.1 F
47 F
4.7 F
IOVDD
AVDD
µ
µ
1 F
47 F
µ
µ
0.1 F
4.7 F
CP
CP
CP
µ
µ
0.1 F
4.7 F
µ
47 F
µ
1 F
58
57
55
54
53
52
51
1
AGND
AVDD
CP
2
3
If using separate analog and
digital ground planes, connect
together on the ADS1605/6 PCB.
6
AGND
CP
ADS1605
ADS1606
AVDD
AGND
7
9
DGND
AGND
µ
µ
NOTE: CP = 1 F 0.1 F
CP
AVDD
AGND
10
11
CP
12
AVDD
18
19
25
CP
26
CP
Figure 27. Recommended Power-Supply Bypassing
26
ꢋ ꢑꢉ ꢀꢁ ꢗꢇ
ꢋ ꢑꢉ ꢀꢁ ꢗꢁ
www.ti.com
SBAS274E − MARCH 2003 − REVISED JUNE 2004
Two approaches can be used for the ground planes: either
a single common plane; or two separate planes, one for the
analog grounds and one for the digital grounds. When
using only one common plane, isolate the flow of current
on pin 57 from pin 1; use breaks on the ground plane to
accomplish this. Pin 57 carries the switching current from
the analog clocking for the modulator and can corrupt the
quiet analog ground on pin 1. When using two planes, it is
recommended that they be tied together right at the PCB.
Do not try to connect the ground planes together after
running separately through edge connectors or cables as
this reduces performance and increases the likelihood of
latchup.
2X MODE
The 2XMODE digital input determines the performance
(16-bit or 14-bit) by setting the oversampling ratio. When
2XMODE = low, the oversampling ratio = 8 for 16-bit
performance. When 2XMODE = high, the oversampling
ratio = 4 for 14-bit performance. Note that when 2XMODE
is high, all 16 bits of DOUT remain active. Decreasing the
oversampling ratio from 8 to 4 doubles the data rate in 2X
mode. For fCLK = 40MHz, the data rate then becomes
10MSPS. In addition, the group delay decreases to 0.9µs
and the settling time becomes 1.3µs or 13 DRDY cycles.
With the reduced oversampling in 2X mode, the noise
increases. Typical SNR performance degrades by 14dB.
THD remains approximately the same. There is an internal
pull-down resistor of 170kΩ on the 2XMODE, however, it
is recommended this pin be forced either high or low. For
more information on the performance of the 2X mode, see
application note Operating the ADS1605 and ADS1606 in
2X Mode: 10MSPS (SLAA180), available for download at
www.ti.com.
In general, keep the resistances used in the driving circuits
for the inputs and reference low to prevent excess thermal
noise from degrading overall performance. Avoid having
the ADS1605/6 digital outputs drive heavy loads. Buffers
on the outputs are recommended unless the ADS1605/6
is connected directly to a DSP or controller situated
nearby. Additionally, make sure the digital inputs are
driven with clean signals as ringing on the inputs can
introduce noise.
LAYOUT ISSUES
The ADS1605/6 uses TI PowerPAD technology. The
PowerPAD is physically connected to the substrate of the
silicon inside the package and must be soldered to the
analog ground plane on the PCB using the exposed metal
pad underneath the package for proper heat dissipation.
Please refer to application report SLMA002, located at
www.ti.com, for more details on the PowerPAD package.
The ADS1605/6 is a very high-speed, high-resolution data
converter. In order to achieve the maximum performance,
careful attention must be given to the printed circuit board
(PCB) layout. Use good high-speed techniques for all
circuitry. Critical capacitors should be placed close to pins
as possible. These include capacitors directly connected
to the analog and reference inputs and the power supplies.
Make sure to also properly bypass all circuitry driving the
inputs and references.
27
ꢋꢑ ꢉꢀ ꢁ ꢗ ꢇ
ꢋꢑ ꢉꢀ ꢁ ꢗ ꢁ
www.ti.com
SBAS274E − MARCH 2003 − REVISED JUNE 2004
INTERFACING THE ADS1606 TO THE
TMS320C6000
APPLICATIONS INFORMATION
INTERFACING THE ADS1605 TO THE
TMS320C6000
Figure 29 illustrates how to directly connect the ADS1606
to the TMS320C6000 DSP. The processor controls
reading using output ARE. The ADS1606 is permanently
selected by grounding the CS pin. The ADS1606 16-bit
data output bus is directly connected to the TMS320C6000
data bus. The data ready output from the ADS1606,
DRDY, drives interrupt EXT_INT7 on the TMS320C6000.
Figure 28 illustrates how to directly connect the ADS1605
to the TMS320C6000 DSP. The processor controls
reading using output ARE. The ADS1605 is selected using
the DSP control output, CE2. The ADS1605 16-bit data
output bus is directly connected to the TMS320C6000 data
bus. The data ready output from the ADS1605, DRDY,
drives interrupt EXT_INT7 on the TMS320C6000.
ADS1606
TMS320C6000
16
DOUT[15:0]
XD[15:0]
ADS1605
TMS320C6000
16
DOUT[15:0]
XD[15:0]
DRDY
CS
EXT_INT7
DRDY
CS
EXT_INT7
CE2
RD
ARE
RD
ARE
Figure 29. ADS1606—TMS320C6000 Interface
Connection
Figure 28. ADS1605—TMS320C6000 Interface
Connection
28
ꢋ ꢑꢉ ꢀꢁ ꢗꢇ
ꢋ ꢑꢉ ꢀꢁ ꢗꢁ
www.ti.com
SBAS274E − MARCH 2003 − REVISED JUNE 2004
INTERFACING THE ADS1605 TO THE
TMS320C5400
INTERFACING THE ADS1606 TO THE
TMS320C5400
Figure 30 illustrates how to connect the ADS1605 to the
TMS320C5400 DSP. The processor controls the reading
using the outputs R/W and IS. The I/O space select signal
(IS) is optional and is used to prevent the ADS1605 RD
input from being strobed when the DSP is accessing other
external memory spaces (address or data). This can help
reduce the possibility of digital noise coupling into the
ADS1605. When not using this signal, replace NAND gate
U1 with an inverter between R/W and RD. Two signals,
IOSTRB and A15, combine using NAND gate U2 to select
the ADS1605. If there are no additional devices connected
to the TMS320C5400 I/O space, U2 can be eliminated.
Simply connect IOSTRB directly to CS. The ADS1605
16-bit data output bus is directly connected to the
TMS320C5400 data bus. The data ready output from the
ADS1605, DRDY, drives interrupt INT3 on the
TMS320C5400.
Figure 31 illustrates how to directly connect the ADS1606
to the TMS320C5400 DSP. The processor controls
reading using outputs R/W and IS. The ADS1606 is
permanently selected by grounding the CS pin. If there are
any additional devices connected to theTMS320C5400
I/O space, address decode logic will be required between
the ADC and the DSP to prevent data bus contention and
ensure only one device at a time is selected. The ADS1606
16-bit data output bus is directly connected to the
TMS320C5400 data bus. The data ready output from the
ADS1606, DRDY, drives interrupt INT3 on the
TMS320C5400.
ADS1606
TMS320C5400
16
DOUT[15:0]
D[15:0]
DRDY
CS
INT3
ADS1605
TMS320C5400
16
DOUT[15:0]
D[15:0]
R/W
IS
U1
RD
DRDY
CS
INT3
IOSTRB
A15
U2
U1
R/W
IS
Figure 31. ADS1606—TMS320C5400 Interface
Connection
RD
Code Composer Studio, available from TI, provides
support for interfacing TI DSPs through a collection of data
converter plugins. Check the TI website, located at
www.ti.com/sc/dcplug−in, for the latest information on
ADS1605/6 support.
Figure 30. ADS1605—TMS320C5400 Interface
Connection
29
PACKAGE OPTION ADDENDUM
www.ti.com
18-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
ADS1605IPAPR
ADS1605IPAPT
ADS1606IPAPR
ADS1606IPAPT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
HTQFP
HTQFP
HTQFP
HTQFP
PAP
64
64
64
64
1000
250
None
None
None
None
CU NIPDAU Level-3-235C-168 HR
CU NIPDAU Level-3-235C-168 HR
CU NIPDAU Level-3-235C-168 HR
CU NIPDAU Level-3-235C-168 HR
PAP
PAP
1000
250
PAP
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2005, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明