ADS5273 [BB]
8-Channel, 12-Bit, 70MSPS ADC with Serialized LVDS Interface; 8通道， 12位， 70MSPS ADC，具有串行LVDS接口
| 型号： | ADS5273 |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | 8-Channel, 12-Bit, 70MSPS ADC with Serialized LVDS Interface |
| 文件： | 总16页 (文件大小：252K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS5273
SBAS305A − JANUARY 2004 − REVISED FEBRUARY 2004
8-Channel, 12-Bit, 70MSPS ADC
with Serialized LVDS Interface
The ADS5273 provides an internal reference, or can
FD EATURES
optionally be driven with an external reference. Best
performance can be achieved through the internal
reference mode.
Maximum Sample Rate: 70MSPS
D
D
D
D
D
D
D
12-Bit Resolution
No Missing Codes
The device is available in a PowerPAD TQFP-80 package
and is specified over a −40°C to +85°C operating range.
Power Dissipation: 1.1W
CMOS Technology
Simultaneous Sample-and-Hold
70.5dB SNR at 10MHz IF
LCLKP
LCLKN
6X ADCLK
1X ADCLK
Serialized LVDS Outputs Meet or Exceed the
Requirements of ANSI TIA/EIA-644-A
Standard
PLL
ADCLKP
ADCLKN
ADCLK
D
D
D
Internal and External References
3.3V Digital/Analog Supply
IN1P
IN1N
OUT1P
OUT1N
12−Bit
ADC
Serializer
Serializer
Serializer
Serializer
Serializer
Serializer
Serializer
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
TQFP-80 PowerPAD Package
IN2P
IN2N
OUT2P
OUT2N
12−Bit
ADC
AD PPLICATIONS
IN3P
IN3N
OUT3P
OUT3N
Portable Ultrasound Systems
12−Bit
ADC
D
D
Tape Drives
Test Equipment
IN4P
IN4N
OUT4P
OUT4N
12−Bit
ADC
IN5P
IN5N
DESCRIPTION
OUT5P
OUT5N
12−Bit
ADC
The ADS5273 is a high-performance, 70MSPS, 8-channel
parallel analog-to-digital converter (ADC). An internal
reference is provided, simplifying system design
requirements. Low power consumption allows for the
highest of system integration densities. Serial LVDS
outputs reduce the number of interface lines and package
size.
IN6P
IN6N
OUT6P
OUT6N
12−Bit
ADC
IN7P
IN7N
OUT7P
OUT7N
12−Bit
ADC
IN8P
IN8N
OUT8P
OUT8N
In LVDS (low-voltage differential signaling), an integrated
phase lock loop multiplies the incoming ADC sampling
clock by a factor of 6. This high-frequency LVDS clock is
used in the data serialization and transmission process
and is converted to an LVDS signal for transmission in
parallel with the data. Providing this additional LVDS clock
allows for easy delay matching. The word output of each
internal ADC is serialized and transmitted either MSB or
LSB first. The bit following the rising edge of the ADC clock
output is the first bit of the word.
12−Bit
ADC
Serializer
Control
Registers
Reference
INT/EXT
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners.
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Copyright 2004, Texas Instruments Incorporated
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SBAS305A − JANUARY 2004 − REVISED FEBRUARY 2004
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handledwith appropriate precautions. Failure to observe
(1)
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Range, AVDD . . . . . . . . . . . . . . . . . . −0.3V to 3.8V
Supply Voltage Range, LVDD . . . . . . . . . . . . . . . . . . −0.3V to 3.8V
Voltage Between AVSS and LVSS . . . . . . . . . . . . . . −0.3V to 0.3V
Voltage Between AVDD and LVDD . . . . . . . . . . . . . . −0.3V to 0.3V
Voltages Applied to External REF Pins . . . . . . . . . . −0.3V to 2.4V
All LVDS Data and Clock Outputs . . . . . . . . . . . . . . −0.3V to 2.4V
ADCLK Peak Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBD
Peak Total Input Current (all inputs) . . . . . . . . . . . . . . . . . . . −30mA
proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
Operating Free-Air Temperature Range, T . . . . . . −40°C to 85°C
A
Lead Temperature 1.6mm (1/16″ from case for 10s) . . . . . . 235°C
(1)
Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not supported.
ORDERING INFORMATION
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE-LEAD
(1)
ADS5273
HTQFP-80
PFP
−40°C to +85°C
ADS5273IPFP
ADS5273IPFP
ADS5273IPFPT
Tray, 96
″
″
″
″
″
Tape and Reel, 250
(1)
For the most current specification and package information, refer to our web site at www.ti.com.
RECOMMENDED OPERATING CONDITIONS
ADS5273
TYP
MIN
MAX
UNIT
SUPPLIES AND REFERENCES
Analog Supply Voltage, AVDD
3.0
3.0
3.3
3.3
3.6
3.6
V
V
Output Driver Supply Voltage, LVDD
CLOCK INPUT AND OUTPUTS
ADCLK Input Sample Rate (low-voltage TTL), 1/t
Low Voltage Level Clock
20
70
1
MSPS
V
C
High Voltage Level Clock
2
V
ADCLK and ADCLK Outputs (LVDS)
35
70
420
+85
MHz
MHz
°C
P
N
(1)
LCLK and LCLK Outputs (LVDS)
210
−40
P
N
Operating Free-Air Temperature, T
A
(1)
6 × ADCLK.
REFERENCE SELECTION
MODE
INT/EXT
DESCRIPTION
2.0V
Internal Reference
Default with internal pull-up.
1
0
PP
Internal reference is powered down. Common mode of external reference should be within
50mV of V . V is derived from the internal bandgap voltage.
External Reference
CM CM
2
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SBAS305A − JANUARY 2004 − REVISED FEBRUARY 2004
ELECTRICAL CHARACTERISTICS
T
= −40°C, and T
= +85°C. Typical values are at T = 25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V,
MIN
MAX A
LVDD = 3.3V, −0.5dBFS, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted.
ADS5273
MIN
TYP
MAX
PARAMETER
TEST CONDITIONS
UNITS
DC ACCURACY
No Missing Codes
DNL Differential Nonlinearity
INL Integral Nonlinearity
Assured
TBD
TBD
TBD
0.5
1
TBD
TBD
TBD
LSB
LSB
(1)
Midscale Offset Error
mV
Offset Temperature Coefficient
(2)
Fixed Gain Error
TBD
1.0
ppm/°C
%FS
∆%/°C
TBD
TBD
Gain Temperature Coefficient
POWER SUPPLY
Total Supply Current
TBD
I
V
V
= FS, F = 10MHz
IN
= FS, F = 10MHz
IN
333
289
mA
mA
CC
IN
IN
IN
I(AVDD) Analog Supply Current
V
= FS, F = 10MHz,
IN
I(LVDD) Digital Output Driver Supply Current
44
mA
W
LVDS Into 100Ω Load
Power Dissipation
V
IN
= FS, F = 10MHz
1.1
IN
REFERENCE VOLTAGES
VREF
Reference Top (internal)
Reference Bottom (internal)
Common-Mode Voltage
2.0
1.0
V
V
T
N
VREF
V
CM
1.5
V
V
Output Current
TBD
mA
V
CM
VREF
Reference Top (external)
1.875
T
B
VREF
Reference Bottom (external)
(3)
Reference Input Resistance
1.125
V
TBD
ANALOG INPUT
DC Differential Input Resistance
1.2
7
kΩ
pF
V
Differential Input Capacitance
Analog Input Common-Mode Range
Differential Input Voltage Range
V
CM
0.05
2.0
1.5
V
PP
Differential Input Signal at 4V
PP
CLK
Cycles
Voltage Overload Recovery Time
Input Bandwidth
4
Recovery to Within 1% of Code
−3dBFS
300
MHz
DIGITAL DATA OUTPUTS
Data Bit Rate
SERIAL INTERFACE
SCLK Serial Clock Input Frequency
420
840
MBPS
20
0.6
MHz
V
V
LOW Input Low Voltage
HIGH Input High Voltage
Input Current
0
IN
V
IN
2.1
VDD
V
TBD
5
µA
pF
Input Pin Capacitance
(1)
(2)
Offset Error is the measured deviation of the midscale transition from the ideal midscale transition.
Gain Error is the difference between the nominal and actual offset point on the transfer function after the offset error has been corrected to zero.
The gain point is the mid-step value when the digital output is full-scale.
(3)
Average switching current drawn from external reference. DC component of current is internally generated even in external reference mode.
3
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SBAS305A − JANUARY 2004 − REVISED FEBRUARY 2004
AC CHARACTERISTICS
T
= −40°C, T
= +85°C. Typical values are at T = 25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V,
MIN
MAX A
LVDD = 3.3V, −0.5dBFS, internal voltage reference, and 2V
differential input, unless otherwise noted.
PP
ADS5273
TYP
PARAMETER
CONDITIONS
MIN
MAX
UNITS
DYNAMIC CHARACTERISTICS
f
f
= 1MHz
= 5MHz
= 10MHz
= 20MHz
= 1MHz
= 5MHz
= 10MHz
= 20MHz
= 1MHz
= 5MHz
= 10MHz
= 20MHz
= 1MHz
= 5MHz
= 10MHz
= 20MHz
= 1MHz
= 5MHz
= 10MHz
= 20MHz
= 10MHz
85
85
dBc
dBc
IN
IN
TBD
SFDR Spurious-Free Dynamic Range
f
f
85
dBc
IN
80
dBc
IN
f
f
90
dBc
IN
IN
TBD
TBD
TBD
TBD
87
dBc
HD
HD
2nd-Order Harmonic Distortion
3rd-Order Harmonic Distortion
2
f
f
80
dBc
IN
76
dBc
IN
f
f
87
dBc
IN
IN
84
dBc
3
f
f
77
dBc
IN
73
dBc
IN
f
f
70.5
70.5
70.5
70.5
70
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Bits
IN
IN
SNR Signal-to-Noise Ratio
f
f
IN
IN
f
f
IN
IN
70
SINAD Signal-to-Noise and Distortion
ENOB Effective Number of Bits
f
f
f
70
IN
IN
IN
70
11.3
Signal Applied to 7 Channels; Measurement Taken on the
Channel with No Input Signal
Crosstalk
−85
dBc
LVDS DIGITAL DATA AND CLOCK OUTPUTS
Test conditions at I = 3.5mA, R
O
= 100Ω, and C = 9pF. All LVDS specifications are characterized but not tested.
LOAD
LOAD
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DC SPECIFICATIONS
V
Output Voltage High, OUT or OUT
R
= 100Ω 1%; See LVDS Timing Diagram, Page 7
1340
1038
350
1475
mV
mV
mV
V
OH
P
N
LOAD
LOAD
V
Output Voltage Low, OUT or OUT
R
R
= 100Ω 1%
= 100Ω 1%
925
325
OL
P
N
LOAD
V
Output Differential Voltage
Output Offset Voltage
375
OD
LOAD
V
R
= 100Ω 1%; See LVDS Timing Diagram, Page 7
1.125
1.250
TBD
1.275
OS
R
∆R
C
Output Impedance, Single-Ended
V
V
V
= 1.0V and 1.4V
= 1.0V and 1.4V
= 1.0V and 1.4V
Ω
%
O
O
O
CM
CM
CM
Mismatch Between OUT and OUT
P
Output Capacitance
TBD
5
N
3
4
pF
mV
mV
∆V
Change in V Between 0 and 1
R
= 100Ω 1%
= 100Ω 1%
25
25
OD
OD
LOAD
LOAD
∆V
Change Between 0 and 1
R
OS
ISOUT ,
P
Output Short-Circuit Current
Drivers Shorted to Ground
40
mA
ISOUT
N
ISOUT
Output Current
Drivers Shorted Together
12
10
mA
mA
NP
I , I
Power-Off Output Leakage
V
= 0V
XN XP
CC
DRIVER AC SPECIFICATIONS
Clock Clock Signal Duty Cycle
6 × ADCLK
45
50
55
50
%
tp
HLP
− tp
or tp
HLN
− tp ,
LHP
LHN
(1)
t
t
Any Differential Pair on Package
ps
SKEW1
Differential Skew
tp − tp
Channel-to-Channel Skew
,
DIFF[X] DIFF[Y]
(2)
Any Two Signals on Package
100
ps
SKEW2
(3)
t
/t
V
Rise Time or V Fall Time
Z
Z
Z
= 100Ω, C = 9pF, I = 2.5mA
400
250
200
150
RISE FALL
OD
OD
LOAD
LOAD
LOAD
I
O
= 100Ω, C = 9pF, I = 3.5mA
ps
ps
ps
I
O
= 100Ω, C = 9pF, I = 4.5mA
I
O
Z
= 100Ω, C = 9pF, I = 6mA
I O
LOAD
(1)
(2)
(3)
Skew measurements are made at the 50% point of the transition.
Skew measurements made at 0V differential (that is, the crossing of single-ended signals).
Where x is any one of the parallel channels and y is any other channel.
4
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SBAS305A − JANUARY 2004 − REVISED FEBRUARY 2004
SWITCHING CHARACTERISTICS
T
= −40°C, T = +85°C. Typical values are at T = 25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V,
MIN
MAX A
LVDD = 3.3V, −0.5dBFS, internal voltage reference, and 2V
differential input, unless otherwise noted.
PP
MIN
TYP
MAX
PARAMETER
CONDITIONS
UNITS
SWITCHING SPECIFICATIONS
t
14.3
50
ns
ps
SAMPLE
t (A) Aperture Delay
120
1
D
Aperture Jitter (uncertainty)
ps
t (pipeline) Latency
6.5
5
cycles
ns
D
t
Propagation Delay
PROP
SERIAL INTERFACE TIMING
Data is shifted in MSB first.
Outputs change on
next rising clock edge
after CS goes high.
ADCLK
Start Sequence
CS
t1
Data latched on
each rising edge of SCLK.
t2
SCLK
t3
SDATA
MSB
D6
D5
D4
D3
D2
D1
D0
t4
t5
PARAMETER
DESCRIPTION
MIN
50
13
13
5
TYP
MAX
UNIT
ns
t
1
t
2
t
3
t
4
t
5
Serial CLK Period
Serial CLK High Time
Serial CLK Low Time
Data Setup Time
ns
ns
ns
Data Hold Time
5
ns
5
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SBAS305A − JANUARY 2004 − REVISED FEBRUARY 2004
SERIAL INTERFACE TIMING
ADDRESS
DATA
DESCRIPTION
REMARKS
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0. LVDS BUFFERS
0
0
1
1
0
1
0
1
Normal ADC Output
Deskew Pattern
Patterns Get Reversed in MSB First
Mode of LVDS
Sync Pattern
Custom Pattern
0
0
1
1
0
1
0
1
Output Current in LVDS = 3.5mA
Output Current in LVDS = 2.5mA
Output Current in LVDS = 4.5mA
Output Current in LVDS = 6.0mA
0
0
0
1
1. LSB/MSB MODE
D3
0
D2
X
D1
X
D0
1
2X LVDS Clock Input Current
LSB Mode
0
0
X
X
0
1
X
X
MSB Mode
0
0
0
0
1
1
0
1
2. POWER-DOWN ADC CHANNELS
D3
D2
D1
D0
Example: 1010 Powers Down
Channels 4 and 2 and Keeps
Channels 1 and 3 Alive
Power-Down Channels 1 to 4; D3 is
for Channel 4 and D0 for Channel 1
X
X
X
X
3. POWER-DOWN ADC CHANNELS
D3
D2
D1
D0
Power-Down Channels 5 to 8; D3 is
for Channel 8 and D0 for Channel 5
X
X
X
X
CUSTOM PATTERN (registers 4-6)
D3
MSB
X
D2
X
D1
X
D0
X
0
0
0
1
1
1
0
0
1
0
1
0
X
X
X
Bits for Custom Pattern
X
X
X
LSB
(1)
TEST PATTERNS
Deskew
101010101010
000000111111
Sync
Custom
Any 12-bit pattern that is defined in the custom pattern registers 4 to 6.
(1)
Default is LSB first. If MSB is selected the above patterns will be reversed.
6
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SBAS305A − JANUARY 2004 − REVISED FEBRUARY 2004
LVDS TIMING DIAGRAM (PER ADC CHANNEL)
Sample n
Sample n+6
Input
1
fS
ADCLK
tSAMPLE
2
LCLKP
6X ADCLK
LCLKN
OUTP
D10 D11
D0 D1
SERIAL DATA
OUTN
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
Sample n data
ADCLKP
1X ADCLK
ADCLKN
tPROP
6.5 Clock Cycles
RESET TIMING
t1
+AVDD
Power
Supply
t1 > TBD
0V
t2 > 100ns
+AVDD
0V
RESET
t2
POWER-DOWN TIMING
µ
10 s
Device Fully
Powers Down
PDN
Device Fully
Powers Up
µ
1 s
7
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SBAS305A − JANUARY 2004 − REVISED FEBRUARY 2004
PIN CONFIGURATION
Top View
TQFP
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
2
60
59
AVDD
IN1P
AVDD
IN8N
IN1N
3
58 IN8P
57
4
AVSS
IN2P
AVSS
5
56 IN7N
55 IN7P
IN2N
6
7
54
AVDD
AVSS
IN3P
AVDD
8
53 AVSS
9
52
51
50
IN6N
IN6P
10
11
IN3N
ADS5273
AVSS
AVSS
IN4P 12
13
49 IN5N
48
IN4N
IN5P
AVDD 14
LVSS 15
47 AVDD
46 LVSS
16
45
PD
RESET
LVSS 17
44 LVSS
18
19
20
43
42
41
LVSS
LCLKP
LCLKN
LVSS
ADCLKN
ADCLKP
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
8
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SBAS305A − JANUARY 2004 − REVISED FEBRUARY 2004
PIN DESCRIPTIONS
NUMBER
OF PINS
NAME
PIN #
I/O
DESCRIPTION
AVDD
AVSS
LVDD
LVSS
1, 7, 14, 47, 54, 60, 63, 70, 75
8
14
2
8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I
I
Analog Power Supply
4, 8, 11, 50, 53, 57, 61, 62, 68, 72-74, 79, 80
Analog Ground
25, 35
I
LVDS Power Supply
15, 17, 18, 26, 36, 43, 44, 46
I
LVDS Ground
IN1
2
I
Channel 1 Differential Analog Input High
Channel 1 Differential Analog Input Low
Channel 2 Differential Analog Input High
Channel 2 Differential Analog Input Low
Channel 3 Differential Analog Input High
Channel 3 Differential Analog Input Low
Channel 4 Differential Analog Input High
Channel 4 Differential Analog Input Low
Channel 5 Differential Analog Input High
Channel 5 Differential Analog Input Low
Channel 6 Differential Analog Input High
Channel 6 Differential Analog Input Low
Channel 7 Differential Analog Input High
Channel 7 Differential Analog Input Low
Channel 8 Differential Analog Input High
Channel 8 Differential Analog Input Low
Reference Top Voltage
P
N
IN1
IN2
3
I
5
I
P
N
IN2
IN3
6
I
9
I
P
N
IN3
IN4
10
12
13
48
49
51
52
55
56
58
59
67
66
65
69
16
19
20
71
21
22
23
24
27
28
29
30
31
32
33
34
37
38
39
40
41
42
64
45
76
77
78
I
I
P
N
IN4
IN5
I
I
P
N
IN5
IN6
I
I
P
N
IN6
IN7
I
I
P
N
IN7
IN8
I
I
P
N
IN8
I
REFT
I/O
I/O
O
I
REFB
Reference Bottom Voltage
V
CM
Common-Mode Output Voltage
INT/EXT
PD
Internal/External Reference Select; 0 = External, 1 = Internal
Power-Down; 0 = Normal, 1 = Power-Down
Positive LVDS Clock
I
LCLK
O
O
I
P
LCLK
Negative LVDS Clock
N
ADCLK
Data Converter Clock Input
OUT1
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I/O
I
Channel 1 Positive LVDS Data Output
Channel 1 Negative LVDS Data Output
Channel 2 Positive LVDS Data Output
Channel 2 Negative LVDS Data Output
Channel 3 Positive LVDS Data Output
Channel 3 Negative LVDS Data Output
Channel 4 Positive LVDS Data Output
Channel 4 Negative LVDS Data Output
Channel 5 Positive LVDS Data Output
Channel 5 Negative LVDS Data Output
Channel 6 Positive LVDS Data Output
Channel 6 Negative LVDS Data Output
Channel 7 Positive LVDS Data Output
Channel 7 Negative LVDS Data Output
Channel 8 Positive LVDS Data Output
Channel 8 Negative LVDS Data Output
Positive LVDS ADC Clock Output
Negative LVDS ADC Clock Output
Bias Current Setting Resistor
P
N
OUT1
OUT2
P
N
OUT2
OUT3
P
N
OUT3
OUT4
P
N
OUT4
OUT5
P
N
OUT5
OUT6
P
N
OUT6
OUT7
P
N
OUT7
OUT8
P
N
OUT8
ADCLK
P
ADCLK
N
ISET
RESET
CS
Reset to Default; 0 = Reset, 1 = Normal
Chip Select; 0 = Select, 1 = No Select
Serial Data Input
I
SDA
I
SCLK
I
Serial Data Clock
9
ꢠꢃ ꢡꢢ ꢣ ꢤ ꢥ
www.ti.com
SBAS305A − JANUARY 2004 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
T
= −40°C, and T = +85°C. Typical values are at T = 25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V,
MAX A
MIN
LVDD = 3.3V, −0.5dBFS, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted.
ADS5273 Spectral Performance
0
fIN = 10MHz
SNR = 70.5dBFS
SFDR = 88dBc
SINAD = 70dBFS
−
−
−
−
20
40
60
80
−
−
100
120
0
5
10
15
20
25
30
35
Frequency (MHz)
10
ꢠ ꢃꢡ ꢢꢣ ꢤꢥ
www.ti.com
SBAS305A − JANUARY 2004 − REVISED FEBRUARY 2004
DRIVING THE ANALOG INPUTS
THEORY OF OPERATION
The analog input biasing is shown in Figure 1. The
recommended method to drive the inputs is through AC
coupling. AC coupling removes the worry of setting the
common-mode of the driving circuit, since the inputs are
biased internally using two 600Ω resistors. The sampling
capacitor used to sample the inputs is 4pF. The choice of
the external AC coupling capacitor is dictated by the
attenuation at the lowest desired input frequency of
operation factor. The attenuation resulting from using a
10nF AC coupling capacitor is 0.04%.
OVERVIEW
The ADS5273 is an 8-channel, high-speed, CMOS ADC,
consisting of a high-performance sample-and-hold circuit
at the input, followed by a 12-bit ADC. The 12 bits given out
by each channel are serialized and sent out on a single pair
of pins in LVDS format. All eight channels of the ADS5273
operate from a single clock referred to as ADCLK. The
sampling clock for each of the eight channels is generated
from the input clock using a carefully matched clock buffer
tree. The 12X clock required for the serializer is generated
internally from ADCLK using a phase lock loop (PLL). A 6X
and a 1X clock are also output in LVDS format along with
the data to enable easy data capture. The ADS5273
operates from an internally generated reference voltage
that is trimmed to ensure matching across multiple devices
on a board. This feature eliminates the need for external
routing of reference lines and also improves matching of
the gain across devices. The nominal values of REFP and
REFN are 2V and 1V, respectively. These values imply that
a differential input of −1V corresponds to the zero code of
the ADC, and a differential input of +1V corresponds to the
full-scale code (4095 LSB). VCM (common-mode voltage
of REFP and REFN) is also made available externally
through a pin, and is nominally 1.5V.
ADS5273
IN+
Ω
Ω
600
Input
Circuitry
600
−
IN
CM Buffer 1
CM Buffer 2
Internal
Voltage
Reference
VCM
The ADC employs a pipelined converter architecture
consisting of a combination of multi-bit and single-bit
internal stages. Each stage feeds its data into the digital
error correction logic, ensuring excellent differential
linearity and no missing codes at the 12-bit level. The
pipeline architecture results in a data latency of 6.5 clock
cycles.
Figure 1. Analog Input Bias Circuitry
If the input is DC coupled, then the output common-mode
voltage of the circuit driving the ADS5273 should match
the VCM (which is provided as an output pin) to within
50mV. It is recommended that the output common-mode
of the driving circuit be derived from VCM provided by the
device.
The output of the ADC goes to a serializer that operates
from a 12X clock generated by the PLL. The 12 data bits
from each channel are serialized and sent LSB first. In
addition to serializing the data, the serializer also
generates a 1X clock and a 6X clock. These clocks are
generated in the same way the serialized data is
generated, so these clocks maintain perfect synchroniza-
tion with the data. The data and clock outputs of the
serializer are buffered externally using LVDS buffers.
Using LVDS buffers to transmit data externally has
multiple advantages, such as a reduced number of output
pins (saving routing space on the board), reduced power
consumption, and reduced effects of digital noise coupling
to the analog circuit inside the ADS5273.
INPUT OVER-VOLTAGE RECOVERY
The differential full-scale input peak-to-peak supported by
the ADS5273 is 2V. For a nominal value of VCM (1.5V), INP
and INN can swing from 1V to 2V. The ADS5273 is
specially designed to handle an over-voltage differential
peak-to-peak voltage of 4V (2.5V and 0.5V swings on INP
and INN). If the input common-mode is not considerably off
from VCM during overload (less than 300mV), recovery
from an over-voltage input condition is expected to be
within 4 clock cycles. All of the amplifiers in the SHA and
ADC are especially designed for excellent recovery from
an overload signal.
The ADS5273 operates from two sets of supplies and
grounds. The analog supply/ground set is denoted as
AVDD/AVSS, while the digital set is denoted by
LVDD/LVSS.
11
ꢠꢃ ꢡꢢ ꢣ ꢤ ꢥ
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SBAS305A − JANUARY 2004 − REVISED FEBRUARY 2004
Another critical specification is the aperture jitter that is
defined as the uncertainty of the sampling instant. The
gates in the clock path are designed so as to give an rms
jitter of about 1ps.
REFERENCE CIRCUIT DESIGN
The digital beam-forming algorithm relies heavily on gain
matching across all receiver channels. A typical system
would have about 12 octal ADCs on the board. In such a
case, it is critical to ensure that the gain is matched,
essentially requiring the reference voltages seen by all the
ADCs to be the same. Matching references within the eight
channels of a chip is done by using a single internal
reference voltage buffer. Trimming the reference voltages
on each chip during production ensures the reference
voltages are well matched across different chips.
The input ADCLK should ideally have a 50% duty cycle.
However, while routing ADCLK to different components on
board, the duty cycle of the ADCLK reaching the ADS5273
could deviate from 50%. A smaller (or larger) duty cycle
eats into the time available for sample or hold phases of
each circuit, and is therefore not optimal. For this reason,
the internal PLL is used to generate an internal clock that
has 50% duty cycle.
All bias currents required for the internal operation of the
device are set using an external resistor to ground at pin
ISET. Using a 56kΩ resistor on ISET generates an internal
reference current of 20µA. This current is mirrored
internally to generate the bias current for the internal
blocks. Using a larger external resistor at ISET reduces the
reference bias current and thereby scales down the device
operating power. However, it is recommended that the
external resistor be within 10% of the specified value of
56k so that the internal bias margins for the various blocks
are proper.
The use of the PLL automatically dictates the lower
frequency of operation to be about 20MHz.
LVDS BUFFERS
The LVDS buffer has two current sources, as shown in
Figure 2. OUTP and OUTN are loaded externally by a
resistive load that is ideally about 100Ω. Depending on the
data being 0 or 1, the currents are directed in one or the
other direction through the resistor. The LVDS buffer has
four current settings. The default current setting is 3.5mA,
and gives a differential drop of about 350mV across the
100Ω resistor.
Buffering the internal bandgap voltage also generates a
voltage called VCM, which is set to the midlevel of REFT
and REFB, and is accessible on a pin. The internal buffer
driving VCM has a drive of 4mA. It is meant as a reference
voltage to derive the input common-mode in case the input
is directly coupled.
The device also supports the use of external reference
voltages. This involves forcing REFT and REFB externally.
In this mode, the internal reference buffer is tri-stated.
Since the switching current for the eight ADCs come from
the externally forced references, it is possible for the
performance to be slightly less than when the internal
references are used. It should be noted that in this mode,
External
Termination
Resistor
High
Low
OUTP
OUTN
Low
High
V
CM and ISET continue to be generated from the internal
bandgap voltage, as in the internal reference mode. It is
therefore important to ensure that the common-mode
voltage of the externally forced reference voltages
matches to within 50mV of VCM
.
CLOCKING
Figure 2. LVDS Buffer
The eight channels on the chip run off a single ADCLK
input. To ensure that the aperture delay and jitter are same
for all the channels, a clock tree network is used to
generate individual sampling clocks to each channel. The
clock paths for all the channels are matched from the
source point all the way to the sample-and-hold. This
ensures that the performance and timing for all the
channels are identical. The use of the clock tree for
matching introduces an aperture delay, which is defined as
the delay between the rising edge of ADCLK and the actual
instant of sampling. The aperture delays for all the
channels are matched, and vary between 2.5ns to 4.5ns.
The LVDS buffer gets data from a serializer that takes the
output data from each channel and serializes it into a
single data stream. For a clock frequency of 40MHz, the
data rate output by the serializer is 480 MBPS. The data
comes out LSB first, with a register programmability to
revert to MSB first. The serializer also gives out a 1X clock
and a 6X clock. The 6X clock (denoted as LCLKP/ LCLKN)
is meant to synchronize the capture of the LVDS data. The
deskew mode can be enabled as well, using a register
setting. This mode gives out a data stream of alternate 0s
and 1s and can be used determine the relative delay
12
ꢠ ꢃꢡ ꢢꢣ ꢤꢥ
www.ti.com
SBAS305A − JANUARY 2004 − REVISED FEBRUARY 2004
between the 6X clock and the output data for optimum
capture. A 1X clock is also generated by the serializer and
transmitted by the LVDS buffer. The 1X clock (referred to
as ADCLKP/ADCLKN) is used to determine the start of the
12-bit data frame. The sync mode (enabled through a
register setting) gives out a data of six 0s followed by six
1s. Using this mode, the 1X clock can be used to determine
the start of the data frame. In addition to the deskew mode
pattern and the sync pattern, a custom pattern can be
defined by the user and output from the LVDS buffer.
It is recommended that the isolation be maintained on
board by using separate supplies to drive AVDD and
LVDD, as well as separate ground planes for AVSS and
LVSS.
The use of LVDS buffers reduces the injected noise
considerably, compared to CMOS buffers. The current in
the LVDS buffer is independent of the direction of
switching. Also, the low output swing as well as the
differential nature of the LVDS buffer results in low-noise
coupling.
POWER-DOWN MODE
NOISE COUPLING ISSUES
The ADS52763 has a power-down pin, PD. Pulling PD
high causes the devices to enter the power-down mode. In
this mode, the reference and clock circuitry as well as all
the channels are powered down. Device power
consumption drops to less than 100mW in this mode.
Individual channels can also be selectively powered down
by programming registers.
High-speed mixed signals are sensitive to various types of
noise coupling. One of the main sources of noise is the
switching noise from the serializer and the output buffers.
Maximum care is taken to isolate these noise sources from
the sensitive analog blocks. As a starting point, the analog
and digital domains of the chip are clearly demarcated.
AVDD and AVSS are used to denote the supplies for the
analog sections, while LVDD and LVSS are used to denote
the digital supplies. Care is taken to ensure that there is
minimal interaction between the supply sets within the
device. The extent of noise coupled and transmitted from
the digital to the analog sections depends on the following:
The ADS5273 also has an internal circuit that monitors the
state of stopped clocks. If ADCLK is stopped (or if it runs
at a speed < 3MHz), this monitoring circuit generates a
logic signal that puts the device in a power-down state. As
a result, the power consumption of the device goes to less
than 100mW when ADCLK is stopped. This circuit can
also be disabled using register options.
1. The effective inductances of each of the
supply/ground sets.
SUPPLY SEQUENCE
2. The isolation between the digital and analog
supply/ground sets.
The following supply sequence is recommended for
powering up the device:
Smaller effective inductance of the supply/ground pins
leads to better suppression of the noise. For this reason,
multiple pins are used to drive each supply/ground. It is
also critical to ensure that the impedances of the supply
and ground lines on board are kept to the minimum
possible values. Use of ground planes in the board as well
as large decoupling capacitors between the supply and
ground lines are necessary to get the best possible SNR
from the device.
1. AVDD is powered up.
2. LVDD is powered up.
After the supplies have stabilized, the device must receive
an active RESET pulse. This results in all internal registers
getting reset to their default value of 0 (inactive). Without
RESET, it is possible that some registers might be in their
non-default state on power-up. This could cause the
device to malfunction.
13
PACKAGE OPTION ADDENDUM
www.ti.com
18-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
ADS5273IPFP
ADS5273IPFPT
PREVIEW
PREVIEW
HTQFP
HTQFP
PFP
80
80
96
None
None
Call TI
Call TI
Call TI
Call TI
PFP
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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