ADS5522 [BB]
14-Bit, 80MSPS Analog-to-Digital Converter; 14位， 80MSPS模拟数字转换器
| 型号： | ADS5522 |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | 14-Bit, 80MSPS Analog-to-Digital Converter |
| 文件： | 总30页 (文件大小：399K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SBAS308A − MAY 2004 − REVISED MARCH 2005
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D
Pin-Compatible with:
FEATURES
− ADS5500 (14-Bit, 125MSPS)
− ADS5541 (14-Bit, 105MSPS)
− ADS5520 (12-Bit, 125MSPS)
− ADS5521 (12-Bit, 105MSPS)
− ADS5522 (12-Bit, 80MSPS)
D
D
D
D
D
D
D
D
14-Bit Resolution
80MSPS Sample Rate
High SNR: 72.9dBFS at 100 MHz f
IN
High SFDR: 88dBc at 100 MHz f
IN
APPLICATIONS
D
2.3V Differential Input Voltage
PP
Wireless Communication
− Communication Receivers
− Base Station Infrastructure
Internal Voltage Reference
3.3V Single-Supply Voltage
D
D
D
D
D
D
Test and Measurement Instrumentation
Single and Multichannel Digital Receivers
Analog Power Dissipation: 545mW
− Output Buffer Power: 129mW
Communication Instrumentation
− Radar, Infrared
D
D
TQFP-64 PowerPADE Package
Recommended Op Amps:
THS3202, THS3201, THS4503,
OPA695, OPA847
Video and Imaging
Medical Equipment
Military Equipment
DESCRIPTION
The ADS5542 is a high-performance, 14-bit, 80MSPS analog-to-digital converter (ADC). To provide a complete converter
solution, it includes a high-bandwidth linear sample-and-hold stage (S&H) and internal reference. Designed for
applications demanding the highest speed and highest dynamic performance in very little space, the ADS5542 has
excellent analog power dissipation of 545mW and output buffer power dissipation of 129mW from a 3.3V single-supply
voltage. This allows an even higher system integration density. The provided internal reference simplifies system design
requirements. Parallel CMOS compatible output ensures seamless interfacing with common logic.
The ADS5542 is available in a 64-pin TQFP PowerPAD package and is pin-compatible with the ADS5500, ADS5541,
ADS5520, ADS5521, and ADS5522. This device is specified over the full temperature range of −40°C to +85°C.
AVDD
DRVDD
CLK+
CLK
CLKOUT
Timing Circuitry
−
D0
V +
14−Bit
Pipeline
ADC Core
Digital
Error
Correction
IN
.
.
.
Output
Control
S&H
V
−
IN
D13
OVR
DFS
Control Logic
Internal
Reference
CM
Serial Programming Register
ADS5542
AGND
DRGND
SCLK
SEN
SDATA
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPad is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
ꢋꢙ ꢚ ꢒꢛ ꢓ ꢜꢝ ꢚꢞ ꢒ ꢌꢜꢌ ꢄꢍ ꢟꢐ ꢖ ꢠꢎ ꢅꢄꢐꢍ ꢄꢡ ꢢꢣ ꢖ ꢖ ꢕꢍꢅ ꢎꢡ ꢐꢟ ꢤꢣꢥ ꢏꢄꢢ ꢎꢅꢄ ꢐꢍ ꢦꢎ ꢅꢕꢧ ꢋꢖ ꢐꢦꢣ ꢢꢅꢡ
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Copyright 2004−2005, Texas Instruments Incorporated
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SBAS308A − MAY 2004 − REVISED MARCH 2005
PACKAGE/ORDERING INFORMATION(1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE−LEAD
ADS5542IPAP
Tray, 160
HTQFP-64(2)
PowerPAD
ADS5542
PAP
−40°C to +85°C
ADS5542I
ADS5542IPAPR
Tape and Reel, 1000
(1)
(2)
For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI website
at www.ti.com.
Thermalpad size: 3.5mm x 3.5mm (min), 4mm x 4mm (max). θJA = 21.47°C/W and θJC = 2.99°C/W, when used with 2oz. copper trace and pad
soldered directly to a JEDEC standard 4 layer 3in x 3in PCB.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to
damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
(1)
over operating free-air temperature range unless otherwise noted
MIN TYP MAX
UNIT
PARAMETER
ADS5542
UNIT
Supplies
AVDD to AGND
DRVDD to DRGND
,
−0.3 to +3.7
V
Analog supply voltage, AVDD
Output driver supply voltage, DRVDD
Analog Input
3.0
3.0
3.3
3.3
3.6
3.6
V
V
Supply
Voltage
AGND to DRGND
0.1
V
V
V
V
(2)
Analog input to AGND
−0.3 to +3.6
−0.3 to DRVDD
−0.3 to DRVDD
−40 to +85
+105
Differential input range
2.3
VPP
V
Logic input to DRGND
(1)
Input common-mode voltage, VCM
Digital Output
1.47 1.57 1.67
Digital data output to DRGND
Operating temperature range
Junction temperature
°C
°C
°C
Maximum output load
Clock Input
10
pF
Storage temperature range
−65 to +150
ADCLK input sample rate (sine
wave) 1/tC
10
1
80 MSPS
(1)
Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not implied.
Clock amplitude, sine wave,
3
VPP
%
(2)
differential
(3)
Clock duty cycle
50
(2)
For more detail, refer to Input Voltage Overstress in the
ApplicationInformation section.
Open free-air temperature range
−40
+85
°C
(1)
(2)
(3)
Input common-mode should be connected to CM.
See Figure 46 for more information.
See Figure 45 for more information.
2
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SBAS308A− MAY 2004 − REVISED MARCH 2005
ELECTRICAL CHARACTERISTICS
Typical values at TA = +25°C, full temperature range is TMIN = −40°C to TMAX = +85°C, AVDD = DRVDD = 3.3V, sampling rate = 80MSPS,
50% clock duty cycle, 3V
differential clock, and −1dBFS differential input, unless otherwise noted.
PP
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Resolution
14
Bits
Analog Inputs
Differential input range
Differential input capacitance
2.3
4
VPP
pF
See Figure 37
Analog input common-mode current (per
input)
200
µA
Analog input bandwidth
Source impedance = 50Ω
750
4
MHz
Voltage overload recovery time
Internal Reference Voltages
Reference bottom voltage, VREFM
Reference top voltage, VREFP
Reference error
Clock Cycles
1.0
2.15
0.6
V
V
−4
+4
%
V
Common-mode voltage output, VCM
1.575
Dynamic DC Characteristics and Accuracy
No missing codes
Tested
0.5
Differential nonlinearity error, DNL
Integral nonlinearity error, INL
Offset error
fIN = 10MHz
−0.9
−5.0
1.1
LSB
LSB
fIN = 10MHz
2.0
+5.0
1.5
mV
Offset temperature coefficient
0.02
mV/°C
∆offset error/∆AVDD from
AVDD = 3.0V to AVDD = 3.6V
DC power supply rejection ratio, DC PSRR
0.25
mV/V
Gain error
0.3
%FS
Gain temperature coefficient
Dynamic AC Characteristics
−0.02
∆%/°C
+25°C to +85°C
72.7
71.5
74.3
74.0
73.7
73.5
73.0
72.9
71.9
70.7
1.1
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
LSB
fIN = 10MHz
fIN = 55MHz
fIN = 70MHz
Full temp range
+25°C to +85°C
71.5
70.0
Signal-to-noise ratio, SNR
Full temp range
fIN = 100MHz
fIN = 150MHz
fIN = 220MHz
RMS idle channel noise
Input tied to common-mode
Room temp
80.0
78.0
92.0
90.0
88.0
87.0
86.0
88.0
85.0
77.0
dBc
fIN = 10MHz
fIN = 55MHz
fIN = 70MHz
Full temp range
dBc
dBc
Room temp
80.0
78.0
dBc
Spurious-free dynamic range, SFDR
Full temp range
dBc
fIN = 100MHz
fIN = 150MHz
fIN = 220MHz
dBc
dBc
dBc
3
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SBAS308A− MAY 2004 − REVISED MARCH 2005
ELECTRICAL CHARACTERISTICS (continued)
Typical values at TA = +25°C, full temperature range is TMIN = −40°C to TMAX = +85°C, AVDD = DRVDD = 3.3V, sampling rate = 80MSPS,
50% clock duty cycle, 3V
differential clock, and −1dBFS differential input, unless otherwise noted.
PP
PARAMETER
CONDITIONS
Room temp
MIN
80.0
78.0
TYP
92.0
90.0
88.0
87.0
86.0
88.0
85.0
77.0
89.0
88.0
79.0
85.0
83.0
83.0
80.0
76.0
88.0
87.0
73.8
73.5
73.2
73.2
72.5
72.5
71.8
69.8
90.0
88.0
83.4
86.0
84.0
83.4
81.2
75.8
11.9
MAX
UNIT
dBc
fIN = 10MHz
fIN = 55MHz
fIN = 70MHz
Full temp range
dBc
dBc
Room temp
80.0
78.0
dBc
Second-harmonic, HD2
Full temp range
dBc
fIN = 100MHz
fIN = 150MHz
fIN = 220MHz
dBc
dBc
dBc
Room temp
80.0
78.0
dBc
fIN = 10MHz
fIN = 55MHz
fIN = 70MHz
Full temp range
dBc
dBc
Room temp
80.0
78.0
dBc
Third-harmonic, HD3
Full temp range
dBc
fIN = 100MHz
fIN = 150MHz
fIN = 220MHz
fIN = 10MHz
fIN = 70MHz
dBc
dBc
dBc
Room temp
dBc
Worst-harmonic/spur
(other than HD2 and HD3)
Room temp
dBc
+25°C to +85°C
Full temp range
72.2
71.0
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
fIN = 10MHz
fIN = 55MHz
fIN = 70MHz
+25°C to +85°C
71.0
69.5
Signal-to-noise + distortion, SINAD
Full temp range
fIN = 100MHz
fIN = 150MHz
fIN = 220MHz
Room temp
78.0
76.0
fIN = 10MHz
fIN = 55MHz
fIN = 70MHz
Full temp range
dBc
dBc
Room temp
78.0
76.0
dBc
Total harmonic distortion, THD
Full temp range
dBc
fIN = 100MHz
fIN = 150MHz
fIN = 220MHz
fIN = 70MHz
dBc
dBc
dBc
Effective number of bits, ENOB
Bits
f = 10.1MHz, 15.1MHz
(−7dBFS each tone)
93.8
92.4
92.6
dBFS
dBFS
dBFS
f = 50.1MHz, 55.1MHz
(−7dBFS each tone)
Two-tone intermodulation distortion, IMD
f = 148.1MHz, 153.1MHz
(−7dBFS each tone)
4
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SBAS308A− MAY 2004 − REVISED MARCH 2005
ELECTRICAL CHARACTERISTICS (continued)
Typical values at TA = +25°C, full temperature range is TMIN = −40°C to TMAX = +85°C, AVDD = DRVDD = 3.3V, sampling rate = 80MSPS,
50% clock duty cycle, 3V
differential clock, and −1dBFS differential input, unless otherwise noted.
PP
PARAMETER
Power Supply
CONDITIONS MIN
TYP
MAX
UNIT
Total supply current, ICC
fIN = 70MHz
fIN = 70MHz
fIN = 70MHz
Analog only
204
165
39
230
180
50
mA
mA
mA
mW
Analog supply current, IAVDD
Output buffer supply current, IDRVDD
545
594
Power dissipation
Standby power
Output buffer power with 10pF load on
digital output to ground
129
180
165
250
mW
mW
With clocks running
DIGITAL CHARACTERISTICS
Valid over full temperature range of TMIN = −40°C to TMAX = +85°C, AVDD = DRVDD = 3.3V, unless otherwise noted.
PARAMETER
Digital Inputs
CONDITIONS
MIN
TYP
MAX
UNIT
High-level input voltage, VIH
Low-level input voltage, VIL
High-level input current, IIH
Low-level input current, IIL
Input current for RESET
Input capacitance
2.4
V
0.8
10
10
V
µA
µA
µA
pF
−20
4
Digital Outputs
Low-level output voltage, VOL
High-level output voltage, VOH
Output capacitance
CLOAD = 10pF
CLOAD = 10pF
0.3
3.0
3
0.4
V
V
2.4
pF
5
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SBAS308A− MAY 2004 − REVISED MARCH 2005
TIMING CHARACTERISTICS
N + 3
N + 4
N + 2
Sample
N
Analog
Input
N + 1
N + 17
N + 16
N + 14
N + 15
Signal
tA
Input Clock
tSTART
t
= t
+ t
PDI START SETUP
Output Clock
tSETUP
Data Out
(D0−D13)
N − 17
N − 16
N − 15
END
N − 14
N − 13
N − 3
N − 2
N − 1
Data Invalid
N
t
tHOLD
16.5 Clock Cycles
NOTE: It is recommended that the loading at CLKOUT and all data lines are accurately matched to ensure that the above timing
matches closely with the specified values.
Figure 1. Timing Diagram
TIMING CHARACTERISTICS(1)(2)
Typical values at TA = +25°C, full temperature range is TMIN = −40°C to tMAX = +85°C, sampling rate = 80MSPS, 50% clock duty cycle, AVDD
=
DRVDD = 3.3V, and 3VPP differential clock, unless otherwise noted.(2)
PARAMETER
Switching Specification
Aperture delay, tA
DESCRIPTION
MIN
TYP
MAX
UNIT
Input CLK falling edge to data sampling point
Uncertainty in sampling instant
1
300
4.2
3
ns
fs
Aperture jitter (uncertainty)
Data setup time, tSETUP
Data hold time, tHOLD
Data valid(3) to 50% of CLKOUT rising edge
50% of CLKOUT rising edge to data becoming invalid(3)
3.2
1.8
ns
ns
Input clock to output data valid
Input clock to Data valid start delay
Input clock to Data valid end delay
3.8
11
5
ns
ns
(4)
start, tSTART
Input clock to output data valid end,
8.4
(4)
tEND
Data rise time, tRISE
Data fall time, tFALL
Data rise time measured from 20% to 80% of DRVDD
Data fall time measured from 80% to 20% of DRVDD
5.6
4.4
6.1
5.1
ns
ns
Output enable (OE) to data output
delay
Time required for outputs to have stable timings with regard to Input
Clock(5) after OE is activated
Clock
Cycles
1000
(1)
Timing parameters are ensured by design and characterization, and not tested in production.
See Table 5 in the Application Information section for timing information at additional sampling frequencies.
Data valid refers to 2.0V for LOGIC HIGH and 0.8V for LOGIC LOW.
Refer to the Output Information section for details on using the input clock for data capture.
Data outputs are available within a clock from assertion of OE; however it takes 1000 clock cycles to ensure stable timing with respect to input
clock.
(2)
(3)
(4)
(5)
6
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RESET TIMING CHARACTERISTICS
Typical values at TA = +25°C, full temperature range is TMIN = −40°C to TMAX = +85°C, AVDD = DRVDD = 3.3V, and 3VPP differential clock, unless
otherwise noted.
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNIT
Switching Specification
Delay from power−on of AVDD and DRVDD to
RESET pulse active
Power-on delay, t1
10
ms
Reset pulse width, t2
Pulse width of active RESET signal
2
2
µs
µs
Register write delay, t3
Delay from RESET disable to SEN active
Power Supply
(AV , DRV
)
DD DD
t ≥ 10ms
1
t ≥ 2µs
t ≥ 2µs
SEN Active
2
3
RESET (Pin 35)
Figure 2. Reset Timing Diagram
SERIAL PROGRAMMING INTERFACE CHARACTERISTICS
The device has a three-wire serial interface. The device
latches the serial data SDATA on the falling edge of
serial clock SCLK when SEN is active.
D
D
D
Data is loaded at every 16th SCLK falling edge
while SEN is low.
In case the word length exceeds a multiple of 16
bits, the excess bits are ignored.
D
D
Serial shift of bits is enabled when SEN is low.
SCLK shifts serial data at falling edge.
Data can be loaded in multiple of 16-bit words within
a single active SEN pulse.
Minimum width of data stream for a valid loading is
16 clocks.
A3
A2
A1
A0
D11
D10
D9
D0
SDATA
ADDRESS
DATA
MSB
Figure 3. DATA Communication is 2-Byte, MSB First
7
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SBAS308A− MAY 2004 − REVISED MARCH 2005
tSLOADS
tSLOADH
SEN
tWSCLK
tWSCLK
tSCLK
SCLK
tOS
tOH
SDATA
MSB
LSB
MSB
LSB
16 x M
Figure 4. Serial Programming Interface Timing Diagram
Table 1. Serial Programming Interface Timing Characteristics
(1)
MIN
(1)
TYP
(1)
MAX
SYMBOL
PARAMETER
SCLK Period
UNIT
ns
tSCLK
tWSCLK
tSLOADS
tSLOADH
tDS
50
25
8
SCLK Duty Cycle
SEN to SCLK setup time
SCLK to SEN hold time
Data Setup Time
50
75
%
ns
6
ns
8
ns
tDH
Data Hold Time
6
ns
(1)
Typ, min, and max values are characterized, but not production tested.
Table 2. Serial Register Table
A3 A2 A1 A0 D11
D10
D9
D8 D7 D6 D5 D4 D3 D2
0 0 0 0 0 0 0
D1
D0
DESCRIPTION
1
1
1
0
0
TP<1> TP<0>
0
0
TP<1:0> − Test modes for output data capture
TP<1:0> = 00: Normal mode of operation
TP<1:0> = 01: All outputs forced to 0
TP<1:0> = 10: All outputs forced to 1
TP<1:0> = 11: Each output bit toggles between 0 and
1. There is no ensured relationship between the bits
See Note 2
1
1
1
1
PDN
0
0
0
0
0
0
0
0
0
0
0
PDN = 0 : Normal mode of operation, PDN = 1 :
Device is put in power down (low current) mode
(1)
(2)
All register contents default to zero on reset.
The patterns given are applicable to the straight offset binary output format. If 2’s complement output format is selected, the test mode outputs
will be the 2’s complement equivalent of these patterns.
Table 3. DATA FORMAT SELECT (DFS TABLE)
DFS-PIN VOLTAGE (V
)
DATA FORMAT
CLOCK OUTPUT POLARITY
DFS
2
12
Straight Binary
Data valid on rising edge
V
t
AV
DD
DFS
5
12
4
12
2’s Complement
Straight Binary
2’s Complement
Data valid on rising edge
Data valid on falling edge
Data valid on falling edge
AV
AV
t V
t V
u
t
t
AV
AV
DD
DD
DD
DD
DFS
8
12
7
12
DFS
10
V
AV
DD
DFS
12
8
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SBAS308A− MAY 2004 − REVISED MARCH 2005
PIN CONFIGURATION
PAP PACKAGE
(TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
2
48
DRGND
SCLK
SDATA
SEN
DRGND
47 D3
3
46
45
D2
D1
4
AVDD
AGND
5
44 D0 (LSB)
43 CLKOUT
42 DRGND
6
AVDD
AGND
7
ADS5542
8
41
40
39
OE
PowerPAD
(Connected to Analog Ground)
9
AVDD
CLKP
DFS
AVDD
10
CLKM 11
38 AGND
12
13
37
36
AGND
AGND
AVDD
AGND
AGND 14
AVDD 15
35 RESET
34 AVDD
16
33
AVDD
AGND
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
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SBAS308A− MAY 2004 − REVISED MARCH 2005
PIN ASSIGNMENTS
TERMINAL
NO.
OF PINS
12
NAME
NO.
I/O
DESCRIPTION
AVDD
5, 7, 9, 15, 22, 24, 26,
28, 33, 34, 37, 39
I
Analog power supply
Analog ground
AGND
6, 8, 12, 13, 14, 16, 18,
21, 23, 25, 27, 32, 36, 38
14
I
DRVDD
DRGND
INP
49, 58
2
6
1
1
1
I
I
Output driver power supply
Output driver ground
1, 42, 48, 50, 57, 59
19
20
29
I
Differential analog input (positive)
Differential analog input (negative)
INM
I
REFP
O
Reference voltage (positive); 0.1µF capacitor in series with a 1Ω
resistor to GND
REFM
30
1
O
Reference voltage (negative); 0.1µF capacitor in series with a 1Ω
resistor to GND
IREF
31
1
1
I
O
I
Current set; 56kΩ resistor to GND; do not connect capacitors
CM
17
Common-mode output voltage
RESET
OE
35
1
Reset (active high), 200kΩ resistor to AV
DD
41
1
I
Output enable (active high)
(1)
Data format and clock out polarity select
DFS
40
1
I
CLKP
10
1
I
Data converter differential input clock (positive)
Data converter differential input clock (negative)
Serial interface chip select
CLKM
11
1
I
SEN
4
1
I
SDATA
SCLK
3
1
I
Serial interface data
2
1
I
Serial interface clock
D0 (LSB)−D13 (MSB)
OVR
44−47, 51−56, 60−63
14
1
O
O
O
Parallel data output
64
43
Over-range indicator bit
CLKOUT
1
CMOS clock out in sync with data
:
NOTE PowerPAD is connected to analog ground.
(1)
Table 3 defines the voltage levels for each mode selectable via the DFS pin.
10
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DEFINITION OF SPECIFICATIONS
Offset Error
Analog Bandwidth
The analog input frequency at which the power of the
fundamental is reduced by 3dB with respect to the low
frequency value.
The offset error is the difference, given in number of
LSBs, between the ADC’s actual average idle channel
output code and the ideal average idle channel output
code. This quantity is often mapped into mV.
Aperture Delay
Temperature Drift
The temperature drift coefficient (with respect to gain
error and offset error) specifies the change per degree
The delay in time between the falling edge of the input
sampling clock and the actual time at which the
sampling occurs.
celcius of the parameter from T
to T
. It is
MIN
MAX
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
calcuated by dividing the maximum deviation of the
parameter across the T to T range by the
MIN
MAX
difference T
−T
.
MAX MIN
Clock Pulse Width/Duty Cycle
The duty cycle of a clock signal is the ratio of the time
the clock signal remains at a logic high (clock pulse
width) to the period of the clock signal. Duty cycle is
typically expressed as a percentage. A perfect
differential sine wave clock results in a 50% duty cycle.
Signal-to-Noise Ratio
SNR is the ratio of the power of the fundamental (P )
S
to the noise floor power (P ), excluding the power at DC
N
and the first eight harmonics.
PS
SNR + 10Log
10 PN
Maximum Conversion Rate
The maximum sampling rate at which certified
operation is given. All parametric testing is performed
at this sampling rate unless otherwise noted.
SNR is either given in units of dBc (dB to carrier) when
the absolute power of the fundamental is used as the
reference, or dBFS (dB to Full Scale) when the power
of the fundamental is extrapolated to the converter’s
full-scale range.
Minimum Conversion Rate
The minimum sampling rate at which the ADC
functions.
Signal-to-Noise and Distortion (SINAD)
SINAD is the ratio of the power of the fundamental (P )
to the power of all the other spectral components
Differential Nonlinearity (DNL)
S
An ideal ADC exhibits code transitions at analog input
values spaced exactly 1LSB apart. The DNL is the
deviation of any single step from this ideal value,
measured in units of LSBs.
including noise (P ) and distortion (P ), but excluding
N
D
DC.
PS
SINAD + 10Log
10 PN ) PD
Integral Nonlinearity (INL)
The INL is the deviation of the ADC’s transfer function
from a best fit line determined by a least squares curve
fit of that transfer function, measured in units of LSBs.
SINAD is either given in units of dBc (dB to carrier) when
the absolute power of the fundamental is used as the
reference, or dBFS (dB to Full-Scale) when the power
of the fundamental is extrapolated to the converter’s
full-scale range.
Gain Error
The gain error is the deviation of the ADC’s actual input
full-scale range from its ideal value. The gain error is
given as a percentage of the ideal input full-scale range.
Gain error does not account for variations in the internal
reference voltages (see the Electrical Specifications
Effective Number of Bits (ENOB)
The ENOB is a measure of a converter’s performance
as compared to the theoretical limit based on
quantization noise.
section for limits on the variation of V
and V
).
REFP
REFM
SINAD * 1.76
ENOB +
6.02
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Total Harmonic Distortion (THD)
THD is the ratio of the power of the fundamental (P ) to
the power of the first eight harmonics (P ).
Two-Tone Intermodulation Distortion
IMD3 is the ratio of the power of the fundamental (at
frequencies f and f ) to the power of the worst spectral
S
D
1
2
component at either frequency 2f −f or 2f −f . IMD3 is
1
2
2 1
PS
THD + 10Log
10 PD
either given in units of dBc (dB to carrier) when the
absolute power of the fundamental is used as the
reference, or dBFS (dB to Full-Scale) when the power
of the fundamental is extrapolated to the converter’s
full-scale range.
THD is typically given in units of dBc (dB to carrier).
Spurious-Free Dynamic Range (SFDR)
The ratio of the power of the fundamental to the highest
other spectral component (either spur or harmonic).
SFDR is typically given in units of dBc (dB to carrier).
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TYPICAL CHARACTERISTICS
Typical values at TA = +25°C, full temperature range is TMIN = −40°C to TMAX = +85°C, AVDD = DRVDD = 3.3V, sampling rate = 80MSPS,
50% clock duty cycle, 3VPP differential clock, and −1dBFS differential input, unless otherwise noted.
SPECTRAL PERFORMANCE
(FFT for 4MHz Input Signal)
SPECTRAL PERFORMANCE
(FFT for 16MHz Input Signal)
0
20
40
60
80
0
20
40
60
80
SFDR = 92.1dBc
SNR = 74.0dBFS
THD = 88.4dBc
SFDR = 92.0dBc
SNR = 73.6dBFS
THD = 88.2dBc
−
−
−
−
−
−
−
−
SINAD = 73.9dBFS
SINAD = 73.5dBFS
−
−
−
−
100
120
100
120
0
0
0
5
5
5
10
15
20
25
30
35
40
40
40
0
0
0
5
10
15
20
25
30
35
40
40
40
−
−
−
−
f
Frequency MHz
f
Frequency MHz
Figure 5
Figure 6
SPECTRAL PERFORMANCE
(FFT for 55MHz Input Signal)
SPECTRAL PERFORMANCE
(FFT for 70MHz Input Signal)
0
0
SFDR = 87.5dBc
SNR = 73.6dBFS
THD = 83.4dBc
−
−
−
−
−
−
−
−
20
40
60
80
20
40
60
80
SINAD = 73.2dBFS
−
−
−
−
100
120
100
120
10
15
20
25
30
35
5
10
15
20
25
30
35
−
−
f
Frequency MHz
−
−
f
Frequency MHz
Figure 7
Figure 8
SPECTRAL PERFORMANCE
(FFT for 100MHz Input Signal)
SPECTRAL PERFORMANCE
(FFT for 125MHz Input Signal)
0
0
SFDR = 87.2dBc
SNR = 72.8dBFS
THD = 83.4dBc
−
−
−
−
−
−
−
−
20
40
60
80
20
40
60
80
SINAD = 72.5dBFS
−
−
−
−
100
120
100
120
10
15
20
25
30
35
5
10
15
20
25
30
35
−
−
−
−
f
Frequency MHz
f
Frequency MHz
Figure 9
Figure 10
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TYPICAL CHARACTERISTICS (continued)
Typical values at TA = +25°C, full temperature range is TMIN = −40°C to TMAX = +85°C, AVDD = DRVDD = 3.3V, sampling rate = 80MSPS,
50% clock duty cycle, 3VPP differential clock, and −1dBFS differential input, unless otherwise noted.
SPECTRAL PERFORMANCE
(FFT for 150MHz Input Signal)
SPECTRAL PERFORMANCE
(FFT for 220MHz Input Signal)
0
20
40
60
80
0
20
40
60
80
SFDR = 78.4dBc
SNR = 70.7dBFS
THD = 75.8dBc
−
−
−
−
−
−
−
−
SINAD = 69.8dBFS
−
−
−
−
100
120
100
120
0
0
0
5
10
15
20
25
30
35
40
40
40
0
0
0
5
10
15
20
25
30
35
40
40
40
−
−
f
Frequency MHz
−
−
f
Frequency MHz
Figure 11
Figure 12
SPECTRAL PERFORMANCE
(FFT for 300MHz Input Signal)
TWO−TONE
INTERMODULATION
0
0
−
−
−
−
−
−
−
−
20
40
60
80
20
40
60
80
−
−
−
−
100
120
100
120
5
10
15
20
25
30
35
5
10
15
20
25
30
35
−
−
−
−
f
Frequency MHz
f
Frequency MHz
Figure 13
Figure 14
TWO−TONE
INTERMODULATION
TWO−TONE
INTERMODULATION
0
0
−
−
f1 = 45.1MHz ( 7dBFS)
f2 = 50.1MHz ( 7dBFS)
2−Tone SFDR = 91.6dBc
−
−
−
−
−
−
−
−
20
40
60
80
20
40
60
80
−
−
−
−
100
120
100
120
5
10
15
20
25
30
35
5
10
15
20
25
30
35
−
−
f
Frequency MHz
−
−
f
Frequency MHz
Figure 15
Figure 16
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TYPICAL CHARACTERISTICS (continued)
Typical values at TA = +25°C, full temperature range is TMIN = −40°C to TMAX = +85°C, AVDD = DRVDD = 3.3V, sampling rate = 80MSPS,
50% clock duty cycle, 3VPP differential clock, and −1dBFS differential input, unless otherwise noted.
DIFFERENTIAL
NONLINEARITY
INTEGRAL
NONLINEARITY
1.0
0.8
0.6
0.4
0.2
0
2.0
1.5
1.0
0.5
0
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
−
−
−
−
0.5
1.0
1.5
2.0
0
2048 4096 6144 8192 10240 12288 14336 16384
Code
0
2048 4096 6144 8192 10240 12288 14336 16384
Code
Figure 17
Figure 18
SPURIOUS−FREE DYNAMIC RANGE
vs INPUT FREQUENCY
SIGNAL−TO−NOISE RATIO
vs INPUT FREQUENCY
100
95
90
85
80
75
70
65
60
76
75
74
73
72
71
70
69
68
67
0
50
100
150
200
250
300
0
50
100
150
200
250
300
−
−
Frequency MHz
Frequency MHz
Figure 19
Figure 20
AC PERFORMANCE
AC PERFORMANCE
vs ANALOG SUPPLY VOLTAGE
vs ANALOG SUPPLY VOLTAGE
100
95
90
85
80
72
70
65
60
98
94
90
86
82
48
74
70
66
fIN = 150MHz
fIN = 70MHz
SFDR
SFDR
SNR
SNR
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.0
3.1
3.2
3.3
3.4
3.5
V
3.6
−
−
−
−
AVDD Analog Supply Voltage
V
AVDD Analog Supply Voltage
Figure 21
Figure 22
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TYPICAL CHARACTERISTICS (continued)
Typical values at TA = +25°C, full temperature range is TMIN = −40°C to TMAX = +85°C, AVDD = DRVDD = 3.3V, sampling rate = 80MSPS,
50% clock duty cycle, 3VPP differential clock, and −1dBFS differential input, unless otherwise noted.
AC PERFORMANCE
AC PERFORMANCE
vs DIGITAL SUPPLY VOLTAGE
vs DIGITAL SUPPLY VOLTAGE
95
90
85
80
75
70
65
95
90
85
80
75
70
65
fIN = 150MHz
fIN = 70MHz
SFDR
SFDR
SNR
SNR
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.0
3.1
3.2
3.3
3.4
3.5
V
3.6
80
0
−
−
−
−
DVDD Digital Supply Voltage
V
DVDD Digital Supply Voltage
Figure 23
Figure 24
POWER DISSIPATION
vs SAMPLE RATE
POWER DISSIPATION
vs SAMPLE RATE
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
fIN = 70MHz
fIN = 150MHz
10
20
30
40
50
60
70
80
10
20
30
40
50
60
70
−
−
Sample Rate MSPS
Sample Rate MSPS
Figure 25
Figure 26
AC PERFORMANCE
vs TEMPERATURE
AC PERFORMANCE
vs INPUT AMPLITUDE
100
95
90
85
80
75
70
65
60
100
90
80
70
60
50
40
30
20
10
0
fIN = 70MHz
SNR (dBFS)
SFDR
SNR
SFDR (dBc)
SNR (dBc)
−
−
−
10
20
30
fIN = 70MHz
−
−
−
−
−
−
−
−
−
−
−
−
10
40
15
+10
+35
+60
+85
100 90
80
70
60
50
40
30 20
− _
−
Temperature
C
Input Amplitude dBFS
Figure 27
Figure 28
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TYPICAL CHARACTERISTICS (continued)
Typical values at TA = +25°C, full temperature range is TMIN = −40°C to TMAX = +85°C, AVDD = DRVDD = 3.3V, sampling rate = 80MSPS,
50% clock duty cycle, 3VPP differential clock, and −1dBFS differential input, unless otherwise noted.
AC PERFORMANCE
vs INPUT AMPLITUDE
AC PERFORMANCE
vs INPUT AMPLITUDE
100
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
SNR (dBFS)
SNR (dBFS)
SFDR (dBc)
SFDR (dBc)
SNR (dBc)
SNR (dBc)
−
−
−
10
20
30
−
−
−
10
20
30
fIN = 220MHz
fIN = 150MHz
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
10
100 90
80
70
60
50
40
30
20
10
0
100 90
80
70
60
50
40
30 20
0
3.0
60
−
−
Input Amplitude dBFS
Input Amplitude dBFS
Figure 29
Figure 30
OUTPUT
AC PERFORMANCE
vs CLOCK AMPLITUDE
NOISE HISTOGRAM
40
35
30
25
20
15
10
5
95
90
85
80
75
70
65
fIN = 70MHz
SFDR
SNR
0
0
0.5
1.0
1.5
2.0
2.5
−
Differential Clock Amplitude
V
Code
Figure 31
Figure 32
WCDMA
AC PERFORMANCE
vs CLOCK DUTY CYCLE
CARRIER
0
100
95
90
85
80
75
70
65
fIN = 20MHz
SFDR
−
20
40
60
80
−
−
−
−
−
−
100
120
140
SNR
0
5
10
15
20
25
30
35
40
40
45
50
55
−
−
−
Clock Duty Cycle %
f
Frequency MHz
Figure 33
Figure 34
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TYPICAL CHARACTERISTICS (continued)
Typical values at TA = +25°C, full temperature range is TMIN = −40°C to TMAX = +85°C, AVDD = DRVDD = 3.3V, sampling rate = 80MSPS,
50% clock duty cycle, 3VPP differential clock, and −1dBFS differential input, unless otherwise noted.
SIGNAL−TO−NOISE RATIO (SNR)
74
72
70
68
66
64
62
100
90
80
70
60
50
40
30
20
10
70
74
69
73
71
72
70
74
69
71
73
72
66
65
70
68
69
67
66
74
71
64
68
65
67
69
70
100
72
73
66
63
50
150
200
250
300
Input Frequency (MHz)
Figure 35
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TYPICAL CHARACTERISTICS (continued)
Typical values at TA = +25°C, full temperature range is TMIN = −40°C to TMAX = +85°C, AVDD = DRVDD = 3.3V, sampling rate = 80MSPS,
50% clock duty cycle, 3VPP differential clock, and −1dBFS differential input, unless otherwise noted.
SPURIOUS−FREE DYNAMIC RANGE (SFDR)
87
100
81
85
81
90
85
80
75
70
65
81
85
79
67
87
90
80
70
60
50
40
30
20
10
75
87
71
87
85
85
73
79
91
87
89
85
69
77
87
85
81
87
89
83
85
79
81
77
71
85
75
91
73
83
85
89
87
81
85
69
71
73
91
83
81
75
79
87
73
87
85
77
87
89
91
75
81
85
50
81
77
150
83
79
71
100
200
250
300
Input Frequency (MHz)
Figure 36
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APPLICATION INFORMATION
latency of 16.5 clock cycles, after which the output data
is available as a 14-bit parallel word, coded in either
straight offset binary or binary two’s complement
format.
THEORY OF OPERATION
The ADS5542 is a low-power, 14-bit, 80MSPS, CMOS,
switched capacitor, pipeline ADC that operates from a
single 3.3V supply. The conversion process is initiated
by a falling edge of the external input clock. Once the
signal is captured by the input S&H, the input sample is
sequentially converted by a series of small resolution
stages, with the outputs combined in a digital correction
logic block. Both the rising and the falling clock edges
are used to propagate the sample through the pipeline
every half clock cycle. This process results in a data
INPUT CONFIGURATION
The analog input for the ADS5542 consists of a
differential sample-and-hold architecture implemented
using a switched capacitor technique, shown in
Figure 37.
S3a
L1
R1a
C1a
INP
S1a
CP1
CP3
R3
S2
CA
L2
R1b
C1b
S1b
VINCM
INM
1V
CP2
CP4
S3b
−
Ω−
L1, L2 : 6nH 10nH effective
Ω
8
R1a, R1b : 5
−
C
1a, C1b : 2.2pF 2.6pF
−
CP1, CP2 : 2.5pF 3.5pF
−
CP3, CP4, : 1.2pF 1.8pF
−
CA : 0.8pF 1.2pF
Ω
Ω
R3 : 80 to 120
Switches: S1a, S1b : On Resistance: 35
Ω−
Ω−
Ω
Ω
50
Ω
S2 : On Resistance: 7.5
S3a, S3b : On Resistance: 40
15
Ω−
60
Ω
All switches Off Resistance: 10G
:
NOTE All switches are ON during sampling phase, which is approximately one half of a clock period.
Figure 37. Analog Input Stage
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This differential input topology produces a high level of
AC performance for high sampling rates. It also results
in a very high usable input bandwidth, especially
important for high intermediate-frequency (IF) or
undersampling applications. The ADS5542 requires
each of the analog inputs (INP, INM) to be externally
biased around the common-mode level of the internal
circuitry (CM, pin 17). For a full-scale differential input,
each of the differential lines of the input signal (pins 19
and 20) swings symmetrically between CM + 0.575V
and CM – 0.575V. This means that each input is driven
with a signal of up to CM 0.575V, so that each input
common-mode current in the order of 400µA (200µA
per input). Equation (1) describes the dependency of
the common-mode current and the sampling
frequency:
400mA fS (in MSPS)
80 MSPS
(1)
Where:
f > 10MSPS.
S
This equation helps to design the output capability and
impedance of the driving circuit accordingly.
When it is necessary to buffer or apply a gain to the
incoming analog signal, it is possible to combine
single-ended operational amplifiers with an RF
transformer, or to use a differential input/output
amplifier without a transformer, to drive the input of the
ADS5542. TI offers a wide selection of single-ended
operational amplifiers (including the THS3201,
THS3202, OPA847, and OPA695) that can be selected
depending on the application. An RF gain block
amplifier, such as TI’s THS9001, can also be used with
an RF transformer for very high input frequency
applications. The THS4503 is a recommended
differential input/output amplifier. Table 4 lists the
recommended amplifiers.
has a maximum differential signal of 1.15V for a total
PP
differential input signal swing of 2.3V . The maximum
PP
swing is determined by the two reference voltages, the
top reference (REFP, pin 29), and the bottom reference
(REFM, pin 30).
The ADS5542 obtains optimum performance when the
analog inputs are driven differentially. The circuit shown
in Figure 38 shows one possible configuration using an
RF transformer.
R0
Z0
Ω
50
Ω
25
Ω
50
INP
1:1
When using single-ended operational amplifiers (such
as the THS3201, THS3202, OPA847, or OPA695) to
provide gain, a three-amplifier circuit is recommended
with one amplifier driving the primary of an RF
transformer and one amplifier in each of the legs of the
secondary driving the two differential inputs of the
ADS5542. These three amplifier circuits minimize
even-order harmonics. For very high frequency inputs,
an RF gain block amplifier can be used to drive a
transformer primary; in this case, the transformer
secondary connections can drive the input of the
ADS5542 directly, as shown in Figure 38, or with the
addition of the filter circuit shown in Figure 39.
R
50
AC Signal
Source
ADS5542
INM
Ω
25
Ω
CM
ADT1−1WT
Ω
10
µ
0.1 F
1nF
Figure 38. Transformer Input to Convert
Single-Ended Signal to Differential Signal
The single-ended signal is fed to the primary winding of
an RF transformer. Placing a 25Ω resistor in series with
INP and INM is recommended to dampen ringing due
to ADC kickback. Since the input signal must be biased
around the common-mode voltage of the internal
Figure 39 illustrates how RIN and CIN can be placed to
isolate the signal source from the switching inputs of the
ADC and to implement a low-pass RC filter to limit the
input noise in the ADC. It is recommended that these
components be included in the ADS5542 circuit layout
when any of the amplifier circuits discussed previously
are used. The components allow fine-tuning of the
circuit performance. Any mismatch between the
differential lines of the ADS5542 input produces a
degradation in performance at high input frequencies,
mainly characterized by an increase in the even-order
harmonics. In this case, special care should be taken to
keep as much electrical symmetry as possible between
both inputs.
circuitry, the common-mode voltage (V ) from the
CM
ADS5542 is connected to the center-tap of the
secondary winding. To ensure a steady low-noise V
CM
reference, best performance is attained when the CM
output (pin 17) is filtered to ground with a 10Ω series
resistor and parallel 0.1µF and 0.001µF low-inductance
capacitors, as illustrated in Figure 37.
Output V
(pin 17) is designed to directly drive the
CM
ADC input. When providing a custom CM level, be
aware that the input structure of the ADC sinks a
21
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SBAS308A− MAY 2004 − REVISED MARCH 2005
Another possible configuration for lower-frequency sig-
nals is the use of differential input/output amplifiers that
can simplify the driver circuit for applications requiring
DC coupling of the input. Flexible in their configurations
(see Figure 40), such amplifiers can be used for single-
ended-to-differential conversion, signal amplification.
Table 4. Recommended Amplifiers to Drive the Input of the ADS5542
INPUT SIGNAL FREQUENCY
RECOMMENDED AMPLIFIER
THS4503
TYPE OF AMPLIFIER
Differential In/Out Amp
USE WITH TRANSFORMER?
DC to 20MHz
DC to 50MHz
No
Yes
Yes
Yes
Yes
Yes
OPA847
OPA695
THS3201
THS3202
THS9001
Operational Amp
Operational Amp
Operational Amp
Operational Amp
RF Gain Block
10MHz to 120MHz
Over 100MHz
−
+5V 5V
RS
RIN
RIN
Ω
100
µ
0.1 F
25Ω
25Ω
VIN
1:1
INP
INM
OPA695
RT
100
CIN
ADS5542
1000pF
Ω
R1
Ω
400
CM
10
AV = 8V/V
(18dB)
R2
57.5
Ω
Ω
µ
0.1 F
Figure 39. Converting a Single-Ended Input Signal to a Differential Signal Using an RF Transformer
22
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SBAS308A− MAY 2004 − REVISED MARCH 2005
RS
RG
RF
+5V
RT
+3.3V
µ
µ
0.1 F
10 F
RIN
RIN
INP
ADS5542
14−Bit/80MSPS
VOCM
INM
µ
1 F
THS4503
CM
µ
µ
0.1 F
10 F
Ω
10
−
5V
RG
RF
µ
0.1 F
Figure 40. Using the THS4503 with the ADS5542
INPUT VOLTAGE OVER-STRESS
POWER SUPPLY SEQUENCE
The ADS5542 can handle absolute maximum voltages
of 3.6V DC on the input pins INP and INM. For DC inputs
between 3.6V and 3.8V, a 25Ω resistor is required in
series with the input pins. For inputs above 3.8V, the
device can handle only transients, which need to have
less than 5% duty cycle of overstress. The input pins
The preferred mode of power supply sequencing is to
power-up AV first, followed by DRV . Raising both
DD
DD
supplies simultaneously is also a valid power supply
sequence. In the event that DRV powers up before
DD
AV in the system, AV must power up within 10ms
DD
DD
of DRV
.
DD
connect internally to an ESD diode to AV , as well as
DD
a switched capacitor circuit. The sampling capacitor of
the switched capacitor circuit connects to the input pins
through a switch in the sample phase. In this phase, an
input larger then 2.65V would cause the switched
capacitor circuit to present an equivalent load of a
forward biased diode to 2.65V, in series with a
POWER DOWN
The device will enter power-down mode in one of two
ways: either by reducing the clock speed to between DC
and 1MHz, or by setting a bit through the serial
programming interface. If reducing the clock speed,
power-down may be initiated for any clock frequency
below 10MHz. The actual frequency at which the device
powers down varies from device to device.
60Ω impedance. Also, beyond the voltage on AV , the
DD
ESD diode to AV starts to become forward biased.
DD
In the phase where the sampling switch is off, the diode
loading from the input switched capacitor circuit is
disconnected from the pin, while the ESD loading to
The device can be powered down by programming the
internal register (see Serial Programming Interface
section). The outputs become tri-stated and only the
internal reference is powered up to shorten the
power-up time. The Power-Down mode reduces power
dissipation to a minimum of 180mW.
AV is still present.
DD
CAUTION:
A violation of any of the previously stated
conditions could damage the device (or reduce
its lifetime) either due to electromigration or
gate oxide integrity. Care should be taken not
to expose the device to input over-voltage for
extended periods of time as it may degrade
device reliability.
23
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SBAS308A− MAY 2004 − REVISED MARCH 2005
REFERENCE CIRCUIT
CM
CM
The ADS5542 has built-in internal reference
generation, requiring no external circuitry on the printed
circuit board (PCB). For optimum performance, it is best
to connect both REFP and REFM to ground with a 1µF
decoupling capacitor in series with a 1Ω resistor, as
shown in Figure 41. In addition, an external 56.2kΩ
resistor should be connected from IREF (pin 31) to
AGND to set the proper current for the operation of the
ADC, as shown in Figure 41. No capacitor should be
connected between pin 31 and ground; only the 56.2kΩ
resistor should be used.
Ω
Ω
5k
5k
CLKP
CLKM
6pF
3pF
3pF
Ω
1
REFP
REFM
29
30
Figure 42. Clock Inputs
µ
1 F
Ω
1
When driven with a single-ended CMOS clock input, it
is best to connect CLKM (pin 11) to ground with a
0.01µF capacitor, while CLKP is AC-coupled with a
0.01µF capacitor to the clock source, as shown in
Figure 43.
µ
1 F
31 IREF
56kΩ
µ
0.01 F
Square Wave
or Sine Wave
CLKP
ADS5542
CLKM
Figure 41. REFP, REFM, and IREF Connections
for Optimum Performance
(3VPP
)
CLOCK INPUT
µ
0.01 F
The ADS5542 clock input can be driven with either a
differential clock signal or a single-ended clock input,
with little or no difference in performance between both
configurations. The common-mode voltage of the clock
inputs is set internally to CM (pin 17) using internal 5kΩ
resistors that connect CLKP (pin 10) and CLKM (pin 11)
to CM (pin 17), as shown in Figure 42.
Figure 43. AC-Coupled, Single-Ended Clock Input
The ADS5542 clock input can also be driven
differentially, reducing susceptibility to common-mode
noise. In this case, it is best to connect both clock inputs
to the differential input clock signal with 0.01µF
capacitors, as shown in Figure 44.
24
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SBAS308A− MAY 2004 − REVISED MARCH 2005
95
90
85
80
75
70
65
µ
0.01 F
fIN = 70MHz
CLKP
ADS5542
CLKM
Differential Square Wave
or Sine Wave
(3VPP
SFDR
)
µ
0.01 F
Figure 44. AC-Coupled, Differential Clock Input
SNR
For high input frequency sampling, it is recommended
to use a clock source with very low jitter. Additionally,
the internal ADC core uses both edges of the clock for
the conversion process. This means that, ideally, a 50%
duty cycle should be provided. Figure 45 shows the
performance variation of the ADC versus clock duty
cycle.
0
0.5
1.0
1.5
2.0
2.5
3.0
−
Differential Clock Amplitude
V
Figure 46. AC Performance vs Clock Amplitude
OUTPUT INFORMATION
The ADC provides 14 data outputs (D13 to D0, with D13
being the MSB and D0 the LSB), a data-ready signal
(CLKOUT, pin 43), and an out-of-range indicator (OVR,
pin 64) that equals 1 when the output reaches the
full-scale limits.
100
fIN = 20MHz
SFDR
95
90
85
80
75
70
65
Two different output formats (straight offset binary or
two’s complement) and two different output clock
polarities (latching output data on rising or falling edge
of the output clock) can be selected by setting DFS
(pin 40) to one of four different voltages. Table 3 details
the four modes. In addition, output enable control (OE,
pin 41, active high) is provided to put the outputs into a
high-impedance state.
SNR
40
45
50
55
60
−
Clock Duty Cycle
%
In the event of an input voltage overdrive, the digital
outputs go to the appropriate full-scale level. For a
positive overdrive, the output code is 0xFFF in straight
offset binary output format, and 0x7FF in 2’s
complement output format. For a negative input
overdrive, the output code is 0x000 in straight offset
binary output format, and 0x800 in 2’s complement
output format. These outputs to an overdrive signal are
ensured through design and characterization
Figure 45. AC Performance vs Clock Duty Cycle
Bandpass filtering of the source can help produce a
50% duty cycle clock and reduce the effect of jitter.
When using a sinusoidal clock, the clock jitter will further
improve as the amplitude is increased. In that sense,
using a differential clock allows for the use of larger
amplitudes without exceeding the supply rails and
absolute maximum ratings of the ADC clock input.
Figure 46 shows the performance variation of the
device versus input clock amplitude. For detailed
clocking schemes based on transformer or PECL-level
clocks, refer to the ADS55xxEVM User’s Guide
(SLWU010), available for download from www.ti.com.
The output circuitry of the ADS5542, by design,
minimizes the noise produced by the data switching
transients, and, in particular, its coupling to the ADC
analog circuitry. Output D2 (pin 51) senses the load
capacitance and adjusts the drive capability of all the
output pins of the ADC to maintain the same output slew
25
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SBAS308A− MAY 2004 − REVISED MARCH 2005
rate described in the timing diagram of Figure 1. Care
should be taken to ensure that all output lines (including
CLKOUT) have nearly the same load as D2 (pin 51).
This circuit also reduces the sensitivity of the output
timing versus supply voltage or temperature. Placing
external resistors in series with the outputs is not
recommended.
The ADS5542 internal registers default to all zeros on
reset. The device is reset by applying a high pulse on
the RESET pin (pin 35) for a minimum of 2µs at least
10ms after both the AV and DRV power supplies
DD
DD
have come up (as illustrated in Figure 2) In reset, the
ADC outputs are forced low. Note that the RESET pin
has a 200kΩ pull-up resistor to AV
.
DD
The timing characteristics of the digital outputs change
for sampling rates below the 80MSPS maximum
sampling frequency. Table 5 shows the timing
parameters for sampling rates of 20MSPS, 40MSPS,
and 65MSPS.
If the ADS5542 is to be used solely in the default mode
set at reset, the serial interface pins can be tied to fixed
voltages. In this case, tie SCLK high, SEN low, and
SDATA to either a high or low voltage.
To use the input clock as the data capture clock, it is
PowerPAD Package
necessary to delay the input clock by a delay, t , that
d
The PowerPAD package is a thermally-enhanced
standard size IC package designed to eliminate the use
of bulky heatsinks and slugs traditionally used in
thermal packages. This package can be easily mounted
using standard PCB assembly techniques, and can be
removed and replaced using standard repair
procedures.
results in the desired setup or hold time. Use either of
the following equations to calculate the value of t .
d
Desired setup time = t − t
d
START
Desired hold time = t
− t
d
END
SERIAL PROGRAMMING INTERFACE
The PowerPAD package is designed so that the
leadframe die pad (or thermal pad) is exposed on the
bottom of the IC. This provides an extremely low
thermal resistance path between the die and the
exterior of the package. The thermal pad on the bottom
of the IC can then be soldered directly to the PCB, using
the PCB as a heatsink.
The ADS5542 has internal registers that enable the
programming of the device into modes as described in
previous sections. Programming is done through a
3-wire serial interface. The timing diagram and register
settings in the Serial Programming Interface section
describe the use of this interface.
Table 2 shows the different modes and the bit values to
be written to the register to enable them.
Table 5. Timing Characteristics at Additional Sampling Frequencies
fS
(MSPS)
tSETUP (ns)
tHOLD (ns)
tSTART (ns)
tEND (ns)
tRISE (ns)
tFALL (ns)
TYP
MIN
4.3
8.5
TYP
5.7
MAX
MIN
2
TYP
MAX
MIN
TYP
MAX
MIN
8.3
8.9
9.5
TYP
MAX
MIN
TYP
MAX
7.2
8
MIN
MAX
6.4
7.8
8
65
40
20
3
2.8
−1
4.5
1.5
2
11.8
14.5
21.6
6.6
7.5
7.5
5.5
11.0
2.6
2.5
3.5
4.7
7.3
17.0 25.7
−9.8
8
7.6
26
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SBAS308A− MAY 2004 − REVISED MARCH 2005
Assembly Process
5. Do not use the typical web or spoke via connection
pattern when connecting the thermal vias to the
ground plane. The spoke pattern increases the
thermal resistance to the ground plane.
1. Prepare the PCB top-side etch pattern including
etch for the leads as well as the thermal pad as
illustrated in the Mechanical Data section.
6. The top−side solder mask should leave exposed
the terminals of the package and the thermal pad
area.
2. Place a 5-by-5 array of thermal vias in the thermal
pad area. These holes should be 13 mils in
diameter. The small size prevents wicking of the
solder through the holes.
7. Cover the entire bottom side of the PowerPAD vias
to prevent solder wicking.
3. It is recommended to place a small number of 25 mil
diameter holes under the package, but outside the
thermal pad area to provide an additional heat path.
8. Apply solder paste to the exposed thermal pad area
and all of the package terminals.
4. Connect all holes (both those inside and outside the
thermal pad area) to an internal copper plane (such
as a ground plane).
For more detailed information regarding the PowerPAD
package and its thermal properties, please refer to
either Application Brief SLMA004B (PowerPAD Made
Easy), or Technical Brief SLMA002 (PowerPAD
Thermally Enhanced Package), both available for
download at www.ti.com.
27
PACKAGE OPTION ADDENDUM
www.ti.com
7-Apr-2005
PACKAGING INFORMATION
Orderable Device
ADS5542IPAP
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
HTQFP
PAP
64
64
64
64
160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
ADS5542IPAPG4
ADS5542IPAPR
ADS5542IPAPRG4
HTQFP
HTQFP
HTQFP
PAP
PAP
PAP
160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
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