DAC8830_技术文档

B

u

r

Ć

B

r

o

w

n

P

r

o

d

u

c

t

s

DAC8830

DAC8831

f

r

o

m

T

e

x

a

s

I

n

s

t

r

u

m

e

n

t

s

®

SLAS449C–FEBRUARY 2005–REVISED NOVEMBER 2006

16-Bit, Ultra-Low Power, Voltage-Output

Digital-to-Analog Converters

FEATURES

DESCRIPTION

•

16-Bit Resolution

The DAC8830 and DAC8831 are single, 16-bit,

serial-input, voltage-output digital-to-analog

2.7 V to 5.5 V Single-Supply Operation

Very Low Power: 15 µW for 3 V Power

High Accuracy, INL: 1 LSB

Low Glitch: 10 nV-s

converters (DACs) operating from a single 3 V to 5 V

power supply. These converters provide excellent

linearity (1 LSB INL), low glitch, low noise, and fast

settling (1.0 µS to 1/2 LSB of full-scale output) over

the specified temperature range of –40°C to +85°C.

The output is unbuffered, which reduces the power

consumption and the error introduced by the buffer.

Low Noise: 10 nV/√Hz

Fast Settling: 1.0 µS

Fast SPI™ Interface, up to 50 MHz

Reset to Zero-Code

These parts feature a standard high-speed (clock up

to 50 MHz), 3 V or 5 V SPI serial interface to

communicate with the DSP or microprocessors.

Schmitt-Trigger Inputs for Direct Optocoupler

Interface

The DAC8830 output is 0 V to V_REF. However, the

DAC8831 provides bipolar output (±V_REF) when

working with an external buffer. The DAC8830 and

DAC8831 are both reset to zero-code after power

up. For optimum performance, a set of Kelvin

connections to external reference and analog ground

input are provided on the DAC8831.

•

Industry-Standard Pin Configuration

APPLICATIONS

•

Portable Equipment

Automatic Test Equipment

Industrial Process Control

Data Acquisition Systems

Optical Networking

The DAC8830 is available in an SO-8 package, and

the DAC8831 in an SO-14 package. Both have

industry standard pinouts (see Table 3, the

cross-reference table in the Application Information

section for details). The DAC8831 is also available in

a QFN-14 package.

DAC8830

DAC8831

Functional Block Diagram

V_DD

−

V_REF

−

F

S

V_REF

R_INVR_FB

RFB

INV

V_OUT

DAC

V_REF

CS

+V

LDAC

V_O

−

+

V_OUT

DAC

AGND

CS

SCLK

SDI

−

V

OPA277

OPA704

OPA727

SCLK

SDI

Input

Register

AGNDF

AGNDS

DAC Latch

Input

Register

DAC Latch

DAC8830

DAC8831

DGND

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SPI, QSPI are trademarks of Motorola, Inc.

Microwire is a trademark of National Semiconductor Corp.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

DAC8830

DAC8831

www.ti.com

SLAS449C–FEBRUARY 2005–REVISED NOVEMBER 2006

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be

more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

ORDERING INFORMATION⁽¹⁾

MINIMUM

RELATIVE

ACCURACY

(LSB)

POWER-

ON

RESET

VALUE

DIFFERENTIAL

NONLINEARITY

(LSB)

SPECIFIED

TEMPERATURE

RANGE

TRANSPORT

MEDIA,

QUANTITY

PACKAGE PACKAGE-

PACKAGE

DESIGNATOR

ORDERING

NUMBER

PRODUCT

MARKING

LEAD

DAC8830ID

DAC8830IDR

Tubes, 75

DAC8830ID

±4

±2

±1

±4

±2

±1

±4

±2

±1

Zero-Code

–40°C to +85°C

8830I

SO-8

D

Tape and Reel, 2500

Tubes, 75

DAC8830IBD

DAC8830ICD

DAC8831ID

8830I

8831I

SO-8

DAC8830IBDR

DAC8830ICD

Tape and Reel, 2500

Tubes, 75

D

DAC8830ICDR

DAC8831ID

Tape and Reel, 2500

Tube, 50

SO-14

QFN-14

D

DAC8831IDR

Tape and Reel, 2500

Tube, 50

DAC8831IBD

DAC8831ICD

DAC8831IRGY

DAC8831IBRGY

DAC8831ICRGY

D

DAC8831IBDR

DAC8831ICD

Tape and Reel, 2500

Tube, 50

D

DAC8831ICDR

DAC8831IRGYT

DAC8831IRGYR

DAC8831IBRGYT

DAC8831IBRGYR

DAC8831ICRGYT

DAC8831ICRGYR

Tape and Reel, 2500

Tape and Reel, 250

Tape and Reel, 1000

Tape and Reel, 250

Tape and Reel, 1000

Tape and Reel, 250

Tape and Reel, 1000

RGY

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI

website at www.ti.com.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

DAC8830, DAC8831

–0.3 to +7

UNIT

V

V_DDto AGND

Digital input voltage to DGND

V_OUTto AGND

–0.3 to +V_DD+ 0.3

–0.3 to +0.3

–40 to +85

–65 to +150

+150

V

AGND, AGNDF, AGNDS to DGND

Operating temperature range

Storage temperature range

Junction temperature range (T_Jmax)

Power dissipation

V

°C

(T_Jmax - T_A) / θ_JA

54.9

W

QFN-14

SO-8

°C/W

Thermal impedance, θ_JA

136.9

SO-14

66.6

(1) Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. Exposure to absolute

maximum conditions for extended periods may affect device reliability.

2

Submit Documentation Feedback

DAC8830

DAC8831

www.ti.com

SLAS449C–FEBRUARY 2005–REVISED NOVEMBER 2006

ELECTRICAL CHARACTERISTICS

All specifications at T_A= T_MINto T_MAX, V_DD= +3 V or V_DD= +5 V, V_REF= +2.5 V unless otherwise noted; specifications subject

to change without notice.

DAC8830, DAC8831

PARAMETER

STATIC PERFORMANCE

CONDITIONS

MIN

TYP

MAX

UNIT

Resolution

16

bits

DAC8830ICD,

DAC8831ICD,

DAC8831ICRGY

±0.5

±1

±2

±4

DAC8830IBD,

DAC8831IBD,

DAC8831IBRGY

Linearity error

LSB

DAC8830ID,

DAC8831ID,

DAC8831IRGY

Differential linearity error

All grades

±0.5

±1

±5

±7

LSB

T_A= +25°C

Gain error

T_A= –40°C to +85°C

Gain drift

±0.1

ppm/°C

LSB

T_A= +25°C

±0.25

±1

±2

Zero code error

T_A= –40°C to +85°C

Zero code drift

±0.05

ppm/°C

OUTPUT CHARACTERISTICS

All devices

Unipolar operation

Bipolar operation

0

+V_REF

V

Voltage output⁽¹⁾

DAC8831 only

–V_REF

Output impedance

Settling time

6.25

1

kΩ

To 1/2 LSB of FS, C_L= 10 pF

C_L= 10 pF

µs

Slew rate⁽²⁾

25

10

0.2

10

18

V/µs

nV-s

Digital-to-analog glitch

Digital feedthrough⁽³⁾

1 LSB change around major carry

DAC8830

DAC8831

Output noise

T_A= +25°C

nV/√Hz

Power-supply rejection

V_DDvaries ±10%

R_FB/ R_INV

±1

LSB

Ω/Ω

%

1

±0.0015

±0.25

Bipolar resistor

matching

DAC8831 only

Ratio error

±0.0076

±5

T_A= +25°C

Bipolar zero error

Bipolar zero drift

DAC8831 only

LSB

T_A= –40°C to +85°C

±7

±0.2

ppm/°C

(1) The DAC8830 output is unipolar (0 V to +V_REF). The DAC8831 output is bipolar (±V_REF) when it connects to an external buffer (see the

Bipolar Output Operation section for details).

(2) Slew Rate is measure from 10% to 90% of transition when the output changes from 0 to full scale.

(3) Digital feedthrough is defined as the impulse injected into the analog output from the digital input. It is measured when the DAC output

does not change; CS is held high, while SCLK and DIN signals are toggled.

3

Submit Documentation Feedback

DAC8830

DAC8831

www.ti.com

SLAS449C–FEBRUARY 2005–REVISED NOVEMBER 2006

ELECTRICAL CHARACTERISTICS (continued)

All specifications at T_A= T_MINto T_MAX, V_DD= +3 V or V_DD= +5 V, V_REF= +2.5 V unless otherwise noted; specifications subject

to change without notice.

DAC8830, DAC8831

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

REFERENCE INPUT

Reference input voltage range

Reference input impedance⁽⁴⁾

1.25

9

V_DD

V

Unipolar mode

kΩ

Bipolar mode, DAC8831

Code = FFFFh

7.5

Reference –3dB bandwidth, BW

Reference feedthrough

1.3

1

MHz

mV

dB

Code = 0000h, V_REF= 1 V_PPat 100 kHz

Signal-to-noise ratio, SNR

92

75

120

Code = 0000h

Code = FFFFh

Reference input capacitance

pF

DIGITAL INPUTS

V_DD= 2.7 V

V_DD= 5 V

V_DD= 2.7 V

V_DD= 5 V

0.6

0.8

V_IL

V_IH

Input low voltage

Input high voltage

V

2.1

2.4

Input current

±1

µA

pF

V

Input capacitance

Hysteresis voltage

10

0.4

POWER SUPPLY

V_DDPower-supply voltage

2.7

5.5

20

V

V_DD= 3 V

V_DD= 5 V

V_DD= 3 V

V_DD= 5 V

5

I_DD

Power-supply current

Power

µA

20

15

25

60

µW

°C

100

TEMPERATURE RANGE

Specified performance

–40

+85

(4) Reference input resistance is code-dependent, minimum at 8555h.

4

Submit Documentation Feedback

DAC8830

DAC8831

www.ti.com

SLAS449C–FEBRUARY 2005–REVISED NOVEMBER 2006

PIN CONFIGURATION (NOT TO SCALE)

D PACKAGE

SO-8

D PACKAGE

SO-14

RGY PACKAGE

QFN-14

(TOP VIEW)

V_OUT

AGND

V_REF

V_DD

1

2

3

4

8

7

6

5

1

2

3

4

5

6

7

14

13

12

11

10

9

V_DD

RFB

V_OUT

INV

DGND

SDI

13 12 11 10

9

DGND

LDAC

SDI

AGNDF

AGNDS

V_REF−S

V_REF−F

CS

SCLK

V_DD14

8

7

SCLK

CS

NC

DAC8831

Thermal Pad⁽¹⁾

8

SCLK

RFB

1

2

3

4

5

6

NOTE: (1) Exposed thermal pad in the QFN package

must be connected to analog ground.

TERMINAL FUNCTIONS

TERMINAL

DESCRIPTION

NO.

NAME

DAC8830

1

V_OUT

Analog output of DAC

Analog ground

2

AGND

V_REF

CS

3

Voltage reference input

4

Chip select input (active low). Data is not clocked into SDI unless CS is low

Serial clock input

5

SCLK

SDI

6

Serial data input. Data is latched into input register on the rising edge of SCLK.

Digital ground

7

DGND

V_DD

8

Analog power supply, +3 V to +5 V

DAC8831

1

2

RFB

Feedback resistor. Connect to the output of external operational amplifier in bipolar mode.

Analog output of DAC

V_OUT

3

AGNDF Analog ground (Force)

AGNDS Analog ground (Sense)

4

5

V_REF–

CS

S

Voltage reference input (Sense). Connect to external voltage reference

Voltage reference input (Force). Connect to external voltage reference

Chip select input (active low). Data is not clocked into SDI unless CS is low.

Serial clock input.

6

F

7

8

SCLK

NC

9

No internal connection

10

SDI

Serial data input. Data is latched into input register on the rising edge of SCLK.

Load DAC control input. Active low. When LDAC is Low, the DAC latch is simultaneously updated with the

content of the input register.

11

12

13

14

LDAC

DGND

INV

Digital ground

Junction point of internal scaling resistors. Connect to external operational amplifier inverting input in bipolar

mode.

V_DD

Analog power supply, +3 V to +5 V.

5

Submit Documentation Feedback

DAC8830

DAC8831

www.ti.com

SLAS449C–FEBRUARY 2005–REVISED NOVEMBER 2006

t

td

CS

DAC

Updated

t

Delay

t

sck

t

Lead

t

DSCLK

t

wsck

Lag

wsck

SCLK

SDI

t

su

ho

BIT15 (MSB)

−−−Don’t Care

BIT13, . . . ,1

BIT0

BIT14

Figure 1. DAC8830 Timing Diagram

Case1: LDAC tied to LOW

CS

t

td

DAC

Updated

t

Delay

t

sck

t

Lead

t

DSCLK

t

wsck

Lag

wsck

SCLK

t

su

ho

SDI

BIT 15 (MSB)

BIT 14

BIT 13, . . . ,1

BIT 0

LDAC

LOW

−−−Don’t Care

Case2: LDAC Active

CS

t

td

t

Delay

t

sck

t

Lead

t

DSCLK

t

wsck

Lag

wsck

SCLK

SDI

t

su

ho

BIT 15 (MSB)

BIT 14

BIT 13, . . . ,1

BIT 0

t

WLDAC

DLADC

DAC

HIGH

LDAC

Updated

−−−Don’t Care

Figure 2. DAC8831 Timing Diagram

6

Submit Documentation Feedback

DAC8830

DAC8831

www.ti.com

SLAS449C–FEBRUARY 2005–REVISED NOVEMBER 2006

TIMING CHARACTERISTICS: V_DD= +5 V⁽¹⁾⁽²⁾

At –40°C to +85°C, unless otherwise noted.

PARAMETER

MIN

20

10

30

10

0

MAX

UNIT

ns

µs

t_sck

SCLK period

t_wsck

t_Delay

t_Lead

t_Lag

SCLK high or low time

Delay from SCLK high to CS low

CS enable lead time

CS enable lag time

t_DSCLK

t_td

Delay from CS high to SCLK high

CS high between active period

Data setup time (input)

Data hold time (input)

t_su

t_ho

t_WLDAC

t_DLDAC

LDAC width

30

10

Delay from CS high to LDAC low

V_DDhigh to CS low (power-up delay)

(1) Assured by design. Not production tested.

(2) Sample tested during the initial release and after any redesign or process changes that may affect this parameter.

TIMING CHARACTERISTICS: V_DD= +3 V⁽¹⁾⁽²⁾

At –40°C to +85°C, unless otherwise noted.

PARAMETER

MIN

20

10

30

10

0

MAX

UNIT

ns

µs

t_sck

SCLK period

t_wsck

t_Delay

t_Lead

t_Lag

SCLK high or low time

Delay from SCLK high to CS low

CS enable lead time

CS enable lag time

t_DSCLK

t_td

Delay from CS high to SCLK high

CS high between active period

Data setup time (input)

t_su

t_ho

Data hold time (input)

t_WLDAC

t_DLDAC

LDAC width

30

10

Delay from CS high to LDAC low

V_DDhigh to CS low (power-up delay)

(1) Assured by design. Not production tested.

(2) Sample tested during the initial release and after any redesign or process changes that may affect this parameter.

7

Submit Documentation Feedback

DAC8830

DAC8831

www.ti.com

SLAS449C–FEBRUARY 2005–REVISED NOVEMBER 2006

TYPICAL CHARACTERISTICS: V_DD= +5 V

At T_A= +25°C and V_REF= +2.5 V, unless otherwise noted.

LINEARITY ERROR

vs DIGITAL INPUT CODE

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE

1.00

0.75

0.50

0.25

0

1.00

0.75

0.50

0.25

0

_

T_A= +25 C

_

T_A= +25 C

V_REF= 2.5 V

−

0.25

0.50

0.75

1.00

0.25

0.50

0.75

1.00

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 3.

Figure 4.

LINEARITY ERROR

vs DIGITAL INPUT CODE

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE

1.00

0.75

0.50

0.25

0

1.00

0.75

0.50

0.25

0

−

_

−

_

T_A

= 40 C

T_A

= 40 C

V_REF= 2.5 V

−

0.25

0.50

0.75

1.00

0.25

0.50

0.75

1.00

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 5.

Figure 6.

LINEARITY ERROR

vs DIGITAL INPUT CODE

DIFFERENTIAL LINEARY ERROR

vs DIGITAL INPUT CODE

1.00

0.75

0.50

0.25

0

1.00

0.75

0.50

0.25

0

_

T_A= +85 C

V_REF= 2.5 V

−

0.25

0.50

0.75

1.00

0.25

0.50

0.75

1.00

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 7.

Figure 8.

8

Submit Documentation Feedback

DAC8830

DAC8831

www.ti.com

SLAS449C–FEBRUARY 2005–REVISED NOVEMBER 2006

TYPICAL CHARACTERISTICS: V_DD= +5 V (continued)

At T_A= +25°C and V_REF= +2.5 V, unless otherwise noted.

LINEARITY ERROR

vs DIGITAL INPUT CODE

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE

1.00

0.75

0.50

0.25

0

_

T_A= +25 C

0.75

V_REF= 5 V

0.50

0.25

0

−

0.25

0.50

0.75

1.00

0.25

−

0.50

0.75

1.00

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 9.

Figure 10.

LINEARITY ERROR

vs REFERENCE VOLTAGE

LINEARITY ERROR

vs SUPPLY VOLTAGE

0.75

0.50

0.25

0

0.75

0.50

0.25

0

V_REF= 2.5 V

DNL

INL

−

0.25

0.50

0.25

0.50

−

0

1

2

3

4

5

6

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Reference Voltage (V)

Supply Voltage (V)

Figure 11.

Figure 12.

GAIN ERROR

vs TEMPERATURE

ZERO-CODE ERROR

vs TEMPERATURE

1.25

1.00

0.75

0.50

0.25

0

0.50

0.25

0

Bipolar Mode

V_REF= 2.5 V

Bipolar Mode

Unipolar Mode

−

0.25

0.50

0.75

0.25

0.50

Unipolar Mode

V_REF= 2.5 V

−

60

40 20

0

20

40

60

80 100 120 140

60

40 20

0

20

40

60

80 100 120 140

_

Temperature ( C)

Figure 13.

Figure 14.

9

Submit Documentation Feedback

DAC8830

DAC8831

www.ti.com

SLAS449C–FEBRUARY 2005–REVISED NOVEMBER 2006

TYPICAL CHARACTERISTICS: V_DD= +5 V (continued)

At T_A= +25°C and V_REF= +2.5 V, unless otherwise noted.

REFERENCE CURRENT

vs CODE (UNIPOLAR MODE)

REFERENCE CURRENT

vs CODE (BIPOLAR MODE)

300

250

200

150

100

50

V_REF= 2.5 V

250

200

150

100

50

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

0

60

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 15.

Figure 16.

SUPPLY CURRENT

vs DIGITAL INPUT VOLTAGE

SUPPLY CURRENT

vs TEMPERATURE

800

5

4

3

2

1

0

V_REF= 2.5 V

700

600

500

400

300

200

100

0

V_DD= 5 V

V_LOGIC= 5 V

V_DD= 3 V

V_LOGIC= 3 V

V_DD= 3 V

0

1

2

3

4

5

−

20

40

0

20 40

60

80 100 120 140

Digital Input Voltage (V)

_

Temperature ( C)

Figure 17.

Figure 18.

SUPPLY CURRENT

vs SUPPLY VOLTAGE

SUPPLY CURRENT

vs REFERENCE VOLTAGE

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

V_REF= 2.5 V

V_DD= 5 V

V_DD= 3 V

2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7 6.0

Supply Voltage (V)

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Reference Voltage (V)

Figure 19.

Figure 20.

10

Submit Documentation Feedback

DAC8830

DAC8831

www.ti.com

SLAS449C–FEBRUARY 2005–REVISED NOVEMBER 2006

TYPICAL CHARACTERISTICS: V_DD= +5 V (continued)

At T_A= +25°C and V_REF= +2.5 V, unless otherwise noted.

MAJOR-CARRY GLITCH

(FALLING)

MAJOR-CARRY GLITCH

(RISING)

V_REF= 2.5 V

5V/div

LDAC

V_OUT

0.1V/div

µ

Time (0.5 s/div)

Figure 21.

Figure 22.

DAC SETTLING TIME

(FALLING)

DAC SETTLING TIME

(RISING)

V_REF= 2.5 V

5V/div

1V/div

5V/div

LDAC

V_OUT

1V/div

µ

Time (0.2 s/div)

Figure 23.

Figure 24.

DIGITAL

FEEDTHROUGH

V_REF= 2.5 V

SDI

5V/div

V_OUT

20mV/div

Time (50ns/div)

Figure 25.

11

Submit Documentation Feedback

DAC8830

DAC8831

www.ti.com

SLAS449C–FEBRUARY 2005–REVISED NOVEMBER 2006

TYPICAL CHARACTERISTICS: V_DD= +3 V

At T_A= +25°C and V_REF= +2.5 V, unless otherwise noted.

LINEARITY ERROR

vs DIGITAL INPUT CODE

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE

1.00

0.75

0.50

0.25

0

1.00

0.75

0.50

0.25

0

_

T_A= +25 C

V_REF= 1.5 V

−

0.25

0.50

0.75

1.00

0.25

0.50

0.75

1.00

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 26.

Figure 27.

LINEARITY ERROR

vs DIGITAL INPUT CODE

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE

1.00

0.75

0.50

0.25

0

1.00

0.75

0.50

0.25

0

−

_

−

_

T_A

=

40 C

T_A= 40 C

V_REF= 1.5 V

−

0.25

0.50

0.75

1.00

0.25

0.50

0.75

1.00

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 28.

Figure 29.

LINEARITY ERROR

vs DIGITAL INPUT CODE

DIFFERENTIAL LINEARY ERROR

vs DIGITAL INPUT CODE

1.00

0.75

0.50

0.25

0

1.00

0.75

0.50

0.25

0

_

T_A= +85 C

V_REF= 1.5 V

−

0.25

0.50

0.75

1.00

0.25

0.50

0.75

1.00

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 30.

Figure 31.

12

Submit Documentation Feedback

DAC8830

DAC8831

www.ti.com

SLAS449C–FEBRUARY 2005–REVISED NOVEMBER 2006

TYPICAL CHARACTERISTICS: V_DD= +3 V (continued)

At T_A= +25°C and V_REF= +2.5 V, unless otherwise noted.

LINEARITY ERROR

vs DIGITAL INPUT CODE

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE

1.00

0.75

0.50

0.25

0

1.00

_

T_A= +25 C

0.75

0.50

0.25

0

V_REF= 3 V

−

0.25

0.50

0.75

1.00

0.25

0.50

0.75

1.00

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 32.

Figure 33.

LINEARITY ERROR

vs REFERENCE VOLTAGE

GAIN ERROR

vs TEMPERATURE

1.00

0.75

0.50

0.25

0

0.75

0.50

0.25

0

Bipolar Mode

DNL

Unipolar Mode

−

0.25

0.50

0.75

1.00

−

0.25

0.50

V_DD= 3 V

V_REF= 2.5 V

−

INL

0.5

1.0

1.5

2.0

2.5

3.0

3.5

−

60

40 20

0

20

40

60

80 100 120 140

_

Temperature ( C)

Reference Voltage (V)

Figure 34.

Figure 35.

ZERO-CODE ERROR

vs TEMPERATURE

REFERENCE CURRENT

vs CODE (UNIPOLAR MODE)

0.50

0.25

0

300

250

200

150

100

50

V_DD= 3 V

V_REF= 2.5 V

V_REF= 1.5 V

Unipolar Mode

−

0.25

0.50

0.75

Bipolar Mode

−

0

−

60

40 20

0

20

40

60

80 100 120 140

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

_

Temperature ( C)

Figure 36.

Figure 37.

13

Submit Documentation Feedback

DAC8830

DAC8831

www.ti.com

SLAS449C–FEBRUARY 2005–REVISED NOVEMBER 2006

TYPICAL CHARACTERISTICS: V_DD= +3 V (continued)

At T_A= +25°C and V_REF= +2.5 V, unless otherwise noted.

REFERENCE CURRENT

vs CODE (BIPOLAR MODE)

DIGITAL

FEEDTHROUGH

300

V_REF= 2.5 V

V_REF= 1.5 V

250

200

150

100

50

SDI

5V/div

V_OUT

20mV/div

0

Time (50ns/div)

0

8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Figure 38.

Figure 39.

MAJOR-CARRY GLITCH

(FALLING)

MAJOR-CARRY GLITCH

(RISING)

V_REF= 2.5 V

5V/div

LDAC

V_OUT

0.1V/div

µ

Time (0.5 s/div)

Figure 40.

Figure 41.

DAC SETTLING TIME

(FALLING)

DAC SETTLING TIME

(RISING)

V_REF= 2.5 V

5V/div

1V/div

LDAC

V_OUT

1V/div

µ

Time (0.2 s/div)

Figure 42.

Figure 43.

14

Submit Documentation Feedback

DAC8830

DAC8831

www.ti.com

SLAS449C–FEBRUARY 2005–REVISED NOVEMBER 2006

THEORY OF OPERATION

GENERAL DESCRIPTION

The DAC8830 and DAC8831 are single, 16-bit, serial-input, voltage-output DACs. They operate from a single

supply ranging from 2.7 V to 5 V, and typically consume 5 µA. Data is written to these devices in a 16-bit word

format, via an SPI serial interface. To ensure a known power-up state, these parts are designed with a power-on

reset function. The DAC8830 and DAC8831 are reset to zero code. In unipolar mode, the DAC8830 and

DAC8831 are reset to 0V, and in bipolar mode, the DAC8831 is reset to –V_REF. Kelvin sense connections for the

reference and analog ground are included on the DAC8831.

DIGITAL-TO-ANALOG SECTIONS

The DAC architecture for both devices consists of two matched DAC sections and is segmented. A simplified

circuit diagram is shown in Figure 44. The four MSBs of the 16-bit data word are decoded to drive 15 switches,

E1 to E15. Each of these switches connects one of 15 matched resistors to either AGND or V_REF. The remaining

12 bits of the data word drive switches S0 to S11 of a 12-bit voltage mode R-2R ladder network.

R

V_OUT

2R

S0

S1

S11

E1

E2

E15

V_REF

12−Bit R−2R Ladder

Four MSBs Decoded into

15 Equal Segments

Figure 44. DAC Architecture

OUTPUT RANGE

The output of the DAC is

V_OUT= (V_REF× Code)/65536.

Where Code is the decimal data word loaded to the DAC latch.

15

Submit Documentation Feedback

DAC8830

DAC8831

www.ti.com

SLAS449C–FEBRUARY 2005–REVISED NOVEMBER 2006

THEORY OF OPERATION (continued)

POWER-ON RESET

Both devices have a power-on reset function to ensure the output is at a known state upon power-up. In the

DAC8830 and DAC8831, on power-up, the DAC latch and Input Registers contain all 0s until new data is loaded

from the input serial shift register. Therefore, after power-up, the output from pin V_OUTof the DAC8830 is 0 V.

The output from pin V_OUTof the DAC8831 is 0V in unipolar mode and –V_REFin bipolar mode.

However, the serial register of the DAC8830 and DAC8831 is not cleared on power-up, so its contents are

undefined. When loading data initially to the device, 16 bits or more should be loaded to prevent erroneous data

appearing on the output. If more than 16 bits are loaded, the last 16 are kept; if less than 16 are loaded, bits will

remain from the previous word. If the device must be interfaced with data shorter than 16 bits, the data should

be padded with 0s at the LSBs.

Serial Interface

The digital interface is standard 3-wire connection compatible with SPI, QSPI™, Microwire™, and TI DSP

interfaces, which can operate at speeds up to 50M-bits/sec. The data transfer is framed by CS, the chip select

signal. The DAC works as a bus slave. The bus master generates the synchronize clock, SCLK, and initiates the

transmission. When CS is high, the DAC is not accessed, and the clock SCLK and serial input data SDI are

ignored. The bus master accesses the DAC by driving pin CS low. Immediately following the high-to-low

transition of CS, the serial input data on pin SDI is shifted out from the bus master synchronously on the falling

edge of SCLK, and latched on the rising edge of SCLK into the input shift register, MSB first. The low-to-high

transition of CS transfers the contents of the input shift register to the input register. All data registers are 16-bit.

It takes 16 clocks of SCLK to transfer one data word to the parts. To complete a whole data word, CS must go

high immediately after 16 SCLKs are clocked in. If more than 16 SCLKs are applied during the low state of CS,

the last 16 bits are transferred to the input register on the rising edge of CS. However, if CS is not kept low

during the entire 16 SCLK cycles, data is corrupted. In this case, reload the DAC with a new 16-bit word.

In the DAC8830, the contents of the input register are transferred into the DAC latch immediately when the input

register is loaded, and the DAC output is updated at the same time.

The DAC8831 has an LDAC pin allowing the DAC latch to be updated asynchronously by bringing LDAC low

after CS goes high. In this case, LDAC must be maintained high while CS is low. If LDAC is tied permanently

low, the DAC latch is updated immediately after the input register is loaded (caused by the low-to-high transition

of CS).

16

Submit Documentation Feedback

DAC8830

DAC8831

www.ti.com

SLAS449C–FEBRUARY 2005–REVISED NOVEMBER 2006

APPLICATION INFORMATION

Unipolar Output Operation

These DACs are capable of driving unbuffered loads of 60 kΩ. Unbuffered operation results in low supply

current (typically 5 µA) and a low offset error. The DAC8830 provides a unipolar output swing ranging from 0 V

to V_REF. The DAC8831 can be configured to output both unipolar and bipolar voltages. Figure 45 and Figure 46

show a typical unipolar output voltage circuit for each device, respectively. The code table for this mode of

operation is shown in Table 1.

Table 1. Unipolar Code

DAC LATCH CONTENTS

MSB

LSB

ANALOG OUTPUT

V_REF× (65,535/65,536)

1111 1111 1111 1111

1000 0000 0000 0000

0000 0000 0000 0001

0000 0000 0000 0000

V_REF× (32,768/65,536) = 1/2 V_REF

V_REF× (1/65,536)

0V

+5 V

+2.5 V

+

µ

10

F

µ

0.1

F

µ

0.1

F

OPA277

OPA704

OPA727

V_DD

V_REF

V_O= 0 to +V_REF

V_OUT

DAC

AGND

CS

SCLK

SDI

Input

Register

DAC Latch

DAC8830

DGND

Figure 45. Unipolar Output Mode of DAC8830

17

Submit Documentation Feedback

DAC8830

DAC8831

www.ti.com

SLAS449C–FEBRUARY 2005–REVISED NOVEMBER 2006

+5 V

+2.5 V

+

µ

F

0.1

F

10

µ

0.1

F

OPA277

OPA704

OPA727

−

V_REF

−

F

V_DD

S

V_REF

R_INV

R_FB

+V

RFB

LDAC

INV

V_O= 0 to +V_REF

V_OUT

DAC

CS

SCLK

SDI

−

V

AGNDF

AGNDS

Input

Register

DAC Latch

DAC8831

DGND

Figure 46. Unipolar Output Mode of DAC8831

Assuming a perfect reference, the worst-case output voltage may be calculated from the following equation:

Unipolar Mode Worst-Case Output

D

2

ǒ_V

_GEǓ _) V

ZSE

V

+

) V

) INL

OUT_UNI

REF

16

Where:

V_{OUT_UNI}= Unipolar mode worst-case output

D = Code loaded to DAC

V_REF= Reference voltage applied to part

V_GE= Gain error in volts

V_ZSE= Zero scale error in volts

INL = Integral nonlinearity in volts

18

Submit Documentation Feedback

DAC8830

DAC8831

www.ti.com

SLAS449C–FEBRUARY 2005–REVISED NOVEMBER 2006

Bipolar Output Operation

With the aid of an external operational amplifier, the DAC8831 may be configured to provide a bipolar voltage

output. A typical circuit of such an operation is shown in Figure 47. The matched bipolar offset resistors R_FBand

R_INVare connected to an external operational amplifier to achieve this bipolar output swing; typically, R_FB= R_INV

= 28 kΩ.

+5 V

+2.5 V

+

µ

F

0.1

F

10

µ

0.1

F

−

V_REF

−

F

V_DD

S

V_REF

R_INV

R_FB

RFB

INV

+V

LDAC

−

= V_REFto +V_REF

V_O

V_OUT

DAC

OPA277

OPA704

OPA727

CS

SCLK

SDI

−

V

AGNDF

AGNDS

Input

Register

DAC Latch

DAC8831

DGND

Figure 47. Bipolar Output Mode of DAC8831

Table 2 shows the transfer function for this output operating mode. The DAC8831 also provides a set of Kelvin

connections to the analog ground and external reference inputs.

Table 2. Bipolar Code

DAC LATCH CONTENTS

MSB

LSB

ANALOG OUTPUT

+V_REF× (32,767/32,768)

1111 1111 1111 1111

1000 0000 0000 0001

1000 0000 0000 0000

0111 1111 1111 1111

0000 0000 0000 0000

+V_REF× (1/32,768)

0V

–V_REF× (1/32,768)

–V_REF× (32,768/32,768) = –V_REF

Assuming a perfect reference, the worst-case output voltage may be calculated from the following equation:

Bipolar Mode Worst-Case Output

ǒ

ƪ _V

Ǔ ₍

_{1 )}_RD)ƫ

)

(

) V

2 ) RD * V

OUT_UNI

OS

REF

V

+

OUT_BIP

2)RD

_{1 )}ǒ

Ǔ

A

Where:

V_OS= External operational amplifier input offset voltage

RD = R_FBand R_INresistor matching error

A = Operational amplifier open-loop gain

19

Submit Documentation Feedback

DAC8830

DAC8831

www.ti.com

SLAS449C–FEBRUARY 2005–REVISED NOVEMBER 2006

Output Amplifier Selection

For bipolar mode, a precision amplifier should be used, supplied from a dual power supply. This provides the

±V_REFoutput.

In a single-supply application, selection of a suitable operational amplifier may be more difficult because the

output swing of the amplifier does not usually include the negative rail; in this case, AGND. This output swing

can result in some degradation of the specified performance unless the application does not use codes near 0.

The selected operational amplifier needs to have low-offset voltage (the DAC LSB is 38 µV with a 2.5 V

reference), eliminating the need for output offset trims. Input bias current should also be low because the bias

current multiplied by the DAC output impedance (approximately 6.25 kΩ) adds to the zero-code error.

Rail-to-rail input and output performance is required. For fast settling, the slew rate of the operational amplifier

should not impede the settling time of the DAC. Output impedance of the DAC is constant and

code-independent, but in order to minimize gain errors the input impedance of the output amplifier should be as

high as possible. The amplifier should also have a 3 dB bandwidth of 1 MHz or greater. The amplifier adds

another time constant to the system, thus increasing the settling time of the output. A higher 3 dB amplifier

bandwidth results in a shorter effective settling time of the combined DAC and amplifier.

Reference and Ground

Since the input impedance is code-dependent, the reference pin should be driven from a low impedance source.

The DAC8830 and DAC8831 operate with a voltage reference ranging from 1.25 V to V_DD. References below

1.25 V result in reduced accuracy.

The DAC full-scale output voltage is determined by the reference. Table 1 and Table 2 outline the analog output

voltage for particular digital codes.

For optimum performance, Kelvin sense connections are provided on the DAC8831. If the application does not

require separate force and sense lines, they should be tied together close to the package to minimize voltage

drops between the package leads and the internal die.

Power Supply and Reference Bypassing

For accurate high-resolution performance, it is recommended that the reference and supply pins be bypassed

with a 10 µF tantalum capacitor in parallel with a 0.1 µF ceramic capacitor.

20

Submit Documentation Feedback

DAC8830

DAC8831

www.ti.com

SLAS449C–FEBRUARY 2005–REVISED NOVEMBER 2006

CROSS-REFERENCE

The DAC8830 and DAC8831 have an industry-standard pinout configuration (see Table 3).

Table 3. Cross-Reference

INL

(LSB)

DNL

(LSB)

POWER-ON

RESET TO

TEMPERATURE

RANGE

PACKAGE

DESCRIPTION

PACKAGE

OPTION

CROSS

REFERENCE

MODEL

AD5541CR,

MAX541AESA

DAC8830ICD

DAC8830IBD

DAC8830ID

±1

±2

±4

±1

Zero-Code

–40°C to +85°C

8-Lead Small Outline IC

SO-8

AD5541BR,

MAX541BESA

AD5541AR,

MAX541CESA

N/A

±1

±2

±4

±1

±2

±1

±2

±4

±1

Zero-Code

–40°C to +85°C

0°C to +70°C

8-Lead Plastic DIP

8-Lead Small Outline IC

8-Lead Plastic DIP

PDIP-8

SO-8

MAX541AEPA

MAX541BEPA

MAX541CEPA

AD5541LR

±1

±1.5

±1

SO-8

AD5541JR

PDIP-8

MAX541AEPA

MAX541BEPA

MAX541CEPA

±1

AD5542CR,

MAX542AESD

DAC8831ICD

DAC8831IBD

DAC8831ID

±1

±2

±4

±1

Zero-Code

–40°C to +85°C

14-Lead Small Outline IC

SO-14

AD5542BR,

MAX542BESD

AD5542AR,

MAX542CESD

DAC8831ICRGY

±1

±2

±4

±1

±2

±4

±1

±2

±1

±2

±4

±1

Zero-Code

–40°C to +85°C

0°C to +70°C

14-Lead QFN

QFN-14

PDIP-14

SO-14

N/A

DAC8831IBRGY

N/A

DAC8831IRGY

±1

14-Lead QFN

N/A

±1

14-Lead Plastic DIP

14-Lead Small Outline IC

MAX542ACPD

MAX542BCPD

MAX542CCPD

AD5542LR

AD5542JR

MAX542AEPD

MAX542BEPD

MAX542CEPD

±1

±1.5

±1

0°C to +70°C

SO-14

0°C to +70°C

SO-14

±1

0°C to +70°C

SO-14

±1

0°C to +70°C

SO-14

21

Submit Documentation Feedback

PACKAGE OPTION ADDENDUM

www.ti.com

8-Jan-2007

PACKAGING INFORMATION

Orderable Device

DAC8830IBDR

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SOIC

D

8

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

DAC8830IBDRG4

DAC8830IBDT

SOIC

QFN

D

8

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

8

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

DAC8830IBDTG4

DAC8830ICDR

D

8

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

D

8

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

DAC8830ICDRG4

DAC8830ICDT

D

8

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

D

8

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

DAC8830ICDTG4

DAC8830IDR

D

8

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

D

8

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

DAC8830IDRG4

DAC8830IDT

D

8

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

D

8

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

DAC8830IDTG4

DAC8831IBD

D

8

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

D

14

50 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

DAC8831IBDG4

DAC8831IBDR

D

50 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

D

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

DAC8831IBDRG4

DAC8831IBRGYR

DAC8831IBRGYRG4

DAC8831IBRGYT

DAC8831IBRGYTG4

DAC8831ICD

D

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

RGY

D

3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

QFN

3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

QFN

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

QFN

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

SOIC

QFN

50 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

DAC8831ICDG4

DAC8831ICDR

D

50 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

D

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

DAC8831ICDRG4

DAC8831ICRGYR

D

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

RGY

1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

8-Jan-2007

Orderable Device

DAC8831ICRGYT

DAC8831ICRGYTG4

DAC8831ID

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

QFN

RGY

14

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

QFN

SOIC

QFN

RGY

D

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

50 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

DAC8831IDG4

D

50 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

DAC8831IDR

D

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

DAC8831IDRG4

DAC8831IRGYR

DAC8831IRGYRG4

DAC8831IRGYT

DAC8831IRGYTG4

D

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

RGY

3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to

discontinue any product or service without notice. Customers should obtain the latest relevant information

before placing orders and should verify that such information is current and complete. All products are sold

subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent

TI deems necessary to support this warranty. Except where mandated by government requirements, testing

of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible

for their products and applications using TI components. To minimize the risks associated with customer

products and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent

right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine,

or process in which TI products or services are used. Information published by TI regarding third-party

products or services does not constitute a license from TI to use such products or services or a warranty or

endorsement thereof. Use of such information may require a license from a third party under the patents or

other intellectual property of the third party, or a license from TI under the patents or other intellectual

property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without

alteration and is accompanied by all associated warranties, conditions, limitations, and notices.

Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not

responsible or liable for such altered documentation.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for

that product or service voids all express and any implied warranties for the associated TI product or service

and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Following are URLs where you can obtain information on other Texas Instruments products and application

solutions:

Products

Amplifiers

Data Converters

DSP

Interface

Applications

Audio

Automotive

Broadband

Digital Control

Military

amplifier.ti.com

dataconverter.ti.com

dsp.ti.com

interface.ti.com

logic.ti.com

www.ti.com/audio

www.ti.com/automotive

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/military

Logic

Power Mgmt

Microcontrollers

Low Power Wireless

power.ti.com

microcontroller.ti.com

www.ti.com/lpw

Optical Networking

Security

Telephony

Video & Imaging

Wireless

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

www.ti.com/wireless

Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265


型号：	DAC8830
厂家：	BURR-BROWN CORPORATION
描述：	16-Bit, Ultra-Low Power, Voltage-Output Digital-to-Analog Converters 16位，超低功耗，电压输出数字 - 模拟转换器转换器
文件：	总29页 (文件大小：937K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DAC8830 [BB]

相关型号：

DAC8830-EP

DAC8830IBD

DAC8830IBD

DAC8830IBDG4

DAC8830IBDR

DAC8830IBDR

DAC8830IBDRG4

DAC8830IBDT

DAC8830IBDTG4

DAC8830ICD

DAC8830ICDG4

DAC8830ICDR