DF1704 [BB]
Stereo, 24-Bit, 96kHz 8X Oversampling Digital Interpolation Filter DIGITAL-TO-ANALOG CONVERTER; 立体声， 24位， 96kHz的8倍过采样数字插补滤波器，数位类比转换器
| 型号： | DF1704 |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | Stereo, 24-Bit, 96kHz 8X Oversampling Digital Interpolation Filter DIGITAL-TO-ANALOG CONVERTER |
| 文件： | 总16页 (文件大小：225K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
DF1704
9%
DF1704
TM
Stereo, 24-Bit, 96kHz
8X Oversampling Digital Interpolation Filter
DIGITAL-TO-ANALOG CONVERTER
FEATURES
DESCRIPTION
● COMPANION DIGITAL FILTER FOR THE
The DF1704 is a high performance, stereo, 8X
oversampling digital interpolation filter designed for
high-end consumer and professional audio applica-
tions. The DF1704 supports 24-bit, 96kHz operation
and features user-programmable functions, including
selectable filter response, de-emphasis, attenuation,
and input/output data formats.
PCM1704 24-BIT AUDIO DAC
● HIGH PERFORMANCE FILTER:
Stopband Attenuation: –115dB
Passband Ripple: ±0.00005dB
● AUDIO INTERFACE:
Input Data Formats: Standard, Left-
Justified, and I2S
Input Word Length: 16, 20, or 24 Bits
Output Word Length: 16, 18, 20, or 24 Bits
Sampling Frequency: 32kHz to 96kHz
The DF1704 is the ideal companion for Burr-Brown’s
PCM1704 24-bit audio digital-to-analog converter.
This combination allows for construction of very high
performance audio systems and components.
● SYSTEM CLOCK: 256fS, 384fS, 512fS, 768fS
● ON-CHIP CRYSTAL OSCILLATOR
● PROGRAMMABLE FUNCTIONS:
Hardware or Software Control Modes
Sharp or Slow Roll-Off Filter Response
Soft Mute
Digital De-Emphasis
Independent Left/Right Digital Attenuation
● +5V SINGLE-SUPPLY OPERATION
● SMALL 28-LEAD SSOP PACKAGE
BCKO
BCKIN
Serial
Input
I/F
LRCIN
DIN
WCKO
8X Oversampling
Digital Filter with
Function
Output I/F
Controller
DOL
DOR
MD/CKO
MC/LRIP
ML/RESV
Mode
Control
I/F
MODE
(MUTE)
RST
SCK
(DEM)
Crystal/OSC
Power Supply
(SF0) (SF1) (SRO)
XTI
XTO
CLKO
VDD
VSS
International Airport Industrial Park
•
Mailing Address: PO Box 11400, Tucson, AZ 85734
•
Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706
•
Tel: (520) 746-1111
Twx: 910-952-1111 Internet: http://www.burr-brown.com/
•
•
Cable: BBRCORP Telex: 066-6491
•
•
FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1998 Burr-Brown Corporation
PDS-1458B
Printed in U.S.A. December, 1998
SPECIFICATIONS
All specifications at +25°C, VDD = +5V, unless otherwise noted.
DF1704E
TYP
PARAMETER
RESOLUTION
CONDITIONS
MIN
MAX
UNITS
24
Bits
INPUT DATA FORMAT
Audio Data Interface Format
Audio Data Bit Length
Audio Data Format
Standard/Left-Justified /I2S
16/20/24 Selectable
MSB-First, Two’s Binary Comp
Sampling Frequency (fS)
System Clock Frequency
32
96
kHz
256/384/512/768fS
OUTPUT DATA FORMAT
Audio Data Interface Format
Audio Data Bit Length
Audio Data Format
Right-Justified
16/20/24 Selectable
MSB-First, Binary Two’s Complement
DIGITAL INPUT/OUTPUT
Input Logic Level: VIH
2.0
V
V
V
V
VIL
Output Logic Level: VOH
VOL
0.8
0.5
IOH = 2mA
IOL = 4mA
4.5
CLKO AC CHARACTERISTICS
Rise Time (tR)
Fall Time (tF)
Duty Cycle
20% to 80% VDD, 10pF
80% to 20% VDD, 10pF
10pF Load
4
3
37
ns
ns
%
DIGITAL FILTER PERFORMANCE
Filter Characteristics 1 (Sharp Roll-Off)
Passband
±0.00005dB
0.454fS
0.493fS
–3dB
Stopband
Passband Ripple
Stopband Attenuation
Filter Characteristics 2 (Sharp Roll-Off)
Passband Ripple
0.546fS
–115
±0.00005
dB
dB
Stopband = 0.546fS
±0.0001dB
0.254fS
0.460fS
–3dB
Stopband
0.732fS
–100
Passband Ripple
Stopband Attenuation
Delay Time
±0.0001
±0.003
dB
dB
sec
dB
Stopband = 0.748fS
45.125/fS
De-Emphasis Error
POWER SUPPLY REQUIREMENTS
Voltage Range
Supply Current: IDD
VDD
4.5
5
20
5.5
30
VDC
mA
Power Dissipation
100
150
mW
TEMPERATURE RANGE
Operation
Storage
–25
–55
+85
+100
°C
°C
®
2
DF1704
PIN CONFIGURATION
PIN ASSIGNMENTS
PIN NAME
I/O
IN
DESCRIPTION
1
2
DIN
Serial Audio Data Input(3)
Bit Clock Input for Serial Audio Data(3)
DIN
BCKIN
I2S
1
2
3
4
5
6
7
8
9
28 LRCIN
27 SRO
26 BCKO
25 WCKO
24 DOL
23 DOR
22 VDD
BCKIN
IN
3
4
I2S
IW0
IN
IN
Input Audio Data Format Selection(2, 4)
Input Audio Data Word Selection(2, 4)
Input Audio Data Word Selection(2, 4)
Oscillator Input /External Clock Input
Oscillator Output
5
IW1
XTI
IN
IN
6
IW0
7
XTO
VSS
OUT
—
IW1
8
Digital Ground
9
CLKO
MODE
OUT
IN
Buffered System Clock Output
Mode Control Selection (H: Software, L: Hardware)(1)
XTI
10
XTO
VSS
11 MD/CKO
IN
Control Data Input/Clock Output Frequency
Select(1, 5)
Control Data Clock/Polarity of LRCK Select(1, 5)
Control Data Latch/Reserved(1, 5)
DF1704E
21 NC
12 MC/LRIP
13 ML/RESV
IN
IN
IN
CLKO
20 OW1
19 OW0
18 SF1
14
RST
Reset. When this pin is LOW, the digital filter
is held in reset.(1)
Mute Control(1, 4)
MODE 10
MD/CKO 11
MC/LRIP 12
ML/RESV 13
RST 14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
MUTE
DEM
SF0
IN
IN
De-Emphasis Control(2, 4)
17 SF0
IN
Sampling Rate Select for De-emphasis(2, 4)
Sampling Rate Select for De-emphasis(2, 4)
Output Audio Data Word and Format Select(2, 4)
Output Audio Data Word and Format Select(2, 4)
No Connection
16 DEM
15 MUTE
SF1
IN
OW0
OW1
NC
IN
IN
—
NC: No Connection
VDD
—
Digital Power, +5V
DOR
DOL
OUT
OUT
OUT
OUT
IN
Rch, Serial Audio Data Output
Lch, Serial Audio Data Output
WCKO
BCKO
SRO
LRCIN
Word Clock for Serial Audio Data Output
Bit Clock for Serial Audio Data Output
Filter Response Select(2, 4)
PACKAGE INFORMATION
PACKAGE DRAWING
NUMBER(1)
PRODUCT
PACKAGE
IN
L/R Clock Input (fS) for Serial Audio Data(3)
DF1704E
28-Lead SSOP
324
NOTES: (1) Pins 10-15; Schmitt-Trigger input with pull-up resistor. (2) Pins
3-5, 16-20, 27; Schmitt-Trigger input with pull-down resister. (3) Pins 1, 2,
28; Schmitt-Trigger input. (4) Pins 3-5, 15-20, 27; these pins are invalid
when MODE (pin 10) is HIGH. (5) Pins 11-13; these pins have different
functions corresponding to MODE (pin 10), (HIGH/LOW).
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VDD , VCC1, VCC2R, VCC2L).................................... +6.5V
Supply Voltage Differences................................................................. ±0.1
GND Voltage Differences.................................................................. ±0.1V
Digital Input Voltage ................................................. –0.3V to (VDD + 0.3V)
Input Current (any pins except power supplies) ............................. ±10mA
Power Dissipation .......................................................................... 300mW
Operating Temperature Range ......................................... –25°C to +85°C
Storage Temperature ...................................................... –55°C to +125°C
Lead Temperature (soldering, 5s)................................................. +260°C
Package Temperature (reflow, 10s) .............................................. +235°C
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
3
DF1704
TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER
DIGITAL FILTER (DE-EMPHASIS OFF, fS = 44.1kHz)
FREQUENCY RESPONSE (Sharp Roll Off)
PASSBAND RIPPLE (Sharp Roll Off)
20
0
0.0001
0.00008
0.00006
0.00004
0.00002
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
–200
–0.00002
–0.00004
–0.00006
–0.00008
–0.0001
0
0.5
1
1.5
2
2.5
3
3.5
4
0
0.5 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Frequency (fS)
Frequency (fS)
TRANSITION CHARACTERISTIC (Slow Roll Off)
FREQUENCY RESPONSE (Slow Roll Off)
0
–5
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
–200
–10
–15
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0
0.5
1
1.5
2
2.5
3
3.5
4
Frequency (fS)
Frequency (fS)
DE-EMPHASIS AND DE-EMPHASIS ERROR
DE-EMPHASIS ERROR (fS = 32kHz)
DE-EMPHASIS (fS = 32kHz)
0
0.01
0.008
0.006
0.004
0.002
0
–2
–4
–0.002
–0.004
–0.006
–0.008
–0.01
–6
–8
–10
0
2
4
6
8
10
12
14
0
2
4
6
8
10
12
14
Frequency (fS)
Frequency ( fS)
®
4
DF1704
TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER
DE-EMPHASIS (fS = 44.1kHz)
DE-EMPHASIS ERROR (fS = 44.1kHz)
0
–2
0.01
0.008
0.006
0.004
0.002
0
–4
–6
–0.002
–0.004
–0.006
–0.008
–0.01
–8
–10
0
2
4
6
8
10
12
14
16
18
20
0
2
4
6
8
10
12
14
16
18
20
Frequency (fS)
Frequency (fS)
DE-EMPHASIS (fS = 48kHz)
DE-EMPHASIS ERROR (fS = 48kHz)
0
–2
0.01
0.008
0.006
0.004
0.002
0
–4
–0.002
–0.004
–0.006
–0.008
–0.01
–6
–8
–10
0
2
4
6
8
10 12 14 16 18 20 22
0
2
4
6
8
10 12 14 16 18 20 22
Frequency (fS)
Frequency (fS)
®
5
DF1704
SYSTEM CLOCK REQUIREMENTS
During the power-on reset period (1024 system clocks), the
DF1704 outputs are forced LOW. For an external forced
reset, the outputs are forced LOW during the initialization
period (1024 system clocks), which occurs after the LOW-
to-HIGH transition of the RST pin as shown in Figure 3.
The system clock of the DF1704 can be supplied by either
an external clock signal at XTI (pin 6), or by the on-chip
crystal oscillator. The system clock rate must run at 256fS,
384fS, 512fS, or 768fS, where fS is the audio sampling rate.
It should be noted that a 768fS system clock cannot be used
when fS = 96kHz. In addition, the on-chip crystal oscillator
is limited to a maximum frequency of 24.576MHz. Table I
shows the typical system clock frequencies for selected
sample rates.
2.6V
VDD 2.2V
1.8V
Reset
The DF1704 includes a system clock detection circuit that
determines the system clock rate in use. The circuit com-
pares the system clock input (XTI) frequency with the
LRCIN input rate to determine the system clock multiplier.
Ideally, LRCIN and BCKIN should be derived from the
system clock to ensure proper synchronization. If the phase
difference between the system clock and LRCIN is larger
than ±6 bit clock (BCKIN) periods, the synchronization of
the system and LRCIN clocks will be performed automati-
cally by the DF1704.
Reset Removal
Internal Reset
1024 system clocks
System Clock
FIGURE 2. Internal Power-On Reset Timing.
Timing requirements for the system clock input are shown in
Figure 1.
tRST
tRST ≥ 20ns
RST
Reset
Reset Removal
tSCKH
Internal Reset
System Clock
1024 system (XTI) clocks
“H”
2.0V
XTI
0.8V
“L”
tSCKL
FIGURE 3. External Forces Reset Timing.
System Clock Pulse Width HIGH :tSCKIH :7ns min(1)
System Clock Pulse Width LOW :tSCKIL :7ns min(1)
NOTE: (1) For fS = 96kHz and SCK = 256fS, tSCKIH = 14ns (min)
AUDIO INPUT INTERFACE
t
SCKIL = 14ns (min)
For fS ≠ 96kHz and SCK = 256fS, tSCKIH = 20ns (min)
SCKIL = 20ns (min)
The audio input interface is comprised of BCKIN (pin 2),
LRCIN (pin 28), and DIN (pin 1).
t
BCKIN is the input bit clock, which is used to clock data
applied at DIN into the DF1704’s input serial interface.
Input data at DIN is clocked into the DF1704 on the rising
edge of BCKIN. The left/right clock, LRCIN, is used as a
word latch for the audio input data.
FIGURE 1. System Clock Timing.
RESET
The DF1704 has both an internal power-on reset circuit and
a reset pin, RST (pin 14), for providing an external reset
signal. The internal power-on reset is performed automati-
cally when power is applied to the DF1704, as shown in
Figure 2. The RST pin can be used to synchronize the
DF1704 with a system reset signal, as shown in Figure 3.
BCKIN can run at 32fS, 48fS, or 64fS, where fS is the audio
sample frequency. LRCIN is run at the fS rate. Figures 4 (a)
through 4 (c) show the input data formats, which are sel-
ected by hardware or software controls. Figure 5 shows the
audio input interface timing requirements.
SYSTEM CLOCK FREQUENCY (MHz)
SAMPLING RATE FREQUENCY (fS)
256fS
384fS
512fS
768fS
32kHz
44.1kHz
48kHz
8.1920
11.2896
12.2880
12.2880
16.9340
18.4320
36.8640(1)
16.3840
22.5792
24.5760
49.1520(1)
24.5760
33.8688(1)
36.8640(1)
96kHz
24.5760(3)
See Notes 1, 2
NOTES: (1) Maximum crystal oscillator frequency is 24.576MHz and cannot be used for these combinations. (2) 768fS system clock cannot be used with 96kHz
sampling rate. (3) Use external system clock applied at XTI.
TABLE I. Typical System Clock Frequencies.
®
6
DF1704
(a) Standard Format (Sony Format); Lch = “H”, Rch = “L”
1/fS
Lch
Rch
LRCIN
BCKIN
AUDIO DATA WORD = 16-BIT
DIN 14 15 16
1
2
15 16
1
2
15 16
19 20
23 24
MSB
LSB
LSB
LSB
AUDIO DATA WORD = 20-BIT
DIN 18 19 20
1
1
2
2
19 20
23 24
1
1
2
2
MSB
MSB
AUDIO DATA WORD = 24-BIT
DIN 22 23 24
MSB
LSB
(b) Left-Justified Format; Lch = “H”, Rch = “L”
1/fS
Lch
Rch
LRCIN
BCKIN
AUDIO DATA WORD = 24-BIT
DIN
1
2
3
22 23 24
LSB
1
2
3
22 23 24
LSB
1
2
3
MSB
MSB
(c) I2S Data Format (Philips Format); Lch = “L”, Rch = “H”
1/fS
Lch
Rch
LRCIN
BCKIN
AUDIO DATA WORD = 16-BIT
DIN
1
1
2
2
15 16
1
1
2
2
15 16
1
2
MSB
MSB
LSB
MSB
MSB
LSB
AUDIO DATA WORD = 24-BIT
DIN
23 24
23 24
1
2
LSB
LSB
FIGURE 4. Audio Data Input Formats.
LRCKIN
1.4V
1.4V
tBCH
tBCL
tLB
BCKIN
tBCY
tBL
1.4V
DIN
tDS
tDH
BCKIN Pulse Cycle Time
BCKIN Pulse Width HIGH
BCKIN Pulse Width LOW
tBCY
tBCH
tBCL
100ns (min)
50ns (min)
50ns (min)
30ns (min)
30ns (min)
30ns (min)
30ns (min)
BCKIN Rising Edge to LRCIN Edge tBL
LRCIN Edge to BCKIN Rising Edge tLB
DIN Set-up Time
DIN Hold Time
tDS
tDH
FIGURE 5. Audio Input Interface Timing.
®
7
DF1704
AUDIO OUTPUT INTERFACE
The output data format used by the DF1704 for DOL and
DOR is Binary Two’s Complement, MSB-first, right-justi-
fied audio data. Figures 6(a) and 6(b) show the output data
formats for the DF1704. Figure 7 shows the audio output
timing.
The audio output interface includes BCKO (pin 26), WCKO
(pin 25), DOL (pin 24), and DOR (pin 23).
BCKO is the output bit clock and is used to clock data into
an audio D/A converter, such as the PCM1704. DOL and
DOR are the left and right audio data outputs. WCKO is the
output word clock and is used to latch audio data words into
an audio D/A converter.
MODE CONTROL
The DF1704 may be configured using either software or
hardware control. The selection is made using the MODE
input (pin 10).
WCKO runs at a fixed rate of 8fS (8X oversampling) for all
system clock rates.
BCKO is fixed at 256fS for system clock rates of 256fS or
512fS.
MODE SETTING
MODE CONTROL SELECTION
MODE = H
MODE = L
Software Mode
Hardware Mode
BCKO is fixed at 192fS for system clock rates of 384fS or
768fS.
TABLE II. MODE Selection.
(a) SYSTEM CLOCK: 256/512fS
1/8fS
WCKO
BCKO
AUDIO DATA WORD = 16-BIT
DOR
14 15 16
DOL
1
2
15 16
MSB
LSB
17 18
AUDIO DATA WORD = 18-BIT
DOR
16 17 18
DOL
1
2
MSB
LSB
19 20
AUDIO DATA WORD = 20-BIT
DOR
18 19 20
DOL
1
2
MSB
LSB
23 24
AUDIO DATA WORD = 24-BIT
DOR
22 23 24
1
2
DOL
MSB
LSB
(b) SYSTEM CLOCK: 384/768fS
1/8fS
WCKO
BCKO
AUDIO DATA WORD = 16-BIT
DOR
14 15 16
DOL
1
2
15 16
MSB
LSB
17 18
AUDIO DATA WORD = 18-BIT
DOR
16 17 18
DOL
1
2
MSB
LSB
19 20
AUDIO DATA WORD = 20-BIT
DOR
18 19 20
DOL
1
2
MSB
LSB
23 24
AUDIO DATA WORD = 24-BIT
DOR
22 23 24
1
2
1
2
DOL
MSB
LSB
FIGURE 6. Audio Output Data Format.
®
8
DF1704
tWCKP
WCKO
BCKO
0.5VDD
tBCKH
tBCKL
tCKWK
0.5VDD
tBCKP
tCKDO
DOL, R
0.5VDD
max
min
typ
BCKO Period
tBCKP
1/256 fS or 1/192 fS
BCKO Pulse Width High(4)
BCKO Pulse Width Low(4)
tBCKH
tBCKL
tCKWK
tWCKP
tCKDO
20ns
100ns
100ns
5ns
20ns
–5ns
Delay Time BCKO Falling Edge to WCKO Valid
WCKO Period
1/8 fS
Delay Time BCKO Falling Edge to DOL, R Valid
–5ns
5ns
Rising Time of All Signals
Falling Time of All Signals
tR
tF
7ns
7ns
NOTES: (1) Timing measurement reference level is (VIH/VIL)/2. (2) Rising and falling time is
measured from 10% to 90% of IN/OUT signals’ swing. (3) Load capacitance of all signals
are 20pF. (4) Exceptions: fS = 96kHz and SCK = 256fS, tBCKH = 14ns (min)
tBCKL = 14ns (min)
FIGURE 7. Audio Output Data Format.
Pins I2S, IW0, and IW1 are used to select the audio data
input format and word length.
Programmable Functions
The DF1704 includes a number of programmable features,
with most being accessible from either Hardware or Soft-
ware mode. Table III summarizes the user programmable
functions for both modes of operation.
Pins OW0 and OW1 are used to select the output data word
length.
The DEM pin is used to enable and disable the digital de-
emphasis function. De-emphasis is only available for 32kHz,
44.1kHz, and 48kHz sample rates.
RESET
DEFAULT
(Software Mode)
SOFTWARE
(MODE = H)
HARDWARE
(MODE = L)
Pins SF0 and SF1 are used to select the sample rate for the
de-emphasis function.
FUNCTION
Input Data Format Selection
O
O
Standard Format
The SRO pin is used to select the digital filter response,
either sharp or slow roll-off.
Input Word Length Selection
Output Word Length Selection
LRCIN Polarity Selection
Digital De-Emphasis
O
O
O
O
O
O
O
O
O
O
O
X
16 Bits
16 Bits
The MUTE pin is used to enable or disable the soft mute
function.
Left/Right = High/Low
OFF
Soft Mute
OFF
The CKO pin is used to select the clock frequency seen at the
CLKO pin, either XTI or XTI ÷ 2.
Digital Attenuation
0dB, Independent L/R
Sample Rate for
De-Emphasis Function
The LRIP pin is used to select the polarity used for the audio
input left/right clock, LRCIN.
O
O
O
O
O
O
44.1 kHz
Filter Roll-Off Selection
Sharp Roll-Off Selected
Same As XTI Input
Finally, the RESV pin is not used by the current DF1704
design, but is reserved for future use.
CLKO Output Frequency Selection
Legend:
O = User Programmable, X = Not Available.
TABLE III. User-Programmable Functions for Software and
Hardware Mode.
Software Mode Controls
With MODE = H, the DF1704 may be configured by
programming four internal registers in software mode. ML
(pin 13), MC (pin 12), and MD (pin 11) make up the 3-wire
software control port, and may be controlled using DSP or
microcontroller general purpose I/O pins, or a serial port.
Table V provides an overview of the internal registers,
labeled MODE0 through MODE3.
Hardware Mode Controls
With MODE = L, the DF1704 may be configured by
utilizing several user-programmable pins. The following is a
brief summary of the pin functions. Table IV provides more
details on setting the hardware mode controls.
®
9
DF1704
PIN
PIN
REGISTER
NAME
BIT
NAME
NAME NUMBER
DESCRIPTION
DESCRIPTION
RESV
LRIP
13
12
Reserved, Not Used
MODE0
MODE1
MODE2
AL[7:0]
LDL
A[1:0]
res
Attenuation Data for the Left Channel
Attenuation Load Control for the Left Channel
Register Address
LRCIN Polarity
LRIP = H: LRCIN= H = Left Channel, LRCIN= L = Right Channel
LRIP = L: LRCIN= L = Left Channel, LRCIN = H = Right Channel
Reserved
AR[7:0]
LDL
A[1:0]
res
Attenuation Data for the Right Channel
Attenuation Load Control for the Right Channel
Register Address
CKO
11
CLKO Output Frequency
CKO = H: CLKO Frequency = XTI/2
CKO = L: CLKO Frequency = XTI
Reserved
MUTE
15
Soft Mute Control: H = Mute Off, L = Mute On
Input Data Format Controls
MUT
DEM
IW[1:0]
OW[1:0]
A[1:0]
res
Soft Mute Control
I2S
IW0
IW1
3
4
5
Digital De-Emphasis Control
Input Data Format and Word Length
Output Data Word Length
Register Address
I2S IW1 IW0
INPUT FORMAT
L
L
L
L
H
H
L
L
H
H
L
L
L
H
L
H
L
16-Bit, Standard, MSB-First, Right-Justified
20-Bit, Standard, MSB-First, Right-Justified
24-Bit, Standard, MSB-First, Right-Justified
24-Bit, MSB-First, Left-Justified
16-Bit, I2S
Reserved
MODE3
I2S
LRP
ATC
SRO
CKO
SF[1:0]
A[1:0]
res
Input Data Format (I2S or Standard/Left-Justified)
LRCIN Polarity
Attenuator Control, Dependent or Independent
Digital Filter Roll-Off Selection (sharp or slow)
CLKO Frequency Selection (XTI or XTI ÷ 2)
Sample Rate Selection for De-Emphasis Function
Register Address
H
24-Bit, I2S
SRO
27
Digital Filter Roll-Off: H = Slow, L = Sharp
Output Data Word Length Controls
OW0
OW1
19
20
Reserved
OW1 OW0 OUTPUT FORMAT
NOTE: All reserved bits should be programmed to 0.
L
L
L
H
L
16-Bit, MSB-First
18-Bit, MSB-First
20-Bit, MSB-First
24-Bit, MSB-First
TABLE V. Internal Register Mapping.
H
H
H
SF0
SF1
17
18
Sample Rate Selection for the Digital De-Emphasis Control
Register Addressing
SF1 SF0
SAMPLING RATE
44.1kHz
Reserved, Not Used
48kHz
A[1:0], bits B10 and B9 of the 16-bit control data word, are
used to indicate the register address to be written to by the
current control port write cycle. Table VI shows how to
address the internal registers using bits A[1:0] of registers
MODE0 through MODE3.
L
L
H
H
L
H
L
H
32kHz
DEM
16
Digital De-Emphasis: H = On, L = Off
TABLE IV. Hardware Mode Controls.
A1
A0
REGISTER SELECTED
0
0
1
1
0
1
0
1
MODE0
MODE1
MODE2
MODE3
Figures 8 through 10 show more details regarding the
control port data format and timing requirements. The data
format for the control port is 16-bit, MSB-first, with Bit B15
being the MSB.
TABLE VI. Internal Register Addressing.
B15
res
B14
res
B13
res
B12
res
B11
res
B10
A1
B9
A0
B8
B7
B6
B5
B4
B3
B2
B1
B0
MODE0
MODE1
LDL
AL7
AL6
AL5
AL4
AL3
AL2
AL1
AL0
res
res
res
res
res
res
res
res
res
res
res
res
res
res
res
A1
A1
A1
A0
A0
A0
LDR
res
AR7
res
AR6
OW1
SF0
AR5
OW0
CKO
AR4
IW1
res
AR3
IW0
AR2
res
AR1
AR0
MODE2
MODE3
DEM MUT
LRP
I2S
res
SF1
SRO
ATC
FIGURE 8. Internal Mode Control Registers.
ML
MC
MD
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
FIGURE 9. Software Interface Format.
®
10
DF1704
tMLL
tMHH
ML(1)
1.4V
1.4V
tMLH
tMLS
tMCH
tMCL
MC(2)
tMCY
LSB
MD
1.4V
tMDS
tMDH
MC Pulse Cycle Time
MC Pulse Width LOW
MC Pulse Width HIGH
MD Hold Time
tMCY
tMCL
tMCH
tMDH
tMDS
tMLL
tMHH
tMLH
tMLS
100ns (min)
40ns (min)
40ns (min)
40ns (min)
40ns (min)
MD Set-Up Time
ML Low Level Time
ML High Level Time
ML Hold Time(2)
40ns + 1SYSCLK(3) (min)
40ns + 1SYSCLK(3) (min)
40ns (min)
ML Set-Up Time(3)
40ns (min)
NOTES: (1) ML rising edge to the next MC rising edge. (2) MC rising edge for LSB to ML rising edge. (3) SYSCK: System Clock Cycle.
FIGURE 10. Software Interface Timing Requirements.
MODE0 Register
MODE1 Register
The MODE0 register is used to set the attenuation data for
the Left output channel, or DOL (pin 24).
The MODE1 register is used to set the attenuation data for
the Right output channel, or DOR (pin 23).
When ATC = 1 (Bit B2 of Register MODE3 = 1), the Left
channel attenuation data AL[7:0] is used for both the Left
and Right channel attenuators.
When ATC = 1 (Bit B2 of Register MODE3 = 1), the Left
channel attenuation data AL[7:0] of register MODE0 is used
for both the Left and Right channel attenuators.
When ATC = 0, (Bit B2 of Register MODE3 = 0), Left
channel attenuation data is taken from AL[7:0] of register
MODE0, and Right channel attenuation data is taken from
AR[7:0] of register MODE1.
When ATC = 0, (Bit B2 of Register MODE3 = 0), Left
channel attenuation data is taken from AL[7:0] of register
MODE0, and Right channel attenuation data is taken from
AR[7:0] of register MODE1.
AL[7:0]
Left Channel Attenuator Data, where AL7 is the
MSB and AL0 is the LSB.
Attenuation Level is given by:
AR[7:0] Right Channel Attenuator Data, where AR7 is
the MSB and AR0 is the LSB. Attenuation
Level is given by:
ATTEN = 0.5 • (DATA – 255)dB
ATTEN = 0.5 • (DATA – 255)dB
For DATA = FFh, ATTEN = –0dB
For DATA = FFh, ATTEN = –0dB
For DATA = FEh, ATTEN = –0.5dB
For DATA = 01h, ATTEN = –127.5dB
For DATA = 00h, ATTEN = infinity = Mute
For DATA = FEh, ATTEN = –0.5dB
For DATA = 01h, ATTEN = –127.5dB
For DATA = 00h, ATTEN = infinity = Mute
LDL
Left Channel Attenuation Data Load Control.
This bit is used to simultaneously set attenua-
tion levels of both the Left and Right channels.
LDR
Right Channel Attenuation Data Load Control.
This bit is used to simultaneously set attenuation
levels of both the Left and Right channels.
When LDL = 1, the Left channel output level is
set by the data in AL[7:0]. The Right channel
output level is set by the data in AL[7:0], or the
most recently programmed data in bits AR[7:0]
of register MODE1.
When LDR = 1, the Right channel output level
is set by the data in AR[7:0], or by the data in
bits AL[7:0] of register MODE0. The Left chan-
nel output level is set to the most recently
programmed data in bits AL[7:0] of register
MODE0.
When LDL = 0, the Left channel output data
remains at its previously programmed level.
When LDR = 0, the Right channel output data
remains at its previously programmed level.
®
11
DF1704
MODE2 Register
ATC
Attenuator Control.
This bit is used to determine whether the Left
and Right channel attenuators operate with inde-
pendent data, or use common data (the Left
channel data in bits AL[7:0] of register MODE0).
The MODE2 register is used to program various functions:
MUT
Soft Mute Function.
When MUT = 0, Soft Mute is ON for both Left
and Right channels.
When MUT = 1, Soft Mute is OFF for both Left
and Right channels.
When ATC = 0, the Left and Right channel
attenuator data is independent.
When ATC = 1, the Left and Right channel
attenuators use common data.
DEM
Digital De-Emphasis Function.
When DEM = 0, de-emphasis is OFF.
When DEM = 1, de-emphasis is ON.
SRO
CKO
Digital Filter Roll-Off Selection.
When SRO = 0, sharp roll-off is selected.
When SRO = 1, slow roll-off is selected.
IW[1:0]
Input Data Format and Word Length.
I2S IW1
IW0
0
Description
CLKO Output Frequency Selection.
0
0
16-Bit Data, Standard
Format (MSB-First,
Right-Justified)
When CKO = 0, the CLKO frequency is the
same as the clock at the XTI input.
When CKO =1, the CLKO frequency is half of
the XTI input clock frequency.
0
0
0
0
1
1
1
0
1
20-Bit Data, Standard
Format
SF[1:0]
Sampling Frequency Selection for the De-Em-
phasis Function.
24-Bit Data, Standard
Format
SF1 SF0
Description
24-Bit Data, MSB-First,
Left-Justified
0
0
1
1
0
1
0
1
44.1 kHz
Reserved
48 kHz
1
1
1
1
0
0
1
1
0
1
0
1
16-Bit Data, I2S Format
24-Bit Data, I2S format
Reserved
32 kHz
Reserved
APPLICATIONS INFORMATION
PCB LAYOUT GUIDELINES
OW[1:0] Output Data Word Length.
OW1 OW0 Description
In order to obtain the specified performance from the DF1704
and its associated D/A converters, proper printed circuit
board layout is essential. Figure 11 shows two approaches
for obtaining the best audio performance.
0
0
1
1
0
1
0
1
16-Bit Data, MSB-First
18-Bit Data, MSB-First
20-Bit Data, MSB-First
24-Bit Data, MSB-First
Figure 11(a) shows a standard, mixed signal layout scheme.
The board is divided into digital and analog sections, each
with its own ground. The ground areas should be put on a
split-plane, separate from the routing and power layers. The
DF1704 and all digital circuitry should be placed over the
digital section, while the audio DACs and analog circuitry
should be located over the analog section of the board. A
common connection between the digital and analog grounds
is required and is done at a single point as shown.
MODE3 Register
The MODE3 register is used to program various functions.
I2S
Input Data Format.
When I2S = 0, standard or left-justified formats
are enabled.
When I2S = 1, the I2S formats are enabled.
LRP
LRCIN Polarity Selection.
For Figure 11(a), digital signals should be routed from the
DF1704 to the audio DACs using short, direct connections
to reduce the amount of radiated high-frequency energy. If
necessary, series resistors may be placed in the clock and
data signal paths to reduce or eliminate any overshoot or
undershoot present on these signals. A value of 50Ω to 100Ω
is recommended as a starting point, but the designer should
experiment with the resistor values in order to obtain the best
results.
When LRP = 0, Left channel is HIGH and Right
channel is LOW.
When LRP = 1, Left channel is LOW and Right
channel is HIGH.
®
12
DF1704
Figure 11(b) shows an improved method for high perfor-
mance, mixed signal board layout. This method adds digital
isolation between the DF1704 and the audio DACs, and
provides complete isolation between the digital and analog
sections of the board. The Burr-Brown ISO150 dual digital
coupler provides excellent isolation, and operates at speeds
up to 80Mbps.
BASIC CIRCUIT CONNECTIONS
Figures 12 and 13 show basic circuit connections for the
DF1704. Figure 12 shows connections for Hardware mode
controls, while Figure 13 shows connections for Software
mode controls. Notice the placement of C1 and C2 in both
figures, as they are physically close to the DF1704.
TYPICAL APPLICATIONS
POWER SUPPLIES AND BYPASSING
The DF1704 will typically be used in high performance
audio equipment, in conjunction with high performance
audio D/A converters. Figure 14 shows a typical application
circuit example, employing the DF1704, a digital audio
receiver, and two PCM1704 24-bit, 96kHz audio DACs.
The DF1704 requires a single +5V power supply for opera-
tion. The power supply should be bypassed by a 10µF and
0.1µF parallel capacitor combination. The capacitors should
be placed as close as possible to VDD (pin 22). Aluminum
electrolytics or tantalum capacitors can be used for the 10µF
value, while ceramics may be used for the 0.1µF value.
®
13
DF1704
(a) Layout Without Isolation
Common
Ground
Connection
Digital Power
Supplies
Analog Power
Supplies
WCKO
BCKO
DOL
DAC
DOR
DF1704
DAC
Digital Section
Analog Section
Split Ground Plane
(b) Layout With Isolation
Digital Power
Supplies
Analog Power
Supplies
WCKO
BCKO
DOL
ISO150
DAC
DOR
DF1704
DAC
ISO150
Digital Section
Analog Section
= DGND
= AGND
Split Ground Plane
FIGURE 11. PCB Layout Model.
®
14
DF1704
DF1704
1
2
3
4
5
6
7
8
9
DIN
LRCIN 28
SRO 27
BCKO 26
WCKO 25
DOL 24
DOR 23
VDD 22
BCKIN
I2S
Audio
Data
and
Clock
Source
D/A
Converters
or
Digital
Couplers
IW0
IW1
XTI
22pF
22pF
XTAL
XTO
VSS
+5V
+
C1
0.1µF
C2
10µF
NC 21
CLKO
OW1 20
OW0 19
SF1 18
(optional)
10 MODE
11 MD/CKO
12 MC/LRIP
13 ML/RESV
14 RST
SF0 17
DEM 16
MUTE 15
Digital
Logic
7
or
7
Manual
Controls
= DGND
NOTE: Do not allow pins 3-5, 11-20, and 27 to float. These pins should be manually
connected to VDD or DGND (hardwired, switch, jumper) or actively driven by logic.
FIGURE 12. Basic Circuit Connections, Hardware Control.
DF1704
Audio
Data
and
Clock
Source
1
2
3
4
5
6
7
8
9
DIN
LRCIN 28
SRO 27
BCKO 26
WCKO 25
DOL 24
DOR 23
VDD 22
BCKIN
I2S
D/A
Converters
or
Digital
Couplers
IWO
IW1
XTI
22pF
22pF
XTAL
XTO
VSS
+5V
+
C1
C2
NC 21
0.1µF
10µF
CLKO
OW1 20
OW0 19
SF1 18
(optional)
10 MODE
11 MD
12 MC
13 ML
+5V
Controller
or
Logic
SF0 17
DEM 16
MUTE 15
14 RST
= DGND
FIGURE 13. Basic Circuit Connection, Software Control.
®
15
DF1704
DIGITAL
SECTION
ANALOG
SECTION
WORD CLOCK
DF1704
Digital
Audio
Input
Digital
Audio
Receiver
DATA
PCM1704
1
2
3
4
5
6
7
8
9
DIN
LRCIN 28
SRO 27
BCKO 26
WCKO 25
DOL 24
DOR 23
VDD 22
BCLK
WCLK
DATA
BIT CLOCK
SYSTEM CLOCK
Left
Channel
Out
BCKIN
I2S
D/A
Converter
Post
Filter
I/V
IWO
IW1
XTI
XTO
VSS
NC 21
CLKO
OW1 20
OW0 19
SF1 18
PCM1704
10 MODE
11 MD
12 MC
13 ML
+5V
BCLK
WCLK
DATA
Micro
Controller
or
Right
Channel
Out
D/A
Converter
Post
Filter
Host
Interface
I/V
SF0 17
Logic
DEM 16
MUTE 15
14 RST
System
Reset
+
+5V
10µF
0.1µF
= DGND
+5V
FIGURE 14. DF1704 Typical Application Circuit.
®
16
DF1704
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