PCM1605Y_技术文档

®

PCM1604

PCM1605

PCM1604

For most current data sheet and other product

information, visit www.burr-brown.com

TM

24-Bit, 192kHz Sampling,6-Channel,

Enhanced Multi-Level, Delta-Sigma

DIGITAL-TO-ANALOG CONVERTER

APPLICATIONS

FEATURES

● INTEGRATED A/V RECEIVERS

● DVD MOVIE AND AUDIO PLAYERS

● HDTV RECEIVERS

● PIN COMPATIBLE WITH PCM1600, PCM1601

● 24-BIT RESOLUTION

●

ANALOG PERFORMANCE:

Dynamic Range: 105dB typ

SNR: 104dB typ

● CAR AUDIO SYSTEMS

● DVD ADD-ON CARDS FOR HIGH-END PCs

● DIGITAL AUDIO WORKSTATIONS

● OTHER MULTI-CHANNEL AUDIO SYSTEMS

THD+N: 0.0018% typ

Full-Scale Output: 3.1Vp-p typ

●

8x OVERSAMPLING INTERPOLATION FILTER:

Stopband Attenuation: –82dB

Passband Ripple: ±0.002dB

DESCRIPTION

● SAMPLING FREQUENCY: 10kHz to 200kHz

● ACCEPTS 16-, 18-, 20-, AND 24-BIT AUDIO DATA

● DATA FORMATS: Standard, I²S, and Left-Justified

● SYSTEM CLOCK: 128/192/256/384/512/768f_S

The PCM1604⁽¹⁾and PCM1605⁽¹⁾are CMOS mono-

lithic integrated circuits which feature six 24-bit audio

digital-to-analog converters, and support circuitry in a

small QFP-48 package. The digital-to-analog convert-

ers utilize Burr-Brown’s enhanced multi-level, delta-

sigma architecture, which employs 4th-order noise

shaping and 8-level amplitude quantization to achieve

excellent signal-to-noise performance, and a high tol-

erance to clock jitter.

●

USER-PROGRAMMABLE FUNCTIONS:

Digital Attenuation: 0dB to –63dB, 0.5dB/Step

Soft Mute

Zero Detect Mute

Zero Flags May Be Used As General

Purpose Logic Outputs

The PCM1604 and PCM1605 accept industry-stan-

dard audio data formats with 16- to 24-bit audio data.

Sampling rates up to 200kHz are supported. A full set

of user-programmable functions are accessible through

a 4-wire serial control port which supports register

write and readback functions.

Digital De-Emphasis

Digital Filter Roll-Off: Sharp or Slow

DUAL SUPPLY OPERATION:

+5V Analog, +3.3V Digital

●

NOTE: (1) The PCM1604 and PCM1605 utilize the same die and are

electrically identical. All references to the PCM1604 apply equally to

the PCM1605.

●

5V TOLERANT DIGITAL LOGIC INPUTS

PACKAGES⁽¹⁾: LQFP-48 (PCM1604) and

MQFP-48 (PCM1605)

International Airport Industrial Park

•

Mailing Address: PO Box 11400, Tucson, AZ 85734

•

Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706

• Tel: (520) 746-1111

Twx: 910-952-1111 Internet: http://www.burr-brown.com/

•

Cable: BBRCORP Telex: 066-6491

•

FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132

•

PDS-1564A

Printed in U.S.A. April, 2000

SPECIFICATIONS

All specifications at +25°C, +V_CC= +5V, +V_DD= +3.3V, system clock = 384f_S(f_S= 44.1kHz) and 24-bit data, unless otherwise noted.

PCM1604Y, PCM1605Y

PARAMETER

RESOLUTION

CONDITIONS

MIN

TYP

MAX

UNITS

24

Bits

DATA FORMAT

Audio Data Interface Formats

User Selectable

Standard, I²S, Left-Justified

16, 18, 20, 24-Bit

Data Bit Length

Audio Data Format

MSB-First, Binary Two’s Complement

Sampling Frequency (f_S)

System Clock Frequency

10

200

kHz

128, 192, 256, 384, 512, 768f_S

TTL-Compatible

DIGITAL INPUT/OUTPUT

Logic Family

Input Logic Level

V_IH

V_IL

2.0

V

0.8

Input Logic Current

(1)

I_IH

V_IN= V_DD

V_IN= 0V

V_IN= V_DD

V_IN= 0V

10

µA

(1)

I_IL

–10

100

–10

(2)

I_IH

I_IL

65

(2)

Output Logic Level

(3)

V_OH

I_OH= –4mA

I_OL= +4mA

2.4

V

(3)

V_OL

1.0

DYNAMIC PERFORMANCE⁽⁴⁾

THD+N, V_OUT= 0dB

f_S= 44.1kHz

f_S= 96kHz

f_S= 44.1kHz

0.0018

0.0035

0.65

0.0045

%

V_OUT= –60dB

f_S= 96kHz

EIAJ, A-Weighted, f_S=44.1kHz

A-Weighted, f_S= 96kHz

EIAJ, A-Weighted, f_S=44.1kHz

A-Weighted, f_S= 96kHz

f_S= 44.1kHz

0.75

105

104

103

102

101

±0.5

%

Dynamic Range

100

98

dB

Signal-to-Noise Ratio⁽⁵⁾

Channel Separation

Level Linearity Error

96

f_S= 96kHz

V_OUT= –90dB

DC ACCURACY

Gain Error

Gain Mismatch, Channel-to-Channel

Bipolar Zero Error

±1.0

±30

% of FSR

mV

V_O= 0.5V_CCat Bipolar Zero

ANALOG OUTPUT

Output Voltage

Center Voltage

Full Scale (0dB)

AC Load

62% of V_CC

50% V_CC

Vp-p

V

Load Impedance

5

kΩ

DIGITAL FILTER PERFORMANCE

Filter Characteristics, Sharp Roll-Off

Passband

±0.002dB

–3dB

0.454f_S

0.490f_S

Hz

Stopband

Passband Ripple

Stopband Attenuation

0.546f_S

Hz

dB

±0.002

Stopband = 0.546f_S

Stopband = 0.567f_S

–75

–82

dB

Filter Characteristics, Slow Roll-Off

Passband

±0.002dB

–3dB

0.274f_S

0.454f_S

Hz

dB

sec

dB

Stopband

0.732f_S

–82

Passband Ripple

Stopband Attenuation

Delay Time

±0.002

Stopband = 0.732f_S

34/f_S

±0.1

De-Emphasis Error

ANALOG FILTER PERFORMANCE

Frequency Response

f = 20kHz

f = 44kHz

–0.03

–0.20

dB

®

2

PCM1604, PCM1605

SPECIFICATIONS (Cont.)

All specifications at +25°C, +V_CC= +5V, +V_DD= +3.3V, system clock = 384f_S(f_S= 44.1kHz) and 24-bit data, unless otherwise noted.

PCM1604Y, PCM1605Y

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

POWER SUPPLY REQUIREMENTS

Voltage Range, V_DD

V_CC

+3.0

+4.5

+3.3

+5.0

20

+3.6

+5.5

28

V

(6)

Supply Current, I_DD

f_S= 44.1kHz

f_S= 96kHz

f_S= 44.1kHz

f_S= 96kHz

f_S= 44.1kHz

f_S= 96kHz

mA

mW

42

I_CC

40

56

42

266

349

Power Dissipation

409

TEMPERATURE RANGE

Operation

–25

–55

+85

°C

Storage

+125

Thermal Resistance, θ_JA

100

°C/W

NOTES: (1) Pins 38, 40, 41, 45-47 (SCKI, BCK, LRCK, DATA1, DATA2, DATA3). (2) Pins 34-37 (MDI, MC, ML, RST). (3) Pins 1-6, 48 (ZERO1-6, ZEROA),

Pin 39 (SCKO). (4) Analog performance specifications are tested with Shibasoku #725 THD Meter 400Hz HPF, 30kHz LPF on, average mode with 20kHz

bandwidth limiting. The load connected to the analog output is 5kΩ or larger, AC-coupled. (5) SNR is tested with Infinite Zero Detection off. (6) SCKO is disabled.

ABSOLUTE MAXIMUM RATINGS

ELECTROSTATIC

Power Supply Voltage, V_DD.............................................................. +4.0V

V_CC.............................................................. +6.5V

DISCHARGE SENSITIVITY

Digital Input Voltage ........................................................... –0.2V to +5.5V

Digital Output Voltage⁽¹⁾........................................... –0.2V to (V_DD+ 0.2V)

This integrated circuit can be damaged by ESD. Burr-Brown

Input Current (except power supply) ............................................... ±10mA

recommends that all integrated circuits be handled with

Power Dissipation .......................................................................... 650mW

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

Operating Temperature Range ......................................... –25°C to +85°C

Storage Temperature ...................................................... –55°C to +125°C

Lead Temperature (soldering, 5s)................................................. +260°C

ESD damage can range from subtle performance degradation

Package Temperature (IR reflow, 10s) .......................................... +235°C

to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric

NOTE: (1) Pin 33 (MDO) when output is disabled.

changes could cause the device not to meet its published

specifications.

PACKAGE/ORDERING INFORMATION

PACKAGE

DRAWING

NUMBER

SPECIFIED

TEMPERATURE

RANGE

PACKAGE

MARKING

ORDERING

NUMBER⁽¹⁾

TRANSPORT

MEDIA

PRODUCT

PACKAGE

PCM1604Y

LQFP-48

340

"

–25°C to +85°C

PCM1604Y

PCM1604Y/2K

PCM1605Y

250-Piece Tray

Tape and Reel

84-Piece Tray

Tape and Reel

"

PCM1605Y

MQFP-48

359

–25°C to +85°C

PCM1605Y

"

PCM1605Y/1K

NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces

of “PCM1604Y/2K” will get a single 2000-piece Tape and Reel.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes

no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change

without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant

any BURR-BROWN product for use in life support devices and/or systems.

®

3

PCM1604, PCM1605

BLOCK DIAGRAM

V_OUT1

Output Amp and

Low-Pass Filter

DAC

BCK

LRCK

V

_OUT2

Output Amp and

Low-Pass Filter

Audio

Serial

I/F

DAC

DATA1

DATA2

DATA3

4x/8x

Oversampling

Digital Filter

with

Function

Controller

V_OUT

3

Output Amp and

Low-Pass Filter

Enhanced

Multi-level

Delta-Sigma

Modulator

V

_COM1

V

_COM2

_OUT4

Output Amp and

Low-Pass Filter

DAC

TEST

RST

ML

V

Serial

Control

I/F

Output Amp and

Low-Pass Filter

V

_OUT5

MC

MDI

MDO

Output Amp and

Low-Pass Filter

_OUT6

System Clock

Manager

Power Supply

Zero Detect

SCKI

SCKO

PIN CONFIGURATION

Top View

LQFP, MQFP

48 47 46 45 44 43 42 41 40 39 38 37

ZERO1/GPO1

1

2

3

4

5

6

7

8

9

36 ML

35 MC

34 MDI

33 MDO

32 NC

31 NC

ZERO2/GPO2

ZERO3/GPO3

ZERO4/GPO4

ZERO5/GPO5

ZERO6/GPO6

AGND

PCM1604

PCM1605

30 V_CC

29 AGND0

28 V_CC

27 AGND1

26

_CC2

25 AGND2

0

V_CC

V_OUT6

1

V

_OUT5 10

V_OUT

4

3

11

12

V

V_OUT

13 14 15 16 17 18 19 20 21 22 23 24

®

4

PCM1604, PCM1605

PIN ASSIGNMENTS

1

NAME

I/O

O

—

O

—

O

I

DESCRIPTION

ZERO1/GPO1

ZERO2/GPO2

ZERO3/GPO3

ZERO4/GPO4

ZERO5/GPO5

ZERO6/GPO6

AGND

Zero Data Flag for V_OUT1. Can also be used as GPO pin.

Zero Data Flag for V_OUT2. Can also be used as GPO pin.

Zero Data Flag for V_OUT3. Can also be used as GPO pin.

Zero Data Flag for V_OUT4. Can also be used as GPO pin.

Zero Data Flag for V_OUT5. Can also be used as GPO pin.

Zero Data Flag for V_OUT6. Can also be used as GPO pin.

Analog Ground

2

3

4

5

6

7

8

V_CC

Analog Power Supply, +5V

9

V_OUT

6

5

4

3

2

1

Voltage Output for Audio Signal Corresponding to Rch on DATA3.

Voltage Output for Audio Signal Corresponding to Lch on DATA3.

Voltage Output for Audio Signal Corresponding to Rch on DATA2.

Voltage Output for Audio Signal Corresponding to Lch on DATA2.

Voltage Output for Audio Signal Corresponding to Rch on DATA1.

Voltage Output for Audio Signal Corresponding to Lch on DATA1.

Common Voltage Output. This pin should be bypassed with a 10µF capacitor to AGND.

Analog Ground

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

V_COM

AGND6

V_CC

AGND5

V_CC

AGND4

V_CC

AGND3

V_CC

AGND2

V_CC

AGND1

V_CC

AGND0

V_CC

2

1

6

Analog Power Supply, +5V

Analog Ground

5

Analog Power Supply, +5V

Analog Ground

4

Analog Power Supply, +5V

Analog Ground

3

Analog Power Supply, +5V

Analog Ground

2

Analog Power Supply, +5V

Analog Ground

1

Analog Power Supply, +5V

Analog Ground

0

Analog Power Supply, +5V

NC

No Connection. Must be open.

MDO

MDI

MC

Serial Data Output for Function Register Control Port⁽³⁾

Serial Data Input for Function Register Control Port⁽¹⁾

Shift Clock for Function Register Control Port⁽¹⁾

Latch Enable for Function Register Control Port⁽¹⁾

System Reset, Active LOW⁽¹⁾

I

ML

I

RST

SCKI

SCKO

I

System Clock In. Input frequency is 128, 192, 256, 384, 512 or 768f_S.⁽²⁾

O

Buffered Clock Output. Output frequency is 128, 192, 256, 384, 512, or 768f_Sor one-half of 128, 192, 256, 384, 512,

or 768f_S.

40

41

42

43

44

45

46

47

48

BCK

LRCK

TEST

I

Shift Clock Input for Serial Audio Data⁽²⁾

Left and Right Clock Input. This clock is equal to the sampling rate, f_S.⁽²⁾

Test Pin. This pin should be connected to DGND.⁽¹⁾

Digital Power Supply, +3.3V

—

I

V_DD

DGND

DATA1

DATA2

DATA3

ZEROA

Digital Ground for +3.3V

Serial Audio Data Input for V_OUT1 and V_OUT2⁽²⁾

Serial Audio Data Input for V_OUT3 and V_OUT4⁽²⁾

Serial Audio Data Input for V_OUT5 and V_OUT6⁽²⁾

Zero Data Flag. Logical “AND” of ZERO1 through ZERO6.

I

O

NOTES: (1) Schmitt-Trigger input with internal pull-down, 5V tolerant. (2) Schmitt-Trigger input, 5V tolerant. (3) Tri-state output.

®

5

PCM1604, PCM1605

TYPICAL PERFORMANCE CURVES

All specifications at +25°C, V_CC= 5V, V_DD= 3.3V, SYSCLK = 384f_S(f_S= 44.1kHz), and 24-bit input data, unless otherwise noted.

DIGITAL FILTER

Digital Filter (De-Emphasis Off, f_S= 44.1kHz)

FREQUENCY RESPONSE

(Sharp Roll-Off)

PASSBAND RIPPLE

(Sharp Roll-Off)

0

–20

0.003

0.002

0.001

0

–40

–60

–80

–100

–120

–140

–160

–0.001

–0.002

–0.003

0

0.5

1

1.5

2

2.5

3

3.5

4

0

0.1

0.2

0.3

0.4

0.5

Frequency (x f_S)

FREQUENCY RESPONSE

(Slow Roll-Off)

TRANSITION CHARACTERISTICS

(Slow Roll-Off)

0

–20

0

–2

–4

–40

–6

–8

–60

–10

–12

–14

–16

–18

–20

–80

–100

–120

–140

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

0

0.1

0.2

0.3

0.4

0.5

0.6

Frequency (x f_S)

De-Emphasis Error

DE-EMPHASIS FREQUENCY RESPONSE (f_S= 32kHz)

DE-EMPHASIS ERROR (f_S= 32kHz)

0

–2

0.5

0.3

–4

0.1

–6

–8

–10

–0.1

–0.3

–0.5

0

2

4

6

8

10

12

14

0

2

4

6

8

10

12

14

Frequency (kHz)

DE-EMPHASIS FREQUENCY RESPONSE (f_S= 44.1kHz)

DE-EMPHASIS ERROR (f_S= 44.1kHz)

0.5

0.3

0

–2

–4

–6

–8

0.1

–0.1

–0.3

–0.5

–10

2

4

6

8

10

12

14

16

18

20

0

2

4

6

8

10

12

14

16

18

20

Frequency (kHz)

DE-EMPHASIS FREQUENCY RESPONSE (f_S= 48kHz)

DE-EMPHASIS ERR0R (f_S= 48kHz)

0

–2

–4

–6

–8

0.5

0.3

0.1

–0.1

–0.3

–0.5

–10

2

4

6

8

10 12 14 16 18 20 22

0

2

4

6

8

10 12 14 16 18 20 22

Frequency (kHz)

®

6

PCM1604, PCM1605

TYPICAL PERFORMANCE CURVES (Cont.)

All specifications at +25°C, V_CC= 5V, V_DD= 3.3V, SYSCLK = 384f_S(f_S= 44.1kHz), and 24-bit input data, unless otherwise noted.

ANALOG DYNAMIC PERFORMANCE

Supply Voltage Characteristics

TOTAL HARMONIC DISTORTION + NOISE

vs POWER SUPPLY (V_DD= 3.3V)

DYNAMIC RANGE

vs POWER SUPPLY (V_DD= 3.3V)

10

1

110

108

106

104

102

100

98

96kHz, 384f_S

44.1kHz, 384f_S

–60dB

44.1kHz, 384f_S

0.1

96kHz, 384f_S

0.01

0.001

0dB

44.1kHz, 384f_S

4.5

96

4.0

5.0

5.5

6.0

4.0

4.5

5.0

5.5

6.0

V_CC(V)

CHANNEL SEPARATION

SIGNAL-TO-NOISE RATIO

vs POWER SUPPLY (V_DD= 3.3V)

110

108

106

104

102

100

98

110

108

106

104

102

100

98

44.1kHz, 384f_S

96kHz, 384f_S

96

4.0

4.5

5.0

5.5

6.0

4.0

4.5

5.0

5.5

6.0

V_CC(V)

V

_CC(V)

®

7

PCM1604, PCM1605

TYPICAL PERFORMANCE CURVES (Cont.)

All specifications at V_DD= +3.3V, 128f_Ssystem clock, 64x oversampling, and 24-bit data. Only two channels (V_OUT1 and V_OUT2) are operated. All other channels

are set to all zero input data and DAC operation is disabled (bits DAC3 through DAC6 of Register 8 are set to 1).

TOTAL HARMONIC DISTORTION + NOISE

vs POWER SUPPLY (V_DD= 3.3V)

DYNAMIC RANGE

vs POWER SUPPLY (V_DD= 3.3V)

10

1

110

108

106

104

102

100

98

–60dB/192kHz-128f_S

192kHz-128f_S

0.1

0.01

0.001

0dB/192kHz-128f_S

96

4

4.5

5

5.5

6

4

4.5

5

5.5

6

V_CC(V)

SIGNAL-TO-NOISE RATIO

vs POWER SUPPLY (V_DD= 3.3V)

CHANNEL SEPARATION

vs POWER SUPPLY (V_DD= 3.3V)

110

108

106

104

102

100

98

110

108

106

104

102

100

98

192kHz-128f_S

96

4

4.5

5

5.5

6

4

4.5

5

5.5

6

V_CC(V)

®

8

PCM1604, PCM1605

TYPICAL PERFORMANCE CURVES (Cont.)

All specifications at +25°C, V_CC= 5V, V_DD= 3.3V, SYSCLK = 384f_S(f_S= 44.1kHz), and 24-bit input data, unless otherwise noted.

ANALOG DYNAMIC PERFORMANCE (Cont.)

Temperature Characteristics

TOTAL HARMONIC DISTORTION + NOISE

vs TEMPERATURE

DYNAMIC RANGE vs TEMPERATURE

110

108

106

104

102

100

98

10

1

96kHz, 384f_S

44.1kHz, 384f_S

–60dB

44.1kHz, 384f_S

0.1

96kHz, 384f_S

0.01

0.001

44.1kHz, 384f_S

0dB

96

–25

0

25

50

75

100

–25

0

25

50

75

100

Temperature (°C)

SIGNAL-TO-NOISE RATIO vs TEMPERATURE

CHANNEL SEPARATION vs TEMPERATURE

110

108

106

104

102

100

98

110

108

106

104

102

100

98

44.1kHz, 384f_S

96kHz, 384f_S

96

–25

0

25

50

75

100

–25

0

25

50

75

100

Temperature (°C)

®

9

PCM1604, PCM1605

TYPICAL PERFORMANCE CURVES (Cont.)

All specifications at V_CC= +5V, V_DD= +3.3V, 128f_Ssystem clock, 64x oversampling, and 24-bit data. Only two channels (V_OUT1 and V_OUT2) are operated. All other

channels are set to all zero input data and DAC operation is disabled (bits DAC3 through DAC6 of Register 8 are set to 1).

TOTAL HARMONIC DISTORTION + NOISE

DYNAMIC RANGE vs TEMPERATURE

vs TEMPERATURE

110

108

106

104

102

100

98

10

1

192kHz-128f_S/–60dB

192kHz-128f_S

0.1

0.01

192kHz-128f_S/0dB

96

0.001

–50

–25

0

25

50

75

100

–50

–25

0

25

50

75

100

Temperature (°C)

SIGNAL-TO-NOISE RATIO vs TEMPERATURE

CHANNEL SEPARATION vs TEMPERATURE

110

108

106

104

102

100

98

110

108

106

104

102

100

98

192kHz-128f_S

96

–50

–25

0

25

50

75

100

–50

–25

0

25

50

75

100

Temperature (°C)

®

10

PCM1604, PCM1605

POWER-ON AND EXTERNAL RESET FUNCTIONS

SYSTEM CLOCK AND RESET

FUNCTIONS

The PCM1604 includes a power-on reset function. Figure 2

shows the operation of this function.

SYSTEM CLOCK INPUT

The system clock input at SCKI should be active for at least

one clock period prior to V_DD= 2.0V. With the system clock

active and V_DD> 2.0V, the power-on reset function will be

enabled. The initialization sequence requires 1024 system

clocks from the time V_DD> 2.0V. After the initialization

period, the PCM1604 will be set to its reset default state, as

described in the Mode Control Register section of this data

sheet.

The PCM1604 and PCM1605 require a system clock for

operating the digital interpolation filters and multi-level

delta-sigma modulators. The system clock is applied at the

SCKI input (pin 38). Table I shows examples of system

clock frequencies for common audio sampling rates.

Figure 1 shows the timing requirements for the system clock

input. For optimal performance, it is important to use a clock

source with low phase jitter and noise. Burr-Brown’s

PLL1700 multi-clock generator is an excellent choice for

providing the PCM1604 system clock source.

The PCM1604 also includes an external reset capability

using the RST input (pin 37). This allows an external

controller or master reset circuit to force the PCM1604 to

initialize to its reset default state. For normal operation, RST

should be set to a logic ‘1’.

To obtain optimal dynamic performance when operating

with a 192kHz sampling frequency, it is recommended that

only two channels be enabled for operation (V_OUT1 and

V_OUT2). The remaining four channels should be disabled by

setting bits DAC3 through DAC6 of control register 8 to

logic 1 state.

Figure 3 shows the external reset operation and timing. The

RST pin is set to logic ‘0’ for a minimum of 20ns. The RST

pin is then set to a logic ‘1’ state, which starts the initializa-

tion sequence, which lasts for 1024 system clock periods.

After the initialization sequence is completed, the PCM1604

will be set to its reset default state, as described in the Mode

Control Registers section of this data sheet.

SYSTEM CLOCK OUTPUT

A buffered version of the system clock input is available at

the SCKO output (pin 39). SCKO can operate at either full

(f_SCKI) or half (f_SCKI/2) rate. The SCKO output frequency

may be programmed using the CLKD bit of Control Regis-

ter 9. The SCKO output pin can also be enabled or disabled

using the CLKE bit of Control Register 9. The default is

SCKO enabled.

The external reset is especially useful in applications where

there is a delay between PCM1604 power up and system

clock activation. In this case, the RST pin should be held at

a logic ‘0’ level until the system clock has been

activated.

SYSTEM CLOCK FREQUENCY (f_SCKI

(MHz)

)

SAMPLING FREQUENCY

(f_S)

128f_S

192f_S

256f_S

384f_S

512f_S

768f_S

16kHz

32kHz

—

4.0960

8.1920

6.1440

12.2880

8.1920

16.3840

12.2880

24.5760

44.1kHz

48kHz

—

11.2896

16.9344

22.5792

33.8688

—

12.2880

22.5792

24.5760

See Note 2

18.4320

24.5760

36.8640

88.2kHz

96kHz

—

33.8688

45.1584

See Note 1

See Note 2

12.2880

22.5792

24.5760

18.4320

33.8688

36.8640

49.1520

176.4kHz

192

See Note 2

NOTE: (1) The 768f_Ssystem clock rate is not supported for f_S> 64kHz. (2) This system clock rate is not supported for the given sampling frequency.

TABLE I. System Clock Rates for Common Audio Sampling Frequencies.

t_SCKIH

2.0V

0.8V

“H”

“L”

SCKI

f_SCKI

t_SCKIH

System Clock Pulse Width High t_SCKIH

System Clock Pulse Width Low t_SCKIL

: 7ns min

FIGURE 1. System Clock Input Timing.

®

11

PCM1604, PCM1605

2.4V

2.0V

1.6V

V_CC= V_DD

Reset

Reset Removal

Internal Reset

1024 system clocks

System Clock

(SCKI)

FIGURE 2. Power-On Reset Timing.

RST

(1)

t_RST

Reset

Reset Removal

Internal Reset

1024 system clocks

System Clock

(SCKI)

NOTE: (1) t_RST= 20ns min.

FIGURE 3. External Reset Timing.

DATA1, DATA2 and DATA3 each carry two audio channels,

designated as the Left and Right channels. The Left channel

data always precedes the Right channel data in the serial data

stream for all data formats. Table II shows the mapping of the

digital input data to the analog output pins.

AUDIO SERIAL INTERFACE

The audio serial interface for the PCM1604 is comprised

of a 5-wire synchronous serial port. It includes LRCK (pin

41), BCK (pin 40), DATA1 (pin 45), DATA2 (pin 46) and

DATA3 (pin 47). BCK is the serial audio bit clock, and is

used to clock the serial data present on DATA1, DATA2

and DATA3 into the audio interface’s serial shift registers.

Serial data is clocked into the PCM1604 on the rising edge

of BCK. LRCK is the serial audio left/right word clock. It

is used to latch serial data into the serial audio interface’s

internal registers.

DATA INPUT

CHANNEL

ANALOG OUTPUT

DATA1

DATA2

DATA3

Left

Right

Left

V_OUT

_OUT2

V_OUT

1

V

3

Right

Left

V_OUT4

V_OUT5

V_OUT6

Both LRCK and BCK must be synchronous to the system

clock. Ideally, it is recommended that LRCK and BCK be

derived from the system clock input or output, SCKI or

SCKO. The left/right clock, LRCK, is operated at the

sampling frequency (f_S). The bit clock, BCK, may be

operated at 48 or 64 times the sampling frequency.

Right

TABLE II. Audio Input Data to Analog Output Mapping.

SERIAL CONTROL INTERFACE

The serial control interface is a 4-wire synchronous serial port

which operates asynchronously to the serial audio interface.

The serial control interface is utilized to program and read the

on-chip mode registers. The control interface includes MDO

(pin 33), MDI (pin 34), MC (pin 35), and ML (pin 36). MDO

is the serial data output, used to read back the values of the

mode registers; MDI is the serial data input, used to program

the mode registers; MC is the serial bit clock, used to shift

data in and out of the control port and ML is the control port

latch clock.

AUDIO DATA FORMATS AND TIMING

The PCM1604 supports industry-standard audio data for-

mats, including Standard, I²S, and Left-Justified. The data

formats are shown in Figure 4. Data formats are selected

using the format bits, FMT[2:0], in Control Register 9. The

default data format is 24-bit Standard. All formats require

Binary Two’s Complement, MSB-first audio data. Figure

5 shows a detailed timing diagram for the serial audio

interface.

®

12

PCM1604, PCM1605

®

13

PCM1604, PCM1605

LRCK

BCK

50% of V_DD

t_BCH

t_BCL

t_LB

t_BCY

t_BL

50% of V_DD

DATA1-DATA3

t_DS

t_DH

SYMBOL

PARAMETER

MIN

MAX

UNITS

(1)

t_BCY

t_BCH

t_BCL

t_BL

BCK Pulse Cycle Time

BCK High Level Time

BCK Low Level Time

48 or 64f_S

35

10

ns

BCK Rising Edge to LRCK Edge

LRCK Falling Edge to BCK Rising Edge

DIN Set Up Time

t_LB

t_DS

t_DH

DIN Hold Time

NOTE: (1) f_Sis the sampling frequency (e.g., 44.1kHz, 48kHz, 96kHz, etc.)

FIGURE 5. Audio Interface Timing.

MSB

LSB

D0

R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0

D7

D6

D5

D4

D3

D2

D1

Register Index (or Address)

Register Data

Read/Write Operation

0 = Write Operation

1 = Read Operation (register index is ignored)

FIGURE 6. Control Data Word Format for MDI.

ML

MC

MDI

X

0

IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 D7 D6 D5

D4 D3 D2 D1 D0

X

D15 D14

FIGURE 7. Write Operation Timing.

REGISTER WRITE OPERATION

SINGLE REGISTER READ OPERATION

All Write operations for the serial control port use 16-bit data

words. Figure 6 shows the control data word format. The most

significant bit is the Read/Write (R/W) bit. When set to ‘0’, this

bit indicates a Write operation. There are seven bits, labeled

IDX[6:0], that set the register index (or address) for the Write

operation. The least significant eight bits, D[7:0], contain the

data to be written to the register specified by IDX[6:0].

Read operations utilize the 16-bit control word format shown

in Figure 6. For Read operations, the Read/Write (R/W) bit is

set to ‘1’. Read operations ignore the index bits, IDX[6:0], of

the control data word. Instead, the REG[6:0] bits in Control

Register 11 are used to set the index of the register that is to be

read during the Read operation. Bits IDX[6:0] should be set to

00_Hfor Read operations.

Figure 7 shows the functional timing diagram for writing the

serial control port. ML is held at a logic ‘1’ state until a register

needs to be written. To start the register write cycle, ML is set

to logic ‘0’. Sixteen clocks are then provided on MC, corre-

sponding to the 16-bits of the control data word on MDI. After

the sixteenth clock cycle has completed, ML is set to logic ‘1’

to latch the data into the indexed mode control register.

Figure 8 details the Read operation. First, Control Register 11

must be written with the index of the register to be read back.

Additionally, the INC bit must be set to logic ‘0’ in order to

disable the Auto-Increment Read function. The Read cycle is

then initiated by setting ML to logic ‘0’ and setting the R/W bit

of the control data word to logic ‘1’, indicating a Read

operation. MDO remains at a high-impedance state until the

®

14

PCM1604, PCM1605

®

15

PCM1604, PCM1605

last 8 bits of the 16-bit read cycle, which corresponds to the

8 data bits of the register indexed by the REG[6:0] bits of

Control Register 11. The Read cycle is completed when ML

is set to ‘1’, immediately after the MC clock cycle for the

least significant bit of indexed control register has com-

pleted.

tion starts on the next HIGH to LOW transition of the ML

pin. The Read cycle starts by setting the R/W bit of the

control word to ‘1’, and setting all of the IDX[6:0] bits to

‘0.’. All subsequent bits input on the MDI are ignored while

ML is set to ‘0.’ For the first 8 clocks of the Read cycle,

MDO is set to a high-impedance state. This is followed by

a sequence of 8-bit words, each corresponding to the data

contained in Control Registers 1 through N, where N is

defined by the REG[6:0] bits in Control Register 11. The

Read cycle is completed when ML is set to ‘1’, immediately

after the MC clock cycle for the least significant bit of

Control Register N has completed.

AUTO-INCREMENT READ OPERATION

The Auto-Increment Read function allows for multiple reg-

isters to be read sequentially. The Auto-Increment Read

function is enabled by setting the INC bit of Control Register

11 to ‘1’. The sequence always starts with Register 1, and

ends with the register indexed by the REG[6:0] bits in

Control Register 11.

CONTROL INTERFACE TIMING REQUIREMENTS

Figure 10 shows a detailed timing diagram for the Serial

Control interface. Pay special attention to the setup and hold

times, as well as t_MLSand t_MLH, which define minimum delays

between edges of the ML and MC clocks. These timing

parameters are critical for proper control port operation.

Figure 9 shows the timing for the Auto-Increment Read

operation. The operation begins by writing Control Register

11, setting INC to ‘1’ and setting REG[6:0] to the last

register to be read in the sequence. The actual Read opera-

t_MHH

50% of V_DD

ML

t_MLS

t_MCH

t_MCL

t_MLH

50% of V_DD

MC

t_MCY

LSB

MDI

50% of V_DD

t_MDS

t_MCH

t_MOS

LSB

50% of V_DD

MDO

SYMBOL

PARAMETER

MIN

MAX

UNITS

t_MCY

t_MCL

t_MCH

t_MHH

t_MLS

t_MLH

t_MDI

MC Pulse Cycle Time

MC Low Level Time

MC High Level Time

ML High Level Time

100

50

ns

50

300

20

ML Falling Edge to MC Rising Edge

ML Hold Time⁽¹⁾

20

Hold Time

15

t_MDS

t_MOS

MDL Set Up Time

20

MC Falling Edge to MDSO Stable

30

NOTE: (1) MC rising edge for LSB to ML rising edge.

FIGURE 10. Control Interface Timing.

®

16

PCM1604, PCM1605

Register Map

MODE CONTROL REGISTERS

User-Programmable Mode Controls

The mode control register map is shown in Table IV. Each

register includes a R/W bit, which determines whether a

register read (R/W =1) or write (R/W = 0) operation is

performed. Each register also includes an index (or address)

indicated by the IDX[6:0] bits.

The PCM1604 includes a number of user-programmable

functions which are accessed via control registers. The

registers are programmed using the Serial Control Interface

which was previously discussed in this data sheet. Table III

lists the available mode control functions, along with their

reset default conditions and associated register index.

FUNCTION

RESET DEFAULT

CONTROL REGISTER

INDEX, IDX[6:0]

Digital Attenuation Control, 0dB to –63dB in 0.5dB Steps

Digital Attenuation Load Control

Digital Attenuation Rate Select

Soft Mute Control

0dB, No Attenuation

Data Load Disabled

2/f_S

1 through 6

01_H- 07_H

07_H

7

07_H

Mute Disabled

DAC 1-6 Enabled

Disabled

7

07_H

DAC 1-6 Operation Control

Infinite Zero Detect Mute

8

08_H

8

08_H

Audio Data Format Control

Digital Filter Roll-Off Control

SCKO Frequency Selection

SCKO Output Enable

24-Bit Standard Format

Sharp Roll-Off

9

09_H

9

09_H

Full Rate (= f_SCKI

SCKO Enabled

)

9

09_H

9

09_H

De-Emphasis Function Control

De-Emphasis Sample Rate Selection

Output Phase Reversal

De-Emphasis Disabled

44.1kHz

10

11

12

0A_H

0B_H

0C_H

Disabled

Read Register Index Control

REG[6:0] = 01_H

Read Auto-Increment Control

Auto-Increment Disabled

Zero Flags Enabled

Disabled

General Purpose Output Enable

General Purpose Output Bits (GPO1-GPO6)

Oversampling Rate Control

64x (32x for 192kHz)

TABLE III. User-Programmable Mode Controls.

B15

R/W

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

Register 0

Register 1

Register 2

Register 3

Register 4

Register 5

Register 6

IDX6

IDX5

IDX4

IDX3

IDX2

IDX1

IDX0

N/A

R/W

IDX6

IDX5

IDX4

IDX3

IDX2

IDX1

IDX0

AT17

AT27

AT37

AT47

AT57

AT67

AT16

AT26

AT36

AT46

AT56

AT66

AT15

AT25

AT35

AT45

AT55

AT65

AT14

AT24

AT34

AT44

AT54

AT64

AT13

AT23

AT33

AT43

AT53

AT63

AT12

AT22

AT32

AT42

AT52

AT62

AT11 AT10

AT21 AT20

AT31 AT30

AT41 AT40

AT51 AT50

AT61 AT60

Register 7

Register 8

Register 9

Register 10

Register 11

Register 12

R/W

IDX6

IDX5

IDX4

IDX3

IDX2

IDX1

IDX0 ATLD ATTS MUT6 MUT5 MUT4 MUT3 MUT2 MUT1

IDX0

res

INC

INZD DAC6 DAC5 DAC4 DAC3 DAC2 DAC1

res

FLT0 CLKD CLKE FMT2 FMT1 FMT0

REV DMF1 DMF0 DM56 DM34 DM12

REG6 REG5 REG4 REG3 REG2 REG1 REG0

IDX0 OVER GPOE GPO6 GPO5 GPO4 GPO3 GPO2 GPO1

TABLE IV. Mode Control Register Map.

®

17

PCM1604, PCM1605

REGISTER DEFINITIONS

B15

R/W

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

Register 1

Register 2

Register 3

Register 4

Register 5

Register 6

IDX6

IDX5

IDX4

IDX3

IDX2

IDX1

IDX0

AT17 AT16

AT27 AT26

AT37 AT36

AT47 AT46

AT57 AT56

AT67 AT66

AT15

AT14

AT13

AT12 AT11 AT10

AT22 AT21 AT20

AT32 AT31 AT30

AT42 AT41 AT40

AT52 AT51 AT50

AT62 AT61 AT60

R/W

IDX6

IDX5

IDX4

IDX3

IDX2

IDX1

IDX0

AT25

AT35

AT45

AT55

AT65

AT24

AT34

AT44

AT54

AT64

AT23

AT33

AT43

AT53

AT63

R/W

Read/Write Mode Select

When R/W = 0, a Write operation is performed.

When R/W = 1, a Read operation is performed.

Default Value: 0

ATx[7:0]

Digital Attenuation Level Setting

where x = 1-6, corresponding to the DAC output V_OUTx.

These bits are Read/Write.

Default Value: 1111 1111_B

Each DAC output, V_OUT1 through V_OUT6, has a digital attenuator associated with it. The attenuator may be

set from 0dB to –63dB, in 0.5dB steps. Alternatively, the attenuator may be set to infinite attenuation (or

mute).

The attenuation data for each channel can be set individually. However, the data load control (ATLD bit of

Control Register 7) is common to all six attenuators. ATLD must be set to ‘1’ in order to change an

attenuator’s setting. The attenuation level may be set using the formula below.

Attenuation Level (dB) = 0.5 (ATx [7:0]_DEC– 255)

where: ATx [7:0]_DEC= 0 through 255

for: ATx [7:0]_DEC= 0 through 128, the attenuator is set to infinite attenuation.

The following table shows attenuator levels for various settings.

ATx[7:0]

Decimal Value

Attenuator Level Setting

1111 1111_B

1111 1110_B

1111 1101_B

255

254

253

•

0dB, No Attenuation (default)

–0.5dB

–1.0dB

•

1000 0010_B

1000 0001_B

1000 0000_B

130

129

128

•

–62.5dB

–63.0dB

Mute

•

0000 0000_B

0

Mute

®

18

PCM1604, PCM1605

B15

R/W

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

Register 7

IDX6

IDX5

IDX4

IDX3

IDX2

IDX1

IDX0

ATLD ATTS MUT6 MUT5 MUT4 MUT3 MUT2 MUT1

R/W

Read/Write Mode Select

When R/W = 0, a Write operation is performed.

When R/W = 1, a Read operation is performed.

Default Value: 0

ATLD

Attenuation Load Control

This bit is Read/Write.

Default Value: 0

ATLD = 0

ATLD = 1

Attenuation Control Disabled (default)

Attenuation Control Enabled

The ATLD bit is used to enable loading of attenuation data set by registers 1 through 6. When ATLD = 0, the

attenuation settings remain at the previously programmed level, ignoring new data loaded to registers 1 through

6. When ATLD = 1, attenuation data written to registers 1 through 6 is loaded normally.

ATTS

Attenuation Rate Select

This bit is Read/Write.

Default Value: 0

ATTS = 0

ATTS = 1

Attenuation rate is 2/f_S(default)

Attenuation rate is 4/f_S

Changes in attenuator levels are made by incrementing or decrementing the attenuator by one step (0.5dB) for

every 2/f_Sor 4/f_Stime interval until the programmed attenuator setting is reached. This helps to minimize

audible ‘clicking’, or zipper noise, while the attenuator is changing levels. The ATTS bit allows you to select

the rate at which the attenuator is decremented/incremented during level transitions.

MUTx

Soft Mute Control

where x = 1-6, corresponding to the DAC output V_OUTx.

These bits are Read/Write.

Default Value: 0

MUTx = 0

MUTx = 1

Mute Disabled (default)

Mute Enabled

The mute bits, MUT1 through MUT6, are used to enable or disable the Soft Mute function for the

corresponding DAC outputs, V_OUT1 through V_OUT6. The Soft Mute function is incorporated into the digital

attenuators. When Mute is disabled (MUTx = 0), the attenuator and DAC operate normally. When Mute

is enabled by setting MUTx = 1, the digital attenuator for the corresponding output will be decremented

from the current setting to the infinite attenuation setting one attenuator step (0.5dB) at a time, with the rate

of change programmed by the ATTS bit. This provides a quiet, ‘pop’ free muting of the DAC output. Upon

returning from Soft Mute, by setting MUTx = 0, the attenuator will be incremented one step at a time to

the previously programmed attenuator level.

®

19

PCM1604, PCM1605

B15

R/W

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

REGISTER 8

IDX6

IDX5

IDX4

IDX3

IDX2

IDX1

IDX0

res

INZD

DAC6 DAC5 DAC4 DAC3 DAC2 DAC1

R/W

Read/Write Mode Select

When R/W = 0, a Write operation is performed.

When R/W = 1, a Read operation is performed.

Default Value: 0

INZD

Infinite Zero Detect Mute Control

This bit is Read/Write.

Default Value: 0

INZD = 0

INZD = 1

Infinite Zero Detect Mute Disabled (default)

Infinite Zero Detect Mute Enabled

The INZD bit is used to enable or disable the Zero Detect Mute function described in the Zero Flag and Infinite

Zero Detect Mute section in this data sheet. The Zero Detect Mute function is independent of the Zero Flag

output operation, so enabling or disabling the INZD bit has no effect on the Zero Flag outputs (ZERO1-ZERO6,

ZEROA).

DACx

DAC Operation Control

where x = 1-6, corresponding to the DAC output V_OUTx.

These bits are Read/Write.

Default Value: 0

DACx = 0

DACx = 1

DAC Operation Enabled (default)

DAC Operation Disabled

The DAC operation controls are used to enable and disable the DAC outputs, V_OUT1 through V_OUT6. When

DACx = 0, the output amplifier input is connected to the DAC output. When DACx = 1, the output amplifier

input is switched to the DC common-mode voltage (V_COM1 or V_COM2), equal to V_CC/2.

®

20

PCM1604, PCM1605

B15

R/W

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

REGISTER 9

IDX6

IDX5

IDX4

IDX3

IDX2

IDX1

IDX0

res

FLT0 CLKD CLKE FMT2 FMT1 FMT0

R/W

Read/Write Mode Select

When R/W = 0, a Write operation is performed.

When R/W = 1, a Read operation is performed.

Default Value: 0

FLT0

Digital Filter Roll-Off Control

These bits are Read/Write.

Default Value: 000_B

FLT0 = 0

FLT0 = 1

Sharp Roll-Off (default)

Slow Roll-Off

Bit FLT0 allows the user to select the digital filter roll-off that is best suited to their application. Two filter roll-

off sections are available: Sharp or Slow. The filter responses for these selections are shown in the Typical

Performance Curves section of this data sheet.

CLKD

SCKO Frequency Selection

This bit is Read/Write.

Default Value: 0

CLKD = 0

CLKD = 1

Full Rate, f_SCKO= f_SCKI(default)

Half Rate, f_SCKO= f_SCKI/2

The CLKD bit is used to determine the clock frequency at the system clock output pin, SCKO.

CLKE

SCKO Output Enable

This bit is Read/Write.

Default Value: 0

CLKE = 0

CLKE = 1

SCKO Enabled (default)

SCKO Disabled

The CLKE bit is used to enable or disable the system clock output pin, SCKO. When SCKO is enabled, it will

output either a full or half rate clock, based upon the setting of the CLKD bit.

FMT[2:0] Audio Interface Data Format

These bits are Read/Write.

Default Value: 000_B

FMT[2:0]

Audio Data Format Selection

000

001

010

011

100

101

110

111

24-Bit Standard Format, Right-Justified Data (default)

20-Bit Standard Format, Right-Justified Data

18-Bit Standard Format, Right-Justified Data

16-Bit Standard Format, Right-Justified Data

I²S Format, 16- to 24-bits

Left-Justified Format, 16- to 24-Bits

Reserved

The FMT[2:0] bits are used to select the data format for the serial audio interface.

®

21

PCM1604, PCM1605

B15

R/W

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

REGISTER 10

IDX6

IDX5

IDX4

IDX3

IDX2

IDX1

IDX0

res

REV

DMF1 DMF0 DM56 DM34 DM12

R/W

Read/Write Mode Select

When R/W = 0, a Write operation is performed.

When R/W = 1, a Read operation is performed.

Default Value: 0

DMF[1:0]

Sampling Frequency Selection for the De-Emphasis Function

These bits are Read/Write.

Default Value: 00_B

DMF[1:0]

De-Emphasis Same Rate Selection

00

01

10

11

44.1 kHz (default)

48 kHz

32 kHz

Reserved

The DMF[1:0] bits are used to select the sampling frequency used for the Digital De-Emphasis function when

it is enabled. The de-emphasis curves are shown in the Typical Performance Curves section of this data sheet.

DM12

Digital De-Emphasis Control for Channels 1 and 2

This bit is Read/Write.

Default Value: 0

DM12 = 0

DM12 = 1

De-Emphasis Disabled for Channels 1 and 2 (default)

De-Emphasis Enabled for Channels 1 and 2

The DM12 bit is used to enable or disable the De-emphasis function for V_OUT1 and V_OUT2, which correspond

to the Left and Right channels of the DATA1 input.

DM34

Digital De-Emphasis Control for Channels 3 and 4

This bit is Read/Write.

Default Value: 0

DM34 = 0

DM34 = 1

De-Emphasis Disabled for Channels 3 and 4 (default)

De-Emphasis Enabled for Channels 3 and 4

The DM34 bit is used to enable or disable the De-Emphasis function for V_OUT3 and V_OUT4, which correspond

to the Left and Right channels of the DATA2 input.

DM56

Digital De-Emphasis Control for Channels 5 and 6

This bit is Read/Write.

Default Value: 0

DM56 = 0

DM56 = 1

De-Emphasis Disabled for Channels 5 and 6 (default)

De-Emphasis Enabled for Channels 5 and 6

The DM56 bit is used to enable or disable the de-emphasis function for V_OUT5 and V_OUT6, which correspond

to the Left and Right channels of the DATA3 input.

REV

Output Phase Reversal

This bit is Read/Write.

Default Value: 0

REV = 0

REV = 1

Normal Output (non-inverted)

Inverted Output

The REV bit is used to invert the output phase for V_OUT1 through V_OUT6. When the REV bit is enabled, the zero-

detect functions (including zero-detect mute and the zero flags) are not available.

®

22

PCM1604, PCM1605

B15

R/W

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

REGISTER 11

IDX6

IDX5

IDX4

IDX3

IDX2

IDX1

IDX0

INC

REG6 REG5 REG4 REG3 REG2 REG1 REG0

R/W

Read/Write Mode Select

When R/W = 0, a Write operation is performed.

When R/W = 1, a Read operation is performed.

Default Value: 0

INC

Auto-Increment Read Control

This bit is Read/Write.

Default Value: 0

INC = 0

INC = 1

Auto-Increment Read Disabled (default)

Auto-Increment Read Enabled

The INC bit is used to enable or disable the Auto-Increment Read feature of the Serial Control Interface. Refer

to the Serial Control Interface section of this data sheet for details regarding Auto-Increment Read operation.

REG[6:0]

Read Register Index

These bits are Read/Write.

Default Value: 01_H

Bits REG[6:0] are used to set the index of the register to be read when performing a Single Register Read

operation. In the case of an Auto-Increment Read operation, bits REG[6:0] indicate the index of the last register

to be read in the in the Auto-Increment Read sequence. For example, if Registers 1 through 6 are to be read

during an Auto-Increment Read operation, bits REG[6:0] would be set to 06_H.

Refer to the Serial Control Interface section of this data sheet for details regarding the Single Register and Auto-

Increment Read operations.

®

23

PCM1604, PCM1605

B15

R/W

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

REGISTER 12

IDX6

IDX5

IDX4

IDX3

IDX2

IDX1

IDX0 OVER GPOE GPO6 GPO5 GPO4 GPO3 GPO2 GPO1

GPOx

General Purpose Logic Output

Where: x = 1 through 6, corresponding to pins GPO1 through GPO6.

These bits are Read/Write.

Default Value: 0

GPOx = 0

GPOx = 1

Set GPOx to ‘0’.

Set GPOx to ‘1’.

The general-purpose output pins, GPO1 through GPO6, are enabled by setting GPOE = 1. These pins are used

as general-purpose outputs for controlling user-defined logic functions. When general-purpose outputs are

disabled (GPOE = 0), they default to the zero-flag function, ZERO1 through ZERO6.

GPOE

General Purpose Output Enable

This bit is Read/Write.

Default Value: 0

GPOE = 0

GPOE = 1

General-Purpose Outputs Disabled.

Pins default to zero-flag function (ZERO1 through ZERO6).

General-Purpose Outputs Enabled.

Data written to GPO1 through GPO6 will appear at the corresponding pins.

OVER

Oversampling Rate Control

This bit is Read/Write.

Default Value: 0

OVER = 0

OVER = 1

64x oversampling for f_S≤ 96kHz, and 32x oversampling for f_S> 96kHz.

128x oversampling for f_S≤ 96kHz, and 64x oversampling for f_S> 96kHz.

The OVER bit is utilized to control the total oversampling performed by the D/A converter, including the digital

interpolation filter and delta-sigma DAC. This is useful for controlling the D/A out-of-band noise spectrum, and

designing a single, fixed value low-pass filter for use with all sampling frequencies.

®

24

PCM1604, PCM1605

ZERO FLAG AND INFINITE ZERO DETECT MUTE

FUNCTIONS

ANALOG OUTPUTS

The PCM1604 includes six independent output channels,

V_OUT1 through V_OUT6. These are unbalanced outputs, each

capable of driving 3.1Vp-p typical into a 5kΩ AC load with

V_CC= +5V. The internal output amplifiers for V_OUT1 through

V_OUT6 are DC biased to the common-mode (or bipolar zero)

voltage, equal to V_CC/2.

The PCM1604 includes circuitry for detecting an all ‘0’ data

condition for the data input pins, DATA1 through DATA3.

This includes two independent functions: Zero Output Flags

and Zero Detect Mute.

Although the flag and mute functions are independent of one

another, the zero detection mechanism is common to both

functions.

The output amplifiers include a RC continuous-time filter,

which helps to reduce the out-of-band noise energy present

at the DAC outputs due to the noise shaping characteristics

of the PCM1604’s delta-sigma D/A converters. The fre-

quency response of this filter is shown in Figure 11. By

itself, this filter is not enough to attenuate the out-of-band

noise to an acceptable level for most applications. An

external low-pass filter is required to provide sufficient out-

of-band noise rejection. Further discussion of DAC post-

filter circuits is provided in the Applications Information

section of this data sheet.

Zero Detect Condition

Zero Detection for each output channel is independent from

the others. If the data for a given channel remains at a ‘0’

level for 1024 sample periods (or LRCK clock periods), a

Zero Detect condition exists for the that channel.

Zero Output Flags

Given that a Zero Detect condition exists for one or more

channels, the Zero flag pins for those channels will be set to

a logic ‘1’state. There are Zero Flag pins for each channel,

ZERO1 through ZERO6 (pins 1 through 6). In addition, all

six Zero Flags are logically ANDed together and the result

provided at the ZEROA pin (pin 48), which is set to a logic

‘1’ state when all channels indicate a zero detect condition.

The Zero Flag pins can be used to operate external mute

circuits, or used as status indicators for a microcontroller,

audio signal processor, or other digitally controlled func-

tions.

20

0

–20

–40

–60

–80

–100

Infinite Zero Detect Mute

Infinite Zero Detect Mute is an internal logic function. The

Zero Detect Mute can be enabled or disabled using the INZD

bit of Control Register 8. The reset default is Zero Detect

Mute disabled, INZD = 0. Given that a Zero Detect Condi-

tion exists for one or more channels, the zero mute circuitry

will immediately force the corresponding DAC output(s) to

the bipolar zero level, or V_CC/2. This is accomplished by

switching the input of the DAC output amplifier from the

delta-sigma modulator output to the DC common-mode

reference voltage.

1

10

100

1k

10k

100k

1M

10M

Log Frequency (Hz)

FIGURE 11. Output Filter Frequency Response.

V_COM1 AND V_COM2 OUTPUTS

Two unbuffered common-mode voltage output pins, V_COM1

(pin 16) and V_COM2 (pin 15), are brought out for decoupling

purposes. These pins are nominally biased to a DC voltage

level equal to V_CC/2. If these pins are to be used to bias

external circuitry, a voltage follower is required for buffer-

ing purposes. Figure 12 shows an example of using the

V_COM1 and V_COM2 pins for external biasing applications.

APPLICATIONS INFORMATION

CONNECTION DIAGRAMS

A basic connection diagram is shown in Figure 13, with the

necessary power supply bypassing and decoupling compo-

nents. Burr-Brown recommends using the component values

shown in Figure 13 for all designs.

PCM1604

PCM1605

A typical application diagram is shown in Figure 14. Burr-

Brown’s REG1117-3.3 is used to generate +3.3V for V_DD

from the +5V analog power supply. Burr-Brown’s PLL1700E

is used to generate the system clock input at SCKI, as well

as generating the clock for the audio signal processor.

4

V_CC

2

1

V_BIAS

≈

OPA337

3

16

15

V_COM

1

V

_COM2

+

10µF

The use of series resistors (22Ω to 100Ω) are recommended

for SCKI, LRCK, BCK, DATA1, DATA2, and DATA3.

The series resistor combines with the stray PCB and device

input capacitance to form a low-pass filter which removes

high frequency noise from the digital signal, thus reducing

high frequency emission.

FIGURE 12. Biasing External Circuits Using the V_COM

1

and V_COM2 Pins.

®

25

PCM1604, PCM1605

+3.3V

Analog

+3.3V

Regulator

+5V Analog

To/From

Decoder

or

+

C₁₂

C₁₃

Microcontroller

36 35 34 33 32 31 30 29 28 27 26 25

37

38

39

40

41

42

43

44

45

46

47

48

24

23

22

21

20

19

18

17

16

15

14

13

V

_CC3

AGND3

V_CC

AGND4

V_CC

AGND5

_CC6

AGND6

RST

SCKI

SCKO

BCK

To/From

Decoder

4

5

LRCK

TEST

V_DD

PCM1604

PCM1605

+3.3V

V

+

Analog

C₁₁

C₁₀

DGND

C₁

+

V_COM

1

2

DATA1

DATA2

DATA3

ZEROA

V_COM

To/From

Decoder

C₂

C₃

+

V

_OUT1

_OUT2

Output

Low-Pass

Filters

1

2

3

4

5

6

7

8

9

10 11 12

C₄

C₆

C₇

+

Zero-

Output

Flags

or

General-

Purpose

Outputs

+5V Analog

+

C₉

C₈

NOTE: C₁- C₇, C₈, C₁₁, C₁₃= 10µF tantalum or aluminum electrolytic

C₉, C₁₀, C₁₂= 0.1µF ceramic

FIGURE 13. Basic Connection Diagram.

®

26

PCM1604, PCM1605

O U T

A G N D 2

A G N D 1

A G N D 0

3

4

5

6

V

C C

O U T

2

1

0

V

O U T

V

C C

O U T

V

C C

V

C C

V

A G N D

N C

Z E R O 6 / G P O 6

Z E R O 5 / G P O 5

Z E R O 4 / G P O 4

Z E R O 3 / G P O 3

Z E R O 2 / G P O 2

Z E R O 1 / G P O 1

M D O

M D I

M C

M L

FIGURE 14. Typical Application Diagram.

®

27

PCM1604, PCM1605

POWER SUPPLIES AND GROUNDING

Multiple Feedback (MFB) circuit arrangement, which re-

duces sensitivity to passive component variations over fre-

quency and temperature. For more information regarding

MFB active filter design, please refer to Burr-Brown Appli-

cations Bulletin AB-034, available from our web site

(www.burr-brown.com) or your local Burr-Brown sales

office.

The PCM1604 requires a +5V analog supply and a +3.3V

digital supply. The +5V supply is used to power the DAC

analog and output filter circuitry, while the +3.3V supply is

used to power the digital filter and serial interface circuitry.

For best performance, the +3.3V supply should be derived

from the +5V supply using a linear regulator, as shown in

Figure 14.

Since the overall system performance is defined by the

quality of the D/A converters and their associated analog

output circuitry, high quality audio op amps are recom-

mended for the active filters. Burr-Brown’s OPA2134 and

OPA2353 dual op amps are shown in Figures 15 and 16, and

are recommended for use with the PCM1604 and PCM1605.

Six capacitors are required for supply bypassing, as shown

in Figure 13. These capacitors should be located as close as

possible to the PCM1604 or PCM1605 package. The 10µF

capacitors should be tantalum or aluminum electrolytic,

while the 0.1µF capacitors are ceramic (X7R type is recom-

mended for surface-mount applications).

D/A OUTPUT FILTER CIRCUITS

Delta-sigma D/A converters utilize noise shaping techniques

to improve in-band Signal-to-Noise Ratio (SNR) perfor-

mance at the expense of generating increased out-of-band

noise above the Nyquist Frequency, or f_S/2. The out-of-band

noise must be low-pass filtered in order to provide the

optimal converter performance. This is accomplished by a

combination of on-chip and external low-pass filtering.

R₂

C₁

2

R₁

R₃

V_IN

R₄

1

V_OUT

OPA2134

3

C₂

R₂

R₁

A

_V≈ –

Figures 15 and 16 show the recommended external low-pass

active filter circuits for dual and single-supply applications.

These circuits are 2nd-order Butterworth filters using the

FIGURE 15. Dual Supply Filter Circuit.

R₂

R₁

A

_V≈ –

R₂

C₁

R₁

R₃

2

R₄

1

V_OUT

OPA2353

C₂

3

PCM1604

PCM1605

V

_OUTX

V_COM

1

2

To Additional

Low-Pass Filter

Circuits

OPA337

V_COM

C₂

10µF

+

where X = 1 to 6

FIGURE 16. Single-Supply Filter Circuit.

®

28

PCM1604, PCM1605

Separate power supplies are recommended for the digital

and analog sections of the board. This prevents the switching

noise present on the digital supply from contaminating the

analog power supply and degrading the dynamic perfor-

mance of the D/A converters. In cases where a common +5V

supply must be used for the analog and digital sections, an

inductance (RF choke, ferrite bead) should be placed be-

tween the analog and digital +5V supply connections to

avoid coupling of the digital switching noise into the analog

circuitry. Figure 18 shows the recommended approach for

single-supply applications.

PCB LAYOUT GUIDELINES

A typical PCB floor plan for the PCM1604 and PCM1605 is

shown in Figure 17. A ground plane is recommended, with

the analog and digital sections being isolated from one

another using a split or cut in the circuit board. The PCM1604

or PCM1605 should be oriented with the digital I/O pins

facing the ground plane split/cut to allow for short, direct

connections to the digital audio interface and control signals

originating from the digital section of the board.

Digital Power

Analog Power

+V_D

DGND

AGND +5VA

+V_S–V_S

REG

V_CC

V_DD

DGND

Digital Logic

and

Audio

Processor

Output

Circuits

PCM1604

PCM1605

Digital

Ground

AGND

Analog

Ground

DIGITAL SECTION

ANALOG SECTION

Return Path for Digital Signals

FIGURE 17. Recommended PCB Layout.

Power Supplies

RF Choke or Ferrite Bead

+5V

AGND +V_S–V_S

REG

V_CC

V_DD

DGND

Output

Circuits

PCM1604

PCM1605

AGND

Common

Ground

DIGITAL SECTION

ANALOG SECTION

FIGURE 18. Single-Supply PCB Layout.

®

29

PCM1604, PCM1605

Figure 21 illustrates the simulated jitter sensitivity of the

PCM1604. To achieve best performance, the system clock

jitter should be less than 300 picoseconds. This is easily

achieved using a quality clock generation IC, like Burr-

Brown’s PLL1700.

THEORY OF OPERATION

The D/A converter section of the PCM1604 is based upon a

multi-bit delta-sigma architecture. This architecture utilizes

an4^th-ordernoiseshaperandan8-levelquantizer,followedby

an analog low-pass filter. A block diagram of the delta-sigma

modulator is shown in Figure 19. This architecture has the

advantage of stability and improved jitter tolerance when

compared to traditional 1-bit (2-level) delta-sigma designs.

CLOCK JITTER

125

120

115

110

105

100

95

The combined oversampling rate of the digital interpolation

filter and the delta-sigma modulator is 32fs, 64fs, or 128fs.

The total oversampling rate is determined by the desired

sampling frequency. If fs ≤ 96kHz, then the OVER bit in

Register 12 may be set to an oversampling rate to 64fs or

128fs. If fs > 96kHz, then the OVER bit may be used to set the

oversampling rate to 32fs or 64fs. Figure 20 shows the out-

of- band quantization noise plots for both the 64x and 128x

oversampling scenarios. Notice that the 128x oversampling

plot shows significantly improved out-of-band noise perfor-

mance, allowing for a simplified low-pass filter to be used at

the output of the DAC.

90

85

80

0

100

200

300

400

500

600

Jitter (ps)

FIGURE 21. Jitter Sensitivity.

–

+

Z^–1

4f_Sor 8f_S

+

8-Level Quantizer

32f_S, 64f_S, or 128f_S

FIGURE 19. Eight-Level Delta-Sigma Modulator.

QUANTIZATION NOISE SPECTRUM

(64x Oversampling)

0

QUANTIZATION NOISE SPECTRUM

(128x Oversampling)

0

–20

–40

–60

–80

–100

–120

–140

–160

–180

–100

–120

–140

–160

–180

0

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

Frequency (f_S)

FIGURE 20. Quantization Noise Spectrum.

®

30

PCM1604, PCM1605

For the PCM1604 and PCM1605 D/A converters, THD+N is

measured with a full scale, 1kHz digital sine wave as the test

stimulus at the input of the DAC. The digital generator is set

to 24-bit audio word length and a sampling frequency of

44.1kHz, or 96kHz. The digital generator output is taken

from the unbalanced S/PDIF connector of the measurement

system. The S/PDIF data is transmitted via coaxial cable to

the digital audio receiver on the DEM-DAI1604 demo board.

The receiver is then configured to output 24-bit data in either

I²S or left-justified data format. The DAC audio interface

format is programmed to match the receiver output format.

The analog output is then taken from the DAC post filter and

connected to the analog analyzer input of the measurment

system. The analog input is band limited using filters resi-

dent in the analyzer. The resulting THD+N is measured by

the analyzer and displayed by the measurement system.

PERFORMANCE MEASUREMENTS

This section provides information on how to measure key

dynamic performance parameters for the PCM1604 and

PCM1605. In all cases, an Audio Precision System Two

Cascade or equivalent audio measurement system is utilized

to perform the testing.

TOTAL HARMONIC DISTORTION + NOISE

Total Harmonic Distortion + Noise (THD+N) is a significant

figure of merit for audio D/A converters, since it takes into

account both harmonic distortion and all noise sources

within a specified measurement bandwidth. The true rms

value of the distortion and noise is referred to as THD+N.

Evaluation Board

DEM-DAI1604

2nd-Order

Low-Pass

Filter

S/PDIF

Receiver

PCM1604

PCM1605

f_–3dB= 54kHz

Analyzer

and

Display

Digital

Generator

S/PDIF

Band Limit

Notch Filter

f_C= 1kHz

Output

100% Full Scale

RMS Mode

HPF = 22Hz⁽¹⁾

LPF = 30kHz⁽¹⁾

Option = 20kHz Apogee Filter⁽²⁾

24-Bit, 1kHz

Sine Wave

NOTES: (1) There is little difference

in measured THD+N when using the

various settings for these filters.

(2) Required for THD+N test.

FIGURE 22. Test Setup for THD+N Measurements.

®

31

PCM1604, PCM1605

DYNAMIC RANGE

IDLE CHANNEL SIGNAL-TO-NOISE RATIO

Dynamic range is specified as A-Weighted, THD+N mea-

sured with a –60dBFS, 1kHz digital sine wave stimulus at

the input of the D/A converter. This measurment is designed

to give a good indicator of how the DAC will perform given

a low-level input signal.

The SNR test provides a measure of the noise floor of the

D/A converter. The input to the D/A is all 0’s data, and the

D/A converter’s Infinite Zero Detect Mute function must

be disabled (default condition at power up for the PCM1604,

PCM1605). This ensures that the delta-sigma modulator

output is connected to the output amplifier circuit so that

idle tones (if present) can be observed and effect the SNR

measurement. The dither function of the digital generator

must also be disabled to ensure an all ‘0’s data stream at the

input of the D/A converter.

The measurement setup for the dynamic range measurement

is shown in Figure 23, and is similar to the THD+N test

setup discussed previously. The differences include the

band limit filter selection, the additional A-Weighting filter,

and the –60dBFS input level.

The measurement setup for SNR is identical to that used for

dynamic range, with the exception of the input signal level

(see the notes provided in Figure 23).

Evaluation Board

DEM-DAI1604

2nd-Order

Low-Pass

Filter

PCM1604⁽¹⁾

PCM1605

S/PDIF

Receiver

f_–3dB= 54kHz

Analyzer

and

Display

Digital

Generator

A-Weight

Filter⁽¹⁾

S/PDIF

Output

Band Limit

Notch Filter

_C= 1kHz

0% Full Scale,

Dither Off (SNR)

–60dBFS,

RMS Mode

HPF = 22Hz

LPF = 22kHz

Option = A-Weighting⁽²⁾

f

NOTES: (1) Infinite Zero Detect Mute disabled.

(2) Results without A-Weighting will be

approximately 3dB worse.

1kHz Sine Wave

(Dynamic Range)

FIGURE 23. Test Set-Up for Dynamic Range and SNR Meeasurements.

®

32

PCM1604, PCM1605


型号：	PCM1605Y
厂家：	BURR-BROWN CORPORATION
描述：	24-Bit, 192kHz Sampling,6-Channel, Enhanced Multi-Level, Delta-Sigma DIGITAL-TO-ANALOG CONVERTER 24位192kHz采样， 6通道，增强多层次， Σ-Δ数位类比转换器转换器
文件：	总32页 (文件大小：263K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PCM1605Y [BB]

相关型号：

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PCM1605Y/1K

PCM1606

PCM1606E

PCM1606E

PCM1606E/2K

PCM1606E/2K

PCM1606E/2KG4

PCM1606EG4

PCM1608

PCM1608KY

PCM1608KY/2K