PCM1606EG4 [TI]
24-Bit, 192-kHz SAMPLING. 6-CHANNEL, ENHANCED MULTILEVEL, DELTA- SIGMA DIGITAL-TO-ANALOG CONVERTER; 24位192 kHz采样。 6通道，增强多层次， Δ-Σ数位类比转换器
| 型号： | PCM1606EG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 24-Bit, 192-kHz SAMPLING. 6-CHANNEL, ENHANCED MULTILEVEL, DELTA- SIGMA DIGITAL-TO-ANALOG CONVERTER |
| 文件： | 总28页 (文件大小：405K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢄ
SLES014B − OCTOBER 2001 − REVISED AUGUST 2002
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FEATURES
DESCRIPTION
D
24-Bit Resolution
The PCM1606 is a CMOS monolithic integrated circuit
that features six 24-bit audio digital-to-analog
converters and support circuitry in a small 20-lead
SSOP package. The digital-to-analog converters utilize
Texas Instruments’ enhanced multilevel, delta-sigma
D
Analog Performance:
− Dynamic Range: 103 dB, Typical
− SNR: 103 dB, Typical
− THD+N: 0.004%, Typical
− Full-Scale Output: 3.1 Vp-p, Typical
nd
architecture, which employs 2 -order noise shaping
and 8-level amplitude quantization to achieve excellent
signal-to-noise performance and a high tolerance to
clock jitter.
D
D
8× Oversampling Interpolation Filter:
− Stopband Attenuation: –55 dB
− Passband Ripple: 0.03 dB
Sampling Frequency:
− 5 kHz to 200 kHz (Channels 1 and 2)
− 5 kHz to 100 kHz (Channels 3, 4, 5, and 6)
The PCM1606 accepts industry-standard audio data
formats with 16- to 24-bit audio data. Sampling rates up
to 200 kHz are supported.
D
D
Accepts 16- and 24-Bit Audio Data
2
Data Formats: Standard, I S, and
Left-Justified, TDM
PCM1606
D
D
System Clock: 128 f , 192 f , 256 f , 384 f ,
(TOP VIEW)
S
S
S
S
512 f , or 768 f
S
S
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DATA1
DATA2
DATA3
FMT1
FMT0
ZEROA
AGND
SCKI
BCK
LRCK
DEMP1
DEMP0
Digital De-Emphasis for 32 kHz, 44.1 kHz,
48 kHz
D
Power Supply: 5-V Single Supply
20-Lead SSOP Package
D
V
V
V
V
V
CC
APPLICATIONS
COM
V
V
V
5
6
1
4
3
2
OUT
OUT
OUT
OUT
OUT
OUT
D
D
D
D
D
D
D
Integrated A/V Receivers
DVD Movie and Audio Players
HDTV Receivers
Car Audio Systems
DVD Add-On Cards for High-End PCs
Digital Audio Workstations
Other Multichannel Audio Systems
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2002, Texas Instruments Incorporated
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ꢣ ꢧ ꢤ ꢣꢜ ꢝꢱ ꢟꢞ ꢢ ꢪꢪ ꢨꢢ ꢠ ꢢ ꢡ ꢧ ꢣ ꢧ ꢠ ꢤ ꢬ
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1
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SLES014B − OCTOBER 2001 − REVISED AUGUST 2002
PACKAGE/ORDERING INFORMATION
PACKAGE
DRAWING
NUMBER
OPERATION
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
PRODUCT
PACKAGE
TRANSPORT MEDIA
†
NUMBER
PCM1606E
TUBE
PCM1606E
20-Lead SSOP
ZZ334-1
–25°C to 85°C
PCM1606E
PCM1606E/2K
Tape and Reel
†
Models with a slash (/) are available only in tape and reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000
pieces of PCM1606Y/2K gets a single 2000-piece tape and reel.
functional block diagram
V
V
V
1
2
3
Output Amp and
Low-Pass Filter
OUT
OUT
OUT
DAC
DAC
DAC
DAC
DAC
DAC
BCK
LRCK
Serial
Input
I/F
Output Amp and
Low-Pass Filter
DATA1(1, 2)
DATA2(3, 4)
DATA3(5, 6)
Output Amp and
Low-Pass Filter
4x / 8x
Oversampling
Digital Filter
with
Function
Controller
Enhanced
Multilevel
Delta-Sigma
Modulator
V
V
Output Amp and
Low-Pass Filter
COM
4
OUT
OUT
OUT
DEMP1
Function
Control
I/F
Output Amp and
Low-Pass Filter
DEMP0
V
V
5
6
FMT1
FMT0
Output Amp and
Low-Pass Filter
System Clock
System Clock
Manager
Zero Detect
Power Supply
SCKI
ZEROA
V
CC
AGND
2
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ꢀ ꢁꢂ ꢃ ꢄꢅ ꢄ
SLES014B − OCTOBER 2001 − REVISED AUGUST 2002
Terminal Functions
TERMINAL
NAME PIN
AGND
I/O
DESCRIPTIONS
7
19
1
—
I
Analog and digital ground
Shift clock input for serial audio data (see Note 2)
BCK
DATA1
DATA2
DATA3
DEMP0
DEMP1
FMT1
FMT0
LRCK
SCKI
I
Serial audio data input for V
Serial audio data input for V
Serial audio data input for V
1 and V
3 and V
5 and V
2 (see Note 2)
4 (see Note 2)
6 (see Note 2)
OUT
OUT
OUT
OUT
OUT
OUT
2
I
3
I
16
17
4
I
De-emphasis control (see Note 1)
De-emphasis control (see Note 1)
Format select (see Note 1)
I
I
5
I
Format select (see Note 1)
18
20
15
14
10
11
12
13
8
I
Left and right clock input. This clock is equal to the sampling rate, f (see Note 2)
S
I
System clock in. Input frequency is 128 f , 192 f , 256 f , 384 f , 512 f or 768 f (see Note 2)
S S S S S S
V
V
V
V
V
V
V
V
—
—
O
O
O
O
O
O
O
Analog and digital power supply, 5 V
CC
Common voltage output. This pin should be bypassed with a 10-µF capacitor to AGND
Voltage output for audio signal corresponding to L-channel on DATA1. Up to 192 kHz
Voltage output for audio signal corresponding to R-channel on DATA1. Up to 192 kHz
Voltage output for audio signal corresponding to L-channel on DATA2. Up to 96 kHz
Voltage output for audio signal corresponding to R-channel on DATA2. Up to 96 kHz
Voltage output for audio signal corresponding to L-channel on DATA3. Up to 96 kHz
Voltage output for audio signal corresponding to R-channel on DATA3. Up to 96 kHz
Zero-data flag. Logical AND of ZERO1 through ZERO6
COM
1
OUT
OUT
OUT
OUT
OUT
OUT
2
3
4
5
6
9
ZEROA
6
NOTES: 1. Schmitt-trigger input with internal pulldown.
2. Schmitt-trigger input.
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V
CC
Digital input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
Analog input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
+ 0.3 V
+ 0.3 V
CC
CC
Input current (except power supply) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA
Ambient temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
Junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Lead temperature (soldering, 5s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C, 5s
Package temperature (IR reflow, 10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235°C, 10s
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
3
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ꢀ ꢁꢂ ꢃꢄ ꢅ ꢄ
SLES014B − OCTOBER 2001 − REVISED AUGUST 2002
electrical characteristics, all specifications at T = 25°C, V
= 5 V, f = 44.1 kHz,
S
A
CC
system clock = 384 f and 24-bit data (unless otherwise noted)
S
PCM1606E
TYP
24
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
RESOLUTION
DATA FORMAT
Bits
2
Audio data interface format
Audio data bit length
Audio data format
Standard, I S, Left-Justified, TDM
16 or 24 bits, selectable
MSB first, 2s complement
V
V
1, V
3, V
2
5
5
200
100
OUT
OUT
f
S
Sampling frequency
kHz
4, V
OUT
5, V 6
OUT OUT
OUT
System clock frequency
128, 192, 256, 384, 512, 768 f
S
DIGITAL INPUT/OUTPUT
Logic family (TTL compatible)
V
V
High-level input voltage
Low-level input voltage
High-level input current
Low-level input current
High-level output voltage
Low-level output voltage
2
V
V
IH
0.8
100
−10
IL
I
I
V
V
= V
67
µA
µA
V
IH
IN
CC
= 0 V
IL
IN
OH
OL
V
V
I
I
= −4 mA
= 4 mA
2.4
OH
1
V
OL
DYNAMIC PERFORMANCE
f
S
f
S
f
S
f
S
f
S
f
S
= 44.1 kHz/384 f
0.004% 0.01%
S
= 96 kHz/256 f
S
0.005%
0.002%
1%
V
V
= 0 dB
OUT
= 192 kHz/128 f
S
Total harmonic
distortion plus noise
THD+N
= 44.1 kHz/348 f
= 96 kHz / 256 f
S
1.2%
1%
= −60 dB
S
OUT
= 192 kHz/128 f
S
EIAJ, A-weighted, f = 44.1 kHz/384 f
S
98
98
95
103
99
S
A-weighted, f = 96 kHz/256 f
Dynamic range
dB
dB
S
S
A-weighted, f = 192 kHz/128 f
101
103
100
101
100
95
S
S
EIAJ, A-weighted, f = 44.1 kHz/384 f
S
S
A-weighted, f = 96 kHz/256 f
Signal-to-noise ratio
Channel separation
S
S
A-weighted, f = 192 kHz/128 f
S
S
f
S
f
S
f
S
= 44.1 kHz/384 f
S
= 96 kHz/256 f
S
dB
dB
= 192 kHz/128 f
100
0.5
S
Level linearity error
DC ACCURACY
V
OUT
= −90 dB
Gain error
1 %FSR
1.3 %FSR
30
Gain mismatch, channel-to-channel
Bipolar zero error
V
OUT
= 0.5 V
CC
at BPZ
mV
ANALOG OUTPUT
Output voltage
Center voltage
Load impedance
Full scale (−0 dB)
Ac load
62% of V
50% of V
Vp-p
Vdc
kΩ
CC
CC
5
4
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ꢀ ꢁꢂ ꢃ ꢄꢅ ꢄ
SLES014B − OCTOBER 2001 − REVISED AUGUST 2002
electrical characteristics, all specifications at T = 25°C, V
= 5 V, f = 44.1 kHz,
S
A
CC
system clock = 384 f and 24-bit data (unless otherwise noted) (continued)
S
PCM1606E
TYP
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
DIGITAL FILTER PERFORMANCE
FILTER CHARACTERISTICS
0.03 dB
−3 dB
0.454 f
S
Passband
0.487 f
S
Stopband
0.546 f
S
Passband ripple
0.03
dB
dB
Stopband = 0.546 f
Stopband = 0.567 f
−50
−55
S
Stopband attenuation
S
ANALOG FILTER PERFORMANCE
Frequency response
At 20 kHz
−0.03
dB
VDC
mA
POWER SUPPLY REQUIREMENTS (see Note 4)
V
Voltage range
Supply current
4.5
5
50
5.5
65
CC
f
S
f
S
f
S
f
S
f
S
f
S
= 44.1 kHz/384 f
S
= 96 kHz/256 f
72
I
S
CC
= 192 kHz/128 f
68
S
= 44.1 kHz/384 f
250
360
340
358
85
S
= 96 kHz/256 f
S
Power dissipation
mW
= 192 kHz/128 f
S
TEMPERATURE RANGE
Operation temperature
Thermal resistance
−25
°C
θ
JA
20-pin SSOP
115
°C/W
NOTES: 3. Analog performance specs are tested using System Two Cascade Plus by Audio Precision with 400-Hz HPF, 30-kHz LPF on at RMS
with 20-kHz LPF, 400-Hz HPF in calculation.
Shibasoku #725 THD meter, 400 Hz HPF, 30 kHz LPF on, at average mode with 20-kHz bandwidth limiting. The load connected
to the analog output is 5 kΩ or larger via capacitance coupling.
4. Condition in 192-kHz operation is channel 3 through channel 6 are disabled.
timing requirements
system clock input
The PCM1606 requires a system clock for operating the digital interpolation filters and multilevel delta-sigma
modulators. The system clock is applied at the SCKI (pin 20). Table 1 shows examples of system clock
frequencies for common audio sampling rates.
Figure 1 shows the timing requirements for the system clock input. For optimal performance, it is important to
use a clock source with low phase jitter and noise. Texas Instruments’ PLL1700 multiclock generator is an
excellent choice for providing the PCM1606 system clock source.
The 192-kHz sampling frequency operation is available on DATA1 for V
1 and V
2. When the system clock
OUT
OUT
of 128 f or 192 f is detected, V
level (= 0.5 V ). Table 1 lists the typical system clock frequency.
3, V
4, V
5 and V
6 are automatically forced to the bipolar zero
S
S
OUT
OUT
OUT
OUT
CC
5
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ꢀ ꢁꢂ ꢃꢄ ꢅ ꢄ
SLES014B − OCTOBER 2001 − REVISED AUGUST 2002
timing requirements (continued)
power-on reset functions
The PCM1606 includes a power-on reset function. Figure 2 shows the operation of this function. With the
system clock active and V
initialization sequence requires 1024 system clocks from the time V
PCM1606 is set to its reset default state.
> 3 V typical (2.2 V to 3.7 V), the power-on reset function is enabled. The
CC
> 3 V. After the initialization period, the
CC
Table 1. System Clock Rates for Common Audio Sampling Frequencies
SYSTEM CLOCK FREQUENCY (f
) (MHz)
SCLK
SAMPLING FREQUENCY
128 f
—
192 f
—
256 f
384 f
512 f
768 f
S
S
S
S
S
S
8 kHz
16 kHz
32 kHz
44.1 kHz
48 kHz
96 kHz
192 kHz
2.048
4.096
3.072
6.144
4.096
8.192
6.144
12.288
—
—
—
—
8.192
12.288
16.384
24.576
—
—
11.2896
12.288
24.576
See Note 6
16.9344
18.432
22.5792
24.576
33.8688
36.864
—
—
—
—
36.864
49.152
See Note 5
See Note 6
24.576
36.864
See Note 6
See Note 6
NOTES: 5. The 768-f system clock rate is not supported for f > 64 kHz.
S
S
6. This system clock is not supported for the given sampling frequency.
t
(SCKH)
2.0 V
0.8 V
System Clock
t
System Clock
(SCKL)
†
Pulse Cycle Time
†
1/128 f , 1/256 f , 1/384 f , 1/512 f and 1/768 f .
S
S
S
S
S
PARAMETERS
MIN
10
MAX
UNIT
ns
t
System clock pulse duration HIGH
System clock pulse duration LOW
(SCKH)
t
10
ns
(SCKL)
Figure 1. System Clock Timing
3.7 V
3.0 V
2.2 V
V
DD
0 V
Reset
Reset Removal
Internal Reset
System Clock
Don’t Care
1024 System Clocks
Figure 2. Power-On Reset Timing
6
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ꢀ ꢁꢂ ꢃ ꢄꢅ ꢄ
SLES014B − OCTOBER 2001 − REVISED AUGUST 2002
timing requirements (continued)
audio serial interface
The audio serial interface for the PCM1606 comprises a 5-wire synchronous serial port. It includes LRCK (pin
18), BCK (pin 19), DATA1 (pin 1), DATA2 (pin 2) and DATA3 (pin 3). BCK is the serial audio bit clock and is used
to clock the serial data present on DATA1, DATA2, and DATA3 into the audio interface serial shift registers. Serial
data is clocked into the PCM1606 on the rising edge of BCK. LRCK is the serial audio left/right word clock. LRCK
is used to latch serial data into the serial audio interface internal registers.
Both LRCK and BCK must be synchronous to the system clock. Ideally, it is recommended that LRCK and BCK
be derived from the system clock input or output, SCKI. The left/right clock, LRCK, is operated at the sampling
frequency (f ). The bit clock, BCK, may be operated at 32, 48, or 64 times the sampling frequency.
S
audio data formats and timing
2
The PCM1606 supports industry-standard audio data formats, including standard, I S, left-justified, and TDM.
The data formats are shown in Figure 6. Data formats are selected using the format pins, FMT1 (pin 4) and
FMT0 (pin 5). All formats require binary 2s complement, MSB-first audio data. Figure 3 shows a detailed timing
diagram for the serial audio interface, with the exception of TDM format.
DATA1, DATA2, and DATA3 each carry two audio channels, designated as the left and right channels. The left
channel data always precedes the right channel data in the serial data stream for all data formats. Table 2 shows
the mapping of the digital input data to the analog output pins.
TDM format is able to interface by 3-wire synchronous serial port. All data inputs from DATA1, BCK can be
operated at 128, 256, and 512 times the sampling frequency. The rising edge of LRCK means the start of a data
frame. Only channel 1 and channel 2 data are acceptable at the 192-kHz sampling frequency (f ); channel 3,
S
channel 4, channel 5, and channel 6 data are don’t care.
Figure 4 shows the timing requirements for BCK input for TDM format. Figure 5 shows the detailed timing
diagram for TDM format.
Table 2. Audio Input Data to Analog Output Mapping
DATA INPUT
DATA1
CHANNEL
Left
ANALOG OUTPUT
†
1
†
2
‡
3
‡
4
‡
5
‡
6
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
DATA1
Right
Left
DATA2
DATA2
Right
Left
DATA3
DATA3
Right
†
‡
Up to 192 kHz
Up to 96 kHz
7
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ꢀ ꢁꢂ ꢃꢄ ꢅ ꢄ
SLES014B − OCTOBER 2001 − REVISED AUGUST 2002
timing requirements (continued)
1.4 V
1.4 V
1.4 V
LRCK
t
t
t
(LB)
(BCH)
(BCL)
BCK
t
t
(BL)
(BCY)
DATA1, DATA2, DATA3
t
t
h(D)
su(D)
PARAMETER
MIN
MAX
32 f / 48 f / 64
UNIT
S
S
t
BCK pulse cycle time
†
(BCY)
f
S
t
t
t
t
t
t
BCK high-level time
BCK low-level time
35
35
10
10
10
10
ns
ns
ns
ns
ns
ns
(BCH)
(BCL)
(BL)
BCK rising edge to LRCK edge
LRCK falling edge to BCK rising edge
DATA setup time
(LB)
su(D)
h(D)
DATA hold time
†
f
S
is the sampling frequency (e.g., 44.1 kHz, 48 kHz, 96 kHz, etc.)
Figure 3. Audio Interface Timing
Table 3. Bit Clock Rates for TDM Format Sampling Frequencies
SYSTEM CLOCK FREQUENCY (f
) (MHz)
512 f
SCKI
SAMPLING
FREQUENCY
128 f
—
256 f
S
S
S
8 kHz
16 kHz
32 kHz
44.1 kHz
48 kHz
96 kHz
192 kHz
2.048
4.096
4.096
—
8.192
16.384
—
8.192
—
11.2896
12.288
24.576
See Note 7
22.5792
24.576
—
—
49.152
24.576
See Note 7
NOTE 7: This bit clock is not supported for the given sampling frequency.
8
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SLES014B − OCTOBER 2001 − REVISED AUGUST 2002
timing requirements (continued)
t
(BCKH)
2.0 V
0.8 V
BCK
t
Bit Clock Pulse
Cycle Time
(BCKL)
†
PARAMETERS
MIN
10
MAX
UNIT
ns
t
t
Bit clock pulse duration HIGH
Bit clock pulse duration LOW
(BCKH)
10
ns
(BCKL)
†
1/128 f , 1/256 f , and 1/512 f .
S
S
S
Figure 4. Bit Clock Timing for TDM Format
1.4 V
LRCK
BCK
t
t
t
(LB)
(BCH)
(BCL)
1.4 V
1.4 V
t
t
(BCY)
(BL)
DATA1
t
t
h(D)
su(D)
PARAMETER
MIN MAX
UNIT
t
t
t
t
t
t
t
BCK pulse cycle time
BCK high-level time
BCK low-level time
20
10
10
7
ns
ns
ns
ns
ns
ns
ns
(BCY)
(BCH)
(BCL)
(BL)
BCK rising edge to LRCK edge
LRCK falling edge to BCK rising edge
DATA setup time
7
(LB)
7
su(D)
h(D)
DATA hold time
7
Figure 5. Audio Interface Timing for TDM Format
9
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SLES014B − OCTOBER 2001 − REVISED AUGUST 2002
timing requirements (continued)
(1) Standard Data Format; L-Channel = HIGH, R-Channel = LOW
1/f
S
LRCK
BCK
R−Channel
L−Channel
(= 32 f , 48 f or 64 f )
S
S
S
16-Bit Right-Justified, BCK = 48 f or 64 f
S
S
DATA 14 15 16
1
2
3
14 15 16
1
2
3
14 15 16
16-Bit Right-Justified, BCK = 32 f
S
MSB
LSB
MSB
LSB
DATA 14 15 16
1
2
3
14 15 16
1
2
3
14 15 16
MSB
LSB
MSB
LSB
(2) Left-Justified Data Format; L-Channel = HIGH, R-Channel = LOW
1/f
S
LRCK
BCK
L−Channel
R−Channel
DATA
1
2
3
N−2 N−1
N
1
2
3
N−2 N−1
N
1
2
MSB
LSB
MSB
LSB
2
(3) I S Data Format; L-Channel = LOW, R-Channel = HIGH
1/f
S
LRCK
BCK
R−Channel
L−Channel
(= 48 f or 64 f
S
)
S
DATA
1
2
3
N−2 N−1
N
1
2
3
N−2 N−1
N
1
2
MSB
LSB
MSB
LSB
Figure 6. Audio Data Input Format
10
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SLES014B − OCTOBER 2001 − REVISED AUGUST 2002
timing requirements (continued)
(4) TDM Data Format
BCK = 256 f
S
1/f
S
Channel 1
32 BCK
Channel 2
32 BCK
Channel 3
Channel 6
LRCK
BCK
1
2
3
22 23 24 LOW Fix
1
24
LOW Fix 64 Bit
1
2
LOW Fix
MSB
LSB
BCK = 128 f
S
1/f
S
Channel 1
32 BCK
Channel 2
32 BCK
LRCK
BCK
1
2
3
22 23 24 LOW Fix
1
24 LOW Fix
LSB
LOW Fix 64 Bit
1
2
MSB
LSB
MSB
BCK = 512 f
S
1/f
S
Channel 1
64 BCK
Channel 2
64 BCK
Channel 3
Channel 6
LRCK
BCK
LOW Fix
1
2
24
LOW Fix
1
LOW Fix
1
MSB
LSB
Figure 6. Audio Data Input Format (Continued)
functional description
The PCM1606 has several built-in functions including digital input data format selection and digital
de-emphasis. These functions are hardware controlled with static control signals and used on pin FMT1 (pin 4),
pin FMT0 (pin 5), pin DEMP1 (pin 17), and DEMP0 (pin 16).
data format selection
The PCM audio data format can be selected by pin FMT1 (pin 4) and FMT0 (pin 5) as shown in Table 4.
Table 4. Data Format Control
FMT1 (pin 4)
LOW
FMT0 (pin 5)
LOW
AUDIO INTERFACE
2
I S
LOW
HIGH
TDM
HIGH
LOW
Standard
Left-justified
HIGH
HIGH
11
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SLES014B − OCTOBER 2001 − REVISED AUGUST 2002
functional description (continued)
de-emphasis control
The de-emphasis control can be selected by DEMP1 (pin 17) and DEMP0 (pin 16). See Table 5.
Table 5. De-Emphasis Control
DEMT1 (pin 17)
LOW
DEMT0 (pin 16)
LOW
AUDIO INTERFACE
OFF
LOW
HIGH
48 kHz
HIGH
LOW
44.1 kHz
32 kHz
HIGH
HIGH
analog outputs
The PCM1606 includes six independent output channels, V
1 through V
6. These are unbalanced
OUT
OUT
outputs, each capable of driving 3.1 Vp-p typical into a 5-kΩ ac load with V = 5 V. The internal output amplifiers
CC
for V
1 through V
6 are dc-biased to the common-mode (or bipolar zero) voltage, equal to V /2.
OUT
OUT CC
The output amplifiers include an RC continuous-time filter, which helps to reduce the out-of-band noise energy
present at the DAC outputs due to the noise shaping characteristics of the PCM1606’s delta-sigma D/A
converters. The frequency response of this filter is shown in Figure 7. By itself, this filter is not enough to
attenuate the out-of-band noise to an acceptable level for most applications. An external low-pass filter is
required to provide sufficient out-of-band noise rejection. Further discussion of DAC post-filter circuits is
provided in the Application Information section of this data sheet.
LEVEL
vs
FREQUENCY
20
0
−20
−40
−60
−80
−100
1
10
100
1k
10k
100k
1M
10M
f − Frequency − Hz
Figure 7. Output Filter Frequency Response
12
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ꢀ ꢁꢂ ꢃ ꢄꢅ ꢄ
SLES014B − OCTOBER 2001 − REVISED AUGUST 2002
functional description (continued)
V
output
COM
One unbuffered common-mode voltage output pin, V
pin is nominally biased to a dc voltage level equal to V /2. If this pin is to be used to bias external circuitry, a
voltage follower is required for buffering purposes. Figure 8 shows an example of using the V
biasing applications.
(pin 14) is brought out for decoupling purposes. This
COM
CC
pin for external
COM
PCM1606
4
−
VCC
2
1
OPA337
+
VBIAS
[
14
3
V
COM
+
10 µF
Figure 8. Biasing External Circuits Using the V
Pin
COM
zero flag
zero detect condition
Zero detection for each output channel is independent from the others. If the data for a given channel remains
at a 0 level for 1024 sample periods (or LRCK clock periods), a zero detect condition exists for that channel.
zero output flag
When the data for all channels remains at a 0 level for 1024 sample periods (or LRCK clock periods), the ZEROA
(pin 6) is set to a logic 1 state. The zero flag pin can be used to operate external mute circuits, or used as a status
indicator for a microcontroller, audio signal processor, or other digitally controlled functions.
13
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SLES014B − OCTOBER 2001 − REVISED AUGUST 2002
TYPICAL CHARACTERISTICS—DIGITAL FILTER
AMPLITUDE
vs
AMPLITUDE
vs
FREQUENCY
FREQUENCY
0
−20
0.05
0.04
V
= 5 V
= 44.1 kHz
= 25°C
CC
V
f
= 5 V
= 44.1 kHz
= 25°C
CC
S
f
T
S
A
T
0.03
A
De-emphasis Off
De-emphasis Off
−40
0.02
0.01
−60
0.00
−80
−0.01
−0.02
−0.03
−0.04
−0.05
−100
−120
−140
0
1
2
3
4
0.0
0.1
0.2
0.3
0.4
0.5
f − Frequency [ꢀ f ]
f − Frequency [ꢀ f ]
S
S
Figure 9
Figure 10
DE-EMPHASIS LEVEL
vs
DE-EMPHASIS ERROR
vs
FREQUENCY
FREQUENCY
0
0.5
V
= 5 V
= 32 kHz
= 25°C
V
= 5 V
CC
CC
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
0.4
0.3
f
T
f
T
= 32 kHz
S
S
= 25°C
A
A
0.2
0.1
−0.0
−0.1
−0.2
−0.3
−0.4
−0.5
0
2
4
6
8
10
12
14
0
2
4
6
8
10
12
14
f − Frequency − kHz
f − Frequency − kHz
Figure 11
Figure 12
All specifications at T = 25°C, V
CC
= 5 V, f = 44.1 kHz, system clock = 384 f and 24-bit data, unless otherwise noted.
S S
A
14
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SLES014B − OCTOBER 2001 − REVISED AUGUST 2002
TYPICAL CHARACTERISTICS—DIGITAL FILTER
DE-EMPHASIS LEVEL
vs
DE-EMPHASIS ERROR
vs
FREQUENCY
FREQUENCY
0
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
0.5
0.4
V
f
T
A
= 5 V
= 44.1 kHz
= 25°C
CC
S
V
= 5 V
= 44.1 kHz
= 25°C
CC
f
T
S
A
0.3
0.2
0.1
−0.0
−0.1
−0.2
−0.3
−0.4
−0.5
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
f − Frequency − kHz
f − Frequency − kHz
Figure 13
Figure 14
DE-EMPHASIS LEVEL
vs
DE-EMPHASIS ERROR
vs
FREQUENCY
FREQUENCY
0
0.5
0.4
V
= 5 V
= 48 kHz
= 25°C
V
= 5 V
CC
CC
−1
−2
−3
−4
−5
−6
−7
−8
−9
f
T
f
T
= 48 kHz
S
S
= 25°C
A
A
0.3
0.2
0.1
−0.0
−0.1
−0.2
−0.3
−0.4
−0.5
−10
0
2
4
6
8
10 12 14 16 18 20 22
0
2
4
6
8
10 12 14 16 18 20 22
f − Frequency − kHz
f − Frequency − kHz
Figure 15
Figure 16
All specifications at T = 25°C, V
CC
= 5 V, f = 44.1 kHz, system clock = 384 f and 24-bit data, unless otherwise noted.
S S
A
15
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ꢀ ꢁꢂ ꢃꢄ ꢅ ꢄ
SLES014B − OCTOBER 2001 − REVISED AUGUST 2002
TYPICAL CHARACTERISTICS—ANALOG DYNAMIC PERFORMANCE
DYNAMIC RANGE
vs
SUPPLY VOLTAGE
TOTAL HARMONIC DISTORTION + NOISE
vs
SUPPLY VOLTAGE
106
104
102
100
98
10
V
= 5 V
= 44.1 kHz
= 25°C
CC
V
= 5 V
= 44.1 kHz
= 25°C
CC
192 kHz
128 f
S
f
T
S
f
T
S
96 kHz
256 f
A
44.1 kHz
A
S
384 f
S
1
44.1 kHz
384 f
−60 dB
S
192 kHz
128 f
0.1
S
96 kHz
256 f
192 kHz
128 f
S
44.1 kHz
384 f
S
96 kHz
256 f
S
0.01
S
0 dB
96
4.0
0.001
4.5
5.0
5.5
6.0
4.0
4.5
5.0
5.5
6.0
V
CC
− Supply Voltage − V
V
CC
− Supply Voltage − V
Figure 17
Figure 18
SNR
vs
CHANNEL SEPARATION
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
106
104
102
100
98
104
102
100
98
V
= 5 V
= 44.1 kHz
= 25°C
V
f
T
A
= 5 V
= 44.1 kHz
= 25°C
CC
CC
S
f
T
S
192 kHz
128 f
S
A
44.1 kHz
384 f
S
44.1 kHz
384 f
S
192 kHz
128 f
S
96 kHz
256 f
S
96
96 kHz
256 f
S
94
96
4.0
92
4.0
4.5
V
5.0
5.5
6.0
4.5
V
5.0
5.5
6.0
− Supply Voltage − V
− Supply Voltage − V
CC
CC
Figure 19
Figure 20
All specifications at T = 25°C, V
CC
= 5 V, f = 44.1 kHz, system clock = 384 f and 24-bit data, unless otherwise noted.
S S
A
16
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ꢀ ꢁꢂ ꢃ ꢄꢅ ꢄ
SLES014B − OCTOBER 2001 − REVISED AUGUST 2002
TYPICAL CHARACTERISTICS—ANALOG DYNAMIC PERFORMANCE
DYNAMIC RANGE
vs
TOTAL HARMONIC DISTORTION + NOISE
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
106
104
102
100
98
10
V
f
= 5 V
V
f
= 5 V
CC
= 44.1 kHz
CC
= 44.1 kHz
192 kHz
128 f
44.1 kHz
384 f
96 kHz
256 f
S
S
S
S
S
1
44.1 kHz
−60 dB
384 f
S
192 kHz
128 f
S
0.1
44.1 kHz
384 f
S
96 kHz
256 f
S
96 kHz
256 f
192 kHz
128 f
S
0.01
S
0 dB
75 100
96
−50
0.001
−25
0
25
50
75
100
−50
−25
0
25
50
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 21
Figure 22
SNR
vs
CHANNEL SEPARATION
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
106
104
102
100
98
104
102
100
98
V
= 5 V
V
= 5 V
CC
= 44.1 kHz
CC
f = 44.1 kHz
S
44.1 kHz
384 f
f
S
S
44.1 kHz
384 f
S
192 kHz
128 f
S
192 kHz
128 f
S
96 kHz
256 f
96 kHz
256 f
96
S
S
96
94
94
−50
92
−50
−25
0
25
50
75
100
−25
0
25
50
75
100
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 23
Figure 24
All specifications at T = 25°C, V
CC
= 5 V, f = 44.1 kHz, system clock = 384 f and 24-bit data, unless otherwise noted.
S S
A
17
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ꢀ ꢁꢂ ꢃꢄ ꢅ ꢄ
SLES014B − OCTOBER 2001 − REVISED AUGUST 2002
TYPICAL CHARACTERISTICS—ANALOG DYNAMIC PERFORMANCE
−90-dB OUTPUT SPECTRUM
−90-dB OUTPUT SPECTRUM
0
−20
0
−20
V
f
T
A
= 5 V
= 44.1 kHz
= 25°C
V
= 5 V
CC
CC
S
f
T
= 44.1 kHz
S
= 25°C
A
−40
−40
−60
−60
−80
−80
−100
−120
−140
−160
−180
−100
−120
−140
−160
−180
0.0
0.5
1.0
1.5
2.0
0.0
0.1
0.2
0.3
0.4
f − Frequency − MHz
f − Frequency − MHz
Figure 25
Figure 26
DYNAMIC RANGE
vs
JITTER
106
104
102
100
98
V
= 5 V
= 44.1 kHz
= 25°C
CC
f
T
S
A
96
94
92
90
0
100
200
300
400
500
600
Jitter − ps
Figure 27
All specifications at T = 25°C, V
CC
= 5 V, f = 44.1 kHz, system clock = 384 f and 24-bit data, unless otherwise noted.
S S
A
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SLES014B − OCTOBER 2001 − REVISED AUGUST 2002
APPLICATION INFORMATION
connection diagrams
A basic connection diagram is shown in Figure 28, with the necessary power supply bypassing and decoupling
components. Texas Instruments recommends using the component values shown in Figure 28 for all designs.
A typical application diagram is shown in Figure 29. Texas Instruments’ PLL1700 is used to generate the system
clock input at SCKI, as well as generating the clock for the audio signal processor.
The use of series resistors (22 Ω to 100 Ω) is recommended for SCKI, LRCK, BCK, DATA1, DATA2, and DATA3.
The series resistor combines with the stray PCB and device input capacitance to form a low-pass filter which
removes high-frequency noise from the digital signal, thus, reducing high-frequency emission.
ML
Microcontroller
MC
MD
PLL1700
SCKO3
+5 V Power Supply
+
10 µF
DATA1
DATA2
DATA3
FMT1
SCKI
BCK
DATA1
DATA2
DATA3
FMT1
1
20
19
18
17
16
15
14
13
12
11
2
3
BCK
LRCK
DEMP1
DEMP0
LRCK
DEMP1
DEMP0
4
FMT0
FMT0
5
PCM1606
ZEROA
AGND
V
CC
ZEROA
6
10 µF
+
V
COM
7
LPF
LPF
LPF
LPF
LPF
LPF
V
OUT
V
OUT
V
OUT
5
6
1
V
V
V
4
3
2
8
OUT
OUT
OUT
9
10
Figure 28. Basic Connection Diagram
19
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ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢄ
SLES014B − OCTOBER 2001 − REVISED AUGUST 2002
APPLICATION INFORMATION
DIGITAL SECTION
ANALOG SECTION
{
µC/µP
w
R
S
DATA1
DATA2
DATA3
FMT1
SCKI
BCK
1
2
20
19
18
17
16
15
14
13
12
11
R
S
S
S
S
Audio DSP
or
Decoder
R
R
R
LRCK
3
DEMP1
DEMP0
4
FMT0
5
10 µF
PCM1606
+
R
ZEROA
AGND
V
CC
6
S
V
COM
7
Down Mix
10 µF
10 µF
10 µF
+
+
+
Buffer
L
V
OUT
V
OUT
V
OUT
5
6
1
V
V
V
4
3
2
8
OUT
OUT
OUT
R
9
PLL1700
LF
RF
}
10
Output
SCKO3
Low-Pass
10 µF
10 µF
10 µF
+
+
+
W
XT1
Filters
LS
RS
27-MHz
Master Clock
CTR
SUB
5-V Analog
10 µF
+
0.1 µF
†
‡
§
¶
Format and de-emphasis control can be provided by the DSP/decoder.
Actual clock output used is determined by the application.
R
= 22 Ω to 100 Ω
S
See the Application Information section of this data sheet for more information.
Figure 29. Typical Application Diagram
power supply and grounding
The PCM1606 requires a 5-V supply. The 5-V supply is used to power the DAC analog output-filter circuitry, the
digital filter, and the serial interface circuitry.
Two capacitors are required for supply bypassing, as shown in Figure 29. These capacitors should be located
as close as possible to the PCM1606 package. The 10-µF capacitors should be tantalum or aluminum
electrolytic, while the 0.1-µF capacitors are ceramic (X7R type is recommended for surface-mount
applications).
20
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SLES014B − OCTOBER 2001 − REVISED AUGUST 2002
APPLICATION INFORMATION
D/A output filter circuits
Delta-sigma D/A converters utilize noise shaping techniques to improve in-band signal-to-noise ratio (SNR)
performance at the expense of generating increased out-of-band noise above the Nyquist frequency, or f /2.
S
The out-of-band noise must be low-pass filtered in order to provide optimal converter performance. This is
accomplished by a combination of on-chip and external low-pass filtering.
Figure 30 and Figure 31 show the recommended external low-pass active filter circuits for dual- and
single-supply applications. These circuits are 2nd-order Butterworth filters using the multiple feedback (MFB)
circuit arrangement, which reduces sensitivity to passive component variations over frequency and
temperature. For more information regarding MFB active filter design, see your local Texas Instruments sales
office.
Because the overall system performance is defined by the quality of the D/A converters and their associated
analog output circuitry, high-quality audio op amps are recommended for the active filters. Texas Instruments’
OPA2134 and OPA2353 dual op amps are shown in Figure 30 and Figure 31, and are recommended for use
with the PCM1606.
R
C
2
1
2
R
R
3
1
R
−
V
IN
4
1
OPA2134
V
OUT
3
C
+
2
R2
AV [ *
R1
Figure 30. Dual-Supply Filter Circuit
R2
AV [ *
R1
R
C
2
1
2
R
R
3
1
R
−
V
IN
4
1
OPA2134
V
OUT
3
C
+
2
PCM1606
V
COM
−
To Additional
Low-Pass Filter
Circuits
OPA337
+
+
C
10 µF
2
Figure 31. Single-Supply Filter Circuit
21
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SLES014B − OCTOBER 2001 − REVISED AUGUST 2002
APPLICATION INFORMATION
PCB layout guidelines
A typical PCB layout for the PCM1606 is shown in Figure 32. A ground plane is recommended, with the analog
and digital sections being isolated from one another using a split or cut in the circuit board. The PCM1606 should
be oriented with the digital I/O pins facing the ground plane split/cut to allow for short, direct connections to the
digital audio interface and control signals originating from the digital section of the board.
Separate power supplies are recommended for the digital and analog sections of the board. This prevents the
switching noise present on the digital supply from contaminating the analog power supply and degrading the
dynamic performance of the D/A converters. In cases where a common 5-V supply must be used for the analog
and digital sections, an inductance (RF choke, ferrite bead) should be placed between the analog and digital
5-V supply connections to avoid coupling of the digital switching noise into the analog circuitry. Figure 33 shows
the recommended approach for single-supply applications.
Digital Power
+V DGND
Analog Power
AGND +5VA
+V
S S
−V
D
V
CC
Digital
Logic
and
Audio
Output
Circuits
PCM1606
AGND
Digital
Ground
Processor
Analog
Ground
Digital Section
Analog Section
Return Path for Digital Signals
Figure 32. Recommended PCB Layout
22
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ꢀ ꢁꢂ ꢃ ꢄꢅ ꢄ
SLES014B − OCTOBER 2001 − REVISED AUGUST 2002
APPLICATION INFORMATION
PCB layout guidelines (continued)
Power Supplies
RF Choke or Ferrite Bead
+5V
AGND +V −V
S S
V
CC
V
DD
Output
Circuits
PCM1606
AGND
Common
Ground
Digital Section
Analog Section
Figure 33. Single-Supply PCB Layout
key performance parameters measurement
This section provides information on how to measure key dynamic performance parameters for the PCM1606.
In all cases, a System Two Cascade Plus by Audio Precision or equivalent audio measurement system is used
to perform the testing.
total harmonic distortion + noise
Total harmonic distortion + noise (THD+N) is a significant figure of merit for audio D/A converters, because it
takes into account both harmonic distortion and all noise sources within a specified measurement bandwidth.
The true rms value of the distortion and noise is referred to as THD+N.
For the PCM1606 D/A converters, THD+N is measured with a full scale, 1-kHz digital sine wave as the test
stimulus at the input of the DAC. The digital generator is set to 24-bit audio word length and a sampling frequency
of 44.1 kHz or 96 kHz. The digital generator output is taken from the unbalanced S/PDIF connector of the
measurement system. The S/PDIF data is transmitted via coaxial cable to the digital audio receiver on the
2
DEM−DAI1606 demo board. The receiver is then configured to output 24-bit data in either I S or left-justified
data format. The DAC audio interface format is programmed to match the receiver output format. The analog
output is then taken from the DAC post filter and connected to the analog analyzer input of the measurement
system. The analog input is band-limited using filters resident in the analyzer. The resulting THD+N is measured
by the analyzer and displayed by the measurement system.
23
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ꢀ ꢁꢂ ꢃꢄ ꢅ ꢄ
SLES014B − OCTOBER 2001 − REVISED AUGUST 2002
APPLICATION INFORMATION
total harmonic distortion + noise (continued)
Evaluation Board
DEM-DAI1606
2nd-Order
Low-Pass
Filter
S/PDIF
Receiver
PCM1606
f
= 54 kHz
−3 dB
Analyzer
and
Display
Digital
Generator
S/PDIF
Output
Band Limit
Notch Filter
= 1 kHz
†
†
100% Full-Scale,
24-Bit,
1-kHz Sine Wave
RMS Mode
HPF = 22 Hz
LPF = 22 kHz
Option = 20-kHz Apogee Filter
f
c
‡
†
‡
There is little difference in measured THD+N when using the various settings for these filters..
Required for THD+N test.
Figure 34. Test Setup for THD+N Measurements
dynamic range
Dynamic range is specified as A-weighted, THD+N measured with a –60 dB of full-scale (FS), 1-kHz digital sine
wave stimulus at the input of the D/A converter. This measurement is designed to give a good indicator of how
the DAC performs given a low-level input signal.
The measurement setup for the dynamic range measurement is shown in Figure 35, and is similar to the THD+N
test setup discussed previously. The differences include the band limit filter selection, the additional A-weighting
filter, and the –60-dB FS input level.
idle channel signal-to-noise ratio
The signal-to-noise ratio (SNR) test provides a measure of the noise floor of the D/A converter. The input to the
D/A is all 0s data. This ensures that the delta-sigma modulator output is connected to the output amplifier circuit
so that idle tones (if present) can be observed and affect the SNR measurement. The dither function of the digital
generator must also be disabled to ensure an all 0s data stream at the input of the D/A converter.
The measurement setup for SNR is identical to that used for dynamic range, with the exception of the input signal
level. (See the note provided in Figure 35).
24
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ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢄ
SLES014B − OCTOBER 2001 − REVISED AUGUST 2002
APPLICATION INFORMATION
idle channel signal-to-noise ratio (continued)
Evaluation Board
DEM-DAI1606
2nd-Order
Low-Pass
Filter
S/PDIF
Receiver
PCM1606
f
= 54 kHz
−3 dB
Analyzer
and
Display
Digital
Generator
A-Weight
Filter
†
S/PDIF
Output
Band Limit
Notch Filter
= 1 kHz
0% Full-Scale,
Dither Off (SNR)
−60 dB FS,
RMS Mode
HPF = 22 Hz
LPF = 22 kHz
Option = A-Weighting
f
c
†
1 kHz Sine Wave
(Dynamic Range)
†
Results without A-Weighting will be approximately 3 dB worse.
Figure 35. Test Setup for Dynamic Range and SNR Measurements
25
www.ti.com
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢄ
SLES014B − OCTOBER 2001 − REVISED AUGUST 2002
MECHANICAL DATA
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,15 NOM
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°−ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /D 09/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15 mm.
D. Falls within JEDEC MO-150
26
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
16-Jun-2009
PACKAGING INFORMATION
Orderable Device
PCM1606E
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SSOP
DB
20
20
20
20
65 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCM1606E/2K
PCM1606E/2KG4
PCM1606EG4
SSOP
SSOP
SSOP
DB
DB
DB
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
65 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
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