PCM1700UJ [BB]

D/A Converter, 2 Func, Serial Input Loading, PDSO28,;
PCM1700UJ
型号: PCM1700UJ
厂家: BURR-BROWN CORPORATION    BURR-BROWN CORPORATION
描述:

D/A Converter, 2 Func, Serial Input Loading, PDSO28,

转换器
文件: 总5页 (文件大小:67K)
中文:  中文翻译
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®
PCM1700U  
PCM1700P  
Dual 18-Bit Monolithic Audio  
DIGITAL-TO-ANALOG CONVERTER  
FEATURES  
DESCRIPTION  
DUAL 18-BIT LOW-POWER MONOLITHIC  
The PCM1700 is a low cost, high-performance, dual  
18-bit digital-to-analog converter. The PCM1700 fea-  
tures low glitch, co-phase current and voltage outputs  
and only requires ±5V supplies. The PCM1700 comes  
complete with an internal reference and optional MSB  
adjustability for even greater THD performance. Total  
power dissipation is less than 400mW max. Low  
maximum Total Harmonic Distortion + Noise (–92dB  
max; PCM1700P-K) is 100% tested. The very fast  
PCM1700 is also capable of 16X oversampling rates  
on both channels simultaneously, providing freedom  
in output filter selection.  
AUDIO D/A CONVERTER  
VERY LOW MAX THD+N: –92dB Without  
External Adjust  
CO-PHASE, LOW-GLITCH ±3V OR ±670µA  
AUDIO OUTPUTS  
CAPABLE OF 16X PER CHANNEL  
OVERSAMPLING RATE  
COMPLETE WITH INTERNAL  
REFERENCE  
SERIAL INPUT FORMAT 100% COMPAT-  
IBLE WITH INDUSTRY STD PCM56P  
The PCM1700 comes in space-saving 28-pin plastic  
DIP and SOIC packages. PCM1700 accepts a serial  
data input format that is compatible with other Burr-  
Brown PCM products such as the industry standard  
PCM56P.  
RUNS ON ±5V SUPPLIES AND  
DISSIPATES 300mW MAX  
COMPACT 28-PIN PLASTIC DIP  
OR SOIC  
MSB Adj Left  
IOUT Left  
Reference  
IOUT Right  
SJ  
18-Bit  
IOUT DAC  
Data Left  
18-Bit  
Serial-to-Parallel  
Shift Register  
VOUT Left  
Clock  
Control  
Logic  
Latch Enable  
18-Bit  
Serial-to-Parallel  
Shift Register  
VOUT Right  
18-Bit  
IOUT DAC  
Data Right  
MSB Adj Right  
SJ  
International Airport Industrial Park  
Tel: (520) 746-1111  
Mailing Address: PO Box 11400  
Tucson, AZ 85734  
Street Address: 6730 S. Tucson Blvd.  
Tucson, AZ 85706  
Twx: 910-952-1111  
Cable: BBRCORP  
Telex: 066-6491  
FAX: (520) 889-1510  
Immediate Product Info: (800) 548-6132  
© 1990 Burr-Brown Corporation  
PDS-1035D  
Printed in U.S.A. August, 1993  
SPECIFICATIONS  
ELECTRICAL  
At 25°C, and ±VCC= ±5.00V unless otherwise noted. Where relevant, specifications apply to both left and right input/output channels.  
PCM1700U/U-J/U-K, PCM1700P/P-J/P-K  
PARAMETER  
RESOLUTION  
DYNAMIC RANGE  
INPUT  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
Bits  
18  
+108  
dB  
DIGITAL INPUT  
Logic Family  
TTL Compatible  
Logic Level: VIH  
+2  
0
+VDD  
+0.8  
+1  
V
V
µA  
µA  
VIL  
IIH  
IIL  
VIH = +2.7V  
VIL = +0.4V  
–50  
Data Format  
Input Clock Frequency  
Serial BTC(1)  
20  
11.288  
MHz  
DYNAMIC CHARACTERISTICS  
TOTAL HARMONIC DISTORTION + N(6)  
PCM1700_:  
f = 991kHz (0dB)  
f
f
S = 352.8kHz(4)  
S = 352.8kHz  
fS = 352.8kHz  
–88  
–74  
–34  
–82  
–68  
–28  
dB  
dB  
dB  
f = 991kHz (–20dB)  
f
IN = 991kHz (–60dB)  
PCM1700_-J:  
f = 991kHz (0dB)  
f = 991kHz (–20dB)  
f = 991kHz (–60dB)  
PCM1700_-K:  
fS = 352.8kHz  
fS = 352.8kHz  
fS = 352.8kHz  
–94  
–76  
–36  
–88  
–74  
–34  
dB  
dB  
dB  
f = 991kHz (0dB)  
f = 991kHz (–20dB)  
f = 991kHz (–60dB)  
fS = 352.8kHz  
fS = 352.8kHz  
fS = 352.8kHz  
–98  
–80  
–40  
–92  
–74  
–34  
dB  
dB  
dB  
CHANNEL SEPARATION  
+96  
+108  
+108  
dB  
dB  
SIGNAL-TO-NOISE RATIO(5)  
TRANSFER CHARACTERISTICS  
20Hz to 20kHz at BPZ(6)  
ACCURACY  
Gain Error  
Gain Mismatch  
±1  
±1  
10  
5
±1  
100  
20  
±3  
±3  
%
%
mV  
mV  
LSB  
Channel to Channel  
Channel to Channel  
Bipolar Zero Error  
BPZ Error Mismatch  
BPZ Differential Linearity Error(7)  
Gain Drift  
Bipolar Zero Drift  
Warm-up Time  
ppm/°C  
ppm of FSR/°C  
minute  
1
POWER SUPPLY REJECTION  
±VCC to VOUT  
+86  
dB  
ANALOG OUTPUT  
Voltage: Output Range  
Output Impedance  
Current Output  
±3  
0.1  
±2  
TBD  
Indefinite  
V
mA  
pF  
Capacitive Load Drive  
Short Circuit Duration  
Settling Time  
R
LOAD = 1.5kΩ  
Sufficient to Meet THD+N Specs  
Meets All THD+N Specs Without External Output Deglitching  
Glitch Energ  
Current:  
Output Range  
Output Impedance  
(±2%)  
(±2%)  
±670  
1.67  
µA  
kΩ  
POWER SUPPLY REQUIREMENTS  
±VCC Supply Voltage  
Supply Current: +ICC  
–ICC  
+4.75  
+5.00  
+18  
–42  
+5.25  
+30  
–65  
V
+VCC = +5.0V  
–VCC = –5.0V  
±VCC = ±5.0V  
mA  
mA  
mW  
Power Dissipation  
280  
475  
TEMPERATURE RANGE  
Specification  
Operating  
Storage  
0
–30  
–60  
+70  
+70  
+100  
°C  
°C  
°C  
NOTES: (1) Binary Two’s Complement coding. (6) Ratio of (DistortionRMS + NoiseRMS) / SignalRMS. (3) D/A converter input frequency/signal level on both left and right  
channels. (4) D/A converter sample frequency (8 X 44.1kHz; 8X oversampling per channel). (5) Ratio of NoiseRMS / SignalRMS. Measured using an A-weighted filter.  
(6) Bipolar zero. (7) Differential non-linearity at bipolar major carry input code. Measured in 16-bit LSBs. Adjustable to zero error.  
®
2
PCM1700  
PIN ASSIGNMENTS (Plastic PKG)  
PIN ASSIGNMENTS (SOIC PKG)  
PIN  
DESCRIPTION  
MNEMONIC  
PIN  
DESCRIPTION  
MNEMONIC  
1
–5V Analog Supply  
–VCC  
9
–5V Analog Supply  
–VCC  
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
Left Channel Servo-Amp Decoupling Point  
Left Channel MSB Adjustment  
No Connect  
Left Channel Bipolar Offset Decoupling Point  
Left Channel Current Output  
Left Channel Analog Common  
Left Channel Summing Junction  
Left Channel Voltage Output  
No Connect  
+5V Digital Supply  
Left Channel Data Input  
Clock Input  
–5V Logic Supply  
CAP  
MSB ADJ (L)  
NC  
10  
11  
19  
12  
13  
14  
15  
16  
17  
18  
20  
21  
22  
23  
24  
25  
26  
27  
28  
1
Left Channel Servo-Amp Decoupling Point  
Left Channel MSB Adjustment  
No Connect  
Left Channel Bipolar Offset Decoupling Point  
Left Channel Current Output  
Left Channel Analog Common  
Left Channel Summing Junction  
Left Channel Voltage Output  
No Connect  
+5V Digital Supply  
Left Channel Data Input  
Clock Input  
–5V Logic Supply  
CAP  
MSB ADJ (L)  
NC  
CAP  
CAP  
IOUT (L)  
ACOM  
SJ (L)  
VOUT (L)  
NC  
+VDD  
DATA  
CLOCK  
–VDD  
LE  
DATA (R)  
DCOM  
NC  
VOUT (R)  
SJ (R)  
ACOM  
IOUT (R)  
CAP  
MSB ADJ (R)  
CAP  
VPOT  
+VCC  
IOUT (L)  
ACOM  
SJ (L)  
VOUT (L)  
NC  
+VDD  
DATA  
CLOCK  
–VDD  
Latch Enable Input  
Right Channel Data Input  
Digital Common  
Latch Enable Input  
Right Channel Data Input  
Digital Common  
LE  
DATA (R)  
DCOM  
NC  
VOUT (R)  
SJ (R)  
ACOM  
IOUT (R)  
CAP  
MSB ADJ (R)  
CAP  
VPOT  
+VDD  
DCOM  
No Connect  
No Connect  
Right Channel Voltage Output  
Right Channel Summing Junction  
Right Channel Analog Common  
Right Channel Current Output  
Right Channel Bipolar Offset Decoupling Point  
Right Channel MSB Adjustment  
Right Channel Servo-Amp Decoupling Point  
MSB Adjustment Potentiometer Voltage Output  
+5V Analog Supply  
Right Channel Voltage Output  
Right Channel Summing Junction  
Right Channel Analog Common  
Right Channel Current Output  
Right Channel Bipolar Offset Decoupling Point  
Right Channel MSB Adjustment  
Right Channel Servo-Amp Decoupling Point  
MSB Adjustment Potentiometer Voltage Output  
+5V Analog Supply  
2
3
4
5
6
7
8
Digital Common  
DCOM  
Digital Common  
NOTE: In the SOIC (PCM1700U) package, the die is rotated 90°. Therefore,  
the pin assignments are different from the DIP. See pin assignments on page  
4 for details.  
ORDERING INFORMATION  
( )  
( )  
PCM1700  
Basic Model Number  
P: Plastic U: SOIC  
Performance Grade Code  
PACKAGE INFORMATION  
PACKAGE DRAWING  
MODEL  
PACKAGE  
NUMBER(1)  
ABSOLUTE MAXIMUM RATINGS  
PCM1700U  
28-Pin SOIC  
28-Pin SOIC  
28-Pin SOIC  
28-Pin Plastic DIP  
28-Pin Plastic DIP  
28-Pin Plastic DIP  
217  
217  
217  
126  
126  
126  
PCM1700U-J  
PCM1700U-K  
PCM1700P  
PCM1700P-J  
PCM1700P-K  
DCSupply Voltages ..................................................................... ±7.5VDC  
Input Logic Voltage ................................................................. –1V to +VCC  
Power Dissipation .......................................................................... 500mW  
Operating Temperature..................................................... –25°C to +70°C  
Storage Temperature ...................................................... –60°C to +100°C  
Lead Temperature (soldering, 10s) ................................................ +300°C  
NOTE: (1) For detailed drawing and dimension table, please see end of data  
sheet, or Appendix D of Burr-Brown IC Data Book.  
®
3
PCM1700  
DIGITAL INPUT  
ANALOG OUTPUT  
> 25ns  
LSB  
Binary Two’s  
Voltage (V)  
VOUT Mode  
Current (mA)  
IOUT Mode  
Data Input  
MSB  
Complement (BTC)  
DAC Output  
1FFFF Hex  
00000 Hex  
3FFFF Hex  
20000 Hex  
+ FS  
BPZ  
+2.99997711  
0.00000000  
–0.00002289  
–3.00000000  
–0.66999489  
0.00000000  
+0.00000511  
+0.67000000  
> 15ns > 15ns  
> 5ns  
BPZ – 1LSB  
– FS  
Clock In  
> 25ns  
> 25ns  
> 60ns  
TABLE I. PCM1700 Input/Output Relationships.  
> 15ns  
Latch  
Enable  
> One Clock Cycle  
> One Clock Cycle  
FIGURE 1. PCM1700P Setup and Hold Timing Diagram.  
P13  
(Clock)  
P12  
Data (L)  
1
MSB  
2
2
3
3
4
4
10 11 12 13 14 15 16 17 18 19  
LSB  
P16  
Data (R)  
1
MSB  
10 11 12 13 14 15 16 17 18 19  
LSB  
P15  
(Latch  
Enable)  
FIGURE 2. Timing Diagram.  
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes  
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change  
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant  
any BURR-BROWN product for use in life support devices and/or systems.  
®
4
PCM1700  
100k  
+5V  
10µF  
+
0.01µF  
–5V  
10µF  
1
2
3
4
5
6
7
8
9
–VCC  
DCOM 28  
+VCC 27  
VPOT 26  
CAP 25  
0.47µF  
100kΩ  
100kΩ  
0.47µF  
CAP  
0.1µF  
0.1µF  
MSB Adj (Left)  
NC  
100kΩ  
.01µF  
0.1µF  
0.1µF  
Optional Bit  
Adjust Circuit  
CAP  
MSB Adj (Right) 24  
CAP 23  
IOUT (Left)  
ACOM (Left)  
SJ (Left)  
IOUT (Right) 22  
ACOM (Right) 21  
SJ (Right) 20  
VOUT (Right) 19  
NC 18  
VOUT (Left)  
10 NC  
11 +VDD  
0.47µF  
0.47µF  
12 DATA (Left)  
13 Clock  
14 –VDD  
DCOM 17  
DATA (Right) 16  
LE 15  
FIGURE 3. Voltage Output Connection Diagram (DIP Package Diagram.)  
100kΩ  
0.01µF  
+5V  
+
10µF  
–5V  
10µF  
1
2
3
4
5
6
7
8
9
–VCC  
DCOM 28  
+VCC 27  
VPOT 26  
CAP 25  
0.47µF  
100kΩ  
100kΩ  
0.47µF  
CAP  
+
0.1µF  
0.1µF  
MSB Adj (Left)  
NC  
4.5k(1)  
100kΩ  
0.1µF  
0.1µF  
Optional Bit  
Adjust Circuit  
0.01µF  
CAP  
MSB Adj (Right) 24  
CAP 23  
4.55k(1)  
VOUT (R)  
IOUT (Left)  
ACOM (Left)  
SJ (Left)  
IOUT (Right) 22  
ACOM (Right) 21  
SJ (Right) 20  
VOUT (Right) 19  
NC 18  
VOUT (L)  
1.22k(1)  
VOUT (Left)  
BB  
OPA602BP  
BB  
10 NC  
OPA602BP  
1.22k(1)  
11 +VDD  
0 .47µF  
12 DATA (Left)  
13 Clock  
14 –VDD  
DCOM 17  
DATA (Right) 16  
LE 15  
NOTES:  
(1) Low TCR resistors  
such as Vishay.  
0.47µF  
FIGURE 4. Current Output Connection Diagram (DIP Package Diagram.)  
5
®
PCM1700  

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