SPT7862 [CADEKA]
10-BIT, 40 MSPS, DUAL-CHANNEL A/D CONVERTER; 10位， 40 MSPS ，双通道A / D转换器
| 型号： | SPT7862 |
| 厂家： | 
CADEKA MICROCIRCUITS LLC. |
| 描述： | 10-BIT, 40 MSPS, DUAL-CHANNEL A/D CONVERTER |
| 文件： | 总10页 (文件大小：188K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SPT7862
10-BIT, 40 MSPS, DUAL-CHANNEL A/D CONVERTER
FEATURES
APPLICATIONS
• Dual-channel, 10-Bit, 40 MSPS analog-to-digital
converter
• Low power dissipation: 320 mW (typical)
• Internal track-and-hold
• Video set-top boxes
• Cellular base stations
• QPSK/QAM RF demodulation
• S-video digitizers
• Single +5 volt supply
• Composite video digitizers
• Portable and handheld instrumentation
• Medical ultrasound
• Tri-state, TTL/CMOS-compatible outputs
• Selectable +3 or +5 V logic I/O
• High ESD protection of 3,500 volts minimum
• Cable modems
• Video frame grabbers
GENERAL DESCRIPTION
The SPT7862 contains two separate 10-bit CMOS analog-
to-digital converters that have sampling rates of up to 40
MSPS. Each device has its own separate clock and refer-
ence inputs so that they can be used independently in
multichannel applications or can be driven from the same
inputs for demanding quadrature demodulation and S-video
applications. On-chip track-and-hold and advanced propri-
etary circuit design in a CMOS process technology provide
very good dynamic performance.
The SPT7862 operates from a single +5 V supply. Digital
data outputs are user selectable at +3 or +5 V. Output data
format is straight binary.
The SPT7862 is available in a 64-lead TQFP package
(10 x 10 mm) over the industrial temperature range of
–40 °C to +85 °C.
BLOCK DIAGRAM
AV
AGND
DV
DGND
DD
DD
OV
(+3.3/5.0 V)
DDA
Output
Buffers
V
ADC
INA
DA9–0
OGND
V
INRA
A
V
RHFA
V
RHSA
DAV
Reference
Ladder
A
V
RLFA
EN
V
RLSA
Timing
Generation
CLK A
OV
(+3.3/5.0 V)
DDB
Output
Buffers
V
INB
ADC
DB9–0
V
INRB
V
RHFB
OGND
B
V
RHSB
Reference
Ladder
DAV
B
V
RLFB
V
RLSB
Timing
Generation
CLK B
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C
Supply Voltages
AVDD .........................................................................+6 V
DVDD .........................................................................+6 V
Output
Digital Outputs .......................................................10 mA
Temperature
Input Voltages
Operating Temperature ............................. –40 to +85 °C
Junction Temperature ......................................... +175 °C
Lead Temperature, (soldering 10 seconds) ........ +300 °C
Storage Temperature............................... –65 to +150 °C
Analog Input................................. –0.5 V to AVDD +0.5 V
VREF ................................................................. 0 to AVDD
CLK Input ................................................................... VDD
AVDD – DVDD......................................................±100 mV
AGND – DGND ..................................................±100 mV
Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal
applied conditions in typical applications.
ELECTRICAL SPECIFICATIONS
TA=TMIN to TMAX, AVDD=DVDD=OVDD=+5.0 V, VIN=0 to 4 V, ƒS=40 MSPS, VRHS=4.0 V, VRLS=0.0 V, unless otherwise specified.
TEST
CONDITIONS
TEST
LEVEL
SPT7862
TYP
PARAMETERS
MIN
MAX
UNITS
Resolution
10
Bits
DC Accuracy
Integral Nonlinearity
Differential Nonlinearity
V
V
±1.0
±0.5
LSB
LSB
Analog Input
Input Voltage Range
Input Resistance
Input Capacitance
Input Bandwidth
Offset
IV
V
V
V
V
V
VRLS
VRHS
V
kΩ
pF
MHz
LSB
LSB
29
5.0
250
±2.0
±2.0
(Small Signal)
Gain Error
Reference Input
Resistance
Voltage Range
VRLS
V
500
Ω
IV
IV
V
V
V
0
3.0
1.0
–
–
4.0
90
75
2.0
AVDD
5.0
V
V
V
mV
mV
VRHS
VRHS – VRLS
∆(VRHF – VRHS
)
∆(VRLS – VRLF
)
Conversion Characteristics
Maximum Conversion Rate
Minimum Conversion Rate
Pipeline Delay (Latency)
Aperture Delay Time
VI
IV
IV
V
40
2
MHz
MHz
12 Clock Cycles
4.0
7
ns
ps(rms)
Aperture Jitter Time
V
Dynamic Performance
Effective Number of Bits
ƒIN = 3.58 MHz
V
VI
9.1
8.3
Bits
Bits
ƒIN = 10.0 MHz
7.8
Signal-to-Noise Ratio
(without Harmonics)
ƒIN = 3.58 MHz
V
I
IV
57.9
54.2
dB
dB
dB
ƒ
IN = 10.0 MHz
TA = +25 °C
TA = TMIN to TMAX
52
47
ƒIN = 10.0 MHz
SPT7862
2
2/23/00
ELECTRICAL SPECIFICATIONS
TA=TMIN to TMAX, AVDD=DVDD=OVDD=+5.0 V, VIN=0 to 4 V, ƒS=40 MSPS, VRHS=4.0 V, VRLS=0.0 V, unless otherwise specified.
TEST
CONDITIONS
TEST
LEVEL
SPT7862
TYP
PARAMETERS
MIN
MAX
UNITS
Dynamic Performance
Harmonic Distortion
9 Distortion bins from
1024 pt FFT
ƒ
IN = 3.58 MHz
V
I
IV
–63
–55.7
dB
dB
dB
ƒIN = 10.0 MHz
ƒIN = 10.0 MHz
TA = +25 °C
TA = TMIN to TMAX
–52
–52
Signal-to-Noise and Distortion
(SINAD)
ƒIN = 3.58 MHz
V
I
IV
56.7
51.8
dB
dB
dB
ƒ
IN = 10.0 MHz
TA = +25 °C
TA = TMIN to TMAX
49
46
ƒIN = 10.0 MHz
Spurious Free Dynamic Range
ƒIN = 10.0 MHz
Differential Phase
Differential Gain
V
V
V
56.8
58.3
±0.3
±0.3
60
dB
Degree
%
Channel-to-Channel Crosstalk
ƒIN = 3.58 MHz
V
V
74
67
dB
dB
ƒIN = 10.0 MHz
Inputs
Logic 1 Voltage
Logic 0 Voltage
Maximum Input Current Low
Maximum Input Current High
Input Capacitance
VI
VI
VI
VI
V
2.1
V
V
µA
µA
pF
0.8
+10
+10
–10
–10
+5
Digital Outputs
Logic 1 Voltage
Logic 0 Voltage
tRISE
IOH = 0.5 mA
VI
VI
V
OVDD –0.5
V
V
ns
ns
I
OL = 1.6 mA
0.44
15 pF load
15 pF load
10
10
tFALL
V
Output Enable to Data
Output Delay
20 pF load, TA = +25 °C
50 pF load over temp.
V
V
10
22
ns
ns
Power Supply Requirements
Voltages OVDD
DVDD
IV
IV
IV
VI
VI
VI
V
3.0
5.0
V
V
V
mA
mA
mW
dB
5.0
5.0
52
12
320
70
AVDD
Currents AIDD + DIDD
OIDD
Power Dissipation
Power Supply Refection Ratio
62
14
380
TEST LEVEL CODES
TEST PROCEDURE
TEST LEVEL
All electrical characteristics are subject to the follow-
ing conditions:
100% production tested at the specified temperature.
I
100% production tested at TA=25 °C, and sample tested at
II
All parameters having min/max specifications are
guaranteed. The Test Level column indicates the
specific device testing actually performed during
production and Quality Assurance inspection. Any
blank section in the data column indicates that the
specification is not tested at the specified condition.
the specified temperatures.
QA sample tested only at the specified temperatures.
III
Parameter is guaranteed (but not tested) by design and
characterization data.
IV
Parameter is a typical value for information purposes only.
V
100% production tested at TA = 25 °C. Parameter is guaran-
VI
teed over specified temperature range.
SPT7862
3
2/23/00
Figure 1a – Timing Diagram 1
1
11
10
12
2
13
9
3
8
17
14
ANALOG IN
CLOCK IN
4
7
15
16
5
6
SAMPLING
CLOCK
(Internal)
INVALID
VALID
DATA OUTPUT
1
2
3
4
5
DATA VALID
Figure 1b – Timing Diagram 2
t
CLK
t
C
t
t
CL
CH
CLOCK IN
DATA
Data Ø
Data 2
Data 3
Data 1
OUTPUT
t
OD
t
S
t
t
CL
DATA VALID
CH
t
S
Table I – Timing Parameters
DESCRIPTION
PARAMETERS MIN TYP MAX UNITS
Conversion Time
Clock Period
tC
tCLK
tCH
tCL
tCLK
25
ns
ns
%
%
Clock High Duty Cycle
Clock Low Duty Cycle
40
50
50
60
60
40
Clock to Output Delay
(30 pF Load)
tOD
17
10
20
16
ns
ns
Clock to DAV (30 pF load) tS
SPT7862
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2/23/00
TYPICAL PERFORMANCE CHARACTERISTICS
THD, SNR, SINAD vs Sample Rate
THD, SNR, SINAD vs Input Frequency
ƒIN = 10 MHz
70
65
60
55
70
65
60
55
THD
SNR
THD
SNR
SINAD
SINAD
50
45
50
45
40
40
0
5
10
15
20
0
1
5
20
40
10
30
50
Input Frequency (MHz)
Sample Rate (MSPS)
THD, SNR, SINAD vs Temperature
Power Dissipation vs Sample Rate
ƒ
IN
= 10 MHz
ƒIN = 10 MHz
70
65
60
600
500
400
300
THD
55
50
45
SNR
200
100
SINAD
40
0
–55
–40
–25
0
25
70
85
125
0
1
5
20
40
10
30
50
60
Temperature (°C)
Sample Rate (MSPS)
Spectral Response
Frequency (MHz)
SPT7862
5
2/23/00
Figure 2 – Typical Interface Circuit
+D5V
Ref In (+4V)
VRHFA
VRHSA
VRLSA
VRLFA
VINA
+3V/5V
10
OVDDA
VINA
DA9–0
OGNDA
DAVA
Interface
Logic
VINRA
ClockINA
CLKA
VCAL
SPT7862
Ref In (+4V)
+3V/5V
10
VRHFB
VRHSB
VRLSB
VRLFB
VINB
OVDDB
DB9–0
OGNDB
DAVB
VINB
Interface
Logic
VINRB
CLKB
ClockINB
EN
AVDD AGND
DVDD
Enable/Tri-State
(Enable = Active Low)
DGND*
+A5
+D5V
FB
+D5
+A5
*To reduce the possibility of latch-up, avoid connecting
the DGND pins of the ADC to the digital ground of the system.
+
+
10 µF
10 µF
NOTES: 1. FB is a 10 µH inductor or ferrite bead. It is
to be located as close to the device as possible.
2. All capacitors are 0.1 µF surface-mount, unless
otherwise specified.
+5V
+5V
Digital
+5V
+5V
Analog
Digital
Return
Analog
Return
The high sample rate is achieved by using multiple SAR
ADC sections in parallel, each of which samples the input
signal in sequence. Each SAR ADC uses 16 clock cycles to
complete a conversion. The clock cycles are allocated as
follows:
TYPICAL INTERFACE CIRCUIT
Very few external components are required to achieve the
stated device performance. Figure 2 shows the typical inter-
face requirements when using the SPT7862 in normal
circuit operation. The following sections provide descrip-
tions of the major functions and outline critical performance
criteria to consider for achieving the optimal device
performance.
Table II – Clock Cycles
Clock
Operation
1
Reference zero sampling
Auto-zero comparison
Auto-calibrate comparison
Input sample
POWER SUPPLIES AND GROUNDING
2
3
CADEKA suggests that both the digital and the analog sup-
ply voltages on the SPT7862 be derived from a single ana-
log supply as shown in figure 2. A separate digital supply
should be used for all interface circuitry. CADEKA suggests
using this power supply configuration to prevent a possible
latch-up condition on power up.
4
5–15
16
11-bit SAR conversion
Data transfer
The 16-phase clock, which is derived from the input clock,
synchronizes these events. The timing signals for adjacent
SAR ADC sections are shifted by one clock cycle so that the
analog input is sampled on every cycle of the input clock by
exactly one SAR ADC section. After 16 clock periods, the
timing cycle repeats. The latency from analog input sample
to the corresponding digital output is 12 clock cycles.
OPERATING DESCRIPTION
The general architecture for the dual CMOS ADC is shown
in the block diagram. Each ADC design contains 16 identi-
cal successive approximation (SAR) ADC sections (all oper-
ating in parallel), a 16-phase clock generator, an 11-bit 16:1
digital output multiplexer, correction logic, and a voltage ref-
erence generator which provides common reference levels
for each ADC section.
SPT7862
6
2/23/00
• Since only 16 comparators are used, a huge power sav-
ings is realized.
Figure 3 – Ladder Force/Sense Circuit for Each ADC
1
AGND
• The auto-zero operation is done using a closed loop sys-
tem that uses multiple samples of the comparator’s
response to a reference zero.
+
-
2
3
V
V
RHF
RHS
• The auto-calibrate operation, which calibrates the gain
of the MSB reference and the LSB reference, is also
done with a closed loop system. Multiple samples of
the gain error are integrated to produce a calibration volt-
age for each SAR ADC section.
4
5
N/C
V
RLS
-
+
6
7
V
RLF
• Capacitive displacement currents, which can induce sam-
pling error, are minimized since only one comparator
samples the input during a clock cycle.
V
IN
All capacitors are 0.01 µF
• The total input capacitance is very low, since sections of
the converter which are not sampling the signal are iso-
lated from the input by transmission gates.
Figure 4 – Simplified Reference Ladder Drive Circuit
Without Force/Sense Circuit
VOLTAGE REFERENCE
+4.0 V
External
Reference
The SPT7862 requires the use of a single external voltage
reference for driving the high side of each reference ladder.
Each ladder is totally independent and may operate at dif-
ferent voltage levels. The high side of the reference ladder
must operate within a range of 3 V to 5 V. The lower side of
each ladder is typically tied to AGND (0.0 V), but can be run
up to 2.0 V with a second reference. The analog input volt-
age range will track the total voltage difference measured
90 mV
R/2
V
RHS
(+3.91 V)
R
R
R
R=30 Ω (typ)
All capacitors are 0.01 µF
R
between the ladder sense lines, VRHS and VRLS
.
R
R
Force and sense taps are provided to ensure accurate and
stable setting of the upper and lower ladder sense line volt-
ages across part-to-part and temperature variations. By
using the configuration shown in figure 3, offset and gain
errors of less than ±2 LSB can be obtained.
V
RLS
(0.075 V)
75 mV
R/2
V
(AGND)
RLF
0.0 V
In cases in which wider variations in offset and gain can be
tolerated, the external reference can be tied directly to VRHF
and AGND can be tied directly to VRLF as shown in figure 4.
Decouple force and sense lines to AGND with a .01 µF ca-
pacitor (chip cap preferred) to minimize high-frequency
noise injection. If this simplified configuration is used, the
following considerations should be taken into account:
Typically, the top side voltage drop for VRHF to VRHS will
equal:
VRHF – VRHS = 2.25 % of (VRHF – VRLF) (typical),
and the bottom side voltage drop for VRLS to VRLF will equal:
VRLS – VRLF = 1.9 % of (VRHF – VRLF) (typical).
The reference ladder circuit shown in figure 4 is a simplified
representation of the actual reference ladder with force and
sense taps shown. Due to the actual internal structure of the
ladder, the voltage drop from VRHF to VRHS is not equivalent
Figure 4 shows an example of expected voltage drops for a
specific case. VREF of 4.0 V is applied to VRHF and VRLF is
tied to AGND. A 90 mV drop is seen at VRHS (= 3.91 V) and
a 75 mV increase is seen at VRLS (= 0.075 V).
to the voltage drop from VRLF to VRLS
.
SPT7862
7
2/23/00
Figure 6 – On-Chip Protection Circuit
ANALOG INPUT
VDD
VINA and VINB are the analog inputs and VINRA and VINRB are
the respective input returns. Each input return is typically
tied to its respective low side reference ladder sense line.
(See Figure 2.) The input voltage range is from VRLS to VRHS
(typically 4.0 V) and will scale proportionally with respect to
the voltage reference. (See the Voltage Reference section.)
Analog
120 Ω
120 Ω
Pad
The drive requirements for the analog inputs are very mini-
mal, when compared to most other converters, due to the
SPT7862’s extremely low input capacitance of only 5 pF
and a high input resistance in excess of 29 kΩ.
Each analog input should be protected through a series
resistor and diode clamping circuit as shown in figure 5.
Figure 5 – Recommended Input Protection Circuit
CLOCK INPUT
+V
AVDD
Each ADC is driven independently from a single-ended
TTL-input clock. Because the pipelined architecture oper-
ates on the rising edge of the clock input, each ADC can
operate over a wide range of input clock duty cycles without
degrading the dynamic performance.
D1
D2
Buffer
ADC
47 Ω
DIGITAL OUTPUTS
The digital outputs (DA9–0 and DB9–0) are driven by sepa-
rate supplies (OVDDA and OVDDB) ranging from +3 V to
+5 V. This feature makes it possible to drive the SPT7862’s
TTL/CMOS-compatible outputs with the user’s logic system
supply. Each digital output supply may be driven indepen-
dently. The format of the output data (D0–D9) is straight
binary. (See Table III.) The outputs are latched on the rising
edge of CLK. The EN pin controls tri-stating of both data
output ports. These outputs can be switched into a tri-state
mode by bringing EN high.
–V
D1 = D2 = Hewlett Packard HP5712 or equivalent
CALIBRATION
The SPT7862 uses a user-transparent, auto-calibration
scheme to ensure 10-bit accuracy over time and tempera-
ture. Gain and offset errors are continually adjusted to 10-bit
accuracy during device operation.
Table III – Output Data Information
Upon power up, the SPT7862 begins its calibration algo-
rithm. In order to achieve the calibration accuracy required,
the offset and gain adjustment step size is a fraction of a 10-
bit LSB. Since the calibration algorithm is an oversampling
process, a minimum of 10,000 clock cycles are required.
This results in a minimum calibration time upon power up of
250 µsec (for a 40 MHz clock). Once calibrated, the
SPT7862 remains calibrated over time and temperature.
ANALOG INPUT
OVERRANGE
OUTPUT CODE
D9–D0
11 1111 1111
11 1111 111Ø
ØØ ØØØØ ØØØØ
00 0000 000Ø
00 0000 0000
D10
+F.S. + 1/2 LSB
+F.S. –1/2 LSB
+1/2 F.S.
1
0
0
0
0
+1/2 LSB
0.0 V
(Ø indicates the flickering bit between logic 0 and 1)
Since the calibration cycles are initiated on the rising edge
of the clock, the clock must be continuously applied for the
SPT7862 to remain in calibration.
EVALUATION BOARD
The EB7862 evaluation board is available to aid designers
in demonstrating the full performance of the SPT7862.
This board includes a reference circuit, clock driver circuit,
output data latches and an on-board reconstruction of the
digital data. An application note describing the operation of
this board as well as information on the testing of the
SPT7862 is also available. Contact the factory for price and
availability.
INPUT PROTECTION
All I/O pads are protected with an on-chip protection circuit
shown in figure 6. This circuit provides ESD robustness and
prevents latch-up under severe discharge conditions with-
out degrading analog transition times.
SPT7862
8
2/23/00
PACKAGE OUTLINE
64-Lead TQFP
G
INCHES
MILLIMETERS
A
B
SYMBOL
MIN
MAX
0.480
0.398
0.023
0.010
MIN
MAX
12.20
10.10
0.58
64
49
A
B
C
D
E
F
0.465
0.390
0.017
0.006
11.80
9.90
48
1
0.42
Index
0.15
0.26
0.295 typ
0.433 typ
0.055
7.5 typ
11 typ
1.40
0.000
0.067
0.005
E F
G
1.70
H
I
0.005
0.125
0-10°
0.30
0.132
0-10°
J
K
0.012
0.028
0.008
0.70
0.20
16
33
0.000
0.00
17
32
C
D
H
K
J
I
SPT7862
9
2/23/00
PIN ASSIGNMENTS
PIN FUNCTIONS
Pin Name Description
VINA
Analog Input (A)
VINB
Analog Input (B)
VINRA
Analog Input Return (A)
Analog Input Return (B)
VREF High Force Input A/B
VREF High Sense Input A/B
VREF Low Force Input A/B
VREF Low Sense Input A/B
Analog VDD
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VINRB
DB1
DB2
48
47
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8
DA9
AGND
1
2
3
VRHFA/B
VRHSA/B
VRLFA/B
VRLSA/B
AVDD
DB3
DB4
DB5
46
45
44
43
4
5
6
7
DB6
SPT7862
42
41
40
DB7
DB8
8
9
TOP VIEW
64L TQFP
DB9
AGND
39
10
DVDD
Digital VDD
AGND
38
37
36
35
34
11
12
AGND
OVDD A/B Digital Output Power Supply +3.3 V to +5.0 V
V
RHFA
AV
AV
DD
V
RHFB
13
DD
AGND
DGND
Analog Ground
Digital Ground
V
RHSA
14
15
16
N/C
V
RHSB
AGND
AGND
V
33
INRA
OGND A/B Digital Output Ground
17 18 19 20 21 22 23 24 25 26 27 28 29 30
31 32
CLK A/B
EN
Input Clock A/B (separate)
Enable Outputs (Active Low)
Data Outputs A (10 bits)
Data Outputs B (10 bits)
Data Available A/B
D0–9A
D0–9B
DAV A/B
VCAL
Decoupling Pin
ORDERING INFORMATION
PART NUMBER
TEMPERATURE RANGE
PACKAGE TYPE
SPT7862SIT
–40 to +85 °C
64-Lead TQFP
SPT7862
10
2/23/00
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