CPCI102BR_技术文档

CMCPCI102B

CompactPCI^®Backplane Interface

Product Description

Features

®

The CMCPCI102BT/BR is a 10-channel backplane

interface/termination IC specifically designed for Com-

•

CompactPCI standards compliant

Allows CompactPCI System Cards to be

used in any Slot

pactPCI

redundant

system-slot

cards.

The

CMCPCI102BT/BR allows CompactPCI boards to

interface to the backplane and provides the versatility

to use system cards in any slot (system or peripheral).

Per the CompactPCI specification, the CMCPCI102BT/

BR provides a 10Ω termination resistor for each chan-

nel to terminate the transmission line stub on the

board. An integral series switch and associated control

signal (SW_EN) permits connection/disconnection of

the channel, so that the device side of the circuit may

be isolated from the backplane side.

•

Provides termination for up to ten channels

Provides a series switch in each channel

Supports hot-swap capability

Very low capacitance load on each line

Industrial temperature range

28-pin TSSOP package

Lead-free version available

The CompactPCI standard requires system boards to

be hot-swappable. To accommodate this requirement,

the CMCPCI102BT/BR features a switched 10kΩresis-

tor connected to the 1V Precharge Supply Voltage. If

the precharge enable pin (P_EN) is asserted, then the

10kΩ pull-up resistors are connected to precharge the

circuits.

Applications

®

•

Redundant System CompactPCI cards

Hot-swap CompactPCI cards

Industrial PCs

Telecom/Datacom equipment

Instrumentation

Computer Telephony

Real-time machine control

In addition, a system board requirement mandates

either a 1.0kΩ pull-up resistor or a 2.7kΩ resistor con-

nected to VIO. CompactPCI slot cards must work in

either 3.3V or 5V systems, hence the need for both

2.7kΩ and 1kΩ resistors. If the 3_EN pin is logic high,

the 2.7kΩresistor is used as the pull-up. If the 5_EN pin

is logic high, the 1kΩ resistor is used.

The CMCPCI102BT/BR integrates all these functions in

a low-profile 28-pin TSSOP package and is available

with optional lead-free finishing.

Simplified Electrical Schematic

1V

VIO

3_EN

5_EN

For all Enable signals:

SW_EN

Logic 0 = switch open

Logic 1 = switch closed

SW_PU2

SW_PU3

SW_PU1

*One of 10 parallel

P_EN

channels is shown.

R_PU2

2.7k

R_PU3

1k

R_PU1

10k

Ω

SW_S

R_S

10

B1-B10*

A1-A10*

Ω

Backplane Side

CompactPCI Device Side

02/28/05 430 N. McCarthy Blvd., Milpitas, CA 95035-5112

●

Tel: 408.263.3214

●

Fax: 408.263.7846

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1

CMCPCI102B

PACKAGE / PINOUT DIAGRAM

Top View

1

2

3

4

28

27

26

B1

A1

A2

B2

A3

B3

A4

B4

25

24

23

22

21

20

19

18

17

16

15

A5

5

6

B5

1V

VIO

5_EN

3_EN

SW_EN

B6

P_EN

GND

CAP

A6

7

8

9

10

11

A7

B7

A8

12

13

14

B8

A9

B9

A10

B10

28-pin TSSOP

Note: This drawing is not to scale.

PIN DESCRIPTIONS

PIN(S)

1-5

NAME

A1 - A5

A6 - A10

B1 - B5

B6 - B10

1V

DESCRIPTION

The backplane-side input signals for channels 1 through 5, respectively.

The backplane-side input signals for channels 6 through 10, respectively.

The device-side connection for channels 1 through 5, respectively.

The device-side connection for channels 6 through 10, respectively.

10-14

24-28

15-19

6

A precharge supply voltage input for all channels. This voltage can be less than or equal to VIO.

7

P_EN

The precharge enable input which controls the precharge pull-up resistors. When this active high

control signal is set to ’1’, the precharge of all channels is enabled.

8

9

GND

CAP

The ground voltage reference for the CMCPCI102BT/BR.

A capacitor must be placed from this pin to GND. The recommended value is 0.01µF,16V.

20

SW_EN

The series switch enable input. When this active high control signal is set to ’1’, the series switch

between the channel’s backplane-side terminal and device-side terminal is closed. When this sig-

nal is cleared to ’0’, the switch is open.

21

22

23

3_EN

5_EN

VIO

The enable signal for the device-side channel pull-up mechanism when 3.3V is the supply volt-

age. When this active high control signal is set to ’1’, the 2.7kΩ pull-up resistor which pulls up the

channel to the supply rail is engaged. Otherwise, this pin should be set to ’0’.

The enable signal for the device-side channel pull-up mechanism when 5V is the supply voltage.

When this active high control signal is set to ’1’, the 1kΩpull-up resistor which pulls up the channel

to the supply rail is engaged. Otherwise, this pin should be set to ’0’.

The positive supply voltage for the CMCPCI102BT/BR. Either 3.3V or 5V may be used.

2

430 N. McCarthy Blvd., Milpitas, CA 95035-5112

●

Tel: 408.263.3214

●

Fax: 408.263.7846

●

www.calmicro.com

02/28/05

CMCPCI102B

Ordering Information

PART NUMBERING INFORMATION

Standard Finish

Lead-free Finish

Ordering Part

Number¹

Ordering Part

Number¹

Pins

Package

Part Marking

28

TSSOP

CMCPCI102BT

CPCI102B

CMCPCI102BR

CPCI102BR

Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.

Specifications

ABSOLUTE MAXIMUM RATINGS

PARAMETER

RATING

UNITS

VIO (supply voltage)

-0.5 to +6

V

Pin Voltages

1V, P_EN, 3_EN, 5_EN, SW_EN

A1-A10

B1-B10

-0.5 to (VIO+0.5)

V

ESD Withstand Voltage

Human Body Model, MIL-STD-883D, Method 3015 (Notes 1, 2)

+2000

-65 to +150

-40 to +85

62

V

°C

Storage Temperature Range

Operating Temperature Range (Ambient)

DC Power per Resistor

°C

mW

W

Package Power Rating

1

Note 1: ESD is applied to input / output pins with respect to GND, one at a time; unused pins are left open.

Note 2: This parameter guaranteed by design.

STANDARD OPERATING CONDITIONS

PARAMETER

RATING

UNITS

VIO (supply voltage)

3 to 5.5

V

Pin Voltages

P_EN, 3_EN, 5_EN, SW_EN, 1V

A1-A10

B1-B10

0 to VIO

V

Ambient Operating Temperature Range

-40 to +85

°C

02/28/05 430 N. McCarthy Blvd., Milpitas, CA 95035-5112

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3

CMCPCI102B

Specifications (Cont’d)

(NOTE 1)

ELECTRICAL OPERATING CHARACTERISTICS

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

R_S1

Series Resistance through R_S

A to B; switch SW_Sclosed;

T_A=25°C

5

10

15

Ω

R_S2

Series Resistance through R_S

Resistance of R_PU1pull-up

A to B; switch SW_Sopen;

T_A=25°C

1

MΩ

R_PU1

T_A=25°C

9.5

18

+5

kΩ

TOL_RPU2Resistance Tolerance

%

(R_PU2and R_PU3

)

TOL_RPU3

TCR_PU

Temperature Coefficient of

Resistance (R_PU1, R_PU2, R_PU3

-100

1.9

ppm/°C

pF

)

C₁

C₂

Capacitance on backplane side

(A side) of series resistor R_S

Measured @ 66MHz,

0VDC, SW_EN=0V; Note 2

Capacitance on device side (B

side) of series resistor R_Sand

series switch SW_S

Measured @ 66MHz,

0VDC, VIO=5V, 5_EN=5V

SW_EN=0V; Note 2

4.2

pF

V_IL

V_IH

Logic Low Input Voltage to P_EN,

3_EN, 5_EN, SW_EN

-0.5

[VIO] x 0.3

[VIO] + 0.5

+10

V

Logic High Input Voltage to P_EN,

3_EN, 5_EN, SW_EN

[VIO] x 0.7

I_LEAK

I_GND

t_PLH

Leakage Current into P_EN, 3_EN, GND < V < VIO

5_EN, SW_EN

+1

0.25

14

µA

mA

ms

Supply Current for internal circuits

(measured at GND pin)

1

Switch SW_Sclosure delay from the Note 2, ’CAP’ pin capaci-

tor=0.01µF

low-to-high transition of SW_EN

t_PHL

t_PPU

Switch SW_Sdelay from the high-to- Note 2, ’CAP’ pin capaci-

12

µs

tor=0.01µF

low transition of SW_EN

Propagation delay for pull-up

switches SW_PU1, SW_PU2, and

Note 2

10

ns

SW_PU3, all transitions

Note 1: Operating Characteristics are over Standard Operating Conditions unless otherwise specified.

Note 2: This parameter is guaranteed by design; it is not tested 100%.

4

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02/28/05

CMCPCI102B

Performance Information

CAP Pin Capacitance

Resistance Variation with Input Voltage

Some external capacitance is necessary to prevent the

voltage on the CAP pin from falling during sustained

data transfers through the device. This ensures that

the logic 1 level does not degrade.

The series resistance R varies with input voltage and

S

supply voltage, as shown in Figure 1.

Variation of 10R Resistor with I/O Voltage, T=25'C

The time required to open and close the series switch,

SWs, varies according to how much capacitance is

present on the CAP pin.

15

14

Vcc5.5

13

Vcc3.0

The minimum usable value is 200pF, placed close to

the pins. A 0.01uF, 16V capacitor is recommended.

See Figure 3 and Figure 4 for variation of switch on/off

times vs. capacitance.

12

11

10

9

8

Switch ON Time vs. CAP Capacitor Value

7

6

16

14

12

10

8

5

0

1

2

3

4

5

6

I/O Voltage [ V ]

Figure 1. Resistance Variation vs. Input Voltage

Resistance Variation with Temperature

The series resistance R also varies with temperature,

S

6

as shown in Figure 2.

4

Temperature Variation of 10R Resistor

2

15

14

0

2000

4000

6000

8000

10000

12000

Capacitor Value on CAP Pin [pF]

V_CC5V_IN

V_CC3V_IN

0

5

0

3

13

12

11

10

9

Figure 3. Switch ON Time vs. CAP Capacitor Value

Switch OFF Time vs. CAP Capacitor Value

14

12

10

8

7

6

5

-40

-20

0

20

40

60

80

100

6

Temperature [ ^oC ]

4

CONDITIONS:

Curve V 3V 0:

CC IN

V

= 3.0V

= 5.5V

channel voltage = 0.0V

channel voltage = 3.0V

channel voltage = 0.0V

channel voltage = 5.5V

2

IO

Curve V 3V 3:

V

CC IN

Curve V 5V 0:

CC IN

0

Curve V 5V 5:

CC IN

0

2000

4000

6000

8000

10000

12000

Capacitor Value on CAP Pin [pF]

Figure 2. Resistance Variation vs. Temperature

Figure 4. Switch OFF Time vs. CAP Capacitor Value

02/28/05 430 N. McCarthy Blvd., Milpitas, CA 95035-5112

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Tel: 408.263.3214

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5

CMCPCI102B

Performance Information (cont’d)

Capacitance Variation with Frequency

The A-side and B-side capacitances, C and C , will

shows a plot of input line A3 (pin 3), measured with

SW_EN=0V and VIO=5V.

1

2

vary with frequency. The backplane capacitance, C is

1,

very linear over a wide frequency range. Figure 5

Figure 5. C (Backplane-side) Capacitance Variation vs. Frequency

1

The CompactPCI device side of the CMCPCI102BT/

The increased capacitance at low frequencies is due to

the parasitic capacitance of the switches connected to

the pull-up resistors. At high frequencies, this parasitic

capacitance is decoupled by the pull-up resistors.

BR has a fairly low capacitance (C ) at 66MHz, but it is

2

higher at lower frequencies.

Figure 6 shows a plot of output line B3 (pin 26), mea-

sured at the worst-case (for capacitance) conditions of

SW_EN=0V, 5_EN=0V, 3_EN=0V and VIO=5V.

Figure 6. C (Device-side) Capacitance Variation vs. Frequency

2

6

430 N. McCarthy Blvd., Milpitas, CA 95035-5112

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Tel: 408.263.3214

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Fax: 408.263.7846

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02/28/05

CMCPCI102B

Application Information

Board Layout Recommendations

The CMCPCI102BT/BR devices should be located on

the board as close as possible to the CompactPCI con-

nector. Whether a signal is terminated or not depends

upon application, as shown in the following table:

SYSTEM SLOT

SIGNAL(S)

BOARDS

32-Bit

terminate

64-Bit

terminate

AD0-AD31

C/BE0#-C/BE3#

PAR

*

FRAME#

IRDY#

TRDY#

STOP#

LOCK#

DEVSEL#

PERR#

SERR#

RST#

REQ64#

ACK64#

INTA#, INTB#, INTC#, INTD# (if

used)

AD32-AD63

C/BE4#-C/BE7

PAR64

N/A

terminate

Figure 7 shows a 64-bit system board connection

between the CMCPCI102BT/BR termination and the

CompactPCI 5-row connector (2 mm pitch) labeled A

to E (row F is Ground). The System slot should have

signal lengths not exceeding 63.5 mm (2.5 inches). To

minimize trace length, it is recommended that the

CMCPCI102BT/BRs be placed on alternate sides of

the PC board. The configuration shown illustrates a

*

fully-terminated

64-bit

board

utilizing

10

CMCPCI102BT/BR devices. Some applications (e.g.

32-bit boards) do not require all lines to be terminated,

per the above table.

*

The CMCPCI102BT/BR resistors have a very low TCR

(typically -100ppm/°C) so that resistance will not fluctu-

ate over temperature. Buffers are implemented on

P_EN, 5_EN and 3_EN inputs to ensure that switches

turn on and off completely.

A typical system slot card may use 10 CMCPCI102BT/

BR devices to replace 10 10-bit FET bus switches and

76 4-resistor packs (0805 form factor), thus providing

significant reduction in both component count and

assembly costs. At the same time this highly integrated

solution improves reliability and manufacturing effi-

ciency, saves board area for space-critical designs,

and satisfies CompactPCI height requirements.

*

Placed on

bottom side

of PC board

Figure 7. Schematic for 64-bit System Board

02/28/05 430 N. McCarthy Blvd., Milpitas, CA 95035-5112

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7

CMCPCI102B

Mechanical Details

TSSOP Mechanical Specifications

Mechanical Package Diagrams

CMCPCI102BT/BR devices are supplied in 28-pin

TSSOP packages. Dimensions are shown below.

For complete information on the TSSOP-28 package,

see the California Micro Devices TSSOP Package

Information document.

TOP VIEW

D

28 27 26 25 24 23 22 21 20 19 18 17 16 15

PACKAGE DIMENSIONS

E

H

Package

Pins

TSSOP

28

Pin 1 Marking

Millimeters

Min Max

Inches

Max

Dimensions

1

2

3

4

5

6

7

8

9

10 11 12 13 14

Min

—

A

—

1.10

0.15

0.30

0.20

9.80

4.50

0.0433

0.006

A1

0.05

0.19

0.09

9.60

4.30

0.002

0.0075

0.0035

0.378

0.169

SIDE VIEW

B

0.0118

0.0079

0.386

C

A

A1

SEATING

PLANE

D

B

e

E

0.177

e

0.65 BSC

0.0256 BSC

H

L

6.25

0.50

6.50

0.70

0.246

0.020

0.256

0.028

END VIEW

C

# per tube

50 pieces*

1000 pieces

# per tape

and reel

L

Controlling dimension: millimeters

* This is an approximate number which may vary.

Package Dimensions for TSSOP-28

8

430 N. McCarthy Blvd., Milpitas, CA 95035-5112

●

Tel: 408.263.3214

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Fax: 408.263.7846

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www.calmicro.com

02/28/05


型号：	CPCI102BR
厂家：	CALIFORNIA MICRO DEVICES CORP
描述：	CompactPCI Backplane Interface 的CompactPCI背板接口 PC
文件：	总8页 (文件大小：222K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CPCI102BR [CALMIRCO]

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