CAT25C64PA-1.8-G [CATALYST]
EEPROM, 8KX8, Serial, CMOS, PDIP8, 0.300 INCH, PLASTIC, MS-001, DIP-8;
| 型号： | CAT25C64PA-1.8-G |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | EEPROM, 8KX8, Serial, CMOS, PDIP8, 0.300 INCH, PLASTIC, MS-001, DIP-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总16页 (文件大小：234K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT25C64
64K-Bit SPI Serial CMOS EEPROM
FEATURES
DESCRIPTION
I 10 MHz SPI compatible
I 1.8 to 5.5 volt operation
I Hardware and software protection
I Low power CMOS technology
I SPI modes (0,0 &1,1)
TheCAT25C64isa64K-BitSPISerialCMOSEEPROM
internally organized as 8Kx8 bits. Catalyst’s advanced
CMOS Technology substantially reduces device power
requirements. The CAT25C64 features a 64-byte page
write buffer. The device operates via the SPI bus serial
interface and is enabled though a Chip Select (CS). In
addition to the Chip Select, the clock input (SCK), data
in (SI) and data out (SO) are required to access the
device. The HOLD pin may be used to suspend any
serial communication without resetting the serial se-
quence. The CAT25C64 is designed with software and
hardware write protection features including Block write
protection. The device is available in 8-pin DIP and
SOIC packages.
I Commercial, industrial and automotive
temperature ranges
I 1,000,000 program/erase cycles
I 100 year data tetention
I Self-timed write cycle
I 8-pin DIP and SOIC
I 64-Byte page write buffer
I Block write protection
– Protect 1/4, 1/2 or all of EEPROM array
PIN CONFIGURATION
FUNCTIONAL SYMBOL
V
CC
PDIP (P, L)
SOIC (S, V)
CS
1
8
V
CC
SI
CS
SO
2
3
4
7
6
5
HOLD
SCK
SI
CAT25C64
WP
WP
SO
V
SS
HOLD
SCK
PIN FUNCTIONS
Pin Name
SO
Function
V
SS
Serial Data Output
Serial Clock
SCK
WP
Write Protect
VCC
+1.8V to +5.5V Power Supply
Ground
VSS
CS
Chip Select
SI
Serial Data Input
Suspends Serial Input
HOLD
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1112, Rev. B
1
CAT25C64
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
Voltage on any Pin with
Respect to VSS(1) .................. –2.0V to +VCC +2.0V
V
CC with Respect to VSS................................ –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Data Retention
Min.
1,000,000
100
Max.
Units
Cycles/Byte
Years
(3)
NEND
(3)
TDR
D.C. OPERATING CHARACTERISTICS
= +1.8V to +5.5V, unless otherwise specified.
V
CC
Limits
Typ.
Symbol
Parameter
Min.
Max.
Test Conditions
Units
ICC1
Power Supply Current
(Operating Write)
10
VCC = 5V @ 10MHz
SO = open; CS = Vss
mA
ICC2
Power Supply Current
(Operating Read)
2
1
VCC = 5.0V
mA
FCLK = 10MHz
(4)
ISB
Power Supply Current
(Standby)
CS = VCC
VIN = VSS or VCC
µA
µA
µA
ILI
Input Leakage Current
Output Leakage Current
2
3
ILO
VOUT = 0V to VCC
,
CS = 0V
(5)
VIL
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
-1
VCC x 0.3
VCC + 0.5
0.4
V
V
(5)
VIH
VCC x 0.7
2.7V ≤ V
< 5.5V
= 3.0mA
VOL1
VOH1
CC
V
V
V
V
I
I
OL
OH
VCC - 0.8
VCC-0.2
= -1.6mA
VOL2
VOH2
Output Low Voltage
Output High Voltage
0.2
1.8V ≤ V
< 2.7V
CC
= 150µA
I
I
OL
OH
= -100µA
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) These parameter are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Maximum standby current (ISB ) = 10µA for the Automotive and Extended Automotive temperature range.
(5) V min and V max are reference values only and are not tested.
IL
IH
Doc. No. 1112, Rev. B
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
2
CAT25C64
(1)
PIN CAPACITANCE
Applicable over recommended operating range from TA=25˚C, f=1.0 MHz, VCC=+5.0V (unless otherwise noted).
Symbol
COUT
CIN
Test Conditions
Max.
Conditions
VOUT=0V
VIN=0V
Units
pF
Output Capacitance (SO)
8
6
Input Capacitance (CS, SCK, SI, WP, HOLD)
pF
A.C. CHARACTERISTICS
CAT25C64-1.8
VCC
1.8V - 5.5V
Min. Max. Min. Max. Min. Max.
CAT25C64
=
VCC
=
VCC =
2.5V - 5.5V
4.5V - 5.5V
Test
SYMBOL PARAMETER
Conditions UNITS
tSU
tH
Data Setup Time
Data Hold Time
50
50
50
50
20
20
40
40
DC
ns
ns
tWH
tWL
fSCK
tLZ
SCK High Time
250
250
DC
125
125
DC
ns
SCK Low Time
ns
Clock Frequency
HOLD to Output Low Z
Input Rise Time
1
50
2
3
50
2
10
50
2
MHz
ns
(1)
tRI
µs
(1)
tFI
Input Fall Time
2
2
2
µs
tHD
tCD
HOLD Setup Time
HOLD Hold Time
Write Cycle Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD to Output High Z
CS High Time
100
100
100
100
40
40
ns
ns
(3)
CL = 50pF
(2)
tWC
tV
10
10
5
ms
ns
ns
ns
ns
ns
ns
ns
250
125
40
tHO
tDIS
tHZ
0
0
0
250
150
250
100
75
50
tCS
tCSS
tCSH
500
500
500
250
250
250
100
100
100
CS Setup Time
CS Hold Time
(4)(5)
Power-Up Timing
Symbol
tPUR
Parameter
Max.
Units
Power-up to Read Operation
Power-up to Write Operation
1
1
ms
ms
tPUW
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) AC Test Conditions:
Input Pulse Voltages: 0.3V to 0.7V
CC
CC
Input rise and fall times: ≤10ns
Input and output reference voltages: 0.5V
CC
Output load: current source IOL max/IOH max; C =50pF
L
(3)
(4) This parameter is tested initially and after a design or process change that affects the parameter.
(5) and t are the delays required from the time V is stable until the specified operation can be initiated.
t
is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
WC
t
PUR
PUW
CC
Doc. No. 1112, Rev. B
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
CAT25C64
FUNCTIONAL DESCRIPTION
PIN DESCRIPTION
The CAT25C64 supports the SPI bus data transmission
protocol. The synchronous Serial Peripheral Interface
(SPI) helps the CAT25C64 to interface directly with
manyoftoday’spopularmicrocontrollers.TheCAT25C64
contains an 8-bit instruction register. (The instruction
set andtheoperationcodesaredetailedintheinstruction
set table)
SI: Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses, and data to be written to the
25C64. Input data is latched on the rising edge of the
serial clock.
SO: Serial Output
SO is the serial data output pin. This pin is used to
transfer data out of the 25C64. During a read cycle, data
is shifted out on the falling edge of the serial clock.
After the device is selected with CS going low, the first
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK.
Thefirstbytecontainsoneofthesixop-codesthatdefine
the operation to be performed.
SCK: Serial Clock
SCKistheserialclockpin.Thispinisusedtosynchronize
Figure 1. Sychronous Data Timing
t
CS
VIH
CS
VIL
t
t
CSS
CSH
VIH
t
t
WL
SCK
SI
WH
t
VIL
VIH
t
H
SU
VALID IN
V
IL
t
RI
FI
t
t
V
t
t
HO
DIS
VOH
VOL
HI-Z
HI-Z
SO
Note: Dashed Line= mode (1, 1) — — — —
INSTRUCTION SET
Instruction
WREN
WRDI
Opcode
0000 0110
Operation
Enable Write Operations
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
RDSR
WRSR
READ
WRITE
Doc. No. 1112, Rev. B
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
4
CAT25C64
the communication between the microcontroller and the
25C64. Opcodes, byte addresses, or data present on
theSIpinarelatchedontherisingedgeoftheSCK. Data
on the SO pin is updated on the falling edge of the SCK.
will interrupt a write to the status register. If the internal
write cycle has already been initiated, WP going low will
have no effect on any write operation to the status
register.TheWPpinfunctionisblockedwhentheWPEN
bit is set to 0.
CS: Chip Select
CSistheChipselectpin.CSlowenablestheCAT25C64
and CS high disables the CAT25C64. CS high takes the
SO output pin to high impedance and forces the devices
into a Standby Mode (unless an internal write operation
is underway). The CAT25C64 draws ZERO current in
the Standby mode. A high to low transition on CS is
required prior to any sequence being initiated. A low to
hightransitiononCS afteravalidwritesequenceiswhat
initiates an internal write cycle.
HOLD: Hold
The HOLD pin is used to pause transmission to the
CAT25C64 while in the middle of a serial sequence
without having to re-transmit entire sequence at a later
time. To pause, HOLD must be brought low while SCK
islow.TheSOpinisinahighimpedancestateduringthe
timethepartispaused, andtransitionsontheSIpinswill
beignored.Toresumecommunication,HOLDisbrought
high, while SCK is low. (HOLD should be held high any
time this function is not being used.) HOLD may be tied
high directly to Vcc or tied to Vcc through a resistor.
Figure 9 illustrates hold timing sequence.
WP: Write Protect
WP is the Write Protect pin. The Write Protect pin will
allow normal read/write operations when held high.
When WP is tied low and the WPEN bit in the status
register is set to “1”, all write operations to the status
register are inhibited. WP going low while CS is still low
STATUS REGISTER
7
6
5
4
3
2
1
0
WPEN
X
X
X
BP1
BP0
WEL
RDY
BLOCK PROTECTION BITS
Status Register Bits
Array Address
Protected
Protection
BP1
BP0
0
0
1
1
0
1
0
1
None
No Protection
1800-1FFF
1000-1FFF
0000-1FFF
Quarter Array Protection
Half Array Protection
Full Array Protection
WRITE PROTECT ENABLE OPERATION
Protected
Blocks
Unprotected
Blocks
Status
WPEN
WP
X
WEL
Register
0
0
1
1
X
X
0
1
0
1
0
1
Protected
Protected
Protected
Protected
Protected
Protected
Protected
Writable
Protected
Writable
Protected
Writable
Protected
Writable
X
Low
Low
High
High
Protected
Protected
Protected
Writable
Doc. No. 1112, Rev. B
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
CAT25C64
The WPEN (Write Protect Enable) is an enable bit for the
WP pin. The WP pin and WPEN bit in the status register
controltheprogrammablehardwarewriteprotectfeature.
HardwarewriteprotectionisenabledwhenWPis lowand
WPENbitissettohigh.Theusercannotwritetothestatus
register (including the block protect bits and the WPEN
bit) and the block protected sections in the memory array
when the chip is hardware write protected. Only the
sections of the memory array that are not block protected
can be written. Hardware write protection is disabled
when either WP pin is high or the WPEN bit is zero.
STATUS REGISTER
The Status Register indicates the status of the device.
The RDY (Ready) bit indicates whether the CAT25C64
is busy with a write operation. When set to 1 a write
cycle is in progress and when set to 0 the device
indicates it is ready. This bit is read only.
The WEL (Write Enable) bit indicates the status of the
write enable latch . When set to 1, the device is in a
Write Enable state and when set to 0 the device is in a
Write Disable state. The WEL bit can only be set by the
WREN instruction and can be reset by the WRDI
instruction.
DEVICE OPERATION
Write Enable and Disable
The BP0 and BP1 (Block Protect) bits indicate which
blocksarecurrentlyprotected. Thesebitsaresetbythe
user issuing the WRSR instruction. The user is allowed
to protect quarter of the memory, half of the memory or
theentirememorybysettingthesebits. Onceprotected
the user may only read from the protected portion of the
array. These bits are non-volatile.
The CAT25C64 contains a write enable latch. This latch
must be set before any write operation. The device
powers up in a write disable state when Vcc is applied.
WREN instruction will enable writes (set the latch) to
thedevice. WRDI instruction will disable writes (reset the
latch) to the device. Disabling writes will protect the
device against inadvertent writes.
Figure 2. WREN Instruction Timing
CS
SCK
1
1
0
SI
0
0
0
0
0
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) — — — —
Figure 3. WRDI Instruction Timing
CS
SCK
SI
1
0
0
0
0
0
0
0
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) — — — —
Doc. No. 1112, Rev. B
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
6
CAT25C64
READ Sequence
To read the status register, RDSR instruction should be
sent. The contents of the status register are shifted out on
the SO line. The status register may be read at any time
even during a write cycle. Read sequece is illustrated in
Figure 4. Reading status register is illustrated in Figure 5.
The part is selected by pulling CS low. The 8-bit read
instructionistransmittedtotheCAT25C64, followedby
the 16-bit address(the three Most Significant Bits are
don’t care.
After the correct read instruction and address are sent,
the data stored in the memory at the selected address
is shifted out on the SO pin. The data stored in the
memory at the next address can be read sequentially
by continuing to provide clock pulses. The internal
address pointer is automatically incremented to the
next higher address after each byte of data is shifted
out. When the highest address (1FFFh) is reached, the
address counter rolls over to 0000h allowing the read
cycle to be continued indefinitely. The readoperation is
terminated by pulling the CS high.
WRITE Sequence
The CAT25C64 powers up in a Write Disable state. Prior to
any write instructions, the WREN instruction must be sent
to CAT25C64. The device goes into Write enable state by
pulling the CS low and then clocking the WREN instruction
into CAT25C64. The CS must be brought high after the
WREN instruction to enable writes to the device. If the write
operation is initiated immediately after the WREN instruc-
tion without CS being brought high, the data will not be
written to thearray because the write enable latch will not
have been properly set. Also, for a successful write opera-
tion the address of the memory location(s) to be pro-
grammed must be outside the protected address field
Figure 4. Read Instruction Timing
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30
SCK
OPCODE
BYTE ADDRESS*
SI
0
0
0
0
0
0
1
1
DATA OUT
HIGH IMPEDANCE
SO
7
6
5
4
3
2
1
0
MSB
*Please check the instruction set table for address
Note: Dashed Line= mode (1, 1) — — — —
Figure 5. RDSR Instruction Timing
CS
0
1
2
3
4
5
1
6
0
7
1
8
9
10
11
12
13
14
SCK
OPCODE
0
0
0
0
0
SI
DATA OUT
HIGH IMPEDANCE
SO
5
7
6
4
3
2
1
0
MSB
Note: Dashed Line= mode (1, 1) — — — —
Doc. No. 1112, Rev. B
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
7
CAT25C64
location selected by the block protection level.
to64bytesof datatotheCAT25C64.Aftereachbyteofdata
is received, six lower order address bits are internally
incremented by one; the high order bits of address will
remain constant. The only restriction is that the 64 bytes
must reside on the same page. If the address counter
reaches the end of the page and clock continues, the
counter will “roll over” to the first address of the page and
overwrite any data that may have been written. The
CAT25C64 is automatically returned to the write disable
state at the completion of the write cycle. Figure 8 illustrates
the page write sequence.
Byte Write
Once the device is in a Write Enable state, the user
may proceed with a write sequence by setting the CS
low, issuing a write instruction via the SI line, followed
by the 16-bit address (the three Most Significant Bits
are don’t care), and then the data to be written.
Programming will start after the CS is brought high.
Figure 6 illustrates byte write sequence.
During an internal write cycle, all commands will be
ignored except the RDSR (Read Status Register)
instruction.
To write to the status register, the WRSR instruction should
be sent. Only Bit 2, Bit 3 and Bit 7 of the status register can
be written using the WRSR instruction. Figure 7 illustrates
the sequence of writing to status register.
The Status Register can be read to determine if the
write cycle is still in progress. If Bit 0 of the Status
Register is set at 1, write cycle is in progress. If Bit 0
is set at 0, the device is ready for the next instruction.
DESIGN CONSIDERATIONS
The CAT25C64 powers up in a write disable state and in a
low power standby mode. A WREN instruction must be
issued to perform any writes to the device after power up.
Also,onpowerupCSshouldbebroughtlowtoenteraready
Page Write
The CAT25C64 features page write capability. After
the first initial byte the host may continue to write up
Figure 6. Write Instruction Timing
CS
0
1
2
3
4
5
6
7
8
21 22 23 24 25 26 27 28 29 30 31
SCK
SI
OPCODE
DATA IN
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
1
0
ADDRESS
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) – – – –
Figure 7. WRSR Instruction Timing
CS
0
1
2
3
4
5
6
7
1
8
9
6
10
5
11
4
12
13
2
14
1
15
0
SCK
OPCODE
DATA IN
SI
0
0
0
0
0
0
0
7
3
MSB
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) — — — —
Doc. No. 1112, Rev. B
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
8
CAT25C64
state and receive an instruction. After a successful byte/ SO is in a high impedance.
page write or status register write the CAT25C64 goes into
When powering down, the supply should be taken down
to 0V, so that the CAT25C64 will be reset when power
is ramped back up. If this is not possible, then, following
a brown-out episode, the CAT25C64 can be reset by
refreshing the contents of the Status Register (See
Application Note AN10).
a write disable mode. CS must be set high after the proper
number of clock cycles to start an internal write cycle.
Access to the array during an internal write cycle is
ignored and program-ming is continued. On power up,
Figure 8. Page Write Instruction Timing
CS
24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1
0
1
2
3
4
5
6
7
8
21 22 23
32-39
24-31
SCK
DATA IN
Data Data
OPCODE
Data
Byte 1
Data Byte N
SI
0
0
0
0
0
0
1
0
ADDRESS
0
Byte 2 Byte 3
7..1
HIGH IMPEDANCE
SO
Note: Dashed Line = mode (1, 1) – – – –
Figure 9. HOLD Timing
CS
t
t
CD
CD
SCK
t
HD
t
HD
HOLD
SO
t
HZ
HIGH IMPEDANCE
t
LZ
Note: Dashed Line= mode (1, 1) — — — —
Figure 10. WP Timing
t
t
WPH
WPS
CS
SCK
WP
t
CSH
WP
Note: Dashed Line= mode (1, 1) — — — —
Doc. No. 1112, Rev. B
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
9
CAT25C64
PACKAGE INFORMATION
8-LEAD 300 MIL WIDE PLASTIC DIP (P, L)
E1
E
D
A2
A
L
A1
e
eB
b2
b
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
0.120
0.015
0.115
0.014
0.045
0.355
0.300
0.300
0.240
0.210
0.130
0.018
0.060
0.365
0.195
0.022
0.070
0.400
0.325
0.325
0.280
b2
D
D2
E
0.310
0.250
E1
e
0.100 BSC
eB
L
0.430
0.150
0.115
0.130
Notes:
1. Complies with JEDEC Standard MS001.
2. All dimensions are in inches.
3. Dimensioning and tolerancing per ANSI Y14.5M-1982
Doc. No. 1112, Rev. B
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
10
CAT25C64
8-LEAD 150 MIL WIDE SOIC (S, V)
E1
E
D
C
A
θ1
e
A1
L
b
SYMBOL
MIN
NOM
MAX
A1
A2
b
0.0040
0.0532
0.013
0.0098
0.0688
0.020
C
0.0075
0.1890
02284
0.149
0.0098
0.1968
0.2440
0.1574
D
E
E1
e
0.050 BSC
f
0.0099
0.0196
θ1
0°
8°
Notes:
1. Complies with JEDEC specification MS-012 dimensions.
2. All linear dimensions in millimeters.
Doc. No. 1112, Rev. B
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
11
CAT25C64
TAPE AND REEL
Direction of Feed
Device Orientation
SPROKET HOLE
TOP COVER
TAPE THICKNESS (t1)
0.10mm (0.004) MAX THICK
DEVICE ORIENTATION
EMBOSSED
CARRIER
PIN 1
PIN 1
PIN 1
EMBOSSMENT
TDFN
SOIC
TSSOP
Reel Dimensions(1)
T
40mm (1.575) MIN.
ACCESS HOLE
AT SLOT LOCATION
B*
A
D*
C
N
FULL RADIUS*
TAPE SLOT IN CORE
FOR TAPE START.
2.5mm (0.098) MIN WIDTH
10mm (0.394) MIN DEPTH
* DRIVE SPOKES OPTIONAL, IF USED
ASTERISKED DIMENSIONS APPLY.
G (MEASURED AT HUB)
Embossed Carrier Dimensions
A
TAPE
SIZE
MAX
QTY/REEL
B MIN
C
D* MIN N MIN
20.2 50
G
T MAX
330
(13.00)
1.5
(0.059)
12.80 (0.504)
12.4 (0.488) _18.4_
12MM
3000
13.20 (0.5200) (0.795) (1.969) 14.4 (0.558) (0.724)
Component/Tape Size Cross-Reference
Component
Package Type
S, V
Tape Size (W)
Part Pitch (P)
8L SOIC
12mm
8mm
Notes:
(1) Metric dimensions will govern; English measurements rounded, for reference only and in parentheses.
Doc. No. 1112, Rev. B
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
12
CAT25C64
Embossed Carrier Dimensions (12 Pape Only)
10 PITCHES
CUMULATIVE TOLERANCE
ON TAPE 0.2mm( 0.008)
K
D
P
0
T
P
2
TOP
COVER
TAPE
E
(2)
A
0
F
W
(2)
B
B
0
K
1
0
P
CENTER LINES
OF CAVITY
D
1
FOR COMPONENTS
2.0mm X 1.2mm
AND LARGER
EMBOSSMENT
FOR MACHINE REFERENCE ONLY
INCLUDING DRAFT AND RADII
USER DIRECTION OF FEED
CONCENTRIC ABOUT B
0
Embossed Tape—Constant Dimensions(1)
Tape Sizes
D
E
P0
T Max.
D1 Min.
A0 B0 K0(2)
1.5 (0.059)
1.6 (0.063)
1.65 (0.065)
1.85 (0.073)
3.9 (0.153)
4.1 (0.161)
400
(0.016)
1.5
(0.059)
12mm
Embossed Tape—Variable Dimensions(1)
Tape Sizes
B1 Max.
F
K Max.
P2
R Min.
W
P
8.2
5.45 (0.0215)
4.5
(0.177)
1.95 (0.077)
2.05 (0.081)
30
(1.181)
11.7 (0.460) 7.9 (0.275)
12.3 (0.484) 8.1 (0.355)
12mm
(0.0323) 5.55 (0.0219)
Note:
(1) Metric dimensions will govern; English measurements rounded, for reference only and in parentheses.
(2) A B K are determined by component size. The clearance between the component and the cavity must be within 0.05 (0.002) min. to
0
0
0
0.65 (0.026) max. for 12mm tape, 0.05 (0.002) min. to 0.90 (0.035) max. for 16mm tape, and 0.05 (0.002) min. to 1.00 (0.039) max. for
24mm tape and larger. The component cannot rotate more than 20° within the determined cavity, see Component Rotation.
Doc. No. 1112, Rev. B
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
13
CAT25C64
ORDERING INFORMATION
Prefix
Device #
25C64
Suffix
-1.8
S
CAT
– GT3
I
Product
Number
Temperature Range
Optional
Company ID
Blank = Commercial (0°C to +70°C)
I = Industrial (-40°C to +85°C)
A = Automotive (-40°C to +105°C)
E = Extended (-40°C to +125°C)
Operating Voltage
Blank = 2.5 to 5.5V
1.8 = 1.8 to 5.5V
Package
P: PDIP
S: SOIC
L: PDIP (Lead-free, Halogen-free)
V: SOIC, JEDEC (Lead-free, Halogen-free)
Lead Finish/Tape & Reel
G: NiPdAu Lead Plating
T: Tape & Reel
3: 3000/Reel
Notes:
(1) The device used in the above example is a 25C64SI-1.8GT3 (SOIC, Industrial Temperature, 1.8 Volt to 5.5 Volt Operating Voltage,
Tape & Reel)
Doc. No. 1112, Rev. B
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
14
CAT25C64
PACKAGE MARKING
8-Lead PDIP
8-Lead SOIC
VV
25C64LI
YYWWC
VV
25C64VI
YYWWC
CSI = Catalyst Semiconductor, Inc.
VV = Voltage Range
CSI = Catalyst Semiconductor, Inc.
VV = Voltage Range
1.8V - 5.5V = 18
1.8V - 5.5V = 18
2.5V - 5.5V = Blank
2.5V - 5.5V = Blank
25C64L = Device Code
I = Temperature Range
YY = Production Year
WW = Production Week
C = Product Revision
25C64V = Device Code
I = Temperature Range
YY = Production Year
WW = Production Week
C = Product Revision
Doc. No. 1112, Rev. B
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
15
REVISION HISTORY
Date
Rev.
Reason
12/22/2005
A
Initial Issue
03/21/06
B
Update D.C. Operating Characteristics
Update A.C. Characteristics
Update Pin Description
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Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
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Publication #: 1112
Revison:
B
Issue date:
03/21/06
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