CH7312A-DEF-TR [CHRONTEL]
Consumer Circuit, CMOS, PQFP48, 7 X 7 MM, LEAD FREE, MS-026D, LQFP-48;
| 型号： | CH7312A-DEF-TR |
| 厂家： | 
CHRONTEL, INC |
| 描述： | Consumer Circuit, CMOS, PQFP48, 7 X 7 MM, LEAD FREE, MS-026D, LQFP-48 商用集成电路 |
| 文件： | 总20页 (文件大小：167K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CH7312A
Chrontel
CH7312A DVI HDCP Transmitter
Features
General Description
•
Digital Visual Interface (DVI) Transmitter up to
165M pixels/second
The CH7312A is a Display Controller device, which accepts a
digital graphics input signal, encodes and transmits data
•
High-bandwidth Digital Content Protection (HDCP) through a DVI link (DFP can also be supported) with optional
support
DVI low jitter PLL
HDCP support. The device accepts one channel of RGB data
over three pairs of serial data ports.
•
•
•
DVI hot plug detection
High-speed SDVO◊ (1G~2Gbps) AC-coupled serial
differential RGB inputs
The DVI processor includes a low jitter PLL for
generation of the high frequency serialized clock, and all
circuitry required to encode, serialize and transmit the
data. The CH7312A is able to drive a DFP display at a
pixel rate of up to 165MHz, supporting UXGA
(1600x1200) resolution displays.
•
•
•
•
•
•
Programmable power management
Fully programmable through serial port
Configuration through Intel® Opcodes◊
Complete Windows and DOS driver support
Offered in a 48-pin LQFP package
Boundary scan support
The CH7312A has the ability to become a HDCP rev1.1
Down-stream compliant DVI transmitter by using an
external HDCP key containing the proper device keys
which can be obtained from Chrontel, Inc.
CH7312A is pin to pin compatible with CH7307C DVI
transmitter.
◊ Intel® Proprietary.
SDVO _R(+,-)
SDVO _G(+,-)
SDVO _B(+,-)
10bit-8bit
decoder
Data Latch ,
Serial to Parallel
Interrept
Generation
3
0
6
SDVO_INT(+/-)
2
H,V,DE
HPDET
SDVO _Clk(+,-)
Clock Driver
Test Block
2
HDCP
Encrypter
PROM 2
PROM 1
TLC, TLC*
2
DVI PLL
TDC0, TDC0*
TDC1, TDC1*
TDC2, TDC2*
2
2
2
DVI
Encoder
DVI
DVI
FIFO
BSCAN
T1
Serializer Driver
VSWING
Reset & Control
RESET *
SC_PROM
SD_PROM
SC_DDC
SD_DDC
AS
SPC
SPD
Serial Port
Control
Figure 1: Functional Block Diagram
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CHRONTEL
CH7312A
Table of Contents
1.0 Pin-Out ____________________________________________________________________ 4
1.1
1.2
Package Diagram ___________________________________________________________________4
Pin Description _____________________________________________________________________5
2.0 Functional Description________________________________________________________ 7
2.1
2.2
2.3
2.4
2.5
Input Interface______________________________________________________________________7
DVI Transmitter ____________________________________________________________________8
HDCP Compatibility ________________________________________________________________8
Command Interface _________________________________________________________________9
Boundary scan Test_________________________________________________________________10
3.0 Register Control ____________________________________________________________ 12
4.0 Electrical Specifications______________________________________________________ 13
4.1
4.2
4.3
4.4
4.5
Absolute Maximum Ratings __________________________________________________________13
Recommended Operating Conditions___________________________________________________13
Electrical Characteristics ____________________________________________________________13
DC Specifications__________________________________________________________________14
AC Specifications__________________________________________________________________16
5.0 Package Dimensions_________________________________________________________ 18
6.0 Revision History ____________________________________________________________ 19
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CH7312A
Figures and Tables
List of Figures
Figure 1: Functional Block Diagram .............................................................................................................................1
Figure 2: 48-Pin LQFP Pin Out.....................................................................................................................................4
Figure 3: Possible Connection Diagram for HDCP.......................................................................................................9
Figure 4: Control Bus Switch ........................................................................................................................................9
Figure 5: NAND Tree Connection...............................................................................................................................10
Figure 6: 48 Pin LQFP Package ..................................................................................................................................18
List of Tables
Table 1: Pin Description................................................................................................................................................5
Table 2: CH7312A supported Pixel Rates, Clock Rates, Data Transfer Rates and Fill Patterns...................................7
Table 3: DVI Output Formats........................................................................................................................................8
Table 4: Popular Panel Sizes .........................................................................................................................................8
Table 5: Signal Order in the NAND Tree Testing.......................................................................................................11
Table 6: Signals not Tested in NAND Test .................................................................................................................11
Table 7: Revisions .......................................................................................................................................................19
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CHRONTEL
CH7312A
1.0 PIN-OUT
1.1 Package Diagram
AVDD_PLL
36
35
34
33
32
AVDD
T1
1
RESET*
2
BSCAN
AS
3
SPC
SDVO_INT-
SDVO_INT+
4
SPD
5
CHRONTEL
CH7312
AGND_PLL
DGND
6
7
31 AGND
DGND
30
29
SD_PROM
SC_PROM
SD_DDC
SC_DDC
DVDD
8
HPDET
9
28 DVDD
PROM2
PROM1
VSWING
10
11
12
27
26
25
Figure 2: 48-Pin LQFP Pin Out
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CH7312A
1.2 Pin Description
Table 1: Pin Description
Pin #
Type
Symbol
RESET*
Description
Reset* Input (Internal pull-up)
When this pin is low, the device is held in the power-on reset condition. When
this pin is high, reset is controlled through the serial port register.
Address Select (Internal pull-up)
This pin determines the serial port address of the device (0,1,1,1,0,0,AS*,0).
When AS is low the address is 72h, when high the address is 70h.
2
3
4
In
In
In
AS
SPC
Serial Port Clock Input
This pin functions as the clock input of the serial port and operates with inputs
from 0 to 2.5V. This pin requires an external 4kΩ - 9kΩ pull up resistor to
2.5V.
5
In/Out
In/Out
Out
SPD
Serial Port Data Input / Output
This pin functions as the bi-directional data pin of the serial port and operates
with inputs from 0 to 2.5V. Outputs are driven from 0 to 2.5V. This pin
requires an external 4kΩ - 9 kΩ pull up resistor to 2.5V.
8
SD_PROM
SC_PROM
SD_DDC
SC_DDC
TLC*, TLC
Routed Data to PROM
This pin functions as the bi-directional data pin of the serial port for PROM on
ADD2 card. This pin will require a pull-up resistor to the desired high state
voltage. Leave open if unused.
9
Routed Clock Output to PROM
This pin functions as the clock bus of the serial port to PROM on ADD2 card.
This pin will require a pull-up resistor to the desired high state voltage. Leave
open if unused.
10
11
In/Out
In/Out
Out
Routed Serial Port Data to DDC
This pin functions as the bi-directional data pin of the serial port to DDC
receiver. This pin will require a pull-up resistor to the desired high state
voltage. Leave open if unused.
Routed Serial Port Clock Output to DDC
This pin functions as the clock bus of the serial port to DDC receiver. This pin
will require a pull-up resistor to the desired high state voltage. Leave open if
unused.
13, 14
DVI Clock Outputs
These pins provide the differential clock output for the DVI interface
corresponding to data on the TDC[2:0] outputs.
16,17
19, 20
22, 23
25
Out
Out
Out
In
TDC0*, TDC0
TDC1*, TDC1
TDC2*, TDC2
VSWING
DVI Data Channel 0 Outputs
These pins provide the DVI differential outputs for data channel 0 (blue).
DVI Data Channel 1 Outputs
These pins provide the DVI differential outputs for data channel 1 (green).
DVI Data Channel 2 Outputs
These pins provide the DVI differential outputs for data channel 2 (red).
DVI Swing Control
This pin sets the swing level of the DVI outputs. A 1.2K ohm resistor should
be connected between this pin and TGND using short and wide traces.
26
In / Out PROM1
PROM Interface 1
This pin functions as an interface to the external EEPROM. Contact Chrontel
Applications for detailed instructions.
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CH7312A
Table 1: Pin Description (contd.)
Pin #
Type
Out
Symbol
PROM2
Description
27
29
PROM Interface 2
This pin functions as an interface to the external EEPROM. Contact Chrontel
Applications for detailed instructions.
Hot Plug Detect (internal pull-down)
This input pin determines whether the DVI output driver is connected to a DVI
monitor. When terminated, the monitor is required to apply a voltage greater
than 2.4 volts. Changes on the status of this pin will be relayed to the graphics
controller via the SDVO_INT+/- pins, where toggling between 100MHz and
200MHz is considered an assertion (‘1’ value), not toggling at all is considered
a de-assertion (‘0’ value).
In
HPDET
Interrupt Output Pair associated with SDVO Data Channel
This pair is used as a hot plug attach/detach notification to VGA controller of a
monitor driven by data SDVO_R+/-, SDVO_G+/-, SDVO_B+/-.
Toggling between 100MHz and 200MHz on this pair is considered an assertion
(‘1’ value); not toggling at all is considered a de-assertion (‘0’ value).
32, 33
Out
SDVO_INT+/-
34
35
In
In
BSCAN
T1
BSCAN (internal pull low)
This pin must be left open (not connected) in the application. This pin enables
the boundary scan for in-circuit testing. See section 2.5 for details. Voltage
level is 0 to DVDD.
Test Pin (internal pull-down)
This pin must be left open (not connected) in the application.
37, 38, 40, In
41, 43, 44
SDVO_R+/-,
SDVO_G+/-,
SDVO_B+/-
SDVO Data Channel Inputs
These pins accept 3 AC-coupled differential pair of inputs from a digital video
port of a graphics controller. These 3 pairs of inputs are R, G, B. The
differential p-p input voltage has a max. value of 1.2V, with a min. value of
175mV.
Differential Clock Input associated with SDVO Data channel
The range of this clock pair is 100~200MHz. For specified pixel rates in
specified modes this clock pair will run at an integer multiple of the pixel rate.
Refer to section 2.1.3 for details. The differential p-p input voltage has a max.
value of 1.2V, with a min. value of 175mV.
46, 47
In
SDVO_CLK+/-
12,28
7,30
15, 21
18, 24
36, 42, 48 Power
31, 39, 45 Power
Power
Power
Power
Power
DVDD
DGND
TVDD
TGND
AVDD
AGND
Digital Supply Voltage (2.5V)
Digital Ground
DVI Transmitter Supply Voltage (3.3V)
DVI Transmitter Ground
Analog Supply Voltage (2.5V)
Analog Ground
1
6
Power
Power
AVDD_PLL
AGND_PLL
DVI PLL Supply Voltage (3.3V)
DVI PLL Ground
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CHRONTEL
CH7312A
2.0 FUNCTIONAL DESCRIPTION
2.1 Input Interface
2.1.1 Overview
One pair of differential clock signal and three differential pairs of data signals (R/G/B) form one channel data. The
input data are 10-bit serialized data. Input data run at 1Gbits/s~2Gbits/s, being a 10x multiple of the clock rate
(SDVO_CLK+/-). The CH7312A de-serializes the input into 10-bit parallel data with synchronization and alignment.
Then the 10-bit characters are mapped into 8-bit color data or control data (Hsync, Vsync, DE).
2.1.2 Interface Voltage Levels
All differential SDVO pairs are AC coupled differential signals. Therefore, there is not a specified DC signal level
for the signals to operate at. The differential p-p input voltage has a min of 175mV, and a max of 1.2V. The
differential p-p output voltage has a min of 0.8V, with a max of 1.2V.
2.1.3 Input Clock and Data Timing
A data character is transmitted least significant bit first. The beginning of a character is noted by the falling edge of
the SDVO_CLK+ edge. The skew among input lanes is required to be no larger than 2ns.
The clock rate runs at 100MHz~200MHz. The pixel rate can be 25MP/s~165MP/s. The pixel rate and the clock rate
do not always equal. The clock rate can be a multiple of the pixel rate (1x, 2x or 4x depending on the pixel rate) so
that the clock rate will be stay in the 100MHz~200MHz range. In the condition that the clock rate is running at a
multiple of the pixel rate, there isn’t enough pixel data to fill the data channels. Dummy fill characters
(‘0001111010’) are used to stuff the data stream. The CH7312A supports the following clock rate multipliers and
fill patterns shown in Table 2.
Table 2: CH7312A supported Pixel Rates, Clock Rates, Data Transfer Rates and Fill Patterns
Pixel Rate
25~50 MP/s
50~100 MP/s
Clock Rate – Multiplier
100~200 MHz – 4xPixel Rate
100~200 MHz – 2xPixel Rate
Stuffing Format
Data, Fill, Fill, Fill
Data, Fill
Data Transfer Rate - Multiplier
1.00~2.00Gbits/s – 10xClock Rate
1.00~2.00Gbits/s – 10xClock Rate
1.00~2.00Gbits/s – 10xClock Rate
100~200 MP/s 100~200 MHz – 1xPixel Rate
Data
2.1.4 Synchronization
Synchronization and channel-to-channel de-skewing is facilitated by the transmission of special characters during
the blank period. The CH7312A synchronizes during the initialization period and subsequently uses the blank
periods to re-synch to the data stream.
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CHRONTEL
CH7312A
2.2 DVI Transmitter
Serialized input data, sync and clock signals are input to the CH7312A from the graphics controller’s digital output
port. Input is through three differential data pairs and one differential clock pair. The data rate is in the range of
1.0~2.0Gbits/s. The clock rate, independent with pixel rate, is 1/10 of the data rate, resulting in the range of
100M~200MHz. Horizontal sync and vertical sync information are embedded in the data stream. Some examples of
modes supported are shown in the Table 3. For Table 3, input pixel frequencies for given modes were taken from
VESA DISPLAY MONITOR TIMING SPECIFICATIONS if they were detailed there, not VESA TIMING
DEFINITION FOR FLAT PANEL MONITORS. The device is not dependent upon this set of timing specifications.
Any values of input pixels/line, lines/frame and clock rate are acceptable, as long as the pixel rate remains below
165MHz.
Table 3: DVI Output Formats
Graphics
Resolution
Active Aspect
Ratio
Pixel Aspect
Ratio
Refresh Rate
(Hz)
Input pixel
Frequency
(MHz)
<35.5
<31.5
<36
DVI
Frequency
(Mbits/Sec)
<355
720x400
640x400
640x480
800x600
1024x768
1280x720
1280x768
1280x1024
1366x768
1360x1024
1400x1050
1600x1200
4:3
8:5
4:3
4:3
4:3
16:9
15:9
4:3
16:9
4:3
1.35:1.00
1:1
<85
<85
<85
<85
<85
<85
<85
<85
<85
<75
<75
<60
<315
<360
<570
<950
<1100
<1190
<1580
<1400
<1450
<1560
<1650
1:1
1:1
1:1
1:1
1:1
1:1
1:1
1:1
<57
<95
<110
<119
<158
<140
<145
<156
4:3
4:3
1:1
1:1
<165
Table 4: Popular Panel Sizes
UXGA
1600x1200
SXGA+
1400x1050
1360x1024
1280x1024
1280x960
1024x768
1024x600
800x600
SXGA
XGA
SVGA
2.3 HDCP Compatibility
High Bandwidth Digital Content Protection (HDCP) provides a means of protecting the video transmission between
a DVI video transmitter and a DVI video receiver. The content protection system includes a process of (a)
authentication in which the video transmitter verifies that a given video receiver is licensed to receive protected
content; (b) encryption in which the transmitted video data is encrypted based on secret codes exchanged during the
authentication process; and (c) renewability in which the video transmitter can identify compromised receivers and
prevent the transmission of protected content.
Each HDCP authorized device (transmitter or receiver) has an array of 40, 56-bit secret device keys and a Key
Selection Vector (KSV) obtainable from Digital Content Protection LLC (http://www.digital-cp.com/). With the
addition of the encrypted HDCP device keys, the CH7312A can be configured to be a HDCP compliant transmitter.
A possible connection diagram is shown in the following figure.
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CHRONTEL
CH7312A
SDVO Data
SDVO Clock
/
6
/
SDVO Data
SDVO Clock
DVI Data Output
/
6
HDCP compliant
DVI
2
CH7312
DVI Clock
/
receiver
SPD
SPC
Serial Data
Serial Clock
1
2
M
O
R
P
M
2
O
R
P
SDVO
Graphics
Controller
AKSV ,
AKEYS
,
CH9901
storage
Authentication exchange
Figure 3: Possible Connection Diagram for HDCP
When the CH7312A is configured as an HDCP non-compliant device, it will not send necessary information to the
graphics controller to be identified as an HDCP compliant device. As a result, the graphics controller will not send
any data that require content protection. Also, the HDCP process is bypassed inside the CH7312A. In this
configuration, the CH7312A operates as DVI Transmitter device similar to the CH7307.
Details of the CH7312A HDCP operation are available in a separate document. Contact Chrontel for details. See
also the “High Bandwidth Digital Content Protection System” specification available at http://www.digital-cp.com/.
2.4 Command Interface
Communication is through two-wire path, control clock (SPC) and data (SPD). The CH7312A accepts incoming
control clock and data from graphics controller, and is capable of redirecting that stream to an ADD2 card PROM,
DDC, or CH7312A internal registers. The control bus is able to run up to 1MHz when communicating with internal
registers, up to 400kHz for the PROM and up to 100kHz for the DDC.
Internal
Device
Registers
control
the
observer
switch
on/off
Control Bus
from VGA
DDC
default
position
PROM
Figure 4: Control Bus Switch
Upon reset, the default state of the directional switch is to redirect the control bus to the ADD2 PROM. At this stage,
the CH7312A observes the control bus traffic. If the observing logic sees a control bus transaction destined for the
internal registers (device address 70h or 72h), it disables the PROM output pairs, and switches to internal registers.
In the condition that traffic is to the internal registers, an opcode command is used to set the redirection circuitry to
the appropriate destination (ADD2 PROM or DDC). Redirecting the traffic to internal registers while at the stage of
traffic to DDC occurs on observing a STOP after a START on the control bus.
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CHRONTEL
CH7312A
2.5 Boundary scan Test
CH7312A provides so called “NAND TREE Testing” to verify IO cell function at the PC board level. This test will
check the interconnect between chip I/O and the printed circuit board for faults (soldering, bend leads, open printed
circuit board traces, etc.). NAND tree test is a simple serial logic which turns all IO cell signals to input mode,
connects all inputs with NAND gates as shown in Figure 5 and switches each signal to high or low according to the
sequence in
Table 5. The test results then pass out at pin #25 (VSWING).
Figure 5: NAND Tree Connection
Testing Sequence
Set BSCAN =1; (internal weak pull low)
Set all signals listed in
Table 5 to 1.
Set all signals listed in
Table 5 to 0, toggle one by one with certain time period, suggested 100 ns. Pin #25 will change its value each time
an input value changed.
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CH7312A
Table 5: Signal Order in the NAND Tree Testing
Order
1
2
3
4
Pin Name
PROM1
PROM2
HPDET
SDVO_INT+
SDVO_INT-
AS
LQFP Pin
26
27
29
32
33
3
5
6
7
SPC
4
8
SPD
5
9
SD_PROM
SC_PROM
SD_DDC
SC_DDC
TLC*
TLC
TDC0*
TDC0
TDC1*
TDC1
TDC2*
TDC2
8
9
10
11
12
13
14
15
16
17
18
19
20
10
13
14
16
17
18
19
20
22
23
Table 6: Signals not Tested in NAND Test
Pin Name
SDVO_R+
SDVO_R-
SDVO_G+
SDVO_G-
SDVO_B+
SDVO_B-
SDVO_CLK+
SDVO_CLK-
RESET*
LQFP Pin
37
38
40
41
43
44
46
47
2
BSCAN
Reserved
VSWING
26
27
25
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CHRONTEL
CH7312A
3.0 REGISTER CONTROL
The CH7312A is controlled via a serial control port. The serial bus uses only the SC clock to latch data into
registers, and does not use any internally generated clocks so that the device can be written to in all power down
modes. The device will retain all register values during power down modes.
Registers 00h to 11h are reserved for opcode use. All registers except bytes 00h to 11h are reserved for internal
factory use. For details regarding Intel® SDVO opcodes, please contact Intel®.
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CH7312A
Electrical Specifications
3.1 Absolute Maximum Ratings
Symbol
Description
Min
Typ
Max
Units
All 2.5V power supplies relative to GND
All 3.3V power supplies relative to GND
-0.5
-0.5
3.0
5.0
V
T
Analog output short circuit duration
Ambient operating temperature
Storage temperature
Indefinite
Sec
°C
°C
°C
°C
°C
°C
SC
T
AMB
0
85
T
STOR
-65
150
150
260
245
225
T
J
Junction temperature
T
VPS
Vapor phase soldering (5 second )
Vapor phase soldering (11 second )
Vapor phase soldering (60 second )
Note:
1) Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device.
These are stress ratings only. Functional operation of the device at these or any other conditions above those
indicated under the normal operating condition of this specification is not recommended. Exposure to absolute
maximum rating conditions for extended periods may affect reliability. The temperature requirements of vapor
phase soldering apply to all standard and lead free parts.
2) The device is fabricated using high-performance CMOS technology. It should be handled as an ESD sensitive
device. Voltage on any signal pin that exceeds the power supply voltages by more than ± 0.5V can induce
destructive latchup.
3.2 Recommended Operating Conditions
Symbol
Description
Min
2.375
3.100
2.375
3.100
3.100
2.375
Typ
2.5
3.3
2.5
3.3
3.3
2.5
Max
2.625
3.500
2.625
3.500
3.500
2.625
Units
AVDD
Analog Power Supply Voltage
Analog PLL Power Supply Voltage
Digital Power Supply Voltage
DVI Power Supply
V
V
V
V
V
V
AVDD_PLL
DVDD
TVDD
VDD33
VDD25
Generic for all 3.3V supplies
Generic for all 2.5V supplies
3.3 Electrical Characteristics
(Operating Conditions: TA = 0°C – 70°C, VDD25 =2.5V ± 5%, VDD33=3.3V± 5%)
Symbol
Description
Min
Typ
Max
Units
Total VDD25 supply current (2.5V supplies)
Pixel Rate=162MHz
Total VDD33 supply current (3.3V supply)
Pixel Rate=162MHz
I
I
I
VDD25
VDD33
PD
210
mA
75
mA
µA
Total Power Down Current (all supplies)
100
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CHRONTEL
CH7312A
4.1 DC Specifications
Symbol
Description
Test Condition
Min
Typ
Max
Unit
VRX-DIFFp-p
SDVO Receiver Differential
Input Peak to Peak Voltage
VRX-DIFFp-p = 2 *
0.175
1.200
120
60
V
⏐VRX-D+ - VRX-D-
⏐
ZRX-DIFF-DC
ZRX-COM-DC
SDVO Receiver DC
80
40
5
100
50
Ω
Ω
Ω
Differential Input Impedance
SDVO Receiver DC Common
Mode Input Impedance
ZRX-COM-
SDVO Receiver Initial DC
Common Mode Input
Impedance
Impedance allowed
when receiver
50
60
INITIAL-DC
terminations are first
turned on
SDVO INT Differential Output
Peak to Peak Voltage
VINT-DIFFp-p
0.8
1.2
V
V
1
VSPOL
Serial Port
I
OL
= 2.0 mA
0.4
Output Low Voltage
2
VSPIH
Serial Port
VDD25 +
0.5
V
V
V
Input High Voltage
2.0
2
VSPIL
Serial Port
Input Low Voltage
GND-0.5
0.4
2
VHYS
Serial Port
Input Hysteresis
0.25
4.0
VDDCIH
DDC Serial Port
VDD5 +
0.5
Input High Voltage
VDDCIL
DDC Serial Port
V
Input Low Voltage
GND-0.5
4.0
0.4
VPROMIH
PROM Serial Port
Input High Voltage
VDD5 +
0.5
VPROMIL
PROM Serial Port
Input Low Voltage
V
V
GND-0.5
0.4
3
Input is VINL at
SD_DDC or
SD_PROM.
VSD_DDCOL
SPD (serial port data) Output
Low Voltage from SD_DDC
(or SD_PROM)
0.9*VINL
0.25
+
4.0kΩ pullup to 2.5V.
4
Input is VINL at SPC
and SPD.
VDDCOL
SC_DDC and SD_DDC
Output Low Voltage
0.933*VINL
+ 0.35
V
V
5.6kΩ pullup to 5.0V.
5
Input is VINL at SPC
and SPD.
VPROMOL
SC_PROM and SD_PROM
Output Low Voltage
0.933*VINL
+ 0.35
5.6kΩ pullup to 5.0V.
6
VMISC1IH
RESET*, BSCAN
Input High Voltage
2.7
GND-0.5
2.0
VDD33 +
0.5
V
V
V
6
RESET*, BSCAN
Input Low Voltage
VMISC1IL
0.5
7
VMISC2IH
AS, T1
VDD25 +
0.5
Input High Voltage
14
201-0000-071
Rev. 1.12,
6/1/2006
CHRONTEL
CH7312A
Symbol
Description
Test Condition
DVDD=2.5V
Min
Typ
Max
Unit
7
VMISC2IL
AS, T1
GND-0.5
0.5
V
Input Low Voltage
8
VMISC3IH
HPDET
2.0
VDD33 +
0.5
V
V
Input High Voltage
8
VMISC3IL
IMISC1PD
IMISC1PU
HPDET
DVDD=2.5V
VIN = 3.3V
GND-0.5
0.5
Input Low Voltage
BSCAN
10
10
40
40
µA
µA
Pull Down Current
RESET*
VIN = 0V
Pull Up Current
HPDET,
VIN = 2.5V
IMISC2PD
5
20
40
µA
Pull Down Current
AS
VIN = 0V
IMISC2PU
VH
10
µA
V
Pull Up Current
DVI Single Ended Output
High Voltage
TVDD = 3.3V ± 5%
TVDD –
0.01
TVDD +
0.01
RTERM = 50Ω ± 1%
DVI Single Ended Output Low
Voltage
RSWING = 1200Ω ± 1%
VL
TVDD –
0.6
TVDD –
0.4
V
DVI Single Ended Output
Swing Voltage
VSWING
VOFF
400
600
mVp-p
V
DVI Single Ended Standby
Output Voltage
TVDD –
0.01
TVDD +
0.01
Notes:
1. Refers to SPD. VSPOL is the output low voltage from SPD when transmitting from internal registers not from DDC or EEPROM.
2. Refers to SPC, SPD.
3.
4.
5.
V
SD_DDCOL is the output low voltage at the SPD pin when the voltage at SD_DDC or SD_PROM is VINL. Maximum output voltage
has been calculated with a worst case pull up of 4.0kΩ to 2.5V on SPD.
DDCOL is the output low voltage at the SC_DDC and SD_DDC pins when the voltage at SPC and SPD is VINL. Maximum output
voltage has been calculated with 5.6k pull up to 5V on SC_DDC and SD_DDC.
PROMOL is the output low voltage at the SC_PROM and SD_PROM pins when the voltage at SPC and SPD is VINL. Maximum
output voltage has been calculated with 5.6kΩ pull up to 5V on SC_PROM and SD_PROM.
V
V
6. VMISC1 refers to RESET* and BSCAN inputs which are 3.3V compliant.
7. VMISC2 refers to AS which are 2.5V compliant.
8.
VMISC3 refers to HPDET which are 2.5V/3.3V compliant.
201-0000-071
Rev. 1.12, 6/1/2006
15
CHRONTEL
CH7312A
4.2 AC Specifications
Symbol
Description
Test Condition
Min
Typ
Max
Unit
UIDATA
SDVO Receiver Unit Interval
for Data Channels
Typ. –
1/[Data
Transfer
Rate]
Typ. +
ps
300ppm
300ppm
fSDVO_CLK
fPIXEL
SDVO CLK Input Frequency
DVI Transmitter Pixel Rate
100
25
1
200
165
2
MHz
MHz
GHz
fSYMBOL
SDVO Receiver Symbol
Frequency
tRX-EYE
SDVO Receiver Minimum Eye
Width
0.4
UI
UI
tRX-EYE-JITTER
SDVO Receiver Max. time
between jitter median and
max. deviation from median
0.3
VRX-CM-Acp
SDVO Receiver AC Peak
150
mV
Common Mode Input Voltage
RLRX-DIFF
RLRX-CM
tSKEW
Differential Return Loss
50MHz – 1.25GHz
50MHz – 1.25GHz
Across all lanes
15
6
dB
dB
ns
Common Mode Return Loss
SDVO Receiver Total Lane to
Lane Skew of Inputs
2
tDVIR
tDVIF
TSPR
DVI Output Rise Time
(20% - 80%)
fXCLK = 165MHz
fXCLK = 165MHz
75
75
242
242
ps
ps
DVI Output Fall Time
(20% - 80%)
SPC, SPD Rise Time
(20% - 80%)
Standard mode 100k
Fast mode 400k
1000
300
150
300
300
150
300
ns
ns
ns
ns
ns
ns
ns
1M running speed
Standard mode 100k
Fast mode 400k
TSPF
SPC, SPD Fall Time
(20% - 80%)
1M running speed
Fast mode 400K
TPROMR
TPROMF
TDDCR
TDDCF
SC_PROM, SD_PROM Rise
Time (20% - 80%)
SC_PROM, SD_PROM Rise
Time (20% - 80%)
Fast mode 400K
300
1000
300
ns
ns
ns
SC_DDC, SD_DDC Rise
Time (20% - 80%)
Standard mode 100k
Standard mode 100k
SC_DDC, SD_DDC Fall
Time (20% - 80%)
1
TDDCR-DELAY
SC_DDC, SD_DDC Rise
Time Delay (50%)
Standard mode 100k
Standard mode 100k
0
3
ns
ns
1
TDDCF-DELAY
SC_DDC, SD_DDC Fall
Time Delay (50%)
tSKDIFF
DVI Output intra-pair skew
fXCLK = 165MHz
90
ps
16
201-0000-071
Rev. 1.12,
6/1/2006
CHRONTEL
CH7312A
Symbol
Description
Test Condition
fXCLK = 165MHz
fXCLK = 165MHz
Min
Typ
Max
Unit
tSKCC
DVI Output inter-pair skew
DVI Output Clock Jitter
1.2
ns
tDVIJIT
150
ps
Notes:
1.
Refers to the figure below, the delay refers to the time pass through the internal switches.
3.3V typ.
2.5V typ.
R=5K
To SPC/SPD pin
To DDC pin
201-0000-071
Rev. 1.12, 6/1/2006
17
CHRONTEL
CH7312A
4.0 PACKAGE DIMENSIONS
TOP VIEW
BOTTOM VIEW
A
B
K
25
36
37
24
B
A
K
48
13
12
1
EXPOSED PAD
D
C
F
E
I
.008"
J
H
G
Figure 6: 48 Pin LQFP Package
Table of Dimensions
No. of Leads
SYMBOL
A
9
B
7
C
D
E
F
G
H
I
J
K
48 (7 X 7 mm)
Milli-
MIN
0.17
0.27
1.35
1.45
0.05
0.15
0.45
0.75
0.09
0.20
0°
7°
4
0.50
1.00
meters
MAX
5.5
Notes:
1. Conforms to JEDEC standard JESD-30 MS-026D.
2. Dimension B: Top Package body size may be smaller than bottom package size by as much as 0.15 mm.
3. Dimension B does not include allowable mold protrusions up to 0.25 mm per side.
18
201-0000-071
Rev. 1.12,
6/1/2006
CHRONTEL
CH7312A
5.0 REVISION HISTORY
Table 7: Revisions
Rev. #
0.4
0.41
1.0
1.1
1.11
Date
1/11/05
2/8/05
6/1/2005
9/27/05
10/05/05
Section
All
All
All
4.4, 4.5
4.4
Description
First draft based on Eng. Spec. 0.4.
Changed all “SDVOB” to “SDVO” from Eng. Spec. 0.4.
Official release
Updated order information and DC, AC specifications
Updated DC spec and order information.
201-0000-071
Rev. 1.12, 6/1/2006
19
CHRONTEL
CH7312A
Disclaimer
This document provides technical information for the user. Chrontel reserves the right to make changes at any time
without notice to improve and supply the best possible product and is not responsible and does not assume any
liability for misapplication or use outside the limits specified in this document. We provide no warranty for the use
of our products and assume no liability for errors contained in this document. The customer should make sure that
they have the most recent data sheet version. Customers should take appropriate action to ensure their use of the
products does not infringe upon any patents. Chrontel, Inc. respects valid patent rights of third parties and does not
infringe upon or assist others to infringe upon such rights.
Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT
SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE SPECIFIC WRITTEN CONSENT OF
Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used
as directed can reasonably expect to result in personal injury or death.
ORDERING INFORMATION
Number of
Part Number
Package Type
Voltage Supply
2.5V & 3.3V
Pins
Lead free LQFP
with exposed pad
Lead free LQFP
with exposed pad
in Tape & Reel
CH7312A-DEF
48
CH7312A-DEF-TR
48
2.5V & 3.3V
Chrontel
2210 O’Toole Avenue, Suite 100,
San Jose, CA 95131-1326
Tel: (408) 383-9328
Fax: (408) 383-9338
www.chrontel.com
E-mail: sales@chrontel.com
©2006 Chrontel, Inc. All Rights Reserved.
Printed in the U.S.A.
20
201-0000-071
Rev. 1.12,
6/1/2006
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