CS497014 [CIRRUS]
High Definition Audio Decoder DSP Family with Dual 32-bit Engine Technology;
| 型号： | CS497014 |
| 厂家： | 
CIRRUS LOGIC |
| 描述： | High Definition Audio Decoder DSP Family with Dual 32-bit Engine Technology |
| 文件： | 总31页 (文件大小：871K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CS4970x4 Data Sheet
FEATURES
High Definition Audio Decoder DSP Family
with Dual 32-bit Engine Technology
Multi-standard 32-bit high-definition audio decoding plus
post-processing
Supports high-definition audio formats including:
— Dolby Digital® Plus
— Dolby® TrueHD
— DTS-HD® High Resolution Audio
— DTS-HD Master Audio™
— DTS Express™ 5.1
Up to 12 Channels of 32-bit Serial Audio Input
Customer Software Security Keys
16 Ch x 32-bit PCM Out with Dual 192 kHz S/PDIF Tx
Two SPI™/I2C™ ports
Large On-chip X, Y, and Program RAM & ROM
SDRAM and Serial Flash Memory Support
Supports legacy audio formats and a wide array of post-
processing
— Dolby Digital® EX, Dolby Pro Logic® II, IIx, IIz 7.1, Dolby
The CS4970x4 DSP family is an enhanced version of the
CS4953xx DSP family with higher overall performance. In
addition to all the mainstream audio processing codes in on-
chip ROM that the CS4953xx DSP offers, the CS4970x4 device
family also supports the decoding of major high-definition audio
formats. Additionally, the CS4970x4, a dual-core device,
performs the high-definition audio decoding on the first core,
leaving the second core available for audio post-processing and
audio enhancement. The CS4970x4 device supports the most
demanding audio post processing requirements. It provides an
easy upgrade path to systems currently using the CS495xx or
CS4953xx device with minor (or no) hardware and software
changes.
Headphone® 2, Dolby Virtual Speaker® 2, Dolby
Volume® (original), Dolby Volume 258 (lite), Audistry®
— DTS-ES 96/24™ Discrete 7.1, DTS-ES™ Discrete 7.1,
DTS-ES™ Matrix 6.1, DTS Neo:6®, DTS Neural
Surround™ DTS Surround Sensation Speaker
— MPEG-2 AAC™ LC 5.1
— SRS® Circle Surround® II, SRS Circle Surround Auto,
SRS Circle Surround Decoder Optimized, SRS
TruVolume™ 7.1 (V 2.1.0.0), SRS TruSurround
HD/HD4®, SRS WOW HD™, SRS CS Headphone™,
SRS Circle Cinema 3D™, SRS Studio Sound HD™
— THX® Ultra2™, THX Select2™
Cirrus Logic’s Applications Library
Ordering Information
See page 27 for ordering information.
— Cirrus Original Multi-Channel Surround 2 (COMS2),
Cirrus Band XpandeR™, Cirrus Virtualization
Technology (CVT), Cirrus Intelligent Room Calibration 2
(IRC2), Cirrus Bass Enhancement (CBE)
— Crossbar Mixer, Signal Generator
— Advanced Post-Processors including: 7.1 Bass Manager
Quadruple Crossover, Tone Control, 11- Band
Parametric EQ, Delay, 2:1/4:1 Decimator, 1:2/1:4
Upsampler
Serial
Control1
Serial
Control2
Parallel
Control
GPIO
Debug
12 Ch. Audio In /
6 Ch. SACD In
STC
D
M
A
Coyote 32-bit
Coyote 32-bit
DSP B
TMR1
TMR2
DSP A
S/PDIF
S/PDIF
P
X
Y
P
X
Y
16 Ch PCM
Audio Out
PLL
Ext. Memory Controller
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Preliminary Product Information
Copyright © 2014 Cirrus Logic, Inc.
All Rights Reserved
FEB 2014
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http://www.cirrus.com
CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
Table of Contents
1 Documentation Strategy ............................................................................................................4
2 Overview .....................................................................................................................................4
2.1 Migrating from CS495xx(3) to CS4970x4 .................................................................................................5
2.2 Licensing ..................................................................................................................................................5
3 Code Overlays ............................................................................................................................5
4 Hardware Functional Description ............................................................................................6
4.1 Coyote DSP Core .....................................................................................................................................6
4.1.1 DSP Memory ...............................................................................................................................6
4.1.2 DMA Controller ............................................................................................................................7
4.2 On-chip DSP Peripherals .........................................................................................................................7
4.2.1 Digital Audio Input Port (DAI) .......................................................................................................7
4.2.2 Digital Audio Output Port (DAO) ..................................................................................................7
2
4.2.3 Serial Control Port 1 & 2 (I C or SPI) ..........................................................................................7
4.2.4 External Memory Interface ..........................................................................................................7
4.2.5 General Purpose Input/Output (GPIO) ........................................................................................7
4.2.6 Phase-locked Loop (PLL)-based Clock Generator ......................................................................7
4.3 DSP I/O Description .................................................................................................................................8
4.3.1 Multiplexed Pins ..........................................................................................................................8
4.3.2 Termination Requirements ...........................................................................................................8
4.3.3 Pads ............................................................................................................................................8
4.4 Application Code Security ........................................................................................................................8
5 Characteristics and Specifications ..........................................................................................8
5.1 Absolute Maximum Ratings ......................................................................................................................8
5.2 Recommended Operating Conditions ......................................................................................................9
5.3 Digital DC Characteristics ........................................................................................................................9
5.4 Power Supply Characteristics ..................................................................................................................9
5.5 Thermal Data (128-pin LQFP) ................................................................................................................10
5.6 Switching Characteristics—RESET ......................................................................................................... 11
5.7 Switching Characteristics — XTI ............................................................................................................ 11
5.8 Switching Characteristics — Internal Clock ............................................................................................12
5.9 Switching Characteristics — Serial Control Port - SPI Slave Mode .......................................................13
5.10 Switching Characteristics — Serial Control Port - SPI Master Mode ...................................................14
2
5.11 Switching Characteristics — Serial Control Port - I C Slave Mode ......................................................15
2
5.12 Switching Characteristics — Serial Control Port - I C Master Mode ....................................................16
5.13 Switching Characteristics — Parallel Control Port - Intel Slave Mode .................................................16
5.14 Switching Characteristics — Parallel Control Port - Motorola Slave Mode .........................................19
5.15 Switching Characteristics — Digital Audio Slave Input Port .................................................................21
5.16 Switching Characteristics — Digital Audio Output Port ........................................................................22
5.17 Switching Characteristics — SDRAM Interface ....................................................................................23
6 Ordering Information ...............................................................................................................27
7 Environmental, Manufacturing, and Handling Information .................................................27
8 Device Pin-Out Diagram ..........................................................................................................28
8.1 128-Pin LQFP Pin-Out Diagram .............................................................................................................28
9 Package Mechanical Drawings ...............................................................................................29
9.1 128-Pin LQFP Package Drawing ...........................................................................................................29
10 Revision History .....................................................................................................................30
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CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
List of Figures
Figure 1. RESET Timing .........................................................................................................................................11
Figure 2. XTI Timing ..............................................................................................................................................11
Figure 3. Serial Control Port - SPI Slave Mode Timing ..........................................................................................13
Figure 4. Serial Control Port - SPI Master Mode Timing ........................................................................................14
2
Figure 5. Serial Control Port - I C Slave Mode Timing ..........................................................................................15
2
Figure 6. Serial Control Port - I C Master Mode Timing ........................................................................................16
Figure 7. Parallel Control Port - IntelÒ Slave Mode Read Cycle ...........................................................................17
Figure 8. Parallel Control Port - Intel Slave Mode Write Cycle ..............................................................................18
Figure 9. Parallel Control Port - MotorolaÒ Slave Mode Read Cycle Timing ........................................................20
Figure 10. Parallel Control Port - Motorola Slave Mode Write Cycle Timing .........................................................20
Figure 11. Digital Audio Input (DAI) Port Timing Diagram .....................................................................................21
Figure 12. DAI Slave Timing Diagram ...................................................................................................................21
Figure 13. Digital Audio Port Output Timing Master Mode .....................................................................................22
Figure 14. Digital Audio Output Timing, Slave Mode (Relationship LRCLK to SCLK) ...........................................23
Figure 15. External Memory Interface - SDRAM Burst Read Cycle .......................................................................24
Figure 16. External Memory Interface - SDRAM Burst Write Cycle .......................................................................24
Figure 17. External Memory Interface - SDRAM Auto Refresh Cycle ....................................................................25
Figure 18. External Memory Interface - SDRAM Load Mode Register Cycle ........................................................26
Figure 19. 128-Pin LQFP Pin-Out Diagram ...........................................................................................................28
Figure 20. 128-Pin LQFP Package Drawing ..........................................................................................................29
List of Tables
Table 1. CS4970x4 Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 2. Device and Firmware Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3. CS4970x4 DSP Memory Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 4. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 5. Environmental, Manufacturing, & Handling Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 6. 128-Pin LQFP Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
1 Documentation Strategy
The CS4970x4 data sheet describes the CS4970x4 family of multichannel audio decoders. This document
should be used in conjunction with the following documents when evaluating or designing a system around the
CS4970x4 family of processors.
Table 1. CS4970x4 Related Documentation
Document Name
Description
This document
CS4970x4 Data Sheet
A new consolidated documentation set that includes:
• Detailed system design information including
Typical Connection Diagrams, Boot-Procedures,
Pin Descriptions, Etc. Also describes use of DSP
Condenser tool.
CS495314/CS4970x4 System Designer’s Guide
• Detailed firmware design information including
signal processing flow diagrams and control API
information
Includes detailed firmware design information
including signal processing flow diagrams and control
API information
AN288 - CS4953xx/CS4970x4 Firmware User’s Manual
The scope of the CS4970x4 data sheet is primarily to provide hardware specifications of the CS4970x4 family
of devices. This includes hardware functionality, characteristic data, pinout, and packaging information.
The intended audience for the CS4970x4 data sheet is the system PCB designer, MCU programmer, and the
quality control engineer.
2 Overview
The CS4970x4 DSP Family, combined with Cirrus Logic’s comprehensive library of audio processing
algorithms, enables the development of next-generation high-definition audio solutions. Cirrus Logic also
provides a broad array of digital interface products and audio converters to meet your audio system-level
design requirements.
Note: The CS4970x4 is available in a 128-pin LQFP package.
The audio processing features of the CS4970x4 product family are a superset of audio features available in
the CS4953xx product family.
Refer to Table 2 on page 5 for the speed and firmware features of the CS4970x4 product family.
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CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
Table 2. Device and Firmware Selection Guide
Virtualizer Processor
Post Processor
Module
Decode Processor
(DSP-A)1
Matrix Processor Module
(DSP-A)1
Module
(DSP-B)1
Device
(DSP-B)1
Dolby Pro Logic II / IIx / IIz 7.1
Stereo PCM
APP
(4:1/2:1 Down-sampling and
1:2/1:4 U-sampling Options)2
(Advanced Post-
processing)
SRS Circle Surround II / Circle
Surround Auto / Circle
Surround Decoder Optimized
(Stereo In)
–Tone Control
–Select 2
–PEQ (up to 11 Bands)
–Delay
Multichannel PCM
(4:1/2:1 Down-sampling and
1:2/1:4 Up-sampling Options)2
Cirrus Virtualizer
Technology
CS497014
300MACS
Cirrus Original Multi-Channel
Surround 2 (Effects / Reverb
Processor)
(Speaker to Listening
Position Alignment
and/or Lip Sync)
–7.1 Bass Manager
–Audio Manager
Dolby Headphone 2
Dolby Virtual Speaker 2
SRS CS Headphone
Dolby Digital
MPEG-2 AAC LC 5.1
Dolby Digital Plus
Crossbar (Down-mix / Up-mix)
(Simultaneous Process)
Dolby TrueHD3
–4:1/2:1 Down-sampling2
Same as CS497014 +
DTS, DTS-ES, DTS96/24
DTS-HD Master Audio3
DTS-HD High Res Audio3
SRS TruSurround HD/HD4
SRS TruVolume 7.1
Multichannel
CS497004
300MACS
Same as CS497014 +
DTS Neo:6, DTS Neural
Surround
Dolby Volume
Multichannel
CS497024
DTS Express 5.1
300MACS
1. Additional processing (MPMA, MPMB/VPM, PPM) post any of the HD audio decoders may be limited. Contact your Cirrus Logic
FAE for the latest concurrency matrix.
2. Downsampling and Upsampling functionality is located in the operating system. The Cirrus Decimator (Down-Sampler) is also
available as a separate post-processing module that is described in the application note AN288PPI.
3. The indicated HD audio decoder algorithms require external SDRAM. Consult your Cirrus Logic FAE for the recommended
SDRAM size for your design.
2.1 Migrating from CS495xx(3) to CS4970x4
CS4970x4 was designed to provide an easy upgrade path from the CS495xx and CS4953x. There are some
small differences the hardware designer should be aware of:
• The PLL supply voltage on the CS4970x4 is 3.3V vs. 1.8V on the CS495xx.
• The PLL filter topology is simpler when using the CS4970x4 rather than the CS495xx.
• The CS4970x4 adds support for Time-division multiplexing (TDM) mode on both audio input and output
ports.
• The CS4970x4 does not support external static random access memory (SRAM) operation.
• The CS4970x4 external Synchronous dynamic random access memory (SDRAM) bus speed is fixed at
150 MHz vs. the 120 MHz maximum bus speed for the CS495xx. Some firmware modules also support a
75 MHz CS4970x4 SDRAM bus speed. Refer to AN304 for details.
• The CS4970x4 CLKOUT pin can output XTALI or XTALI/2. The CS495xx can only output XTALI.
2.2 Licensing
Licenses are required for all of the third party audio decoding/processing algorithms listed below, including the
application notes. Contact your local Cirrus Sales representative for more information.
3 Code Overlays
The suite of software available for the CS4970x4 family consists of operating systems (OS) and a library of
overlays. The overlays have been divided into three main groups: decoders, matrix processors, and
postprocessors. All software components are defined in the following list:
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CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
• OS/Kernel - Encompasses all non-audio processing tasks, including loading data from external memory,
processing host messages, calling audio-processing subroutines, auto-detection, error concealment, etc.
• Decoders - Any module that initially writes data into the audio I/O buffers, e.g. AC-3™, DTS, PCM, etc. All
the decoding/processing algorithms listed require delivery of PCM or IEC61937-packed, compressed data
2
via I S- or LJ-formatted digital audio to the CS4970x4 from A/D converters, SPDIF Rx, HDMI Rx, etc.
• Matrix-processors - Any module that processes audio I/O buffer PCM data in-place before the Post-
processors. Generally speaking, these modules alter the number of valid channels in the audio I/O buffer
through processes like Virtualization (n2 channels) or Matrix Decoding (2n channels). Examples are
Dolby ProLogic IIx and DTS Neo:6.
• Virtualizer-processor - Any module that encodes PCM data into fewer output channels than input
channels (n2 channels) with the effect of providing “phantom” speakers to represent the physical audio
channels that were eliminated. Examples are Dolby Headphone 2 and Dolby Virtual Speaker 2. Generally
speaking, these modules reduce the number of valid channels in the audio I/O buffer.
• Post-processors - Any module that processes audio I/O buffer PCM data in-place after the matrix
processors. Examples are bass management, audio manager, tone control, EQ, delay, customer-specific
effects, Dolby Headphone/Virtual Speaker, etc.
The overlay structure reduces the time required to reconfigure the DSP when a processing change is
requested. Each overlay can be reloaded independently without disturbing the other overlays. For example,
when a new decoder is selected, the OS, matrix-, and post-processors do not need to be reloaded — only the
new decoder (the same is true for the other overlays).
4 Hardware Functional Description
4.1 Coyote DSP Core
The CS4970x4 is a dual-core Coyote DSP with separate X and Y data and P code memory spaces. Each core
is a high-performance, 32-bit, user-programmable, fixed-point DSP that is capable of performing two multiply
accumulate (MAC) operations per clock cycle. Each core has eight 72-bit accumulators, four X- and four Y-data
registers, and 12 index registers.
Both DSP cores are coupled to a flexible DMA engine. The DMA engine can move data between peripherals
such as the digital audio input (DAI) and digital audio output (DAO), external memory, or any DSP core
memory, all without the intervention of the DSP. The DMA engine offloads data move instructions from the DSP
core, leaving more MIPS available for signal processing instructions.
CS4970x4 functionality is controlled by application codes that are stored in on-board ROM or downloaded to
the CS4970x4 from a host MCU or external FLASH/EEPROM. Users can choose to use standard audio
decoder and post-processor modules which are available from Cirrus Logic.
The CS4970x4 is suitable for audio decoder, audio post-processor, audio encoder, DVD audio/video player,
and digital broadcast decoder applications.
4.1.1 DSP Memory
Each DSP core has its own on-chip data and program RAM and ROM and does not require external memory
for any of today’s popular audio algorithms including Dolby Digital Surround EX, AAC Multichannel, DTS-ES
96/24, and THX Ultra2. However, if the end-system design requires support of the new high-definition audio
formats, external SDRAM will be needed to support Dolby TrueHD and DTS-HD master audio.
The memory maps for the DSPs are as follows. All memory sizes are composed of 32-bit words.
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CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
Table 3. CS4970x4 DSP Memory Sizes
Memory
Type
DSP A
DSP B
X
Y
P
16K SRAM, 32K ROM
24K SRAM, 32K ROM
8K SRAM, 32K ROM
10K SRAM, 8K ROM
16K SRAM, 16K ROM
8K SRAM, 24K ROM
4.1.2 DMA Controller
The powerful 12-channel DMA controller can move data between 8 on-chip resources. Each resource has its
own arbiter: X, Y, and P RAM/ROMs on DSP A; X, Y, and P RAM/ROMs on DSP B; external memory; and the
peripheral bus. Modulo and linear addressing modes are supported, with flexible start address and increment
controls. The service interval for each DMA channel as well as up to 6 interrupt events, is programmable.
4.2 On-chip DSP Peripherals
4.2.1 Digital Audio Input Port (DAI)
The 12-channel (6-line) DAI port supports a wide variety of data input formats. The port is capable of accepting
PCM or IEC61937. Up to 32-bit word lengths are supported. Additionally, support is provided for audio data
input to the DSP via the DAI from an HDMI receiver.
The port has two independent slave-only clock domains. Each data input can be independently assigned to a
clock domain. The sample rate of the input clock domains can be determined automatically by the DSP, which
off-loads the task of monitoring the SPDIF receiver from the host. A time-stamping feature allows the input data
to be sample-rate converted via software.
4.2.2 Digital Audio Output Port (DAO)
There are two DAO ports. Each port can output 8 channels of up to 32-bit PCM data. The port supports data
rates from 32 kHz to 192 kHz. Each port can be configured as an independent clock domain in slave mode, or
the ratio of the two clocks can be set to even multiples of each other in master mode. The two ports can also be
ganged together into a single clock domain. Each port has one serial audio pin that can be configured as a
192-kHz SPDIF transmitter (data with embedded clock on a single line).
2
4.2.3 Serial Control Port 1 & 2 (I C or SPI)
There are two on-chip serial control ports that are capable of operating as master or slave in either I2C or SPI
modes. SCP1 defaults to slave operation. It is dedicated for external host-control and supports an external
clock up to 50 MHz in SPI mode. This high clock speed enables very fast code download, control or data
delivery. SCP2 defaults to master mode and is dedicated for booting from external serial Flash memory or for
audio sub-system control.
4.2.4 External Memory Interface
The external memory interface controller supports up to 128 Mbits of SDRAM, using a 16-bit data bus.
4.2.5 General Purpose Input/Output (GPIO)
Many of the CS4970x4 peripheral pins are multiplexed with GPIO. Each GPIO can be configured as an output,
an input, or an input with interrupt. Each input-pin interrupt can be configured as rising edge, falling edge,
active-low, or active-high.
4.2.6 Phase-locked Loop (PLL)-based Clock Generator
The low-jitter PLL generates integer or fractional multiples of a reference frequency which are used to clock the
DSP core and peripherals. Through a second PLL divider chain, a dependent clock domain can be output on
the DAO port for driving audio converters. The CS4970x4 defaults to running from the external reference
frequency and can be switched to use the PLL output after overlays have been loaded and configured, either
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CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
through master boot from an external FLASH or through host control. A built-in crystal oscillator circuit with a
buffered output is provided. The buffered output frequency ratio is selectable between 1:1 (default) or 2:1.
4.3 DSP I/O Description
4.3.1 Multiplexed Pins
Many of the CS4970x4 pins are multi-functional. For details on pin functionality please refer to the CS4970x4
System Designer’s Guide.
4.3.2 Termination Requirements
Open-drain pins on the CS4970x4 must be pulled high for proper operation. Please refer to the CS4970x4
System Designer’s Guide to identify which pins are open-drain and what value of pull-up resistor is required for
proper operation.
Mode select pins on the CS4970x4 are used to select the boot mode upon the rising edge of reset. A detailed
explanation of termination requirements for each communication mode select pin can be found in the
CS4970x4 System Designer’s Guide.
4.3.3 Pads
The CS4970x4 I/O operates from the 3.3 V supply and is tolerant within 5 V.
4.4 Application Code Security
The external program code may be encrypted by the programmer to protect any intellectual property it may
contain. A secret, customer-specific key is used to encrypt the program code that is to be stored external to the
device.
5 Characteristics and Specifications
Note: All data sheet minimum and maximum timing parameters are guaranteed over the rated voltage
and temperature. All data sheet typical parameters are measured under the following conditions:
T = 25 °C, C = 20 pF, VDD = 1.8 V, VDDA = VDDIO = 3.3 V, GNDD = GNDIO = GNDA = 0 V.
L
5.1 Absolute Maximum Ratings
(GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0 V)
Parameter Symbol
Min
Max
Unit
DC power supplies:
Core supply
PLL supply
I/O supply
VDD
VDDA
VDDIO
–0.3
–0.3
–0.3
—
2.0
3.6
3.6
0.3
V
V
V
V
|VDDA – VDDIO|
Input pin current, any pin except supplies
Input voltage on PLL_REF_RES
Input voltage on I/O pins
I
—
+/- 10
3.6
mA
V
in
V
-0.3
-0.3
-65
filt
V
5.0
V
inio
Storage temperature
T
150
°C
stg
CAUTION: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is
not guaranteed at these extremes.
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CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
5.2 Recommended Operating Conditions
(GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0 V)
Parameter
Symbol
Min
Typ
Max
Unit
DC power supplies:
Core supply
PLL supply
I/O supply
VDD
VDDA
VDDIO
1.71
3.13
3.13
1.8
3.3
3.3
0
1.89
3.46
3.46
V
V
V
V
|VDDA – VDDIO|
Ambient operating temperature
T
A
Commercial Grade (CQZ/CVZ)
Commercial
0
0
+25
+ 70
°C
T
+125
ºC
j
Note: It is recommended that the 3.3 V IO supply come up ahead of or simultaneously with the 1.8 V core supply.
5.3 Digital DC Characteristics
(Measurements performed under static conditions.)
Parameter
High-level input voltage
Symbol
Min
2.0
Typ
—
Max
—
Unit
V
V
IH
Low-level input voltage, except XTI
Low-level input voltage, XTI
Input Hysteresis
V
—
—
—
—
—
0.4
—
0.8
0.6
—
V
V
V
V
IL
V
ILXTI
V
V
hys
OH
High-level output voltage (IO = -4mA), except XTI, SDRAM
VDDIO * 0.9
—
pins
Low-level output voltage (IO = 4mA), except XTI, SDRAM
V
—
—
VDDIO * 0.1
V
OL
pins
SDRAM High-level output voltage (IO = -8mA)
SDRAM Low-level output voltage (IO = 8mA)
Input leakage current (all digital pins with internal pull-up
V
V
I
VDDIO * 0.9
—
—
—
—
V
V
A
OH
—
—
VDDIO * 0.1
5
OL
IN
resistors disabled)
Input leakage current (all digital pins with internal pull-up
I
—
—
70
A
IN-PU
resistors enabled, and XTI)
5.4 Power Supply Characteristics
(Measurements performed under operating conditions.)
Parameter
Power supply current:
Min
Typ
Max
Unit
Core and I/O operating: VDD1
—
—
—
350
3.5
120
—
—
—
mA
mA
mA
PLL operating: VDDA
With external memory and most ports operating: VDDIO
1.Dependent on application firmware and DSP clock speed.
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CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
5.5 Thermal Data (128-pin LQFP)
Parameter
Symbol
Min
Typ
Max
Unit
Thermal Resistance (Junction to Ambient)
ja
°C / Watt
Two-layer Board1
Four-layer Board2
—
—
53
44
—
—
Thermal Resistance (Junction to Top of Package)
Two-layer Board1
Four-layer Board2
jt
°C / Watt
—
—
.45
.39
—
—
Notes: 1. Two-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz. copper covering 20% of the top and
bottom layers.
2. Four-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz. copper covering 20% of the top and
bottom layers and 0.5-oz. copper covering 90% of the internal power plane and ground plane layers.
3. To calculate the die temperature for a given power dissipation
j = Ambient Temperature + [ (Power Dissipation in Watts) * ja ]
4. To calculate the case temperature for a given power dissipation
c = j - [ (Power Dissipation in Watts) * jt
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CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
5.6 Switching Characteristics—RESET
Parameter
RESET minimum pulse width low
Symbol
Min
1
Max
—
Unit
s
T
rstl
All bidirectional pins high-Z after RESET low
Configuration pins setup before RESET high
Configuration pins hold after RESET high
T
—
100
—
ns
rst2z
T
50
20
ns
rstsu
T
—
ns
rsthld
RESET#
HS[3:0]
All Bidirectional
Pins
Trstsu
Trsthld
Trst2z
Trstl
Figure 1. RESET Timing
5.7 Switching Characteristics — XTI
Parameter
External Crystal operating frequency1
XTI period
Symbol
Min
12.288
41
Max
24.576
81.4
—
Unit
MHz
ns
F
xtal
T
clki
XTI high time
T
16.4
16.4
10
ns
clkih
XTI low time
T
—
ns
clkil
External Crystal Load Capacitance (parallel resonant)2
External Crystal Equivalent Series Resistance
C
18
pF
L
ESR
—
50
1. Part characterized with the following crystal frequency values: 12.288 and 24.576 MHz.
2. CL refers to the total load capacitance as specified by the crystal manufacturer. Crystals which require a CL outside this range
should be avoided. The crystal oscillator circuit design should follow the crystal manufacturer’s recommendation for load capacitor
selection.
XTI
tclkih
tclkil
Tclki
Figure 2. XTI Timing
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CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
5.8 Switching Characteristics — Internal Clock
Parameter
Symbol
Min
Max
–
Unit
Internal DCLK frequency1
F
MHz
dclk
—
CS497004-CQZ
CS497004-CQZR
CS497024-CVZ
CS497024-CVZR
CS497014-CVZ
CS497014-CVZR
CS497024-CVZ
CS497024-CVZR
F
131
xtal
Internal DCLK period1
DCLKP
—
–
ns
CS497004-CQZ
CS497004-CQZR
CS497024-CVZ
CS497024-CVZR
CS497014-CVZ
CS497014-CVZR
CS497024-CVZ
CS497024-CVZR
7.63
1/F
xtal
1. After initial power-on reset, Fdclk = Fxtal. After initial kick-start commands, the PLL is locked to max Fdclk and remains locked until
the next power-on reset.
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CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
5.9 Switching Characteristics — Serial Control Port - SPI Slave Mode
Parameter
SCP_CLK frequency1,2
Symbol
Min
—
24
20
20
5
Typical
—
Max
25
—
—
—
—
—
11
20
—
—
—
—
Units
MHz
ns
f
t
spisck
spicss
SCP_CS falling to SCP_CLK rising2
SCP_CLK low time2
—
t
—
ns
spickl
spickh
spidsu
SCP_CLK high time2
t
—
ns
Setup time SCP_MOSI input
t
—
ns
Hold time SCP_MOSI input
t
5
—
ns
spidh
SCP_CLK low to SCP_MISO output valid2
SCP_CLK falling to SCP_IRQ rising2
SCP_CS rising to SCP_IRQ falling2
SCP_CLK low to SCP_CS rising2
SCP_CS rising to SCP_MISO output high-Z
SCP_CLK rising to SCP_BSY falling2
t
—
—
0
—
ns
spidov
spiirqh
t
—
ns
t
—
ns
spiirql
t
24
—
—
—
ns
spicsh
t
20
ns
spicsdz
t
3 DCLKP+20
*
ns
spicbsyl
1. The specification fspisck indicates the maximum speed of the hardware. The system designer should be aware that the actual
maximum speed of the communication port may be limited by the firmware application. Flow control using the SCP_BSY pin
should be implemented to prevent overflow of the input data buffer. At boot the maximum speed is Fxtal/3.
2. When SCP1 is in SPI slave mode, very slow rise and fall times of the SCP_CLK edges may make the edges of the SCP_CLK
more susceptible to noise, resulting in non-smooth edges. Any glitch at the threshold levels of the SCP port input signals could
result in abnormal operation of the port. In systems that have noise coupling onto SCP_CLK, slow rise and fall times may cause
host communication problems. Increasing rise time makes host communication more reliable.
tspicss
SCP_CS#
tspickl
tspicsh
1
2
6
7
0
7
0
5
6
SCP_CLK
SCP_MOSI
SCP_MISO
SCP_IRQ#
SCP_BSY#
fspisck
tspickh
A6
A5
A0
R/W
MSB
MSB
LSB
LSB
tspidsu
tspidh
tspidov
tspicsdz
tspiirqh
tspiirql
tspibsyl
Figure 3. Serial Control Port - SPI Slave Mode Timing
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CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
5.10 Switching Characteristics — Serial Control Port - SPI Master Mode
Parameter
SCP_CLK frequency1, 2
Symbol Min
Typical
Max
Units
MHz
ns
f
—
—
—
F
/2
xtal
spisck
spicss
SCP_CS falling to SCP_CLK rising 3
t
11*DCLKP +
—
(SCP_CLK PERIOD)/2
SCP_CLK low time
t
16.9
16.9
11
—
—
—
—
—
—
—
—
—
—
11
—
—
ns
ns
ns
ns
ns
ns
ns
spickl
spickh
spidsu
SCP_CLK high time
t
Setup time SCP_MISO input
Hold time SCP_MISO input
SCP_CLK low to SCP_MOSI output valid
SCP_CLK low to SCP_CS falling
SCP_CLK low to SCP_CS rising
t
t
5
spidh
t
—
spidov
t
7
spicsl
t
—
11*DCLKP +
spicsh
(SCP_CLK PERIOD)/2
Bus free time between active SCP_CS
t
—
—
3*DCLKP
—
—
ns
ns
spicsx
SCP_CLK falling to SCP_MOSI output high-Z
t
20
spidz
1. The specification fspisck indicates the maximum speed of the hardware. The system designer should be aware that the actual
maximum speed of the communication port may be limited by the firmware application.
2. See Section 5.7.
3. SCP_CLK PERIOD refers to the period of SCP_CLK as being used in a given application. It does not refer to a tested parameter.
.
tspicsx
tspicss
EE_CS#
tspickl
tspicsh
tspicsl
1
2
6
7
0
7
0
5
6
SCP_CLK
SCP_MISO
SCP_MOSI
fspisck
tspickh
A6
A5
A0
R/W
MSB
MSB
LSB
LSB
tspidsu
tspidh
tspidov
tspidz
Figure 4. Serial Control Port - SPI Master Mode Timing
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CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
2
5.11 Switching Characteristics — Serial Control Port - I C Slave Mode
Parameter
Symbol Min
Typical
—
Max
400
—
Units
kHz
µs
SCP_CLK frequency1
SCP_CLK low time
SCP_CLK high time
f
—
iicck
t
1.25
1.25
1.25
—
iicckl
t
—
—
µs
iicckh
SCP_SCK rising to SCP_SDA rising or falling for START or
STOP condition
t
—
—
µs
iicckcmd
START condition to SCP_CLK falling
t
1.25
2.5
3
—
—
—
—
—
—
—
—
—
—
—
—
18
µs
µs
µs
ns
ns
ns
ns
ns
ns
iicstscl
SCP_CLK falling to STOP condition
t
iicstp
Bus free time between STOP and START conditions
Setup time SCP_SDA input valid to SCP_CLK rising
Hold time SCP_SDA input after SCP_CLK falling2
SCP_CLK low to SCP_SDA out valid
SCP_CLK falling to SCP_IRQ rising
t
iicbft
iicsu
t
100
0
t
iich
t
—
iicdov
iicirqh
t
—
3 DCLKP + 40
*
NAK condition to SCP_IRQ low
t
—
3 DCLKP + 20
*
3 DCLKP + 20
—
iicirql
SCP_CLK rising to SCB_BSY low
t
—
—
iicbsyl
*
1. The specification fiicck indicates the maximum speed of the hardware. The system designer should be aware that the actual
maximum speed of the communication port may be limited by the firmware application. Flow control using the SCP_BSY pin
should be implemented to prevent overflow of the input data buffer.
2. This parameter is measured from the ViL level at the falling edge of the clock.
tiicckcmd
tiicckl
tiicr
tiicf
tiicckcmd
0
1
6
7
8
0
1
6
7
8
SCP_CLK
SCP_SDA
SCP_IRQ#
SCP_BSY#
tiicstp
tiicstscl
tiicckh
tiicdov
R/W
fiicck
tiicbft
A6
A0
ACK MSB
ACK
LSB
tiicirqh
tiicirql
tiicsu
tiich
tiiccbsyl
Figure 5. Serial Control Port - I2C Slave Mode Timing
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CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
2
5.12 Switching Characteristics — Serial Control Port - I C Master Mode
Parameter
Symbol
Min
—
Max
400
—
Units
kHz
µs
SCP_CLK frequency1
SCP_CLK low time
SCP_CLK high time
f
iicck
t
1.25
1.25
1.25
iicckl
t
—
µs
iicckh
SCP_SCK rising to SCP_SDA rising or falling for START or STOP
condition
t
—
µs
iicckcmd
START condition to SCP_CLK falling
t
1.25
2.5
3
—
—
—
—
—
36
µs
µs
µs
ns
ns
ns
iicstscl
SCP_CLK falling to STOP condition
t
iicstp
Bus free time between STOP and START conditions
Setup time SCP_SDA input valid to SCP_CLK rising
Hold time SCP_SDA input after SCP_CLK falling2
SCP_CLK low to SCP_SDA out valid
t
iicbft
iicsu
t
100
0
t
iich
t
—
iicdov
1. The specification fiicck indicates the maximum speed of the hardware. The system designer should be aware that the actual
maximum speed of the communication port may be limited by the firmware application.
2. This parameter is measured from the ViL level at the falling edge of the clock.
tiicckcmd
t
tiicr
t
iicf
tiicckcmd
iicckl
0
1
6
7
8
0
1
6
7
8
SCP_CLK
SCP_SDA
t
iicstp
tiicstscl
t
tiicdov
R/W
fiicck
tiicb
iicckh
A6
A0
ACK MSB
ACK
LSB
tiicsu
tiich
Figure 6. Serial Control Port - I2C Master Mode Timing
5.13 Switching Characteristics — Parallel Control Port - Intel Slave Mode
Parameter
Symbol Min
Typical
Max Unit
Address setup before PCP_CS and PCP_RD low or PCP_CS and
PCP_WR low
t
5
—
—
ns
ias
Address hold time after PCP_CS and PCP_RD low or PCP_CS and
PCP_WR high
t
5
—
—
ns
iah
Read
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CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
Parameter
Symbol Min
Typical
Max Unit
Delay between PCP_RD then PCP_CS low or PCP_CS then
PCP_RD low
t
0
—
—
ns
icdr
Data valid after PCP_CS and PCP_RD low
PCP_CS and PCP_RD low for read
t
—
24
8
—
—
—
—
—
18
—
—
18
—
ns
ns
ns
ns
ns
idd
t
irpw
Data hold time after PCP_CS or PCP_RD high
Data high-Z after PCP_CS or PCP_RD high
t
idhr
t
—
30
idis
PCP_CS or PCP_RD high to PCP_CS and PCP_RD low for next
read1
t
ird
PCP_CS or PCP_RD high to PCP_CS and PCP_WR low for next
write1
t
30
—
—
—
—
ns
ns
irdtw
t
12
PCP_RD rising to PCP_IRQ rising
irdirqhl
Write
Delay between PCP_WR then PCP_CS low or PCP_CS then
PCP_WR low
t
0
—
—
ns
icdw
Data setup before PCP_CS or PCP_WR high
PCP_CS and PCP_WR low for write
t
8
24
8
—
—
—
—
—
—
—
—
ns
ns
ns
ns
idsu
t
iwpw
Data hold after PCP_CS or PCP_WR high
t
idhw
iwtrd
PCP_CS or PCP_WR high to PCP_CS and PCP_RD low for next
read1
t
30
PCP_CS or PCP_WR high to PCP_CS and PCP_WR low for next
write1
t
30
—
—
—
—
ns
ns
iwd
t
2*DCLKP + 20
PCP_WR rising to PCP_BSY falling
iwrbsyl
1. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware
application. Hardware handshaking on the PCP_BSY pin/bit should be observed to prevent overflowing the input data buffer.
CS4953x4/CS4970x4 System Designer’s Guide should be consulted for the firmware speed limitations.
PCP_A[3:0]
tiah
LSP
tidhr
MSP
PCP_D[7:0]
PCP_CS#
PCP_WR#
PCP_RD#
PCP_IRQ#
tias
tidd
ticdr
tidis
tirpw
tird
tirdtw
tirdirqh
Figure 7. Parallel Control Port - Intel Slave Mode Read Cycle
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CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
PCP_A[3:0]
PCP_D[7:0]
PCP_CS#
PCP_RD#
PCP_WR#
PCP_BSY#
tiah
LSP
MSP
tias
tidhw
ticdw
tidsu
tiwpw
tiwd
tiwtrd
tiwrbsyl
Figure 8. Parallel Control Port - Intel Slave Mode Write Cycle
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CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
5.14 Switching Characteristics — Parallel Control Port - Motorola Slave Mode
Symbo
l
Parameter
Min
5
Typical
—
Max
—
Unit
ns
Address setup before PCP_CS and PCP_DS low
Address hold time after PCP_CS and PCP_DS low
t
mas
mah
t
5
—
—
ns
Read
Delay between PCP_DS then PCP_CS low or PCP_CS then
PCP_DS low
t
0
—
—
ns
mcdr
Data valid after PCP_CS and PCP_DS low with PCP_R/W high
PCP_CS and PCP_DS low for read
t
—
24
8
—
—
—
—
—
19
—
—
18
—
ns
ns
ns
ns
ns
mdd
t
mrpw
Data hold time after PCP_CS or PCP_DS high after read
Data high-Z after PCP_CS or PCP_DS high after read
t
mdhr
t
—
30
mdis
PCP_CS or PCP_DS high to PCP_CS and PCP_DS low for next
read1
t
mrd
PCP_CS or PCP_DS high to PCP_CS and PCP_DS low for next
write1
t
30
—
—
—
—
ns
ns
mrdtw
t
12
PCP_RW rising to PCP_IRQ falling
mrwirqh
Write
Delay between PCP_DS then PCP_CS low or PCP_CS then
PCP_DS low
t
0
—
—
ns
mcdw
Data setup before PCP_CS or PCP_DS high
PCP_CS and PCP_DS low for write
t
8
24
24
8
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
mdsu
t
mwpw
mrwsu
PCP_R/W setup before PCP_CS AND PCP_DS low
PCP_R/W hold time after PCP_CS or PCP_DS high
Data hold after PCP_CS or PCP_DS high
t
t
mrwhld
t
8
mdhw
mwtrd
PCP_CS or PCP_DS high to PCP_CS and PCP_DS low with
PCP_R/W high for next read1
t
30
PCP_CS or PCP_DS high to PCP_CS and PCP_DS low for next
write1
t
30
—
—
ns
ns
mwd
t
—
2*DCLKP + 20
—
PCP_RW rising to PCP_BSY falling
mrwbsyl
1. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware
application. Hardware handshaking on the PCP_BSY pin/bit should be observed to prevent overflowing the input data buffer.
CS4953x4/CS4970x4 System Designer’s Guide should be consulted for the firmware speed limitations.
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CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
PCP_A[3:0]
PCP_AD[7:0]
PCP_CS#
tmas
tmah
LSP
tmdhr
MSP
tmdd
tmrwsu
tmcdr
tmdis
tmrwhld
PCP_WR#
PCP_DS#
tmrdtw
tmrpw
tmrd
tmrwirqh
PCP_IRQ#
Figure 9. Parallel Control Port - Motorola Slave Mode Read Cycle Timing
PCP_A[3:0]
tmas
t
mah
LSP
tmdsu
MSP
PCP_AD[7:0]
PCP_CS#
PCP_WR#
PCP_DS#
PCP_IRQ#
tmdhw
tmrwhld
tmwpw
tmcdw
tmrwsu
tmwd
tmwtrd
tmrwirql
Figure 10. Parallel Control Port - Motorola Slave Mode Write Cycle Timing
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CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
5.15 Switching Characteristics — Digital Audio Slave Input Port
Parameter
Symbol
Min
40
45
10
10
10
5
Max
—
Unit
ns
%
DAI_SCLK period
T
daiclkp
DAI_SCLK duty cycle
—
55
—
DAI_LRCLK transition from DAI_SCLK active edge
DAI_SCLK active edge from DAI_LRCLK transition
Setup time DAI_DATAn
t
t
ns
ns
ns
ns
daisstlr
daislrts
—
t
—
daidsu
Hold time DAI_DATAn
t
—
daidh
Note: In these diagrams, falling edge is the inactive edge of DAI_SCLK.
DAI_SCLK
tdaidsu
tdaidh
DAI_DATAn
Figure 11. Digital Audio Input (DAI) Port Timing Diagram
Tdaiclkp
tdaislrts
DAI_LRCLK
DAI_LRCLK
DAI_SCLK
DAI_SCLK
Tdaiclkp
tdaisstlr
DAIn_DATAn
DAIn_DATAn
Figure 12. DAI Slave Timing Diagram
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CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
5.16 Switching Characteristics — Digital Audio Output Port
Parameter
Symbol
Min
40
Max
—
Unit
ns
DAO_MCLK period
T
daomclk
—
DAO_MCLK duty cycle
45
55
—
%
DAO_SCLK period for Master or Slave mode1
DAO_SCLK duty cycle for Master or Slave mode1
T
40
ns
daosclk
—
40
60
%
1,2
Master Mode (Output A1 Mode)
DAO_SCLK delay from DAO_MCLK rising edge,
DAO_MCLK as an input
t
t
—
19
ns
daomsck
DAO_SCLK delay from DAO_LRCLK transition3
DAO_LRCLK delay from DAO_SCLK transition3
t
—
—
—
8
8
ns
ns
ns
daomlrts
daomstlr
DAO1_DATA[3..0], DAO2_DATA[1..0]
delay from DAO_SCLK transition3
t
10
daomdv
4
Slave Mode (Output A0 Mode)
DAO_SCLK active edge to DAO_LRCLK transition
DAO_LRCLK transition to DAO_SCLK active edge
DAO_Dx delay from DAO_SCLK inactive edge
t
10
10
—
—
—
ns
ns
ns
daosstlr
t
daoslrts
t
12.5
daosdv
1. Master mode timing specifications are characterized, not production tested.
2. Master mode is defined as the CS4970x4 driving both DAO_SCLK, DAO_LRCLK. When MCLK is an input, it is divided to produce
DAO_SCLK, DAO_LRCLK.
3. This timing parameter is defined from the non-active edge of DAO_SCLK. The active edge of DAO_SCLK is the point at which the
data is valid.
4. Slave mode is defined as DAO_SCLK, DAO_LRCLK driven by an external source.
tdaomlclk
tdaomlclk
DAO_MCLK
DAO_SCLK
DAO_MCLK
DAO_SCLK
tdaomsck
tdaomsck
tdaomdv
tdaomdv
DAOn_DATAn
DAO_LRCLK
DAOn_DATAn
DAO_LRCLK
tdaomlrts
tdaomlrts
Note: In these diagrams, falling edge is the inactive edge of DAO_SCLK.
Figure 13. Digital Audio Port Output Timing Master Mode
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CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
tdaosclk
DAO_LRCLK
DAO_SCLK
DAO_LRCLK
tdaoslrts
DAO_SCLK
tdaosclk
tdaosstlr
tdaosdv
DAO_Dx
DAO_Dx
Note: In these diagrams, Falling edge is the inactive edge of DAO_SCLK
Figure 14. Digital Audio Output Timing, Slave Mode (Relationship LRCLK to SCLK)
5.17 Switching Characteristics — SDRAM Interface
Refer to Figure 15 through Figure 18.
(SD_CLKOUT = SD_CLKIN)
Parameter
Symbol
Min
2.3
2.3
—
Typical
—
Max
Unit
ns
SD_CLKIN high time
SD_CLKIN low time
t
—
—
1
sdclkh
t
—
ns
sdclkl
SD_CLKOUT rise/fall time
t
—
ns
sdclkrf
SD_CLKOUT Frequency
—
—
150
—
—
55
3.8
—
—
—
—
—
—
MHz
%
SD_CLKOUT duty cycle
—
45
—
SD_CLKOUT rising edge to signal valid
Signal hold from SD_CLKOUT rising edge
SD_CLKOUT rising edge to SD_DQMn valid
SD_DQMn hold from SD_CLKOUT rising edge
SD_DATA valid setup to SD_CLKIN rising edge
SD_DATA valid hold to SD_CLKIN rising edge
SD_CLKOUT rising edge to ADDRn valid
t
—
ns
sdcmdv
t
—
1.1
3.8
—
ns
sdcmdh
t
—
ns
sddqv
t
1.38
1.3
2.1
—
ns
sddqh
t
—
ns
sddsu
t
—
ns
sddh
t
3.8
ns
sdav
DS752F1
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SD_CLKOUT
SD_CS#
tsdclkrf
tsdcmdv
tsdcmdh
SD_RAS#
SD_CAS#
SD_WE#
tsddqh
tsddqv
SD_DQMn
11
00
SD_An
tsdav
tsddsu
tsddh
CAS=2
LSP1
MSP1
LSP2
MSP2
SD_Dn
LSP0
MSP0
LSP3
MSP3
SD_CLKIN
tsdclkl
tsdclkh
Figure 15. External Memory Interface - SDRAM Burst Read Cycle
SD_CLKOUT
tsdcmdv
tsdcmdh
SD_CS#
SD_RAS#
SD_CAS#
SD_WE#
LSP0
MSP0
LSP1
MSP1
LSP2
MSP2
LSP3
MSP3
SD_Dn
SD_An
tsdav
SD_DQMn
00
11
tsddqv
tsddqh
Figure 16. External Memory Interface - SDRAM Burst Write Cycle
CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
SD_CLKOUT
tsdcmdv
tsdcmdv
tsdcmdh
SD_CS#
SD_RAS#
SD_CAS#
SD_WE#
SD_DQMn
SD_An
SD_Dn
Figure 17. External Memory Interface - SDRAM Auto Refresh Cycle
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CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
SD_CLKOUT
tsdcmdv
tsdcmdh
SD_CS#
SD_RAS#
SD_CAS#
SD_WE#
SD_DQMn
SD_An
OPCODE
SD_Dn
Figure 18. External Memory Interface - SDRAM Load Mode Register Cycle
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CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
6 Ordering Information
The CS4970x4 family part number is described as follows:
CS497NNI-XYZ
where
NN - Product Number Variant
I - ROM ID Number
X - Product Grade
Y - Package Type
Z - Lead (Pb) Free
Table 4. Ordering Information
Grade
Part No.
Status
Temp. Range
Package
CS497014-CVZ
Active
Active
Active
Active
Commercial
Commercial
Commercial
Commercial
0 to +70 °C
0 to +70 °C
0 to +70 °C
0 to +70 °C
128-pin LQFP
1
CS47014-CVZR
CS497024-CVZ
CS497024-CVZR
128-pin LQFP
1
1. R = Tape and reel
Note: Please contact the factory for availability of the -D (automotive grade) package.
7 Environmental, Manufacturing, and Handling Information
Table 5. Environmental, Manufacturing, & Handling Information
Model Number
Peak Reflow Temp
MSL Rating*
Max Floor Life
CS497014-CVZ
CS47014-CVZR
CS497024-CVZ
CS497024-CVZR
260 °C
260 °C
260 °C
260 °C
3
3
3
3
7 Days
7 Days
7 Days
7 Days
* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
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CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
8 Device Pin-Out Diagram
8.1 128-Pin LQFP Pin-Out Diagram
1
5
SD_A0, EXT_A0
SD_A1, EXT_A1
GPIO38, PCP_WR# / DS#, SCP2_CLK
GPIO11, PCP_A3, AS#, SCP2_MISO / SDA
100
GPIO10, PCP_A2 / A10, SCP2_MOSI
VDDIO5
SD_A2, EXT_A2
GND4
GPOI9, SCP1_IRQ#
GPIO8, PCP_IRQ#, SCP2_IRQ#
SD_A3, EXT_A3
SD_A4, EXT_A4
95 VDD4
GPIO7, SCP1_CS#, IOWAIT
GPIO6, PCP_CS#, SCP2_CS#
VDDIO7
EXT_CS2#
GNDIO7
SD_A5, EXT_A5
GNDIO4
10
15
20
25
30
35
GPIO3, DDAC
GPIO2
SD_A6, EXT_A6
90 SD_A7, EXT_A7
VDDIO4
VDD7
GPIO1
GPIO0, EE_CS#
SD_A8, EXT_A8
SD_A9, EXT_A9
GND3
GND7
XTAL_OUT
XTI
85 SD_A11, EXT_A11
SD_A12, EXT_A12
VDD3
XTO
GNDA
CS497xx4
128-Pin LQFP
PLL_REF_RES
SD_CLKEN
SD_CLKIN
VDDA (3.3V)
VDD8
80 SD_CLKOUT
SD_DQM1
GPIO14, DAI1_DATA3, TM3, DSD3
GPIO13, DAI1_DATA2, TM2, DSD2
GND8
SD_D8, EXT_D8
SD_D9, EXT_D9
GNDIO3
GPIO12, DAI1_DATA1, TM1, DSD1
DAI1_DATA0, TM0, DSD0
VDDIO8
75 SD_D10, EXT_D10
SD_D11, EXT_D11
VDDIO3
DAI1_SCLK, DSD_CLK
DAI1_LRCLK, DSD4
SD_D12, EXT_D12
SD_D13, EXT_D13
70 SD_D14, EXT_D14
SD_D15, EXT_D15
SD_D0, EXT_D0
GNDIO8
GPIO42, BDI_REQ# , DAI2_LRCLK, PCP_IRQ# / BSY#
GPIO43, BDI_CLK, DAI2_SCLK
BDI_DATA, DAI2_DATA, DSD5
GPIO26, DAO2_DATA3 / XMTB
GNDIO2
DBDA
DBCK
EXT_WE#
65 SD_D1, EXT_D1
GPIO20, DAO2_DATA2
Figure 19. 128-Pin LQFP Pin-Out Diagram
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CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
9 Package Mechanical Drawings
9.1 128-Pin LQFP Package Drawing
D
D1
E1
E
1
e
b
A
A1
L
Figure 20. 128-Pin LQFP Package Drawing
Table 6. 128-Pin LQFP Package Characteristics
MILLIMETERS
INCHES
NOM
DIM
MIN
NOM
MAX
MIN
MAX
A
A1
b
—
—
1.60
0.15
0.27
—
—
—
.063”
.006”
.011”
0.05
0.17
—
.002”
.007”
0.22
.009”
.866”
.787”
.630”
.551”
.020”
3.5
D
22.00 BSC
20.00 BSC
16.00 BSC
14.00 BSC
0.50 BSC
3.5
D1
E
E1
e
q
0°
7°
0°
7°
L
0.45
0.60
0.75
.018”
.024”
.039” REF
.030”
L1
1.00 REF
TOLERANCES OF FORM AND POSITION
ddd
0.08
.003”
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CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
10 Revision History
Revision
Date
Changes
PP9
November, 2010
Added “Status” column and footnote 1 to Table 4.
Added Tj conditions to Section 5.2.
Changed 500 ma to 350 ma in Section 5.4.
Updated Section 5.15 “Switching Characteristics — Digital Audio Slave Input Port”
on page 21.
PP10
March, 2011
Updated Section 5.16 “Switching Characteristics — Digital Audio Output Port” on
page 22.
Added max internal DCLK frequency and min internal DCLK period to Section 5.8.
Added notes to Section 5.9. Updated tspickl and tspickh values in Section 5.10.
Updated tdaosdv max value in Section 5.16.
PP11
February, 2012
PP12
F1
October, 2013
February, 2014
Updated note in Section 2 overview. Minor change to Section 2.1 title.
Updated note in Section 2 overview regarding CS4970x4. Changed status of
CS497024-CVZ and CS497024-CVZR to “Active” in Table 4.
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CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find the one nearest you, go to www.cirrus.com.
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to
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Cirrus Logic, Cirrus, Cirrus Logic logo designs, Cirrus Framework, and DSP Condenser are trademarks of Cirrus Logic, Inc. All other brand and product names in this
document may be trademarks or service marks of their respective owners.
THX is a registered trademark of THX, Ltd. THX Select 2 and THX Ultra 2 are trademarks of THX, Ltd.
Dolby, Dolby Digital, Dolby Headphone, Virtual Speaker, Pro Logic, Audistry, and Dolby Volume are registered trademarks of Dolby Laboratories, Inc. AAC, AC-3,
Dolby TrueHD, and Dolby Volume 258 are trademarks of Dolby Laboratories, Inc. Supply of an implementation of Dolby Technology does not convey a license nor
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DTS and DTS Neo:6 are registered trademarks of the Digital Theater Systems, Inc. DTS-ES 96/24, DTS-ES, DTS 6.1, DTS 96/24, DTS Neural Surround, and DTS
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SRS, SRS 3D, SRS CS Auto, SRS CS Headphone, SRS Circle Cinema 3D, SRS Circle Surround, SRS Circle Surround II, SRS GEQ, SRS Hardlimiter, SRS
Headphone, SRS Headphone 360, SRS HPF, SRS StudioSound HD, SRS TruEQ, SRS TruMedia, SRS TruSurround, SRS TruSurround XT, SRS TruSurround HD,
SRS TruSurround HD4, SRS TruVolume, SRS VIP+, SRS WOW, SRS WOW XT, SRS WOW HD are either trademarks or registered trademarks of SRS Labs, Inc.
SRS, SRS 3D, SRS CS Auto, SRS CS Headphone, SRS Circle Cinema 3D, SRS Circle Surround, SRS Circle Surround II, SRS GEQ, SRS Hardlimiter, SRS
Headphone, SRS Headphone 360, SRS HPF, SRS StudioSound HD, SRS TruEQ, SRS TruMedia, SRS TruSurround, SRS TruSurround XT, SRS TruSurround HD,
SRS TruSurround HD4, SRS TruVolume, SRS VIP+, SRS WOW, SRS WOW XT, SRS WOW HD technologies are incorporated under license from SRS Labs, Inc.
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Headphone, SRS Headphone 360, SRS HPF, SRS StudioSound HD, SRS TruEQ, SRS TruMedia, SRS TruSurround, SRS TruSurround XT, SRS TruSurround HD,
SRS TruSurround HD4, SRS TruVolume, SRS VIP+, SRS WOW, SRS WOW XT, SRS WOW HD technologies incorporated in the Cirrus Logic CS4953xx products
are owned by SRS Labs, a U.S. Corporation and licensed to Cirrus Logic, Inc. Purchaser of Cirrus Logic CS4953xx products must sign a license for use of the chip
and display of the SRS Labs trademarks. Any products incorporating the Cirrus Logic CS4953xx products must be sent to SRS Labs for review. SRS, SRS 3D, SRS
CS Auto, SRS CS Headphone, SRS Circle Cinema 3D, SRS Circle Surround, SRS Circle Surround II, SRS GEQ, SRS Hardlimiter, SRS Headphone, SRS Headphone
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TruVolume, SRS VIP+, SRS WOW, SRS WOW XT, SRS WOW HD technologies are protected under US and foreign patents issued and/or pending. Neither the
purchase of the Cirrus Logic CS4953xx products, nor the corresponding sale of audio enhancement equipment conveys the right to sell commercialized recordings
made with any SRS technology/solution. SRS Labs requires all set makers to comply with all rules and regulations as outlined in the SRS Trademark Usage Manual.
Motorola is a registered trademark of Motorola, Inc. SPI is a trademark of Motorola, Inc.
Intel is a registered trademark of Intel Corporation.
I2C is a trademark of Philips Semiconductor.
DS752F1
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相关型号：
CS497024-CVZR
High Definition Audio Decoder DSP Family with Dual 32-bit DSP Engine Technology
CIRRUS
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