CS5467-ISZR [CIRRUS]
Analog Circuit, 1 Func, CMOS, PDSO28, LEAD FREE, MO-150, SSOP-28;型号: | CS5467-ISZR |
厂家: | CIRRUS LOGIC |
描述: | Analog Circuit, 1 Func, CMOS, PDSO28, LEAD FREE, MO-150, SSOP-28 光电二极管 |
文件: | 总46页 (文件大小:373K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CS5467
Four-channel Power/Energy IC
Features & Description
Description
• Energy Linearity: ±0.1% of Reading over 1000:1
Dynamic Range
• On-chip Functions:
The CS5467 is a watt-hour meter on a chip. It
measures line voltage and current and calcu-
lates active, reactive, apparent power, energy,
power factor, and RMS voltage and current.
- Voltage and Current Measurement
- Active, Reactive, and Apparent Power/Energy
- RMS Voltage and Current Calculations
- Current Fault and Voltage Sag Detection
- Calibration
An internal RMS voltage reference can be used
if voltage measurement is disabled by
tampering.
- Phase Compensation
Four analog-to-digital converters are used to
measure two voltages and two currents. Option-
ally, voltage2 channel can be used for
temperature measurement.
- Temperature Sensor
- Energy Pulse Outputs
• Meets Accuracy Spec for IEC, ANSI, & JIS
• Low Power Consumption
• Voltage Tamper Correction
The CS5467 is designed to interface to a variety
of voltage and current sensors.
• Ground-referenced Inputs with Single Supply
• On-chip 2.5 V Reference (40 ppm / °C typ.)
• Power Supply Monitor Function
• Three-wire Serial Interface to Microcontroller or
E2PROM
Additional features include system-level calibra-
tion, voltage sag and current fault detection,
peak detection, phase compensation, and ener-
gy pulse outputs.
• Power Supply Configurations
GND: 0 V, VA+: +5 V, VD+: +3.3 V to +5 V
ORDERING INFORMATION
See Page 45.
VA+
RESET
VD+
IIN1+
IIN1-
4th Order
Modulator
Digital
Filter
HPF
Option
PGA
x10
MODE
CS
SDI
VIN1+
VIIN1-
2nd Order
Modulator
SDO
SCLK
INT
Digital
Filter
HPF
Option
Serial
Interface
Power
Calculation
Engine
E1
E2
E3
IIN2+
IIN2-
4th Order
Modulator
Digital
Filter
HPF
Option
E-to-F
PGA
VIN2+
VIN2-
2nd Order
Modulator
Digital
Filter
HPF
Option
Calibration
x10
x1
VREFIN
Temperature
Sensor
System
Clock
Clock
Generator
Power
Monitor
/K
Voltage
VREFOUT
Reference
PFMON
XIN XOUT CPUCLK
DGND
AGND
JAN ‘11
DS714F3
Copyright Cirrus Logic, Inc. 2011
http://www.cirrus.com
(All Rights Reserved)
CS5467
TABLE OF CONTENTS
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2. Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Control Pins and Serial Data I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Analog Inputs/Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3. Characteristics & Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Analog Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Analog Inputs (All Inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Analog Inputs (Current Inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Analog Inputs (Voltage Inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Reference Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Reference Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Digital Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Master Clock Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Input/Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Serial Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SDI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SDO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
E2PROM mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
E1, E2, and E3 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4. Signal Path Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1 Analog-to-Digital Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2 Decimation Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.3 Phase Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.4 DC Offset and Gain Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.5 High-pass Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.6 Low-Rate Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.7 RMS Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.8 Power and Energy Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.9 Peak Voltage and Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.10 Power Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1 Analog Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1.1 Voltage1 & Voltage2 Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1.2 Current1 & Current2 Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1.3 Power Fail Monitor Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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5.1.4 Voltage Reference Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1.5 Voltage Reference Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1.6 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2 Digital Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2.1 Reset Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2.2 CPU Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2.3 Interrupt Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2.4 Energy Pulse Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2.5 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6. Setting Up the CS5467 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.1 Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.2 CPU Clock Inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.3 Interrupt Pin Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.4 Current Input Gain Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.5 High-pass Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.6 Cycle Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.7 Energy Pulse Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.8 No Load Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.9 Energy Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.10 Energy Pulse Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.11 Voltage Sag/Current Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.12 Epsilon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.13 Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7. Using the CS5467 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.2 Power-down States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.3 Voltage Tamper Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.4 Command Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.5 Register Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.6 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.1 Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.2 Page 0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.3 Page 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.4 Page 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.5 Page 5 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9. System Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.1 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.1.1 Offset Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.1.1.1 DC Offset Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.1.1.2 AC Offset Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.1.2 Gain Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.1.2.1 AC Gain Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.1.2.2 DC Gain Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
DS714F3
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CS5467
9.1.3 Calibration Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.1.4 Temperature Sensor Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.1.4.1 Temperature Offset Calibration . . . . . . . . . . . . . . . . . . . . . . . 41
9.1.4.2 Temperature Gain Calibration . . . . . . . . . . . . . . . . . . . . . . . . 41
10. E2PROM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2
10.1 E PROM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2
10.2 E PROM Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2
10.3 Which E PROMs Can Be Used? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
11. Basic Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
12. Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
13. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
14. Environmental, Manufacturing, & Handling Information . . . . . . . . . . . . . . . . . 45
15. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
LIST OF FIGURES
Figure 1. CS5467 Read and Write Timing Diagrams ................................................................. 12
Figure 2. Timing Diagram for E1, E2, and E3 .............................................................................. 13
Figure 3. Signal Flow for V1, I1, P1, Q1 Measurements ............................................................ 14
Figure 4. Signal Flow for V2, I2, P2, Q2 Measurements ............................................................ 14
Figure 5. Low-rate Calculations.................................................................................................. 16
Figure 6. Two-channel Power Summation.................................................................................. 16
Figure 7. Oscillator Connections................................................................................................. 18
Figure 8. Sag and Fault Detect................................................................................................... 22
Figure 9. Fixed RMS Voltage Selection...................................................................................... 23
Figure 10. Calibration Data Flow ................................................................................................ 40
Figure 11. System Calibration of Offset...................................................................................... 40
Figure 12. System Calibration of Gain........................................................................................ 41
Figure 13. Typical Interface of E2PROM to CS5467 .................................................................. 42
Figure 14. Typical Connection Diagram ..................................................................................... 43
LIST OF TABLES
Table 1. Interrupt Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 2. Current Input Gain Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 3. High-pass Filter Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 4. E2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 5. E3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 6. E1 / E2 Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 7. E3 Pin with E1MODE enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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CS5467
1. OVERVIEW
The CS5467 is a CMOS power measurement integrated circuit utilizing four analog-to-digital convert-
ers to measure two line voltages and two currents. Optionally, voltage2 channel can be used for temper-
ature measurement. It calculates active, reactive, and apparent power as well as RMS and peak voltage
and current. It handles other system-related functions, such as pulse output conversion, voltage sag, cur-
rent fault, voltage zero crossing, line frequency, and voltage tamper correction.
The CS5467 is optimized to interface to current transformers or shunt resistors for current measurement,
and to resistive dividers or voltage transformers for voltage measurement. Two full-scale ranges are pro-
vided on the current inputs to accommodate both types of current sensors. The CS5467’s four differential
inputs have a common-mode input range from analog ground (AGND) to the positive analog supply
(VA+).
An additional analog input (PFMON) is provided to allow the application to determine when a power failure
is in progress. By monitoring the unregulated power supply, the application can take any required action
when a power loss occurs.
An on-chip voltage reference (nominally 2.5 volts) is generated and provided at analog output, VREFOUT.
This reference can be supplied to the chip by connecting it to the reference voltage input, VREFIN. Alter-
natively, an external voltage reference can be supplied to the reference input.
Three digital outputs (E1, E2, E3) provide a variety of output signals and, depending on the mode select-
ed, provide energy pulses, power failure indication, or other choices.
The CS5467 includes a three-wire serial host interface to an external microcontroller or serial E2PROM.
Signals include serial data input (SDI), serial data output (SDO), serial clock (SCLK), and optionally a chip
select (CS), which allows the CS5467 to share the SDO signal with other devices. A MODE input is used
to control whether an E2PROM will be used instead of a host microcontroller.
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CS5467
2. PIN DESCRIPTION
Crystal Out
XOUT
CPUCLK
VD+
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
XIN
SDI
Crystal In
CPU Clock Output
Positive Digital Supply
Digital Ground
Serial Data Input
Energy Output 2
Energy Output 1
Interrupt
E2
E1
INT
RESET
E3
PFMON
IIN1+
IIN1-
VA+
AGND
IIN2+
IIN2-
DGND
SCLK
SDO
Serial Clock
Serial Data Ouput
Chip Select
Reset
CS
Energy Output 3
Power Fail Monitor
Differential Current Input
Differential Current Input
Positive Analog Supply
Analog Ground
Mode Select
Differential Voltage Input
Differential Voltage Input
MODE
VIN1+
VIN1-
9
10
11
12
13
14
Voltage Reference Output VREFOUT
Voltage Reference Input
Differential Voltage Input
Differential Voltage Input
VREFIN
VIN2+
VIN2-
Differential Current Input
Differential Current Input
Clock Generator
Crystal Out
Crystal In
XOUT, XIN — Connect to an external quartz crystal. Alternatively, an external clock can be sup-
plied to the XIN pin to provide the system clock for the device.
1,28
2
CPU Clock Output
CPUCLK — Logic-level output from crystal oscillator. Can be used to clock an external CPU.
Control Pins and Serial Data I/O
SCLK — Clocks serial data from the SDI pin and to the SDO pin when CS is low. SCLK is a
Schmitt-trigger input when MODE is low and a driven output when MODE is high.
Serial Clock
5
6
7
Serial Data Output
Chip Select
SDO — Serial data output. Data is clocked out by SCLK.
CS — An input that enables the serial interface when MODE is low and a driven output when
MODE is high.
MODE — High selects external E2PROM, Low selects external microcontroller. MODE includes a
weak internal pull-down and therefore selects microcontroller mode if not connected.
Mode Select
8
22, 25,
26
E3, E1, E2 — Primarily active-low energy pulse outputs. These can be programmed to output
other conditions.
Energy Output
Reset
23
24
27
RESET — An active-low Schmitt-trigger input used to reset the chip.
INT — Active-low output, indicates that an enabled condition has occurred.
SDI — Serial data input. Data is clocked in by SCLK.
Interrupt
Serial Data Input
Analog Inputs/Outputs
9,10
13, 14
Differential Voltage Inputs
VIN1+, VIN1-, VIN2+, VIN2- — Differential analog inputs for the voltage channels.
20,19,
16,15
Differential Current Inputs
Voltage Reference Output
Voltage Reference Input
IIN1+, IIN1-, IIN2+, IIN2- — Differential analog inputs for the current channels.
11
VREFOUT — The on-chip voltage reference output. Nominally 2.5 V, referenced to AGND.
VREFIN — The voltage reference input. Can be connected to VREFOUT or external 2.5 V refer-
ence.
12
Power Supply Connections
Positive Digital Supply
Digital Ground
3
4
VD+ — The positive digital supply.
DGND — Digital ground.
Positive Analog Supply
Analog Ground
18
17
VA+ — The positive analog supply.
AGND — Analog ground.
PFMON — Used to monitor the unregulated power supply via a resistive divider. If the PFMON
voltage drops below its low limit, the low-supply detect (LSD) bit is set in the Status register.
Power Fail Monitor
21
6
DS714F3
CS5467
3. CHARACTERISTICS & SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
Parameter
Positive Digital Power Supply
Positive Analog Power Supply
Voltage Reference
Symbol
VD+
Min
3.135
4.75
-
Typ
5.0
5.0
2.5
-
Max
Unit
V
5.25
5.25
-
VA+
V
VREFIN
V
Specified Temperature Range
T
-40
+85
°C
A
ANALOG CHARACTERISTICS
• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.
• Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.
• VA+ = VD+ = 5 V ±5%; AGND = DGND = 0 V; VREFIN = +2.5 V. All voltages with respect to 0 V.
• DCLK = 4.096 MHz.
Parameter
Symbol
Min
Typ
Max
Unit
Accuracy
Active Power
(Note 1)
All Gain Ranges
Input Range 0.1% - 100%
P
ACTIVE
-
-
±0.1
±0.2
-
-
%
%
Reactive Power
(Note 1 and 2)
All Gain Ranges
Input Range 0.1% - 100%
Q
AVG
Power Factor
(Note 1 and 2)
All Gain Ranges
Input Range 1.0% - 100%
PF
-
-
±0.2
±0.27
-
-
%
%
Input Range 0.1% - 1.0%
Current RMS
(Note 1)
All Gain Ranges
Input Range 1.0% - 100%
Input Range 0.1% - 1.0%
%
%
%
I
-
-
±0.1
±0.17
-
-
RMS
Voltage RMS
(Note 1)
All Gain Ranges
Input Range 5% - 100%
V
RMS
-
±0.1
-
%
Analog Inputs (All Inputs)
Common Mode Rejection
Common Mode + Signal
(DC, 50, 60 Hz)
CMRR
80
-
-
-
dB
V
-0.25
VA+
Analog Inputs (Current Inputs)
Differential Input Range
[(IIN+) – (IIN-)]
(Gain = 10)
(Gain = 50)
-
-
500
100
-
-
mV
mV
P-P
P-P
IIN
Total Harmonic Distortion
(Gain = 50)
THD
80
-
94
-115
27
-
-
-
-
-
dB
Crosstalk from Voltage input at Full Scale
Input Capacitance
(50, 60 Hz)
dB
pF
k
IC
-
Effective Input Impedance
Noise (Referred to Input)
EII
30
(Gain = 10)
(Gain = 50)
-
-
-
-
22.5
4.5
µV
rms
rms
N
I
µV
Offset Drift (Without the High-pass Filter)
Gain Error
OD
GE
-
-
4.0
-
µV/°C
%
(Note 3)
±0.4
Notes: 1. Applies when the HPF option is enabled.
2. Applies when the line frequency is equal to the product of the output word rate (OWR) and the value of
Epsilon.
DS714F3
7
CS5467
ANALOG CHARACTERISTICS (Continued)
Parameter
Symbol
Min
Typ
Max
Unit
mV
Analog Inputs (Voltage Inputs)
Differential Input Range
[(VIN+) – (VIN-)]
VIN
-
500
-
P-P
Total Harmonic Distortion
Crosstalk from Current inputs at Full Scale
Input Capacitance
THD
65
-
75
-70
2.0
-
-
dB
dB
(50, 60 Hz)
-
All Gain Ranges
IC
-
-
-
pF
Effective Input Impedance
Noise (Referred to Input)
EII
2
-
M
µV
rms
N
-
140
V
Offset Drift (Without the High-pass Filter)
Gain Error
OD
GE
-
-
16.0
±3.0
-
µV/°C
%
(Note 3)
Temperature
Temperature Accuracy
Power Supplies
T
-
±5
-
°C
Power Supply Currents (Active State)
IA+
PSCA
PSCD
PSCD
-
-
-
1.5
3.5
2.3
-
-
-
mA
mA
mA
ID+ (VA+ = VD+ = 5 V)
I
D+ (VA+ = 5 V, VD+ = 3.3 V)
Power Consumption
(Note 4)
Active State (VA+ = VD+ = 5 V)
Active State (VA+ = 5 V, VD+ = 3.3 V)
-
-
-
-
25
15
7
33
20
-
mW
mW
mW
uW
PC
Stand-by State
Sleep State
10
-
Power Supply Rejection Ratio (50, 60 Hz)
(Note 5)
Voltage
Current (Gain = 50x)
Current (Gain = 10x)
48
68
60
55
75
65
-
-
-
dB
dB
dB
PSRR
PFMON Low-voltage Trigger Threshold
(Note 6)
PMLO
PMHI
2.3
-
2.45
2.55
-
V
V
PFMON High-voltage Power-on Trip Point
(Note 7)
2.7
Notes: 3. Applies before system calibration.
4. All outputs unloaded. All inputs CMOS level.
5. Measurement method for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 5 V, a 150 mV
(zero-to-peak) (60 Hz) sinewave is imposed onto the +5 V DC supply voltage at VA+ and VD+ pins. The
“+” and “-” input pins of both input channels are shorted to AGND. The CS5467 is then commanded to
continuous conversion acquisition mode, and digital output data is collected for the channel under test.
The (zero-to-peak) value of the digital sinusoidal output signal is determined, and this value is converted
into the (zero-to-peak) value of the sinusoidal voltage (measured in mV) that would need to be applied
at the channel’s inputs, in order to cause the same digital sinusoidal output. This voltage is then defined
as Veq. PSRR is (in dB):
150
Veq
---------
PSRR = 20 log
6. When the voltage level on PFMON is sagging and LSD bit = 0, this is the voltage at which LSD is set to 1.
7. If the LSD bit has been set to 1 (because PFMON voltage fell below PMLO), this is the voltage level on
PFMON at which the LSD bit can be permanently reset back to 0.
8
DS714F3
CS5467
VOLTAGE REFERENCE
Parameter
Symbol
Min
Typ
Max
Unit
Reference Output
Output Voltage
VREFOUT
+2.4
-
+2.5
40
+2.6
-
V
Temperature Coefficient
(Note 8) TC
ppm/°C
VREF
Load Regulation
(Note 9)
V
-
6
10
mV
R
Reference Input
Input Voltage Range
Input Capacitance
Input CVF Current
VREFIN
+2.4
+2.5
4
+2.6
V
-
-
-
-
pF
nA
100
Notes: 8. The voltage at VREFOUT is measured across the temperature range. From these measurements the
following formula is used to calculate the VREFOUT temperature coefficient.
(
(
(
1.0 x 10 6
(VREFOUTMAX - VREFOUTMIN)
VREFOUTAVG
1
TCVREF
=
(
(
(
TAMAX - TAMIN
9. Specified at maximum recommended output of 1 µA, source or sink.
DS714F3
9
CS5467
DIGITAL CHARACTERISTICS
• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.
• Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.
• VA+ = VD+ = 5V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V.
• DCLK = 4.096 MHz.
Parameter
Symbol
Min
Typ
Max
Unit
Master Clock Characteristics
Master Clock Frequency
Master Clock Duty Cycle
CPUCLK Duty Cycle
Internal Gate Oscillator (Note 11) DCLK
(Note 12 and 13)
2.5
40
40
4.096
20
60
60
MHz
%
-
-
%
Filter Characteristics
Phase Compensation Range
Input Sampling Rate
(60 Hz, OWR = 4000 Hz)
DCLK = MCLK/K
(Both channels) OWR
-3 dB
-5.4
-
+5.4
°
Hz
-
-
DCLK/8
-
Digital Filter Output Word Rate
High-pass Filter Corner Frequency
DCLK/1024
-
-
Hz
-
0.5
-
Hz
Full-scale DC Calibration Range (Referred to Input) (Note 14) FSCR
25
100
%FS
µs
Channel-to-channel Time-shift Error
Input/Output Characteristics
High-level Input Voltage
(Note 15)
1.0
All Pins Except XIN and SCLK and RESET
0.6 VD+
(VD+) – 0.5
0.8VD+
-
-
-
-
-
-
V
V
V
V
IH
XIN
SCLK and RESET
Low-level Input Voltage (VD = 5 V)
All Pins Except XIN and SCLK and RESET
-
-
-
-
-
-
0.8
1.5
0.2VD+
V
V
V
V
V
IL
IL
XIN
SCLK and RESET
Low-level Input Voltage (VD = 3.3 V)
All Pins Except XIN and SCLK and RESET
-
-
-
-
-
-
0.48
0.3
0.2VD+
V
V
V
XIN
SCLK and RESET
High-level Output Voltage
Low-level Output Voltage
Iout = +5 mA
V
(VD+) - 1.0
-
-
V
OH
Iout = -5 mA (VD = +5V)
V
-
-
-
-
0.4
0.4
V
V
OL
Iout = -2.5 mA (VD = +3.3V)
Input Leakage Current
3-state Leakage Current
(Note 16)
I
-
-
-
±1
-
±10
±10
-
µA
µA
pF
in
I
OZ
Digital Output Pin Capacitance
C
5
out
Notes: 10. All measurements performed under static conditions.
11. If a crystal is used, XIN frequency must remain between 2.5 MHz - 5.0 MHz. If an external oscillator is
used, XIN frequency range is 2.5 MHz - 20 MHz, but K must be set so that MCLK is between
2.5 MHz - 5.0 MHz.
12. If external MCLK is used, the duty cycle must be between 45% and 55% to maintain this specification.
13. The frequency of CPUCLK is equal to MCLK.
14. The minimum FSCR is limited by the maximum allowed gain register value. The maximum FSCR is
limited by the full-scale signal applied to the input.
15. Configuration register (Config) bits PC[6:0] are set to “0000000”.
16. The MODE pin is pulled low by an internal resistor.
10
DS714F3
CS5467
SWITCHING CHARACTERISTICS
• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.
• Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.
• VA+ = 5 V ±5% VD+ = 3.3 V ±5% or 5 V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V.
• Logic Levels: Logic 0 = 0 V, Logic 1 = VD+.
Parameter
Symbol
Min
Typ
Max
Unit
Rise Times
(Note 17)
t
-
-
-
50
1.0
-
µs
ns
rise
Any Digital Output
Any Digital Output
Fall Times
(Note 17)
t
-
-
-
50
1.0
-
µs
ns
fall
ost
Start-up
Oscillator Start-up Time
XTAL = 4.096 MHz (Note 18)
t
-
60
-
ms
Serial Port Timing
Serial Clock Frequency
Serial Clock
SCLK
-
-
2
MHz
Pulse Width High
Pulse Width Low
t
t
200
200
-
-
-
-
ns
ns
1
2
SDI Timing
CS Falling to SCLK Rising
t
t
t
50
50
-
-
-
-
-
-
ns
ns
ns
3
4
5
Data Set-up Time Prior to SCLK Rising
Data Hold Time After SCLK Rising
100
SDO Timing
CS Falling to SDO Driving
t
t
t
-
-
-
20
20
20
50
50
50
ns
ns
ns
6
7
8
SCLK Falling to New Data Bit (hold time)
CS Rising to SDO Hi-Z
2
E PROM mode Timing
Serial Clock
Pulse Width Low
Pulse Width High
t
8
8
DCLK
DCLK
9
t
10
MODE setup time to RESET Rising
RESET rising to CS falling
CS falling to SCLK rising
t
50
48
ns
DCLK
DCLK
DCLK
ns
11
12
13
14
15
16
t
t
t
t
t
100
8
SCLK falling to CS rising
16
CS rising to driving MODE low
SDO setup time to SCLK rising
50
100
ns
Notes: 17. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.
18. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an
external clock source.
DS714F3
11
CS5467
t3
C S
t1
t2
SC LK
SD I
t4
t5
Com m and Tim e 8 S C LK s
High B yte
M id B yte
Low B yte
SDI Write Timing (Not to Scale)
CS
t8
High Byte
Mid Byte
Low Byte
t6
SDO
SCLK
SDI
UNKNOW N
t1
t7
t2
Command Time 8 SCLKs
SYNC0 or SYNC1
Command
SYNC0 or SYNC1
Command
SYNC0 or SYNC1
Command
SDO Read Timing (Not to Scale)
t1 1
t1 5
M O D E
(IN P U T )
R E S E T
(IN P U T )
t1 4
t1 2
t7
t1 3
C S
(O U T P U T )
S C L K
(O U T P U T )
t1 0
t1 6
t9
t4
S D O
(O U T P U T )
t5
L a s t 8
B its
S D I
(IN P U T )
D a ta fro m E E P R O M
E2PROM mode Sequence Timing (Not to Scale)
Figure 1. CS5467 Read and Write Timing Diagrams
12
DS714F3
CS5467
SWITCHING CHARACTERISTICS (Continued)
Parameter
Symbol
Min
Typ
Max
Unit
E1, E2, and E3 Timing
(Note 19 and 20)
Period
t
500
244
6
-
-
-
-
-
-
-
-
-
-
s
s
s
s
s
period
Pulse Width
t
pw
Rising Edge to Falling Edge
E2 Setup to E1 and/or E3 Falling Edge
E1 Falling Edge to E3 Falling Edge
t
3
t
1.5
248
4
t
5
Notes: 19. Pulse output timing is specified at DCLK = 4.096 MHz, E2MODE = 0, and E3MODE[1:0] = 0. Refer to
6.7 Energy Pulse Outputs on page 20 for more information on pulse output pins.
20. Timing is proportional to the frequency of DCLK.
tperiod
t3
tpw
E1
t4
E2
E3
tperiod
t3
t5
t4
tpw
t5
Figure 2. Timing Diagram for E1, E2, and E3
ABSOLUTE MAXIMUM RATINGS
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
Parameter
Symbol
Min
Typ
Max
Unit
DC Power Supplies
(Notes 21 and 22)
Positive Digital
Positive Analog
VD+
VA+
-0.3
-0.3
-
-
+6.0
+6.0
V
V
Input Current, Any Pin Except Supplies
(Notes 23, 24, 25)
I
-
-
-
-
±10
100
mA
mA
IN
Output Current, Any Pin Except VREFOUT
I
OUT
Power Dissipation
(Note 26)
PD
-
-
-
500
mW
V
Analog Input Voltage
All Analog Pins
V
V
- 0.3
(VA+) + 0.3
INA
Digital Input Voltage
All Digital Pins
-0.3
-40
-65
-
-
-
(VD+) + 0.3
V
IND
Ambient Operating Temperature
Storage Temperature
T
85
°C
°C
A
T
150
stg
Notes: 21. VA+ and AGND must satisfy [(VA+) - (AGND)] + 6.0 V.
22. VD+ and AGND must satisfy [(VD+) - (AGND)] + 6.0 V.
23. Applies to all pins including continuous over-voltage conditions at the analog input pins.
24. Transient current of up to 100 mA will not cause SCR latch-up.
25. Maximum DC input current for a power supply pin is ±50 mA.
26. Total power dissipation, including all input currents and output currents.
DS714F3
13
CS5467
V1
V1
GAIN
OFF
FGA
1
VHPF1 IHPF1
I1
I1
OFF
GAIN
Figure 3. Signal Flow for V1, I1, P1, Q1 Measurements
4. SIGNAL PATH DESCRIPTION
The data flow for voltage and current measurement and
the other calculations are shown in Figures 3, 4, and 5.
IIR “anti-sinc” filters, used to compensate for the ampli-
tude roll-off of the decimation filters.
4.1 Analog-to-Digital Converters
4.3 Phase Compensation
Voltage1 channel and voltage2/temperature channel
use second-order delta-sigma modulators and the two
current channels use fourth-order delta-sigma modula-
tors to convert the analog inputs to single-bit digital data
streams. The converters sample at a rate of DCLK/8.
This high sampling provides a wide dynamic range and
simplifies anti-alias filter design.
Phase compensation changes the phase of current rel-
ative to voltage by changing the sampling time in the
decimation filters. The amount of phase shift is set by
bits PC[7:0] in the Configuration register (Config) for
channel 1 and bits PC[7:0] in the Control register (Ctrl)
for channel 2.
Phase compensation, PC[7:0] is a signed two’s comple-
ment binary value in the range of -1.0 to almost +1.0
output word rate (OWR) samples. For a sample rate of
4000 Hz, the delay range is ±250 uS, a phase shift of
±4.5° at 50 Hz and ±5.4° at 60 Hz. The step size would
be 0.0352° at 50 Hz and 0.0422° at 60 Hz at this sample
rate.
4.2 Decimation Filters
The single-bit modulator output data is widened to 24
bits and down-sampled to DCLK/1024 with low-pass
decimation filters. These decimation filters are third-or-
der Sinc. Their outputs are passed through third-order
V2
V2
GAIN
OFF
V2
V2Q
Q2
FGA
2
VHPF2 IHPF2
P2
2
Control Register
I2
I2
I2
OFF
GAIN
Figure 4. Signal Flow for V2, I2, P2, Q2 Measurements
14
DS714F3
CS5467
of interest, but passes DC. For more information, see
6.5 High-pass Filters on page 20. The HPF filter multi-
plexers drive the I1, V1, I2, and V2 result registers.
4.4 DC Offset and Gain Correction
The system and chip inherently have gain and offset er-
rors which can be removed using the gain and offset
registers. (See Section 9. System Calibration on page
40). Each measurement channel has its own registers.
For every channel, the output of the IIR filter is added to
the offset register and multiplied by the gain register.
4.6 Low-Rate Calculations
Low-rate results are derived from sample-rate results
integrated over N samples, where N is the value stored
in the Cycle Count register. The low-rate interval is the
sample interval multiplied by N.
4.5 High-pass Filters
Optional high-pass filters (HPF in Figures 3 and 4) re-
move any DC from the selected signal paths. Subse-
quently, DC will also be removed from power, and all
low-rate results. (see Figures 5).
4.7 RMS Results
The root mean square (RMS in Figure 5) calculations
are performed on N instantaneous voltage and current
samples, using the formula:
Each energy channel has a current and voltage path. If
an HPF is enabled in only one path, a phase-matching
filter (PMF) is applied to the other path which matches
the amplitude and phase delay of the HPF in the band
N – 1
2
n
I
I
=
RMS
n = 0
--------------------
N
DS714F3
15
CS5467
V1ACOFF
(V2ACOFF
)
P1
OFF(P2OFF
)
I1ACOFF
(I2ACOFF
)
Figure 5. Low-rate Calculations
4.8 Power and Energy Results
The instantaneous voltage and current samples are
multiplied to obtain the instantaneous power (P1, P2)
(see Figure 3 and 4). The product is then averaged over
QWB
=
S2 – PA2ctive
Quadrature power (Q1, Q2) are sample rate results ob-
tained by multiplying instantaneous current (I1, I2) by in-
stantaneous quadrature voltage (V1Q, V2Q) which are
created by phase shifting instantaneous voltage (V1,
V2) 90 degrees using first-order integrators. (See Fig-
ure 3 and 4). The gain of these integrators is inversely
related to line frequency, so their gain is corrected by
the Epsilon register, which is based on line frequency.
N conversions to compute active power (P1
,
AVG
P2
).
AVG
Apparent power (S1, S2) is the product of RMS voltage
and current as shown:
S = VRMS IRMS
Power factor (PF1, PF2) is active power divided by ap-
parent power as shown below. The sign of the power
factor is determined by the active power.
Reactive power (Q1 , Q2
grating the instantaneous quadrature power over N
samples.
) is generated by inte-
AvG
Avg
PActive
Active power (P1
and reactive power (Q1
, P2
), apparent power (S1, S2),
------------------
PF =
AVG
AVG
S
, Q2
) of the two channels
AVG
AVG
are summed up and then divided by 2. The calculation
results are placed in E , S , and Q reg-
isters which can be configured to drive energy pulse
outputs. (See Figure 6.)
Wideband reactive power (Q1 , Q2 ) is calculated
by doing a vector subtraction of active power from ap-
parent power.
WB
WB
PULSE
PULSE
PULSE
OVF=
EACCM
P1AVG
÷2
÷2
÷2
EPULSE
+
+
+
×
×
×
+
+
+
P2AVG
S1
OVF=
SACCM
SPULSE
S2
OVF=
QACCM
Q1AVG
Q2AVG
QPULSE
( E1, E2, E3 )
PulseRate
Figure 6. Two-channel Power Summation
16
DS714F3
CS5467
chip’s power supply, or from inductance from a nearby
transformer.
4.9 Peak Voltage and Current
Peak current (I1
, I2
) and peak voltage
PEAK
PEAK
These offsets can be either positive or negative, indicat-
ing crosstalk coupling either in phase or out of phase
with the applied voltage input. The power offset regis-
ters can compensate for either condition.
(V1
, V2
) are the largest current and voltage
PEAK
PEAK
samples detected in the previous low-rate interval.
4.10 Power Offset
The power offset registers, P1
(P2
) can be used
OFF
OFF
To use this feature, measure the average power at no
load using either Single or Continuous Conversion com-
to offset erroneous power sources resident in the sys-
tem not originating from the power line. Residual power
offsets are usually caused by crosstalk into current
paths from voltage paths or from ripple on the meter or
mands. Take the measured result (from the P1
AVG
(P2
) register), invert (negate) the value and write it
AVG
to the associated power offset register, P1
(P2
).
OFF
OFF
DS714F3
17
CS5467
5. PIN DESCRIPTIONS
5.1 Analog Pins
5.1.6 Crystal Oscillator
The CS5467 has four differential inputs: VIN1VIN2
IIN1, and IIN2 are the voltage1, voltage2, current1,
and current2 inputs, respectively. A single-ended power
fail monitor input, voltage reference input, and voltage
reference output are also available.
An external quartz crystal can be connected to the XIN
and XOUT pins as shown in Figure 7. To reduce system
cost, each pin is supplied with an on-chip, phase-shift-
ing capacitor to ground.
.
5.1.1 Voltage1 & Voltage2 Inputs
XOUT
The output of the line voltage resistive divider or trans-
former is connected to the VIN1+ (VIN2+) and VIN1-
(VIN2-) input pins of the CS5467. The voltage channel
is equipped with a 10x, fixed-gain amplifier. The
full-scale signal level that can be applied to the voltage
channel is ±250 mV. If the input signal is a sine wave,
C1
Oscillator
Circuit
XIN
C2
the
maximum
RMS
voltage
is
250 mVp / 2 176.78 mVRMS which is approximate-
ly 70.7% of maximum peak voltage.
DGND
C1 = C2 = 22 pF
5.1.2 Current1 & Current2 Inputs
The output of the current-sensing resistor or transform-
er is connected to the IIN1+ (IIN2+) and IIN1- (IIN2-) in-
put pins of the CS5467. To accommodate different
current-sensing elements, the current channel incorpo-
rates a programmable gain amplifier (PGA) with two se-
lectable input gains. The full-scale signal level for the
current channels is ±50 mV or ±250 mV. If the input sig-
nal is a sine wave, the maximum RMS voltage is
35.35 mVRMS or 176.78 mVRMS which is approxi-
mately 70.7% of maximum peak voltage.
Figure 7. Oscillator Connections
Alternatively, an external clock source can be connect-
ed to the XIN pin.
5.2 Digital Pins
5.2.1 Reset Input
The active-low RESET pin, when asserted, will halt all
CS5467 operations and reset internal hardware regis-
ters and states. When de-asserted, an initialization se-
quence begins, setting default register values.
5.1.3 Power Fail Monitor Input
An analog input (PFMON) is provided to determine
when a power loss is imminent. By connecting a resis-
tive divider from the unregulated meter power supply to
the PFMON input, an interrupt can be generated, or the
Low Supply Detected (LSD) Status register bit can be
monitored to indicate low-supply conditions. The PF-
MON input has a comparator that trips around the level
of the voltage reference input (VREFIN).
5.2.2 CPU Clock Output
A logic-level clock output (CPUCLK) is provided at the
crystal frequency to drive an external CPU or microcon-
troller clock. Two phase choices are available.
5.2.3 Interrupt Output
The INT pin indicates an enabled Internal Status regis-
ter (Status) bit is set. Status register bits indicate condi-
tions such as data ready, modulator oscillations, low
supply, voltage sag, current faults, numerical overflows,
and result updates.
5.1.4 Voltage Reference Input
The CS5467 requires a stable voltage reference of
2.5 V applied to the VREFIN pin. This reference can be
supplied from an external voltage reference or from the
VREFOUT output. A bypass capacitor of at least 0.1 F
is recommended at the VREFIN pin.
5.2.4 Energy Pulse Outputs
The CS5467 provides three pins (E1, E2, E3) for pulse
energy outputs. These pins can also be used to output
other conditions, such as voltage1 sign, power fail mon-
itor, or energy sign.
5.1.5 Voltage Reference Output
The CS5467 generates a 2.5 V reference (VREFOUT).
It is suitable for driving the VREFIN pin, but has very lit-
tle fan-out capacity and is not recommended for driving
external circuits.
18
DS714F3
CS5467
for host microcontrollers, and a driven output for serial
E PROMs.
5.2.5 Serial Interface
2
The CS5467 provides 5 pins, SCLK, SDI, SDO, CS, and
MODE for communication between a host microcon-
SDI is the serial data input to the CS5467.
2
troller or serial E PROM and the CS5467.
SDO is the serial data output from the CS5467. It’s out-
put drivers are disabled whenever CS is de-asserted, al-
lowing other devices to drive the SDO line.
MODE is an input that, when high, indicates to the
2
CS5467 that a serial E PROM is being used instead of
a host microcontroller. It has a weak pull-down allowing
it to be left unconnected if microcontroller mode is used.
CS is the chip select input for the serial bus. A high logic
level de-asserts it, tri-stating the SDO pin and clearing
the serial interface. A low logic level enables the serial
port. This pin may be tied low for systems not requiring
multiple SDO drivers. CS is a driven output when inter-
SCLK is used to shift and qualify serial data. Serial data
changes as a result of the falling edge of SCLK and is
valid during the rising edge. It is a Schmitt-trigger input
2
facing to serial E PROMs.
DS714F3
19
CS5467
6. SETTING UP THE CS5467
6.1 Clock Divider
The internal clock to the CS5467 needs to operate
around 4 MHz. However, by using the internal clock di-
vider, a higher crystal frequency can be used. This is im-
portant when driving an external microcontroller
requiring a faster clock and using the CPUCLK output.
path within a channel, a phase matching filter (PMF) is
applied to the other path within that channel. The PMF
filter matches the amplitude and phase response of the
HPF in the band of interest, but passes DC.
VHPF
IHPF
Filter Configuration
0
0
1
1
0
1
0
1
No filter on Voltage or Current
HPF on Current, PMF on Voltage
HPF on Voltage, PMF on Current
HPF on Current and Voltage
K is the divide ratio from the crystal input to the internal
clock and is selected with Configuration register (Con-
fig) bits K[3:0]. It has a range of 1 to 16. A value of zero
results in a setting of 16.
Table 3. High-pass Filter Configuration
6.2 CPU Clock Inversion
6.6 Cycle Count
By default, CPUCLK is inverted from XIN. Setting Con-
figuration register bit iCPU removes this inversion. This
can be useful when one phase adds more noise to the
system than the other.
Low-rate calculations, such as average power and RMS
voltage and current integrate over several (N) output
word rate (OWR) samples. The duration of this averag-
ing window is set by the Cycle Count (N) register. By de-
fault, Cycle Count is set to 4000 (1 second at output
word rate [OWR] of 4000 Hz). The minimum value for
Cycle Count is 10.
6.3 Interrupt Pin Behavior
The behavior of the INT pin is controlled by the IMODE
and IINV bits in the Configuration register as shown.
6.7 Energy Pulse Outputs
IMODE
IINV
INT Pin
By default, E1 outputs total active energy, E3, total re-
active energy, and E2, the sign of both active and reac-
tive energy. (See Figure 2. Timing Diagram for E1, E2,
and E3 on page 13.)
0
0
Active-low Level
0
1
1
1
0
1
Active-high Level
Low Pulse
Three pairs of bits in the Mode Control (Modes) register
control the operation of these outputs. These bits are
named
E1MODE[1:0],
E2MODE[1:0],
and
High Pulse
E3MODE[1:0]. Some combinations of these bits over-
ride others, so read the following paragraphs carefully.
Table 1. Interrupt Configuration
The E2 pin can output energy sign, or total apparent en-
ergy. Table 4 lists the functions of E2 as controlled by
E2MODE[1:0] in the Modes register.
If IMODE = 1, the duration of the INT pulse will be two
DCLK cycles, where DCLK = MCLK/K.
6.4 Current Input Gain Ranges
Control register bits I1gain (I2gain) select the input
range of the current inputs.
Note: E2MODE[1:0]=3 is a special mode.
E2MODE1 E2MODE0
E2 output
Energy Sign
0
0
1
1
0
1
0
1
I1gain, I2gain Maximum Input
Gain
Total Apparent Energy
Not Used
0
1
±250 mV
±50 mV
10x
50x
Enable E1MODE
Table 2. Current Input Gain Ranges
Table 4. E2 Pin Configuration
6.5 High-pass Filters
Mode Control (Modes) register bits VHPF and IHPF ac-
tivate the HPF in the voltage and current paths, respec-
tively. Each energy channel has separate VHPF and
IHPF bits. When a high-pass filter is enabled in only one
The E3 pin can output total reactive energy, power fail
monitor status, voltage1 sign, or total apparent energy.
Table 5 lists the functions of E3 as controlled by
20
DS714F3
CS5467
E3MODE[1:0] in the Modes register when E1MODE is
not enabled.
6.8 No Load Threshold
The No Load Threshold register (Load ) is used to
MIN
zero out the contents of E
their magnitude is less than the Load
and Q
registers if
register value.
PULSE
PULSE
E3MODE1 E3MODE0
E3 output
MIN
0
0
1
1
0
1
0
1
Total Reactive Energy
Power Fail Monitor
Voltage1 Sign
6.9 Energy Pulse Width
Note: Energy Pulse Width (PulseWidth) only applies to
E1, E2, or E3 pins that are configured to output pulses.
When any are configured to output steady-state signals,
such as voltage1 sign, power fail monitor, or energy
sign, pulse widths and output rates do not apply.
Total Apparent Energy
Table 5. E3 Pin Configuration
The pulse width time (t ) in Figure 2, is set by the value
in the PulseWidth register which is an integer multiple of
the sample or output word rate (OWR). At OWR of
pw
When both E2MODE bits are high, the E1MODE bits
are enabled, allowing active, apparent, reactive, or wide
band reactive energy for both energy channels to be
output on E1 and E2. Table 6 lists the functions of E1
and E2 with E1MODE enabled.
4000 Hz (a period of 250 uS) t
= PulseWidth x
pw
250 uS. By default, PulseWidth is set to 1.
6.10 Energy Pulse Rate
E1MODE1 E1MODE0
E1 / E2 outputs
Active Energy
The full-scale pulse frequency of enabled E1, E2, E3
pins is the value in PulseRate x output word rate
(OWR)/2. The actual pulse frequency is the full-scale
pulse frequency multiplied by the pulse register’s
0
0
1
1
0
1
0
1
Apparent Energy
Reactive Energy
Wideband Reactive
(E
, S
, or Q
) value.
PULSE
PULSE
PULSE
Example:
If the output word rate (OWR) is 4000 Hz, and the
PulseRate register is set to 0.05, the full-rate pulse fre-
Table 6. E1 / E2 Modes
quency is 0.05 x 4000 / 2 = 100 Hz. If the E
ter, driving E1, is 0.4567, the pulse output rate on E1 will
be 100 Hz x 0.4567 = 45.67 Hz.
regis-
PULSE
When E1MODE bits are enabled, the E3 pin outputs ei-
ther the power fail monitor status, or the sign of the E1
and E2 outputs. Table 7 list the functions of the E3 pin
using E3MODE[1:0] in the Modes register when
E1MODE is enabled .
6.11 Voltage Sag/Current Fault Detection
Voltage sag detection is used to determine when aver-
aged voltage falls below a predetermined level for a
specified interval of time. Current fault detection deter-
mines when averaged current falls below a predeter-
mined level for a specified interval of time.
E3MODE1 E3MODE0
E3 output
Power Fail Monitor
Energy Sign
not used
0
0
1
1
0
1
0
1
The specified interval of time (duration) is set by the val-
ue in the V1Sag
(V2Sag
) and I1Fault
DUR
DUR DUR
(I2Fault
) registers. Setting any of these to zero (de-
DUR
not used
fault) disables the detect feature for the given channel.
The value is in output word rate (OWR) samples. The
predetermined level is set by the values in the
Table 7. E3 Pin with E1MODE enabled
V1Sag
(V2Sag
)
and
I1Fault
LEVEL
LEVEL
LEVEL
(I2Fault
) registers.
LEVEL
DS714F3
21
CS5467
For each enabled input channel, the measured value is
rectified and compared to the associated level register.
Over the duration window, the number of samples
above and below the level are counted. If the number of
samples below the level exceeds the number of sam-
updated. The Voltage2 register (V2) will not update dur-
ing the temperature measurement, but resume mea-
surement afterwards.
Temperature measurements are stored in the Temper-
ature register (T) which, by default, is configured to a
range of ±128 degrees on the Celsius (°C) scale.
ples above, a Status register bit V1
(V2
),
SAG
SAG
I1
(I2
) is set, indicating a sag or fault condi-
FAULT
FAULT
The application program can change both the scale and
range of Temperature (T) by changing the Temperature
tion. (see Figure 8)..
Gain (T
) and Temperature Offset (T
) registers.
GAIN
OFF
Two values must be known — the transistor’s VBE per
degree, and the transistor’s VBE at 0 degrees. At the
time of this publication, these values are:
VBE (per degree) = 0.2769523 mV/°C or °K
V
0 = 79.2604368 mV at 0°C
BE
To determine the values to write to T
and T
, use
OFF
GAIN
the following formulae:
17
T
T
= AD / VBE / T x 2
GAIN
OFF
FS
FS
23
= -V 0 / AD x 2
BE
FS
Figure 8. Sag and Fault Detect
In the above equations, AD
is the full-scale input
FS
range of the temperature A/D converter or 833.333 mV
and T is the desired full-scale range of the Tempera-
ture (T) register. The binary exponents are the bit posi-
tions of the binary point of these registers.
FS
6.12 Epsilon
The Epsilon register is used to set the gain of the 90°
phase shift used in the quadrature power calculation.
To use the Celsius scale (°C) and cover the chip’s oper-
ating temperature range of -40°C to +85°C, the Temper-
The value in the Epsilon register is the ratio of the line
frequency to the output word rate (OWR). It is, by de-
fault, 50/4000 (0.0125), for 50 Hz line and 4000 Hz sam-
ple (OWR) frequencies.
ature register range needs to be ±128 degrees. T
should be 128 degrees.
FS
T
= 833.333 / 0.2769523 / 128 x 131072
= 3081155 (0x2F03C3)
For 60 Hz line frequency, it is 60/4000 (0.015). Other
output word rates (OWR) can be used.
GAIN
Epsilon can also be calculated automatically by the
CS5467 by setting the AFC bit in the Mode Control
(Modes) register. The Frequency Update bit (FUP) in
the Status register is set every time the Epsilon register
has been automatically updated.
T
= -79.2604368 / 833.333 x 8388608
= -797862 (0xF3D35A)
OFF
These are the actual default values for these registers.
and T can also be used to calibrate the gain
T
GAIN
OFF
and/or offset of the temperature sensor or A/D convert-
er. (See Section 9. System Calibration on page 40).
6.13 Temperature Measurement
The on-chip temperature sensor is designed to mea-
sure temperature and optionally compensate for tem-
perature drift of the voltage reference. It uses the VBE of
a transistor to determine temperature.
To use the Kelvin (°K) scale, simply add 273 times VBE
23
/ AD x 2 to T
since 0°C = 273°K,. You will also
FS
OFF
need more range. Since -40°C to +85°C is 233°K to
358°K, a T of 512 degrees should be used in the
FS
In the CS5467, voltage2 and temperature are multi-
plexed on one ADC channel. To initiate a temperature
measurement, write 1 to the Temperature Measure-
T
calculation.
GAIN
To use the Fahrenheit (°F) scale, multiply VBE by 5/9
23
and add 32 times the newVBE/ AD x 2 to T
ment (T
) register. T
will go through counts 1,
FS
OFF
MEAS
MEAS
since 0°C = 32°F. You will also want to use aT of 256
2, 4, and back to 0. Wait for T
to return to 0. When
FS
MEAS
degrees to cover the -40°C to +85°C range.
done, Temperature (T) is updated. The Status register
bit TUP also indicates when the Temperature register is
22
DS714F3
CS5467
7. USING THE CS5467
7.1 Initialization
The CS5467 uses a power-on-reset circuit (POR) to
provide an internal reset until the analog voltage reach-
es 4.0 V. The RESET input pin can also be used by the
application circuit to reset the part.
to entering the stand-by state. When returning from
sleep mode, a complete initialization occurs.
7.3 Voltage Tamper Correction
The CSS5467 provides compensation for meter tam-
pering on voltage channels.
After RESET is removed and the oscillator is stable, an
initialization program is executed to set the default reg-
ister values.
If the application detects that the voltage input has been
impaired it may choose to use the fixed internal RMS
voltage reference by setting the VFIX bit in the Modes
A Software Reset command is also provided to allow
the application to run the initialization program without
removing power or asserting RESET.
register. The value of this reference (VF
) is by de-
RMS
fault 0.707107 (full-scale RMS) but can be changed by
the application program. (See figure 9)
The application should avoid sending commands during
initialization. The DRDY bit in the Status register indi-
cates when the initialization program has completed.
7.2 Power-down States
The CS5467 has two power-down states, stand-by and
sleep. In the stand-by state, all circuitry except the volt-
age reference and crystal oscillator is powered off. In
sleep state, all circuitry except the instruction decoder is
powered off.
To return the device to the active state, send a Wake-
up/Halt command to the device. When returning from
stand-by mode, registers will retain their contents prior
Figure 9. Fixed RMS Voltage Selection
DS714F3
23
CS5467
Synchronizing commands are also used to synchronize
the serial port to a byte boundary. The CS and RESET
pins will also synchronize the serial port.
7.4 Command Interface
Commands and data are transferred most-significant bit
(MSB) first. Figure 1 on page 12, defines the serial port
timing. Commands are clocked in on SDI using SCLK.
They are a single byte (8 bits) long and fall into one of
four basic types:
Register writes require three bytes of write data to fol-
low, clocked in on the SDI pin, MSB first by SCLK.
Instructions are commands that will interrupt any in-
struction currently executing and begin the new instruc-
tion. These include conversions, calibrations, power
control, and soft reset.
1. Register Read
2. Register Write
3. Synchronizing
4. Instructions
(See Section 7.6 Commands on page 25).
7.5 Register Paging
Register reads will cause up to four bytes of register
data to be clocked out, MSB first on the SDO pin by
SCLK. During this time, other commands can be
clocked in on the SDI pin. Other commands will not in-
terrupt read data, except another register read, which
will cause the new read data to appear on SDO.
Read and Write commands access one of 32 registers
within a specified page. The Register Page Select reg-
ister’s (Page) default value is 0. To access registers in
another page, write the desired page number to the
Page register. The Page register is always at address
31 and is accessible from within any page.
Synchronizing can be sent while read data is being
clocked out if no other commands need to be sent.
24
DS714F3
CS5467
7.6 Commands
All commands are 1 byte (8 bits) long. Many command values are unused and should NOT be written by the
application program. All commands except register reads, register writes, or synchronizing commands will
abort any conversion, calibration, or any initialization sequence currently executing. This includes reset. No
commands other than reads or synchronizing should be executed until the reset sequence completes.
7.6.1 Conversion
B7
B6
B5
B4
B3
B2
B1
B0
1
1
1
0
CC
0
0
0
Executes a conversion (measurement) program.
CC
Continuous/Single Conversion
0 = Perform a Single Conversion (0xE0)
1 = Perform Continuous Conversion (0xE8)
7.6.2 Synchronization (SYNC0 and SYNC1)
B7
B6
B5
B4
B3
B2
B1
B0
1
1
1
1
1
1
1
SYNC
The serial interface is bidirectional. While reading data on the SDO output, the SDI input must be receiving
commands. If no command is needed during a read, SYNC0 or SYNC1 commands can be sent while read
data is received on SDO.
The serial port is normally initialized by de-asserting CS. An alternative method of initialization is to send 3 or
more SYNC1 commands followed by a SYNC0. This is useful in systems where CS is not used and tied low.
7.6.3 Power Control (Stand-by, Sleep, Wake-up/Halt and Software Reset)
B7
B6
B5
B4
B3
B2
B1
B0
1
0
S1
S0
0
0
0
0
The CS5467 has two power-down states, stand-by and sleep. In stand-by, all circuitry except the voltage ref-
erence and clocks are turned off. In sleep mode, all circuitry except the command decoder is turned off. A
Wake-up/Halt command restores full-power operation after stand-by and issues a hardware reset after sleep.
The Software Reset command is a program that emulates a pin reset and is not a power control function.
S[1:0]
00 = Software Reset
01 = Sleep
10 = Wake-up/Halt
11 = Stand-by
DS714F3
25
CS5467
7.6.4 Calibration
B7
B6
B5
B4
B3
B2
B1
B0
1
0
CAL5 CAL4 CAL3 CAL2 CAL1 CAL0
The CS5467 can perform gain and offset calibrations using either DC or AC signals. Proper input levels must
be applied to the current inputs and voltage input before performing calibrations.
CAL[5:4]*
CAL[3:0]
Note:
00 = DC Offset
01 = DC Gain
10 = AC Offset
11 = AC Gain
0001 = Current for Channel 1
0010 = Voltage for Channel 1
0100 = Current for Channel 2
1000 = Voltage for Channel 2
Anywhere from 1 to all 4 channels can be calibrated simultaneously.
26
DS714F3
CS5467
7.6.5 Register Read and Write
B7
B6
B5
B4
B3
B2
B1
B0
0
W/R
RA4
RA3
RA2
RA1
RA0
0
Read and Write commands provide access to on-chip registers. After a Read command, the addressed data
can be clocked out the SDO pin by SCLK. After a Write command, 24 bits of write data must follow. The data
th
is transferred to the addressed register after the 24 data bit is received. Registers are organized into pages
of 32 addresses each. To access a desired page, write its number to the Page register at address 31.
W/R
Write/Read control
0 = Read
1 = Write
RA[4:0]
Register address.
Page 0 Registers
Address
0
RA[4:0]
Name
Config
I1
V1
P1
Description
Configuration
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
1
2
3
4
5
6
7
8
Instantaneous Current Channel 1
Instantaneous Voltage Channel 1
Instantaneous Power Channel 1
Active Power Channel 1
RMS Current Channel 1
RMS Voltage Channel 1
Instantaneous Current Channel 2
Instantaneous Voltage Channel 2
Instantaneous Power Channel 2
Active Power Channel 2
RMS Current Channel 2
RMS Voltage Channel 2
Reactive Power Channel 1
Instantaneous Quadrature Power Channel 1
Internal Status
Reactive Power Channel 2
Instantaneous Quadrature Power Channel 2
Peak Current Channel 1
Peak Voltage Channel 1
Apparent Power Channel 1
Power Factor Channel 1
Peak Current Channel 2
Peak Voltage Channel 2
Apparent Power Channel 2
Power Factor Channel 2
Interrupt Mask
P1
AVG
I1
RMS
V1
I2
RMS
V2
P2
P2
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 R
AVG
RMS
I2
V2
RMS
Q1
Q1
AVG
Status
Q2
Q2
AVG
I1
PEAK
V1
S1
PEAK
PF1
I2
PEAK
V2
S2
PEAK
PF2
Mask
T
Temperature
Control
Active Energy Pulse Output
Apparent Energy Pulse Output
Reactive Energy Pulse Output
Register Page Select
Ctrl
E
S
PULSE
PULSE
Q
PULSE
31 W 11111
Page
Warning: Do not write to unpublished register locations.
DS714F3
27
CS5467
Page1 Registers
Address
0
RA[4:0]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10011
10100
10101
10110
10111
11001
11010
11011
11100
11101
Name
Description
Current DC Offset Channel 1
Current Gain Channel 1
Voltage DC Offset Channel 1
Voltage Gain Channel 1
Power Offset Channel 1
Current AC (RMS) Offset Channel 1
Voltage AC (RMS) Offset Channel 1
Current DC Offset Channel 2
Current Gain Channel 2
Voltage DC Offset Channel 2
Voltage Gain Channel 2
I1
I1
OFF
1
2
3
4
5
6
7
8
GAIN
V1
V1
P1
OFF
GAIN
OFF
I1
ACOFF
V1
ACOFF
OFF
I2
I2
GAIN
9
V2
V2
P2
OFF
GAIN
OFF
10
11
12
13
14
15
16
17
19
20
21
22
23
25
26
27
28
29
Power Offset Channel 2
I2
Current AC (RMS) Offset Channel 2
Voltage AC (RMS) Offset Channel 2
Pulse Output Width
Pulse Output Rate (frequency)
Mode Control
ACOFF
V2
ACOFF
PulseWidth
PulseRate
Modes
Epsilon
N
Ratio of Line to Sample Frequency
Cycle Count (Number of OWR Samples in One Low-rate Interval)
Wideband Reactive Power from Power Triangle Channel 1
Wideband Reactive Power from Power Triangle Channel 2
Temperature Sensor Gain
Temperature Sensor Offset
Filter Settling Time for Conversion Startup
No Load Threshold
Voltage RMS Fixed Reference
System Gain
System Time (in samples)
Q1
Q2
WB
WB
T
T
T
GAIN
OFF
SETTLE
Load
MIN
RMS
VF
G
Time
31 W 11111
Page
Register Page Select
Page2 Registers
Address
RA[4:0]
00000
00001
00100
00101
01000
01001
01100
01101
Name
V1Sag
V1Sag
I1Fault
I1Fault
V2Sag
V2Sag
I2Fault
I2Fault
Page
Description
0
1
4
5
8
9
12
13
V Sag Duration Channel 1
V Sag Level Channel 1
I Fault Duration Channel 1
I Fault Level Channel 1
V Sag Duration Channel 2
V Sag Level Channel 2
I Fault Duration Channel 2
I Fault Level Channel 2
Register Page Select
DUR
LEVEL
DUR
LEVEL
DUR
LEVEL
DUR
LEVEL
31 W 11111
Page5 Register
Address
26
RA[4:0]
11010
Name
Description
Temperature Measurement
Register Page Select
T
MEAS
31 W 11111
Page
Warning: Do not write to unpublished register locations.
28
DS714F3
CS5467
8. REGISTER DESCRIPTIONS
1. “Default” = bit states after power-on or reset
2. DO NOT write a “1” to any unpublished register bit.
3. DO NOT write to any unpublished register address.
8.1 Page Register
8.1.1 Page – Address: 31, Write-only, can be written from ANY page.
MSB
LSB
26
25
24
23
22
21
20
Default = 0
Register Read and Write commands contain only 5 address bits. But the internal address bus of the CS5467
is 12 bits wide. Therefore, registers are organized into “Pages”. There are 128 pages of 32 registers each.
The Page register provides the 7 high-order address bits and selects one of the 128 register pages. Not all
pages are used,
Page is a write-only integer containing 7 bits.
8.2 Page 0 Registers
8.2.1 Configuration (Config) – Address: 0
23
22
21
20
19
18
17
16
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
15
14
13
12
11
10
9
8
EWA
-
-
IMODE
IINV
-
-
-
7
6
5
4
3
2
1
0
-
-
-
iCPU
K3
K2
K1
K0
Default = 1 (K=1)
PC[7:0]
Phase compensation for channel 1. Sets a delay in voltage, relative to current. Phase is
signed and in the range of -1.0 value 1.0 sample (OWR) intervals.
EWA
Allows the E1 and E2 pins to be configured as open-drain outputs.
0 = Normal Outputs
1 = Open-drain Outputs
IMODE, IINV
Interrupt configuration. Selects INT pin behavior.
00 = Low Logic Level When Asserted
01 = High Logic Level When Asserted
10 = Low-going Pulse on New Interrupt
11 = High-going Pulse on New Interrupt
iCPU
Inverts the CPUCLK output.
0 = Default
1 = Invert CPUCLK.
K[3:0]
Clock divider. Divides MCLK by K to generate internal clock DCLK. (DCLK = MCLK/K). K
is unsigned and in the range of 1 to 16. When zero, K = 16. At reset, K = 1.
DS714F3
29
CS5467
8.2.2 Instantaneous Current (I1, I2), Voltage (V1, V2), and Power (P1, P2)
Address: 1 (I1), 2 (V1), 3 (P2), 7 (I2), 8 (V2), 9 (P2)
MSB
-(20)
LSB
2-23
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-17
2-18
2-19
2-20
2-21
2-22
.....
I1 (I2) and V1 (V2) contain instantaneous current and voltage, respectively, which are multiplied to yield instan-
taneous power, P1 (P2). These are two's complement values in the range of -1.0 value 1.0, with the binary
point to the right of the MSB.
8.2.3 Active Power (P1AVG , P2AVG
)
Address: 4 (P1
), 10 (P2
)
AVG
AVG
MSB
LSB
-(20)
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-17
2-18
2-19
2-20
2-21
2-22
2-23
.....
Instantaneous power is averaged over each low-rate interval (N samples) to compute active power, P1
AVG
(P2
). These are two's complement values in the range of -1.0 value 1.0, with the binary point to the
AVG
right of the MSB.
8.2.4 RMS Current (I1RMS , I2RMS ) and Voltage (V1RMS , V2RMS
)
Address: 5 (I1
), 6 (V1
), 11 (I2
), 12 (V2
)
RMS
RMS
RMS
RMS
MSB
LSB
2-1
2-2
2-3
2-4
) and V1
2-5
(V2
2-6
2-7
2-8
2-18
2-19
2-20
2-21
2-22
2-23
2-24
.....
I1
(I2
) contain the root mean square (RMS) values of I1 (I2) and V1 (V2), calcu-
RMS
RMS
RMS
RMS
lated each low-rate interval. These are unsigned values in the range of 0 value 1.0, with the binary point
to the left of the MSB.
8.2.5 Instantaneous Quadrature Power (Q1, Q2)
Address: 14 (Q1), 17 (Q2)
MSB
LSB
-(20)
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-17
2-18
2-19
2-20
2-21
2-22
2-23
.....
Instantaneous quadrature power, Q1 (Q2), the product of voltage1 (voltage2) shifted 90 degrees and current1
(current2). These are two's complement values in the range of -1.0 value 1.0, with the binary point to the
right of the MSB.
8.2.6 Reactive Power (Q1Avg , Q2AVG
)
Address: 13 (Q1
), 16 (Q2
)
AVG
AVG
MSB
LSB
-(20)
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-17
2-18
2-19
2-20
2-21
2-22
2-23
.....
Reactive power Q1
(Q2
) is Q1 (Q2) averaged over every N samples. These are two's complement
AVG
AVG
values in the range of -1.0 value 1.0, with the binary point to the right of the MSB.
30
DS714F3
CS5467
8.2.7 Peak Current (I1PEAK, I2PEAK ) and Peak Voltage (V1PEAK, V2PEAK
)
Address: 18 (I1
), 19 (V1
), 22 (I2
), 23 (V2
PEAK
)
PEAK
PEAK
PEAK
MSB
LSB
-(20)
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-17
2-18
2-19
2-20
2-21
2-22
2-23
.....
Peak current, I1
(I2
) and peak voltage, V1
(V2
) are the instantaneous current and voltage
PEAK
PEAK
PEAK
PEAK
samples with the greatest magnitude detected during the last low-rate interval. These are two's complement
values in the range of -1.0 value 1.0, with the binary point to the right of the MSB.
8.2.8 Apparent Power (S1, S2)
Address: 20 (S1), 24 (S2)
MSB
LSB
-(20)
2-1
Apparent power S1 (S2) is the product of V1
2-2
2-3
2-4
2-5
2-6
2-7
2-17
(V2
2-18
2-19
2-20
2-21
2-22
2-23
.....
and I1
and I2 ), These are two's complement
RMS
RMS
RMS
RMS
values in the range of 0 value 1.0, with the binary point to the right of the MSB.
8.2.9 Power Factor (PF1, PF2)
Address: 21 (PF1), 25 (PF2)
MSB
LSB
-(20)
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-17
2-18
2-19
2-20
2-21
2-22
2-23
.....
Power factor is calculated by dividing active power by apparent power. The sign is determined by the active
power sign. These are two's complement values in the range of -1.0 value 1.0, with the binary point to the
right of the MSB.
8.2.10 Temperature (T) – Address: 27
MSB
LSB
-(27)
26
25
24
23
22
21
20
2-10
2-11
2-12
2-13
2-14
2-15
2-16
.....
T contains results from the on-chip temperature measurement. By default, T uses the Celsius scale, and is a
two's complement value in the range of -128.0 value 128.0 (oC), with the binary point to the right of bit 16.
T can be rescaled by the application using the T
and T
registers.
OFF
GAIN
8.2.11 Active, Apparent, and Reactive Energy Pulse Outputs (EPULSE , SPULSE , QPULSE
)
Address: 29 (E
), 30 (S
), 31 (Q
)
PULSE
PULSE
PULSE
MSB
LSB
-(20)
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-17
2-18
2-19
2-20
2-21
2-22
2-23
.....
These drive the pulse outputs when configured to do so. These are two's complement values in the range of
-1.0 value 1.0, with the binary point to the right of the MSB. Refer to 4.8 Power and Energy Results on
page 16.
DS714F3
31
CS5467
8.2.12 Internal Status (Status) and Interrupt Mask (Mask)
Address: 15 (Status); 26 (Mask)
23
22
21
20
19
18
17
16
DRDY
I2OR
V2OR
CRDY
I2ROR
V2ROR
I1OR
V1OR
15
14
13
12
11
10
9
8
E2OR
I1ROR
V1ROR
E1OR
I1FAULT
V1SAG
I2FAULT
V2SAG
7
6
5
4
3
2
1
0
TUP
V2OD
I2OD
V1OD
I1OD
LSD
FUP
IC
Default =
1 (Status), 0 (Mask)
The Status register indicates a variety of conditions within the chip. Writing a '1' to a Status register bit will
clear that bit if the condition that set it has been removed. Writing a '0' to any bit has no effect.
The Mask register is used to control the activation of the INT pin. Writing a '1' to a Mask register bit will allow
the corresponding Status register bit to activate the INT pin when set.
DRDY
Data Ready. During conversion, this bit indicates that low-rate results have been updated.
It indicates completion of other commands and the reset sequence.
I1OR (I2OR)
V1OR (V2OR)
CRDY
Current Out of Range. Set when the measured current would cause the I1 (I2) register to
overflow.
Voltage Out of Range. Set when the measured voltage would cause the V1 (V2) register
to overflow.
Conversion Ready. Indicates that sample rate (output word rate) results have been updat-
ed.
I1ROR (I2ROR)
RMS Current Out of Range. Set when RMS current would cause the I1
(I2
) regis-
RMS
RMS
ter to overflow.
V1ROR (V2ROR) RMS Voltage Out of Range. Set when RMS voltage would cause the V1
(V2
) reg-
RMS
RMS
ister to overflow.
E1OR (E2OR)
Energy Out of Range. Set when average power would cause P1
(P2
) to overflow.
AVG
AVG
I1FAULT (I2FAULT)Indicates when a current fault condition has occurred.
V1SAG (V2SAG) Indicates when a voltage sag condition has occurred.
TUP
Indicates when the Temperature register (T) has been updated.
V1OD (V2OD)
I1OD (I2OD)
LSD
Modulator oscillation has been detected in the voltage1 (voltage2) A/D.
Modulator oscillation has been detected in the current1 (current2) A/D.
Low Supply Detect. Set when the voltage on the PFMON pin falls below the specified low
level. The LSD bit cannot be reset until the voltage rises above the specified high level.
FUP
IC
Frequency Updated. Indicates the Epsilon register has been updated.
Invalid Command. Normally logic 1. Set to 0 when an invalid command is received. It may
also indicate loss of serial command synchronization and the part may need to be re-ini-
tialized.
32
DS714F3
CS5467
8.2.13 Control (Ctrl) – Address: 28
23
22
21
20
19
18
17
16
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
15
14
13
12
11
10
9
8
-
-
-
I2gain
-
-
-
STOP
7
6
5
4
3
2
1
0
-
-
I1gain
INTOD
-
NOCPU
NOOSC
-
Default = 0
PC[7:0]
Phase compensation for channel 2. Sets a delay in voltage relative to current. Phase is
signed and in the range of -1.0 value 1.0 sample (OWR) intervals.
I1gain (I2gain)
STOP
Sets the gain of the current1 (current2) input.
0 = Gain is set for ±250mV range.
1 = Gain is set for ±50mV range.
2
Terminates E PROM command sequence (if used).
0 = No Action
2
1 = Stop E PROM Commands.
INTOD
Converts INT output pin to an open drain output.
0 = Normal Output
1 = Open-drain Output
NOCPU
NOOSC
Saves power by disabling the CPUCLK output pin.
0 = CPUCLK Enabled
1 = CPUCLK Disabled
Disables the crystal oscillator, making XIN a logic-level input.
0 = Crystal Oscillator Enabled
1 = Crystal Oscillator Disabled
DS714F3
33
CS5467
8.3 Page 1 Registers
8.3.1 DC Offset for Current (I1OFF , I2OFF ) and Voltage (V1OFF , V2OFF
)
Address: 0 (I1
), 2 (V1
), 7 (I2
), 9 (V2
)
OFF
OFF
OFF
OFF
MSB
LSB
-(20)
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-17
2-18
2-19
2-20
2-21
2-22
2-23
.....
Default = 0
DC offset registers I1
& V1
(I2
& V2
) are initialized to zero on reset. During DC offset calibra-
OFF
OFF
OFF
OFF
tion, selected registers are written with the inverse of the DC offset measured. The application program can
also write the DC offset register values. These are two's complement values in the range of -1.0 value 1.0,
with the binary point to the right of the MSB.
8.3.2 Gain for Current (I1GAIN , I2GAIN ) and Voltage (V1GAIN , V2GAIN
)
Address: 1 (I1
), 3 (V1
), 8 (I2
), 10 (V2
)
GAIN
GAIN
GAIN
GAIN
MSB
LSB
21
20
2-1
2-2
2-3
2-4
2-5
2-6
2-16
2-17
2-18
2-19
2-20
2-21
2-22
.....
Default = 1.0
Gain registers I1
& V1
(I2
& V2
) are initialized to 1.0 on reset. During AC or DC gain calibra-
GAIN
GAIN
GAIN
GAIN
tion, selected register are written with the multiplicative inverse of the gain measured. These are unsigned
fixed-point values in the range of 0 value 4.0, with the binary point to the right of the second MSB.
8.3.3 Power Offset (P1OFF , P2OFF
Address: 4 (P1
)
)
), 11 (P2
OFF
OFF
MSB
LSB
-(20)
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-17
2-18
2-19
2-20
2-21
2-22
2-23
.....
Default = 0
Power offset P1
(P2
) is added to instantaneous power and averaged over a low-rate interval to yield
OFF
OFF
P1
(P2
) register results. It can be used to reduce systematic energy errors. These are two's comple-
AVG
AVG
ment values in the range of -1.0 value 1.0, with the binary point to the right of the MSB.
8.3.4 AC Offset for Current (I1ACOFF , I2ACOFF ) and Voltage (V1ACOFF , V2ACOFF
)
Address: 5 (I1
), 6 (V1
), 12 (I2
), 13 (V2
)
ACOFF
ACOFF
ACOFF
ACOFF
MSB
LSB
-(20)
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-17
2-18
2-19
2-20
2-21
2-22
2-23
.....
Default = 0
AC offset registers I1
& V1
(V
& V2
) are initialized to zero on reset. These are added
ACOFF
ACOFF ACOFF
ACOFF
to the RMS results before being stored to the RMS result registers. They can be used to reduce systematic
errors in the RMS results. These are two's complement values in the range of -1.0 value 1.0, with the bi-
nary point to the right of the MSB.
34
DS714F3
CS5467
8.3.5 Mode Control (Modes) – Address: 16
23
22
21
20
19
18
17
16
-
VFIX
-
-
-
-
-
-
15
14
13
12
11
10
9
8
-
E1MODE1
E1MODE0
-
-
E2MODE1
E2MODE0
VHPF2
7
6
5
4
3
2
1
0
IHPF2
VHPF1
IHPF1
-
E3MODE1
E3MODE0
POS
AFC
Default = 0
VFIX
Use internal RMS voltage reference instead of voltage input for average active power.
0 = Use voltage input.
1 = Use internal RMS voltage reference, VF
.
RMS
E1MODE[1:0]
E1, E2, and E3 alternate output mode (when enabled by E2MODE).
00 = E1, E2 = P1AVG, P2AVG
01 = E1, E2 = S1, S2
10 = E1, E2 = Q1AVG, Q2AVG
11 = E1, E2 = Q1WB, Q2WB
E2MODE[1:0]
VHPF2:IHPF2
VHPF1:IHPF1
E3MODE[1:0]
E3MODE[1:0]
E2 Output Mode
00 = Energy Sign
01 = Total Apparent Energy
10 = Not Used
11 = Enable E1MODE
High-pass Filter Enable for Energy Channel 2
00 = No Filter
01 = HPF on Current, PMF on Voltage
10 = HPF on Voltage, PMF on Current
11 = HPF on both Voltage and Current
High-pass Filter Enable for Energy Channel 1
00 = No Filter
01 = HPF on Current, PMF on Voltage
10 = HPF on Voltage, PMF on Current
11 = HPF on both Voltage and Current
E3 Output Mode (with E1MODE disabled)
00 = Total Reactive Energy (default)
01 = Power Fail Monitor
10 = Voltage1 Sign
11 = Total Apparent Energy
E3 Output Mode (with E1MODE enabled)
00 = Power Fail Monitor
01 = Energy Sign
10 = Not Used
11 = Not Used
POS
AFC
Positive Energy Only. Suppresses negative values in P1
is calculated, zero will be stored instead.
and P2
. If a negative value
AVG
AVG
Enables automatic line frequency measurement which sets Epsilon every time a new line
frequency measurement completes. Epsilon is used to control the gain of the 90 degree
phase shift integrator used in quadrature power calculations.
DS714F3
35
CS5467
8.3.6 Line to Sample Frequency Ratio (Epsilon) – Address: 17
MSB
-(20)
LSB
2-23
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-17
2-18
2-19
2-20
2-21
2-22
.....
Default = 0.0125 (4.0 kHz x 0.0125 or 50 Hz)
Epsilon is the ratio of the input line frequency to the output word rate (OWR). It can either be written by the ap-
plication program or calculated automatically from the line frequency (from the voltage input) using the AFC bit
in the Modes register. It is a two's complement value in the range of -1.0 value 1.0, with the binary point to
the right of the MSB. Negative values are not used.
8.3.7 Pulse Output Width (PulseWidth) – Address: 14
MSB
LSB
222
221
220
219
218
217
216
26
25
24
23
22
21
20
0
.....
Default = 1 (250 uS at OWR = 4 kHz)
PulseWidth sets the duration of energy pulses. The actual pulse duration is the contents of PulseWidth divided
by the output word rate (OWR). PulseWidth is an integer in the range of 1 to 8,388,607.
8.3.8 Pulse Output Rate (PulseRate) – Address: 15
MSB
LSB
-(20)
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-17
2-18
2-19
2-20
2-21
2-22
2-23
.....
Default= -1
PulseRate sets the full-scale frequency for E1, E2, E3 pulse outputs. For a 4 kHz sample rate, the maximum
pulse rate is 2 kHz. This is a two's complement value in the range of -1 value 1, with the binary point to the
left of the MSB.
Refer to 6.10 Energy Pulse Rate on page 21 for more information.
8.3.9 Cycle Count (N) – Address: 19
MSB
LSB
222
Default = 4000
221
220
219
218
217
216
26
25
24
23
22
21
20
.....
0
Determines the number of output word rate (OWR) samples to use in calculating low-rate results. Cycle Count
(N) is an integer in the range of 10 to 8,388,607. Values less than 10 should not be used.
8.3.10 Wideband Reactive Power (Q1WB , Q2WB
)
Address: 20 (Q1
), 21 (Q2
)
WB
WB
MSB
LSB
-(20)
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-17
2-18
2-19
2-20
2-21
2-22
2-23
.....
Wideband reactive power is calculated using vector subtraction. (See Section 4.8 Power and Energy Results
on page 16). The value is signed, but has a range of 0 value 1.0. The binary point is to the right of the MSB.
36
DS714F3
CS5467
8.3.11 Temperature Gain (TGAIN ) – Address: 22
MSB
LSB
26
25
24
23
22
21
20
2-1
2-11
2-12
2-13
2-14
2-20
23
2-15
2-21
22
2-16
2-22
21
2-17
.....
Default = 0x2F02C3
Refer to 6.13 Temperature Measurement on page 22 for more information.
8.3.12 Temperature Offset (TOFF ) – Address: 23
MSB
-(20)
LSB
2-23
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-17
2-18
2-19
.....
Default = 0xF3D35A
Refer to 6.13 Temperature Measurement on page 22 for more information.
8.3.13 Filter Settling Time for Conversion Startup (TSETTLE ) – Address: 25
MSB
223
LSB
20
222
221
220
219
218
217
216
26
25
24
.....
Default = 30
Sets the number of output word rate (OWR) samples that will be used to allow filters to settle at the beginning
of Conversion and Calibration commands. This is an integer in the range of 0 to 8,388,607 samples.
8.3.14 No Load Threshold (LoadMIN ) – Address: 26
MSB
LSB
-(20)
2-1
Default = 0
2-2
2-3
2-4
2-5
2-6
2-7
2-17
2-18
2-19
2-20
2-21
2-22
2-23
.....
Load
E
is used to set the no load threshold. When the magnitude of the E
register is less than Load
,
MIN
MIN
PULSE
will be zeroed. If the magnitude of the Q
register is less than Load , Q
will be zeroed.
PULSE
MIN
PULSE
pulse
Load
is a two’s compliment value in the range of -1.0 value 1.0, with the binary point to the right of the
MIN
MSB. Negative values are not used.
8.3.15 Voltage Fixed RMS Reference (VFRMS ) – Address 27
MSB
-(20)
LSB
2-23
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-17
2-18
2-19
2-20
2-21
2-22
.....
Default = 0.7071068 (full scale RMS)
If the application program detects that the meter has possibly been tampered with in such a manner that the
voltage input is no longer working, it may choose to use this internal RMS reference instead of the disabled
voltage input by setting the VFIX bit in the Modes register. This is a two's complement value in the range of
0 value 1.0, with the binary point to the right of the MSB. Negative values are not used.
DS714F3
37
CS5467
8.3.16 System Gain (G) – Address: 28
MSB
LSB
-(21)
20
Default = 1.25
2-1
2-2
2-3
2-4
2-5
2-6
2-16
2-17
2-18
2-19
2-20
2-21
2-22
.....
System Gain (G) is applied to all channels. By default, G = 1.25, but can be finely adjusted to compensate for
voltage reference error. It is a two's complement value in the range of -2.0 value 2.0, with the binary point
to the right of the second MSB. Values should be kept within 5% of 1.25.
8.3.17 System Time (Time) – Address: 29
MSB
LSB
223
222
Default = 0
221
220
219
218
217
216
26
25
24
23
22
21
20
.....
System Time (Time) is measured in output word rate (OWR) samples. This is an unsigned integer in the range
of 0 to 16,777,215 samples. At OWR = 4.0 kHz, OWR will overflow every 1 hour, 9 minutes, and 54 seconds.
Time can be used by the application to manage real-time events.
38
DS714F3
CS5467
8.4 Page 2 Registers
8.4.1 Voltage Sag and Current Fault Duration (V1SagDUR , V2SagDUR , I1FaultDUR , I2FaultDUR
)
Address: 0 (V1Sag
), 8 (V2Sag
), 4 (I1Fault
), 12 (I2Fault
)
DUR
DUR
DUR
DUR
MSB
LSB
222
221
220
219
218
217
216
26
25
24
23
22
21
20
0
.....
Default = 0
Voltage sag duration, V1Sag
(V2Sag
) and current fault duration, I1Fault
(I2Fault
) determine
DUR
DUR
DUR
DUR
the count of output word rate (OWR) samples utilized to determine a sag or fault event. These are integers in
the range of 0 to 8,388,607 samples. A value of zero disables the feature.
8.4.2 Voltage Sag and Current Fault Level (V1SagLEVEL , V2SagLEVEL , I1FaultLEVEL , I2FaultLEVEL
)
Address: 1 (V1Sag
), 9 (V2Sag
), 5 (I1Fault
), 13 (I2Fault
)
LEVEL
LEVEL
LEVEL
LEVEL
MSB
LSB
-(20)
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-17
2-18
2-19
2-20
2-21
2-22
2-23
.....
Default = 0
Voltage sag level, V1Sag
(V2Sag
) and current fault level, I1Fault
(I2Fault
) establish
LEVEL
LEVEL
LEVEL
LEVEL
an input level below which a sag or fault is triggered. These are two's complement values in the range of
-1.0 value 1.0, with the binary point to the right of the MSB. Negative values are not used.
8.5 Page 5 Register
8.5.1 Temperature Measurement (TMEAS ) – Address: 26
MSB
223
LSB
20
222
221
220
219
218
217
216
26
25
24
23
22
21
.....
Default = 0
The Temperature Measurement (T
) register is used to cycle-steal voltage channel2 for temperature
MEAS
measurement. Writing a one to the LSB causes the temperature to be measured and the Temperature register
(T) to be updated.
Refer to 6.13 Temperature Measurement on page 22 for more information.
DS714F3
39
CS5467
9. SYSTEM CALIBRATION
9.1 Calibration
The CS5467 provides DC offset and gain calibration
that can be applied to the voltage and current measure-
ments, and AC offset calibration which can be applied to
the voltage and current RMS calculations.
External
Connections
+
-
+
-
IN+
+
-
0V
XGAIN
Since the voltage and current channels have indepen-
dent offset and gain registers, offset and gain calibra-
tion can be performed on any channel independently.
IN-
+
-
CM
The data flow of the calibration is shown in Figure 10.
The CS5467 must be operating in its active state and
ready to accept valid commands. Refer to 7.6 Com-
mands on page 25.
Figure 11. System Calibration of Offset
9.1.1.1 DC Offset Calibration
The value in the Cycle Count register (N) determines
the number of output word rate (OWR) samples that are
averaged during a calibration. DC offset and gain cali-
The DC Offset Calibration command measures and av-
erages DC values read on specified voltage or current
channels at zero input and stores the inverse result in
the associated offset registers. This will be added to in-
stantaneous measurements in subsequent conver-
sions, removing the offset.
brations take at least N + T
samples. AC offset
SETTLE
calibrations take at least 6(N) + T
samples. As N
SETTLE
is increased, the accuracy of calibration results tends to
also increase.
Gain registers for channels being calibrated should be
set to 1.0 prior to performing DC offset calibration.
The DRDY bit in the Status register will be set at the
completion of Calibration commands. If an overflow oc-
curs during calibration, other Status register bits may be
set as well.
9.1.1.2 AC Offset Calibration
The AC Offset Calibration command measures the re-
sidual RMS values read on specified voltage or current
channels at zero input and stores the inverse result in
the associated AC offset registers. This will be added to
RMS measurements in subsequent conversions, re-
moving the offset.
9.1.1 Offset Calibration
During offset calibrations, no line voltage or current
should be applied to the meter. A zero-volt differential
signal can also be applied to the voltage inputs VIN1
VIN2 or current inputs IIN1 (IIN2of the CS5467.
(see Figure 11.)
AC offset registers for channels being calibrated should
first be cleared prior to performing the calibration.
V1, I1, V2, I2
RMS
I1RMS, V1RMS
I2RMS, V2RMS
+
N
,
Filter
Modulator
In
X
N
X
+
+
+
I1ACOFF, V1ACOFF
,
N
I1DCOFF, V1DCOFF
,
I1GAIN, V1GAIN,
I2DCOFF, V2DCOFF I2GAIN, V2GAIN
I2ACOFF, V2ACOFF
AC Offset
DC Gain
DC Offset AC Gain
Negate
1
N
Negate
DCAVG
DC AVG
0.6
RMS
= READABLE/WRITABLE REGISTERS.
Figure 10. Calibration Data Flow
40
DS714F3
CS5467
During AC gain calibration the RMS level of the applied
reference is measured with the preset gain, then divided
into 0.6 and the quotient stored back into the corre-
sponding gain register.
9.1.2 Gain Calibration
During gain calibration, a full-scale reference signal
must be applied to the meter or optionally, scaled to the
VIN1VIN2,IIN1 (IIN2pins of the CS5467. A DC
reference must be used for DC gain calibration. Either
an AC or DC reference can be used for RMS AC calibra-
tions. If DC is used, the associated high-pass filter
(HPF) must be off.
9.1.2.2 DC Gain Calibration
With a DC reference applied, the DC Gain Calibration
command measures and averages DC values read on
the specified voltage or current channels and stores the
reciprocal result in the associated gain registers, con-
verting measured voltage into needed gain. Subse-
quent conversions will use the new gain value.
Figure 12 shows the basic setup for gain calibration.
External
Connections
+
-
+
-
9.1.3 Calibration Order
1. DC offset.
IN+
Reference
Signal
+
-
XGAIN
2. DC or AC gain.
IN-
+
-
CM
3. AC offset (if needed).
If both AC gain and offset calibrations were performed,
it is possible to repeat both to obtain additional accuracy
as AC gain and offset may interact.
Figure 12. System Calibration of Gain.
Using a reference that is too large or too small can
cause an over-range condition during calibration. Either
condition can set Status register bits I1OR (I2OR)
V1OR (V2OR) for DC and I1ROR (I2ROR) V1ROR
(V2ROR) for AC calibration.
9.1.4 Temperature Sensor Calibration
Temperature sensor calibration involves the adjustment
of two parameters - VBE and VBE0. These values must
be known in order to calibrate the temperature sensor.
See Section 6.13 Temperature Measurement on page
22 for an explanation of VBE and VBE0 and how to cal-
Full scale (FS) for the voltage input is ±250 mV peak
and for the current inputs is ±250 mV or ±50 mV peak
depending on selected gain range. The normal peak
voltage applied to these pins should not exceed these
levels during calibration or normal operation.
culate T
and T
register values from them.
OFF
GAIN
9.1.4.1 Temperature Offset Calibration
Offset calibration can be done at any temperature, but
should be done mid-scale if any gain error exists.
The range of the gain registers limits the gain calibration
range and subsequently the range of the reference level
that can be applied. The reference should not exceed
FS or be lower than FS/4.
Subtract the measured T register temperature from the
actual temperature to determine the offset error. Multi-
ply this error by VBE and add it to VBE0 to yield a new
9.1.2.1 AC Gain Calibration
VBE0 value. Recalculate T
using this new value.
OFF
Full scale for AC RMS gain calibrations is 60% of the in-
put’s full-scale range, which is either 250 mV or 50 mV
depending on the gain range selected. That’s 150 mV or
30 mV, again depending on range. So the normal refer-
9.1.4.2 Temperature Gain Calibration
Two temperature points far enough apart to give rea-
sonable accuracy, for example 25°C and 85°C, are re-
quired to calibrate temperature gain.
ence input level should be either 150 or 30 mV
or DC.
, AC
RMS
Divide the actual temperature difference by the mea-
sured (T register) difference for the two temperatures.
Prior to executing an AC Gain Calibration command,
gain registers for any channel to be calibrated should be
set to 1.0 if the reference level mentioned above is
used, or to that level divided by the actual reference lev-
el used.
This gives a gain correction factor. Update the T
GAIN
register by multiplying it’s value by this correction factor.
Update VBE by dividing its old value by the gain cor-
rection factor. It will be needed for subsequent offset
calibrations.
DS714F3
41
CS5467
2
10. E PROM OPERATION
2
The CS5467 can accept commands from a serial
10.2 E PROM Code
2
E PROM connected to the serial interface instead of a
The EEPROM code should do the following:
host microcontroller. A high level (logic 1) on the MODE
2
1. Set any Configuration or Control register bits, such as
HPF enables and phase compensation settings.
input indicates that an E PROM is connected. This
makes the CS and SCLK pins become driven outputs.
After reset and after running the initialization program,
the CS5467 begins reading commands from the con-
2. Write any calibration data to gain and offset registers.
3. Set energy output pulse width, rate, and formats.
4. Execute a Continuous Conversion command.
5. Set the STOP bit in the Control register (last).
2
nected E PROM.
2
10.1 E PROM Configuration
A typical connection between the CS5467 and a
E PROM is shown in Figure 13.
2
Below is an example E PROM code set.
2
-7E 00 00 01
The CS5467 asserts CS (logic 0), clocks SCLK, and
Change to page 1.
2
sends Read commands to the E PROM on SDO.
-60 00 01 E0
Command format is identical to microcontroller mode,
except the CS5467 will not attempt to write to the EE-
PROM device. The command sequence stops when the
STOP bit in the Control register (Ctrl) is written by the
command sequence.
Write Modes Register, turn high-pass filters on.
-42 7F C4 A9
Write value of 0x7FC4A9 to I1
-46 FF B2 53
Write value of 0xFFB253 to V1
-50 7F C4 A9
Write value of 0x7FC4A9 to I2
-54 FF B2 53
Write value of 0xFFB253 to V2
-7E 00 00 00
register.
register.
register.
register.
GAIN
GAIN
VD
+
E1
Pulse Output
GAIN
Counter
E2
5 K
EEPROM
CS5467
GAIN
SCLK
SCK
SDI
SO
SI
Change to page 0.
-74 00 00 04
SDO
CS
5 K
MODE
CS
Set LSD bit to 1 in the Mask register.
-E8
Start continuous conversions
-78 00 01 00
Connector to Calibrator
Write STOP bit to the Control register (Ctrl) to
terminate E PROM command sequence.
2
Figure 13. Typical Interface of E PROM to CS5467
2
2
10.3 Which E PROMs Can Be Used?
Figure 13 also shows the external connections that
would be made to a calibration device, such as a note-
book computer, handheld calibrator, or tester during
meter assembly, The calibrator or tester can be used to
control the CS5467 during calibration and program the
2
Several industry-standard serial E PROMs can be used
with the CS5467. Some are listed below:
•
•
•
Atmel AT25010, AT25020 or AT25040
National Semiconductor NM25C040M8 or NM25020M8
2
required values into the E PROM.
Xicor X25040SI
2
These serial E PROMs expect a specific 8-bit com-
mand (00000011) in order to perform a memory read.
The CS5467 has been hardware programmed to trans-
2
mit this 8-bit command to the E PROM after reset.
42
DS714F3
CS5467
11. BASIC APPLICATION CIRCUITS
Figure 14 shows the CS5467 configured to measure
power in a single-phase, 3-wire system while operating
in a single-supply configuration. In this diagram, current
transformers (CT) are used to sense the line currents
and voltage dividers are used to sense the line voltages.
5 k
10 k
L2
N
L1
10
500
500
0.1 µF
470 µF
0.1 µF
2 uF
3
18
VA+
VD+
13
VIN2+
C
V+
CS5467
CVdiff
R
R
1
2
CV-
RV-
21
14
9
VIN2-
VIN1+
PFMON
CPUCLK
XOUT
2
1
4.096 MHz
C
V+
CVdiff
R
R
2
Optional
Clock
Source
1
28
XIN
CV-
RV-
10
19
VIN1-
IIN1-
R I-
23
CI-
CI+
½ RBurden
½ RBurden
RESET
CS
7
CIdiff
CT
Serial
Data
Interface
27
6
SDI
20
SDO
SCLK
INT
IIN1+
IIN2-
5
RI+
24
RI-
15
16
26
25
E2
E1
CI-
CI+
½ RBurden
½ RBurden
CIdiff
CT
Pulse Output
Counter
IIN2+
RI+
12
VREFIN
LOAD
LOAD
11
VREFOUT
0.1 µF
AGND
17
DGND
4
Figure 14. Typical Connection Diagram (Single-phase, 3-wire – Direct Connect to Power Line)
DS714F3
43
CS5467
12. PACKAGE DIMENSIONS
28L SSOP PACKAGE DRAWING
N
D
E11
A2
A
E
A1
b2
e
L
END VIEW
SEATING
PLANE
SIDE VIEW
1
2 3
TOP VIEW
INCHES
NOM
--
0.006
0.069
--
0.4015
0.307
0.209
0.026
0.0354
4°
MILLIMETERS
NOTE
DIM
A
A1
A2
b
D
E
E1
e
L
MIN
--
MAX
0.084
0.010
0.074
0.015
0.413
0.323
0.220
0.030
0.041
8°
MIN
--
NOM
--
0.15
1.75
--
10.20
7.80
5.30
0.65
0.90
4°
MAX
2.13
0.25
1.88
0.38
10.50
8.20
5.60
0.75
1.03
8°
0.002
0.064
0.009
0.390
0.291
0.197
0.022
0.025
0°
0.05
1.62
0.22
9.90
7.40
5.00
0.55
0.63
0°
2,3
1
1
JEDEC #: MO-150
Controlling Dimension is Millimeters
Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch
and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side.
2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in
excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more
than 0.07 mm at least material condition.
3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
44
DS714F3
CS5467
13. ORDERING INFORMATION
Model
Temperature
Package
CS5467-ISZ (lead free)
-40 to +85 °C
28-pin SSOP
14. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION
Model Number
Peak Reflow Temp
MSL Rating*
Max Floor Life
7 Days
260 °C
3
CS5467-ISZ (lead free)
* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
DS714F3
45
CS5467
15. REVISION HISTORY
Revision
PP1
Date
Changes
FEB 2007
FEB 2007
Initial release.
PP2
Corrections to implicitly state that temperature measurement is a secondary func-
tion of voltage2 channel. Updated typical connection diagram. Changed Phase
Compensation Range from ±2.8° to ±5.4°.
F1
F2
MAR 2007
JAN 2010
Updated to F1 for quality process level (QPL).
Increased on-chip reference temperature coefficient from 25 ppm / °C typ. to
40 ppm / °C typ.
F3
APR 2011
Removed lead-containing (Pb) device ordering information.
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com
IMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available.
Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,
copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con-
sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent
does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP-
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IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRIT-
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FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOM-
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Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
46
DS714F3
相关型号:
CS5480-INZ/B0
ADC, Delta-Sigma, 24-Bit, 1 Func, 3 Channel, Serial Access, CMOS, 4 X 4 MM, MO-220, QFN-24
CIRRUS
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