EP9303-CBZ_技术文档

EP9303 Data Sheet

FEATURES

•

200 MHz ARM920T Processor

ARM9 SOC with Display,

USB and Touchscreen

•

16 Kbyte Instruction Cache

16 Kbyte Data Cache

®

•

Linux , Microsoft Windows CE enabled MMU

•

One Serial Peripheral Interface (SPI) Port

100 MHz System Bus

2

•

2-channel Serial Audio Interface (I S)

™

•

MaverickCrunch Math Engine

2-channel low-cost Serial Audio Interface (AC'97)

2 High Resolution PWM (16 bits each)

•

Floating point, integer and signal processing

instructions

•

Internal Peripherals

Optimized for digital music compression and

decompression algorithms

•

12 Direct Memory Access (DMA) Channels

Real-time Clock with software Trim

Dual PLL controls all clock domains

Watchdog Timer

Hardware interlocks allow in-line coding

™

•

MaverickKey IDs

•

32-bit unique ID can be used for DRM compliance

128-bit random ID

Two general purpose 16-bit timers

One general purpose 32-bit timer

One 40-bit Debug Timer

Integrated Peripheral Interfaces

•

32-bit SDRAM Interface up to 4 banks

32/16-bit SRAM/FLASH/ROM

Serial EEPROM Interface

Three UARTs

Interrupt Controller

Boot ROM

•

Package

272 pin TFBGA

•

Three-port USB 2.0 Full Speed Host (OHCI)

(12 Mbits per second)

•

IrDA Interface

LCD and Raster Interface with Graphics

Accelerator

•

Touchscreen Interface with ADC

8 x 8 Keypad Scanner

Serial

Audio

Interface

Peripheral Bus

Clocks &

Timers

MaverickCrunch^TM

ARM920T

10 Channel DMA

Interrupts

& GPIO

(3) UARTs

w/

MaverickKey^TM

IrDA

D-Cache

16KB

I-Cache

16KB

Keypad &

Touch

Screen I/F

(3) USB

Hosts

Boot

ROM

Bus

Bridge

MMU

Processor Bus

Unified

SDRAM I/F

SRAM &

Flash I/F

Graphic

Accelerator

Video/LCD

Controller

MEMORY AND STORAGE

FEB ‘04

DS645A1

http://www.cirrus.com

1

EP9303

ARM9 SOC with Display, USB and Touchscreen

™

MaverickKey unique hardware programmed IDs are a

OVERVIEW

solution to the growing concern over secure web content

and commerce. With Internet security playing an

important role in the delivery of digital media such as

books or music, traditional software methods are quickly

becoming unreliable. The MaverickKey unique IDs

provide OEMs with a method of utilizing specific

hardware IDs such as those assigned for SDMI (Secure

Digital Music Initiative) or any other authentication

mechanism.

The EP9303 is an ARM920T-based system-on-a-chip

design with a large peripheral set targeted to a variety of

applications:

•

Thin client computers for business and home

Internet radio

Personal digital assistants

Internet access devices

Industrial computers

2

External interfaces to SPI, I S audio, Raster/LCD,

Industrial hand-held devices

Point of sale terminals

keypad and touchscreen are included. A three-port USB

2.0 Full Speed Host (OHCI) (12 Mbits per second) and

three UARTs are included as well.

Test and measurement equipment

The EP9303 is a high-performance, low-power RISC-

based single-chip computer built around an ARM920T

microprocessor core with a maximum operating clock

rate of 200 MHz (184 MHz for industrial conditions). The

ARM core operates from a 1.8 V supply, while the I/O

operates at 3.3 V with power usage between 100 mW

and 750 mW (dependent on speed).

The EP9303 is one of a series of ARM920T-based

devices. Each chip in the series has differently focused

peripheral sets, power consumption refinements, and

coprocessors.

The ARM920T microprocessor core with separate

16 Kbyte, 64-way set-associative instruction and data

caches is augmented by the MaverickCrunch™ co-

processor enabling faster than real-time compression of

audio CDs.

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative.

To find one nearest you go to www.cirrus.com

IMPORTANT NOTICE

"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries

("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS

IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that infor-

mation being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including

those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this infor-

mation as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by

furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual

property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within

your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribu-

tion, advertising or promotional purposes, or for creating any work for resale.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY

OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIR-

CRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL AP-

PLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SECURITY DEVICES).

INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND

MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICU-

LAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR

PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS,

DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY

RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.

Cirrus Logic, Cirrus, MaverickCrunch, MaverickKey, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this

document may be trademarks or service marks of their respective owners.

Microsoft and Windows are registered trademarks of Microsoft Corporation.

MicrowireTM is a trademark of National Semiconductor Corp. National Semiconductor is a registered trademark of National Semiconductor Corp.

Texas Instruments is a registered trademark of Texas Instruments, Inc.

Motorola is a reigistered trademark of Motorola, Inc.

LINUX is a registered trademark of Linus Torvalds.

2

DS645A1

EP9303

ARM9 SOC with Display, USB and Touchscreen

provide OEMs with a method of utilizing specific

hardware IDs such as those assigned for SDMI (Secure

Digital Music Initiative) or any other authentication

mechanism.

Processor Core - ARM920T

The ARM920T is a Harvard architecture processor with

separate 16 Kbyte instruction and data caches with an 8-

word line length but a unified memory. The processor

utilizes a five-stage pipeline consisting of fetch, decode,

execute, memory and write stages. Key features include:

Both a specific 32-bit ID as well as a 128-bit random ID is

programmed into the EP9303 through the use of laser

probing technology. These IDs can then be used to

match secure copyrighted content with the ID of the

target device the EP9303 is powering, and then deliver

the copyrighted information over a secure connection. In

addition, secure transactions can benefit by also

matching device IDs to server IDs. MaverickKey IDs

provide a level of hardware security required for today’s

Internet appliances.

•

ARM (32-bit) and Thumb (16-bit compressed)

instruction sets

32-bit Advanced Micro-Controller Bus Architecture

(AMBA)

•

16 Kbyte Instruction Cache with lockdown

16 Kbyte Data Cache (programmable write-through or

write-back) with lockdown

®

•

MMU for Linux , Microsoft Windows CE and other

operating systems

General Purpose Memory Interface (SDRAM,

SRAM, ROM, FLASH)

Translation Look Aside Buffers with 64 Data and 64

Instruction Entries

The EP9303 features a unified memory address model

where all memory devices are accessed over a common

address/data bus. A separate internal port is dedicated to

the read-only Raster/LCD refresh engine, while the rest

of the memory accesses are performed via the Processor

bus. The SRAM memory controller supports 8, 16 and

32-bit devices and accommodates an internal boot ROM

concurrently with 32-bit SDRAM memory.

Programmable Page Sizes of 64 Kbyte, 4 Kbyte, and

1 Kbyte

Independent lockdown of TLB Entries

™

MaverickCrunch Math Engine

The MaverickCrunch Engine is

a

mixed-mode

coprocessor designed primarily to accelerate the math

processing required to rapidly encode digital audio

formats. It accelerates single and double precision

integer and floating point operations plus an integer

•

1-4 banks of 32-bit 66 or 100 MHz SDRAM

One internal port dedicated to the Raster/LCD

Refresh Engine (Read Only)

multiply-accumulate

(MAC)

instruction

that

is

•

One internal port dedicated to the rest of the chip via

the Processor bus

considerably faster than the ARM920T's native MAC

instruction. The ARM920T coprocessor interface is

utilized thereby sharing its memory interface and

instruction stream. Hardware forwarding and interlock

allows the ARM to handle looping and addressing while

MaverickCrunch handles computation. Features include:

Address and data bus shared between SDRAM,

SRAM, ROM, and FLASH memory

Both NAND and NOR FLASH memory supported

Table A. General Purpose Memory Interface Pin Assignments

•

IEEE-754 single and double precision floating point

32/64-bit integer

Pin Mnemonic

Pin Description

SDCLK

SDRAM Clock

Add/multiply/compare

SDCLKEN

SDCSn[3:0]

RASn

SDRAM Clock Enable

SDRAM Chip Selects 3-0

SDRAM RAS

Integer MAC 32-bit input with 72-bit accumulate

Integer Shifts

Floating point to/from integer conversion

Sixteen 64-bit register files

CASn

SDRAM CAS

SDWEn

SDRAM Write Enable

Chip Selects 7, 6, 3, 2, 1, 0

Address Bus 25-0

Four 72-bit accumulators

CSn[7:6] and CSn[3:0]

AD[25:0]

DA[31:0]

DQMn[3:0]

WRn

™

MaverickKey Unique ID

Data Bus 31-0

MaverickKey unique hardware programmed IDs are a

solution to the growing concern over secure web content

and commerce. With Internet security playing an

important role in the delivery of digital media such as

books or music, traditional software methods are quickly

becoming unreliable. The MaverickKey unique IDs

SDRAM Output Enables / Data Masks

SRAM Write Strobe

SRAM Read/OE Strobe

SRAM Wait Input

RDn

WAITn

DS645A1

3

EP9303

ARM9 SOC with Display, USB and Touchscreen

2

•

Dedicated data path to SDRAM controller for

improved system performance

Serial Interfaces (SPI, I S and AC ’97)

The SPI port can be configured as a master or a slave,

Pixel depths of 4, 8, 16, or 18-bits per pixel or 256

levels of grayscale

®

supporting the National Semiconductor , Motorola and

®

•

Hardware Cursor up to 64 x 64 pixels

256 x 18 Color Lookup Table

Hardware Blinking

Texas Instruments signaling protocols.

The AC'97 port supports multiple codecs for multichannel

2

audio output with a single stereo input. The I S port can

be configured to support two channel, 24 bit audio.

8-bit interface to low end panel

2

Table C. LCD Interface Pin Assignments

These ports are multiplexed so that the I S port will take

over either the AC'97 pins or the SPI pins.

Pin Mnemonic

Pin Description

•

Normal Mode: One SPI Port and one AC’97 Port.

SPCLK

Pixel Clock

2

P[17:0]

Pixel Data Bus [17:0]

I S on SSP Mode: One AC’97 Port and one I S Port.

Horizontal

Synchronization/Line Pulse

2

I S on AC’97 Mode: One SPI Port and one I S Port.

HSYNC/LP

Note: I²S may not be output on AC’97 and SSP ports at the

same time.

Vertical or Composite

Synchronization / Frame Pulse

VCSYNC/FP

BLANK

Composite Blank

Table B. Audio Interfaces Pin Assignment

BRIGHT

Pulse Width Modulated Brightness

I2S on SSP

Mode

I2S on AC'97

Mode

Normal Mode

Name

Graphics Accelerator

Description

Pin Description Pin Description

The EP9303 contains a hardware graphics acceleration

engine that improves graphic performance by handling

block copy, block fill and hardware line draw operations.

The Graphics Accelerator is used in the system to off-

load graphics operations from the processor.

SCLK1

SFRM1

SPI Bit Clock

I2S Serial Clock

SPI Bit Clock

SPI Frame Clock I2S Frame Clock

SPI Frame Clock

SPI Serial Input

SSPRX1 SPI Serial Input I2S Serial Input

SPI Serial

SSPTX1

I2S Serial Output SPI Serial Output

Output

Pixel depths supported by the Graphics Accelerator are

4, 8, 16 or 24 bits per pixel. The 24 bits per pixel mode

can be operated as packed (4 pixels every 3 words) or

unpacked (1 pixel per word with the high byte unused.)

(No I2S Master

Clock)

ARSTn

AC'97 Reset

I2S Master Clock

I2S Serial Clock

ABITCLK AC'97 Bit Clock AC'97 Bit Clock

The block copy operations of the Graphics Accelerator

are similar to a DMA (Direct Memory Access) transfer

that understands pixel organization, block width,

transparency, and transformation from 1bpp to higher 4,

8, 16 or 24bpp.

AC'97 Frame

Clock

AC'97 Frame

Clock

ASYNC

ASDI

I2S Frame Clock

AC'97 Serial

Input

AC'97 Serial Input I2S Serial Input

AC'97 Serial

Output

AC'97 Serial

I2S Serial Output

Output

ASDO

The line draw operations also allow for solid lines or

dashed lines. The colors for line drawing can be either

foreground color and background color or foreground

color with the background being transparent.

Raster/LCD Interface

The Raster/LCD interface provides data and interface

signals for a variety of display types. It features fully

programmable video interface timing for non-interlaced

flat panel or dual scan displays. Resolutions up to

1280 x 1024 are supported from a unified SDRAM based

frame buffer. A 16-bit PWM provides control for LCD

panel contrast. LCD specific features include:

•

Timing and interface signals for digital LCD and TFT

displays

Full programmability for either non-interlaced or dual-

scan color and grayscale flat panel displays

4

DS645A1

EP9303

ARM9 SOC with Display, USB and Touchscreen

Touch Screen Interface with 12-bit Analog-

to-Digital Converter (ADC)

Universal Asynchronous

Receiver/Transmitters (UARTs)

The touch screen interface performs all sampling,

averaging, ADC range checking, and control for a wide

variety of analog resistive touch screens. This controller

only interrupts the processor when a meaningful change

occurs. The touch screen hardware may be disabled and

the switch matrix and ADC controlled directly if desired.

Features include:

Three 16550-compatible UARTs are supplied. Two

provide asynchronous HDLC (High-level Data Link

Control) protocol support for full duplex transmit and

receive. The HDLC receiver handles framing, address

matching, CRC checking, control-octet transparency, and

optionally passes the CRC to the host at the end of the

packet. The HDLC transmitter handles framing, CRC

generation, and control-octet transparency. The host

must assemble the frame in memory before

transmission. The HDLC receiver and transmitter use the

•

Support for 4, 5, 7, or 8-wire analog resistive touch

screens.

Flexibility - unused lines may be used for temperature

sensing or other functions.

®

UART FIFOs to buffer the data streams. A third IrDA

compatible UART is also supplied.

Touch screen interrupt function.

•

UART1 supports modem bit rates up to 115.2 Kbps,

supports HDLC and includes a 16 byte FIFO for

receive and a 16 byte FIFO for transmit. Interrupts are

generated on Rx, Tx and modem status change.

Table D. Touch Screen Interface with 12-bit Analog-to-Digital

Converter Pin Assignments

Pin Mnemonic

Pin Description

UART2 contains an IrDA encoder operating at either

the slow (up to 115 Kbps), medium (0.576 or 1.152

Mbps), or fast (4 Mbps) IR data rates. It also has a 16

byte FIFO for receive and a 16 byte FIFO for transmit.

Xp, Xm

Touch screen ADC X Axis

Touch screen ADC Y Axis

Yp, Ym

Touch screen ADC X Axis

Voltage Feedback

SXp, SXm

UART3 supports HDLC and includes a 16 byte FIFO

for receive and a 16 byte FIFO for transmit. Interrupts

are generated on Rx and Tx.

Touch screen ADC Y Axis

Voltage Feedback

SYp, SYm

Table F. Universal Asynchronous Receiver / Transmitters Pin

Assignments

64-Keypad Interface

The keypad circuitry scans an 8 x 8 array of 64 normally

open, single pole switches. Any one or two keys

depressed will be de-bounced and decoded. An interrupt

is generated whenever a stable set of depressed keys is

detected. If the keypad is not utilized, the 16 column/row

pins may be used as general purpose I/O. The Keypad

interface:

Pin Mnemonic

Pin Name - Description

TXD0

UART1 Transmit

RXD0

UART1 Receive

UART1 Clear To

Send / Transmit Enable

CTSn

UART1 Data Set

Ready / Data Carrier Detect

DSRn/DCDn

•

Provides scanning, debounce and decoding for a 64-

key array.

DTRn

UART1 Data Terminal Ready

UART1 Ready To Send

UART1 Ring Indicator

RTSn

•

Scans an 8-row by 8-column matrix.

May decode 2 keys at once.

EGPIO[0]/RI

UART2 Transmit / IrDA

Output

Generates an interrupt when a new stable key is

determined.

TXD1/SIROUT

RXD1/SIRIN

TXD2

UART2 Receive / IrDA Input

UART3 Transmit

•

Also generates a 3-key reset interrupt.

RXD2

UART3 Receive

Table E. 64-Key Keypad Interface Pin Assignments

TENn

HDLC3 Transmit Enable

Pin Mnemonic

Alternative Usage

Description

Internal Boot ROM

Key Matrix Column

Inputs

COL[7:0]

ROW[7:0]

General Purpose I/O

The Internal 16 Kbyte ROM allows booting from FLASH

memory, SPI or UART.

Key Matrix Row

Inputs

DS645A1

5

EP9303

ARM9 SOC with Display, USB and Touchscreen

Triple Port USB Host

Real-Time Clock with Software Trim

The USB Open Host Controller Interface (Open HCI)

provides full speed serial communications ports at a

baud rate of 12 Mbits/sec. Up to 127 USB devices

(printer, mouse, camera, keyboard, etc.) and USB hubs

can be connected to the USB host in the USB “tiered-

start” topology.

The software trim feature on the real time clock (RTC)

provides software controlled digital compensation of the

32.768 KHz crystal oscillator. This compensation is

accurate to 1.24 sec/month.

Table I. Real-Time Clock with Pin Assignments

This includes the following features:

Pin Mnemonic

Pin Name - Description

RTCXTALI

Real-Time Clock Oscillator Input

Real-Time Clock Oscillator Output

•

Compliance with the USB 2.0 specification

RTCXTALO

Compliance with the Open HCI Rev 1.0 specification

Supports both low speed (1.5 Mbps) and full speed

(12 Mbps) USB device connections

PLL and Clocking

•

Root HUB integrated with 3 downstream USB ports

The Processor and the Peripheral Clocks operate from a

single 14.7456 MHz crystal.

Transceiver buffers integrated, over-current protection

on ports

The Real Time Clock operates from a 32.768 KHz crystal

oscillator.

•

Supports power management

Operates as a master on the bus

The Open HCI host controller initializes the master DMA

transfer with the AHB bus:

Table J. PLL and Clocking Pin Assignments

Pin Mnemonic

Pin Name - Description

•

Fetches endpoint descriptors and transfer descriptors

Accesses endpoint data from system memory

Accesses the HC communication area

XTALI

Main Oscillator Input

XTALO

Main Oscillator Output

Main Oscillator Power

Main Oscillator Ground

VDD_PLL

GND_PLL

Writes status and retire transfer descriptor

Table G. Triple Port USB Host Pin Assignments

Timers

Pin Mnemonic

Pin Name - Description

The Watchdog Timer insures proper operation by

requiring periodic attention to prevent a reset-on-time-

out.

USBp[2:0]

USBm[2:0]

USB Positive signals

USB Negative Signals

Two 16-bit timers operate as free running down-counters

or as periodic timers for fixed interval interrupts and have

a range of 0.03 ms to 4.27 seconds.

Two-Wire Interface With EEPROM Support

The two-wire interface provides communication and

control for EEPROM devices.

One 32-bit timer, plus a 6-bit prescale counter, has a

range of 0.03 µs to 73.3 hours.

Table H. Two-Wire Port with EEPROM Support Pin Assignments

Alternative

Pin Mnemonic Pin Name - Description

Usage

One 40-bit debug timer, plus 6-bit prescale counter, has a

range of 1.0 µs to 12.7 days.

EEPROM / Two-Wire

Interface Clock

General

Purpose I/O

EECLK

EEDATA

SLA[0]

Interrupt Controller

EEPROM / Two-Wire

Interface Data

General

Purpose I/O

The interrupt controller allows up to 62 interrupts to

generate an Interrupt Request (IRQ) or Fast Interrupt

Request (FIQ) signal to the processor core. Thirty-two

hardware priority assignments are provided for assisting

IRQ vectoring, and two levels are provided for FIQ

vectoring. This allows time critical interrupts to be

processed in the shortest time possible. Internal

interrupts may be programmed as active high or active

low level sensitive inputs. GPIO pins programmed as

External Power Switch

Control

General

Purpose I/O

6

DS645A1

EP9303

ARM9 SOC with Display, USB and Touchscreen

interrupts may be programmed as active high level

sensitive, active low level sensitive, rising edge triggered,

falling edge triggered, or combined rising/falling edge

triggered.

Table M. General Purpose Input/Output Pin Assignment

Pin Mnemonic

Pin Name - Description

EGPIO[15:7]

EGPIO[2:0]

Expanded General Purpose Input / Output

Pins with Interrupts

•

Supports 62 interrupts from a variety of sources (such

as UARTs, GPIO, and key matrix)

Expanded General Purpose Input / Output

Pins with Interrupts

FGPIO[7:1]

Routes interrupt sources to either the ARM920T’s

IRQ or FIQ (Fast IRQ) inputs

Reset and Power Management

Four dedicated off-chip interrupt lines operate as

active high level sensitive interrupts

The chip may be reset through the PRSTn pin or through

the open drain common reset pin, RSTOn.

Any of the 19 GPIO lines maybe configured to

generate interrupts

Clocks are managed on a peripheral-by-peripheral basis

and may be turned off to conserve power.

Software supported priority mask for all FIQs and

IRQs

The processor clock is dynamically adjustable from 0 to

200 MHz (184 MHz for industrial conditions).

Table K. Interrupt Controller Pin Assignment

Pin Mnemonic

Pin Name - Description

Table N. Reset and Power Management Pin Assignments

INT[3:0]

External Interrupts 3, 2, 1, 0

Pin Mnemonic

Pin Name - Description

PRSTn

RSTOn

Power On Reset

Dual LED Drivers

User Reset In/Out – Open Drain –

Preserves Real Time Clock value

Two pins are assigned specifically to drive external

LEDs.

Hardware Debug Interface

Table L. Dual LED Pin Assignments

Pin Name -

The JTAG interface allows use of ARM’s Multi-ICE or

other in-circuit emulators.

Pin Mnemonic

Alternative Usage

Description

GRLED

Green LED

Red LED

General Purpose I/O

Table O. Hardware Debug Interface

REDLED

Pin Mnemonic

Pin Name - Description

TCK

JTAG Clock

General Purpose Input/Output (GPIO)

TDI

JTAG Data In

The 12 EGPIO pins may each be configured individually

as an output, an input, or an interrupt input.

TDO

TMS

TRSTn

JTAG Data Out

JTAG Test Mode Select

JTAG Port Reset

There are 21 pins that may alternatively be used as input,

output, or open-drain pins, but do not support interrupts.

These pins are:

12-Channel DMA Controller

• Key Matrix ROW[7:0], COL[7:0]

• Both LED Outputs

• EEPROM Clock and Data

• SLA [0]

The DMA module contains 12 separate DMA channels.

These may be used for peripheral-to-memory or

memory-to-peripheral access. Two of these are

dedicated to memory-to-memory transfers. Each DMA

channel is connected to the 16-bit DMA request bus.

6 pins may alternatively be used as inputs only:

• CTSn, DSRn/DCDn

• 4 Interrupt Lines

The request bus is a collection of requests, Serial Audio

and UARTs. Each DMA channel can be used

independently or dedicated to any request signal. For

each DMA channel, source and destination addressing

can be independently programmed to increment,

decrement, or stay at the same value. All DMA

addresses are physical, not virtual addresses.

2 pins may alternatively be used as outputs only:

• RTSn

• ARSTn

DS645A1

7

EP9303

ARM9 SOC with Display, USB and Touchscreen

Electrical Specifications

Absolute Maximum Ratings

(All grounds = 0 V, all voltages with respect to 0 V)

Parameter

Symbol

Min

Max

Unit

RVDD

CVDD

VDD_PLL

VDD_ADC

-

3.96

2.16

3.96

V

Power Supplies

Total Power Dissipation

(Note 1)

-

2

10

W

mA

V

Input Current per Pin, DC (Except supply pins)

Output current per pin, DC

Digital Input voltage

-

50

(Note 2)

-0.3

-40

RVDD+0.3

+125

Storage temperature

°C

Note: 1. Includes all power generated due to AC and/or DC output loading.

2. The power supply pins are at maximum values listed in “Recommended Operating Conditions”, below.

3. At ambient temperatures above 70° C, total power dissipation must be limited to less than 2.5 Watts.

WARNING: Operation beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

Recommended Operating Conditions

(All grounds = 0 V, all voltages with respect to 0 V)

Parameter

Symbol

Min

Typ

Max

Unit

RVDD

CVDD

VDD_PLL

VDD_ADC

3.0

1.65

3.0

3.3

1.80

3.3

3.6

1.94

3.6

V

Power Supplies

T_A

Operating Ambient Temperature - Commercial

0

+25

+70

°C

Operating Ambient Temperature - Industrial

Processor Clock Speed - Commercial

Processor Clock Speed - Industrial

System Clock Speed - Commercial

System Clock Speed - Industrial

-40

+25

+85

200

184

100

92

°C

FCLK

HCLK

-

MHz

8

DS645A1

EP9303

ARM9 SOC with Display, USB and Touchscreen

DC Characteristics

(T = 0 to 70° C; CVDD = VDD_PLL = 1.8; RVDD = 3.3 V;

A

All grounds = 0 V; all voltages with respect to 0 V unless otherwise noted)

Parameter

Symbol

Min

Max

Unit

V_oh

V_ol

V_ih

V_il

I_ih

High level output voltage

Low level output voltage

High level input voltage

Low level input voltage

High level leakage current

Low level leakage current

Iout = -4 mA

Iout = 4 mA

(Note 4)

0.85 × RVdd

-

V

-

0.15 × RVDD

VDD + 0.3

0.35 × RVDD

10

(Note 5)

0.65 × RVdd

V

−0.3

V

Vin = 3.3 V

Vin = 0

-

µA

I_il

-10

Parameter

Min

Typ

Max

Unit

Power Supply Pins (Outputs Unloaded)

Power Supply Current:

CVDD/VDD_PLL Total

RVDD

-

200

20

-

mA

Low-Power Mode Supply Current

CVDD/VDD_PLL Total

RVDD

-

2.5

1.0

-

mA

Note: 4. For open drain pins, high level output voltage is dependent on the external load.

5. All inputs that do not include internal pull-ups or pull-downs, must be externally driven for proper operation (See Table S on

page 38). If an input is not driven, it should be tied to power or ground, depending on the particular function. If an I/O pin is not

driven and programmed as an input, it should be tied to power or ground through its own resistor.

DS645A1

9

EP9303

ARM9 SOC with Display, USB and Touchscreen

Timings

Timing Diagram Conventions

This data sheet contains one or more timing diagrams. The following key explains the components used in these

diagrams. Any variations are clearly labelled when they occur. Therefore, no additional meaning should be attached

unless specifically stated.

Clock

High to Low

High/Low to High

Bus Change

Bus Valid

Undefined/Invalid

Valid Bus to High Impedance State

Bus/Signal Omission

Figure 1. Timing Diagram Drawing Key

Timing Conditions

Unless specified otherwise, the following conditions are true for all timing measurements.

• T = 0 to 70° C

A

• CVDD = VDD_PLL = 1.8V

• RVDD = 3.3 V

• All grounds = 0 V

• Logic 0 = 0 V, Logic 1 = 3.3 V

• Output loading = 50 pF

• Timing reference levels = 1.5 V

• The Processor Bus Clock (HCLK) is programmable and is set by the user. The frequency is typically between

33 MHz and 100 MHz (92 MHz for industrial conditions).

10

DS645A1

EP9303

ARM9 SOC with Display, USB and Touchscreen

Memory Interface

Figure 2 through Figure 5 define the timings associated with all phases of the SDRAM. The following table contains the

values for the timings of each of the SDRAM modes.

Parameter

Symbol

t_{clk_high}

t_{clk_low}

t_clkrf

Min

Typ

Max

Unit

(t_HCLK)/2

SDCLK high time

SDCLK low time

SDCLK rise/fall time

-

ns

(t_HCLK)/2

-

3

8

4

6

-

TBD

t_d

Signal delay from SDCLK rising edge time

Signal hold from SDCLK rising edge time

DQMn delay from SDCLK rising edge time

DQMn hold from SDCLK rising edge time

DA high-impedance time

-

TBD

t_h

TBD

-

t_DQd

t_DQh

t_DAz

t_DAs

DA valid setup to SDCLK rising edge time

DA valid hold from SDCLK rising edge time

-

t_DAh

-

SDRAM Load Mode Register Cycle

t_{clk_low}

t_{clk_high}

t_clkrf

SDCLK

t_d

t_h

SDCSn

RASn

CASn

SDWEn

DQMn

AD

OP-Code

DA

Figure 2. SDRAM Load Mode Register Cycle Timing Measurement

DS645A1

11

EP9303

ARM9 SOC with Display, USB and Touchscreen

SDRAM Burst Read Cycle

t_{clk_high}

t_{clk_low}

SDCLK

SDCSn

t_clkrf

t_h

RASn

t_d

CASn

SDWEn

t

t_h

DQh

t_DQs

DQd

DQMn

AD

t_DAz

t_DAh

DA

t_DAs

Figure 3. SDRAM Burst Read Cycle Timing Measurement

12

DS645A1

EP9303

ARM9 SOC with Display, USB and Touchscreen

SDRAM Burst Write Cycle

t_{clk_high}

t_{clk_low}

SDCLK

t_clkrf

t_d

t_h

SDCSn

RASn

CASn

SDWEn

DQMn

AD

DA

Figure 4. SDRAM Burst Write Cycle Timing Measurement

DS645A1

13

EP9303

ARM9 SOC with Display, USB and Touchscreen

SDRAM Auto Refresh Cycle

t_{clk_high}

t_{clk_low}

SDCLK

t_clkrf

t_d

t_h

7

b

d

e

SDCSn

RASn

CASn

SDWEn

Note: Chip select shown as bus to illustrate multiple devices being put into auto refresh in one access

Figure 5. SDRAM Auto Refresh Cycle Timing Measurement

14

DS645A1

EP9303

ARM9 SOC with Display, USB and Touchscreen

Static Memory Single Word Read Cycle

Parameter

Symbol

t_ADs

Min

Typ

Max

Unit

t_HCLK

AD setup to RDn assert time

-

ns

t_ADh

t_HCLK

AD hold from RDn deassert time

RDn assert time

-

t_RDpw

t_RDd

t_HCLK× (WST1 + 2)

t_HCLK× 33

-

CSn assert to RDn assert delay time

CSn deassert to RDn deassert delay time

CSn assert to DQMn assert delay time

CSn deassert to DQMn deassert delay time

DA setup to RDn deassert time

DA hold from RDn deassert time

-

0

-

t_RDh

-

t_DQMd

t_DQMh

t_DAs

-

0

-

0

-

10

0

t_DAh

0

See “Timing Conditions” on page 10 for definition of HCLK.

t_ADs

t_ADh

AD

CSn

W Rn

t_RDd1

t_RDd2

h

t_RDpw

RDn

t_DQMd1

t_DQMd2

h

DQMn

t_DAh

t_DAs

DA

W AIT

Figure 6. Static Memory Single Word Read Cycle Timing Measurement

DS645A1

15

EP9303

ARM9 SOC with Display, USB and Touchscreen

Static Memory Single Word Write Cycle

Parameter

Symbol

Min

Typ

Max

Unit

t_ADs

t_ADh

2 × t_HCLK

t_HCLK

AD setup to WRn assert time

AD hold from WRn deassert time

WRn deassert to CSn deassert time

CSn to WRn assert delay time

WRn assert time

-

ns

t_CSh

t_WRd

t_WRpw

t_DQMd

t_DQMh

t_DAs

0

t_HCLK× (WST1 + 1)

CSn to DQMn assert delay time

WRn deassert to DQMn deassert time

DA setup time to WRn assert time

WRn deassert to DA transition time

0

t_HCLK× 2

t_HCLK

t_DAh

t_ADs

t_{AD h}

AD

t_CSh

CSn

t_{W Rd}

t_{W Rpw}

W Rn

RDn

t_{D QMd}

t_DQMh

DQMn

t_{D As}

t_DAh

DA

W AIT

Figure 7. Static Memory Single Word Write Cycle Timing Measurement

16

DS645A1

EP9303

ARM9 SOC with Display, USB and Touchscreen

Static Memory 32-bit Read on 8-bit External Bus

Parameter

Symbol

t_ADs

Min

Typ

Max

Unit

t_HCLK

AD setup to RDn assert time

-

ns

t_AD1

t_HCLK× (WST1 + 1)

RDn assert to Address 1 transition time

Address 2 assert time

t_AD2

t_HCLK× (WST1 + 1)

t_AD3

t_HCLK× (WST1 + 1)

Address 3 assert time

t_AD4

t_HCLK× (WST1 + 2)

AD transition to RDn deassert time

AD hold from RDn deassert time

RDn assert time

t_ADh

t_HCLK

t_RDpwL

t_RDd

t_HCLK× (4 × WST1 + 5)

CSn assert to RDn assert delay time

CSn deassert to RDn deassert delay time

CSn assert to DQMn assert delay time

CSn deassert to DQMn deassert delay time

DA setup to AD transition time

DA to RDn setup time

0

6

0

t_RDh

t_DQMd

t_DQMh

t_DAs1

t_DAs2

t_DAh1

t_DAh2

AD transition to DA transition hold time

RDn deassert to DA transition hold time

t_ADs

t_AD1

t_AD2

t_AD3

t_AD4

t_ADh

AD

CSn

W Rn

RDn

t_RDd

t_RDh

t_RDPwL

t_DQMd

t_DQMh

DQMn

DA

t_DAh₁

t_DAh1

t_DAh2

1

t_DAs1

t_DAs2

W AIT

Figure 8. Static Memory Multiple Word Read 8 Bit Cycle Timing Measurement

DS645A1

17

EP9303

ARM9 SOC with Display, USB and Touchscreen

Static Memory 32-bit Write on 8-bit External Bus

Parameter

Symbol

t_ADs

Min

Typ

t_HCLK× 2

t_HCLK

Max

Unit

AD setup to WRn assert time

WRn deassert to AD transition time

AD hold from WRn deassert time

CSn hold from WRn deassert time

CSn to WRn assert delay time

WRn assert time

-

ns

t_ADd

t_ADh

t_HCLK

t_CSh

t_HCLK

t_WRd

0

t_WRpwL

t_WRpwH

t_DQMd

t_DQMpwL

t_DQMpwH

t_DAs1

t_HCLK× (WST1 + 1)

t_HCLK× 2

WRn deassert time

CSn to DQMn assert delay time

DQMn assert time

0

t_HCLK× (WST1 + 1)

t_HCLK× 2

DQMn deassert time

DA setup 1 to WRn/DQMn

DA setup to WRn/DQMn

0

t_DAs

t_HCLK

t_DAh

WRn/DQMn deassert to DA transition time

t_{A D s}

t_{A D d}

t_{A D h}

A D

t_{C S p w}

C S n

t_{C S h}

t_{W R p wL}

t_{W R d}

t_{W R p wL}

W R n

t_{W R p wH}

R D n

t_{D Q M d}

t_{D Q M pw L}

D Q M n

t_{D Q M pw H}

t_{D Q M pwH}

t_{D A s 1}

t_{D A s}

D A

t_{D A h}

W A I T

Figure 9. Static Memory Multiple Word Write 8 bit Cycle Timing Measurement

18

DS645A1

EP9303

ARM9 SOC with Display, USB and Touchscreen

Static Memory 32-bit Read on 16-bit External Bus

Parameter

Symbol

t_ADs

Min

Typ

t_HCLK

Max

Unit

AD setup to RDn assert time

RDn assert to AD transition time

AD transition to RDn deassert time

AD hold from RDn deassert time

RDn assert time

-

ns

t_ADd1

t_ADd2

t_ADh

t_HCLK× (WST1 + 1)

t_HCLK× (WST1 + 2)

t_HCLK

t_RDpwL

t_RDd

t_HCLK× (2 × WST1 + 3)

CSn to RDn assert delay time

CSn to RDn deassert delay time

CSn to DQMn assert delay time

CSn to DQMn deassert delay time

DA to ADsetup time

0

t_RDh

0

t_DQMd

t_DQMh

t_DAs1

t_DAs2

t_DAh1

t_DAh2

0

6

t_HCLK

DA to RDn setup time

AD transition to DA transition hold time

RDn deassert to DA transition hold time

2

0

t_ADh

t_ADs

t_ADd1

t_ADd2

AD

CSn

W Rn

RDn

t_{RD d}

t_{RD h}

t_{R DpwL}

t_DQMd

t_{D QMh}

DQMn

t_{D As1}

t_DAh1

t

t_DAh2

t_DAs2

D As2

DA

W AIT

Figure 10. Static Memory Multiple Word Read 16 Bit Cycle Timing Measurement

DS645A1

19

EP9303

ARM9 SOC with Display, USB and Touchscreen

Static Memory 32-bit Write on 16-bit External Bus

Parameter

Symbol

t_ADs

Min

Typ

2 × t_HCLK

t_HCLK

Max

Unit

AD setup to WRn assert time

WRn deassert to AD transition time

AD hold from WRn deassert time

CSn hold from WRn deassert time

CSn to WRn assert delay time

WRn assert time

-

ns

t_ADd

t_ADh

2 × t_HCLK

t_HCLK

t_CSh

t_WRd

0

t_WRpwL

t_WRpwH

t_DQMd

t_DQMpwL

t_DQMpwH

t_DAs1

t_HCLK× (WST1 + 1)

t_HCLK× 2

WRn deassert time

CSn to DQMn assert delay time

DQMn assert time

0

t_HCLK× (WST1 + 1)

t_HCLK× 2

t_HCLK

DQMn deassert time

DA setup to WRn/DQMn assert

WRn/DQMn deassert to DA transition time

t_DAs2

t_DAh1

t_HCLK

t_DAh2

t_HCLK

t_ADs

t_ADd

t_ADh

AD

CSn

t_CSh

t_{W Rd}

t_{W RpwL}

W Rn

t_{W RpwH}

RDn

t

t_DQMd

t_DQMpwL

DQpwL

DQMn

t

t_D_DQ_Q_M_p_p_w_w_H_H

t_DAs1

t_DAs2

DA

t_DAh1

t_DAh2

W AIT

Figure 11. Static Memory Multiple Word Write 16 bit Cycle Timing Measurement

20

DS645A1

EP9303

ARM9 SOC with Display, USB and Touchscreen

Static Memory Burst Read Cycle

Parameter

Symbol

t_ADd1

t_ADd2

t_ADh

Min

Typ

t_HCLK× (WST1 + 1)

t_HCLK× (WST2 + 1)

t_HCLK× 2

Max Unit

CSn assert to Address 1 transition time

Address 2 assert time

-

0

-

ns

AD hold from CSn deassert time

CSn assert time

t_CSpw

t_RDd

t_HCLK× ((WST1 + 1) + 4(WST2 + 1))

CSn to RDn assert delay time

RDn assert time

0

t_RDpw

t_DQMd

t_DQMpw

t_DAs1

t_HCLK× ((WST1 + 1) + 4(WST2 + 1))

CSn to DQMn assert delay time

DQMn assert time

4

t_HCLK× ((WST1 + 1) + 4(WST2 + 1))

DA to AD setup time

6

t_DAs2

2 + t_HCLK

DA to CSn setup time

t_DAh1

t_DAh2

AD transition to DA transition hold time

CSn deassert to DA transition hold time

2

0

Note: These characteristics are valid when the Page Mode Enable (Burst Mode) bit is set. See the User's Guide for details.

t_ADd1

t_ADd2

t_ADh

AD

CSn

t_CSpw

WRn

RDn

t_RDd

t_RDpw

t_DQMd

t_DQMpw

DQMn

t_DAh1

t_DAh2

DA

t_DAs1

t_DAs2

WAIT

Figure 12. Static Memory Burst Read Cycle Timing Measurement

DS645A1

21

EP9303

ARM9 SOC with Display, USB and Touchscreen

Static Memory Single Read Wait Cycle

Parameter

Symbol

t_RDd

Min

Typ

Max

Unit

CSn to RDn deassert delay time

CSn to DQMn deassert delay time

CSn to DA transition delay time

CSn assert to WAIT time

-

0

-

ns

t_DQMd

t_DAh

-

12 - t_HCLK

t_HCLK× (WST1+1)

-

t_WAITd

t_WAITpw

t_CSnd

-

t_HCLK× 2

t_HCLK× 3

t_HCLK× 510

t_HCLK× 4

WAIT assert time

-

WAIT to CSn deassert delay time

AD

CSn

WRn

t_RDd

RDn

t_DQMd

DQMn

t_DAh

DA

t_WAITd

t_CSnd

t_WAITpw

WAIT

Figure 13. Static Memory Single Read Wait Cycle Timing Measurement

22

DS645A1

EP9303

ARM9 SOC with Display, USB and Touchscreen

Static Memory Single Write Wait Cycle

Parameter

Symbol

t_WRd

Min

Typ

Max

Unit

t_HCLK× 2

t_HCLK× 3

WAIT to WRn deassert delay time

CSn assert to WAIT time

-

ns

t_WAITd

t_WAITpw

t_CSnd

t_HCLK× (WST2+1)

-

t_HCLK× 2

t_HCLK× 3

t_HCLK× 510

t_HCLK× 4

WAIT assert time

-

WAIT to CSn deassert delay time

AD

CSn

t_WRd

WRn

RDn

DQMn

DA

t_WAITd

t_CSnd

t_WAITpw

WAIT

Figure 14. Static Memory Single Write Wait Cycle Timing Measurement

DS645A1

23

EP9303

ARM9 SOC with Display, USB and Touchscreen

Static Memory Turnaround Cycle

Parameter

Symbol

Min

Typ

Max

Unit

t_BTcyc

t_HCLK× (IDCY+1)

CSnX deassert to CSnY assert time

-

ns

Note: X and Y represent any two chip select numbers.

t_BTcyc

AD

X

CSn0

Y

CSn1

WRn

RDn

DQMn

DA

WAIT

Figure 15. Static Memory Turnaround Cycle Timing Measurement

24

DS645A1

EP9303

ARM9 SOC with Display, USB and Touchscreen

Keyscan Interface

Parameter

Symbol

t_ROWa

Min

Typ

t_KEY× (PRSCL + 1)

TBD

Max

Unit

ROWn assert time

-

ns

t_ROWn

Delay to ROWn+1 assert time

t _{R O}

t _R

O

W

a

W n

R O W

n

R O W n + 1

Figure 16. Keyscan Timing Measurement

DS645A1

25

EP9303

ARM9 SOC with Display, USB and Touchscreen

Audio Interface

The following table contains the values for the timings of each of the SPI modes.

Parameter

Symbol

t_{clk_per}

t_{clk_high}

t_{clk_low}

t_clkrf

Min

Typ

Max

Unit

SCLK cycle time

SCLK high time

SCLK low time

-

tspix_clk

-

ns

(tspix_clk)/2

SCLK rise/fall time

4.5 / 1.5

t_DMd

Data from master valid delay time

Data from master setup time

Data from master hold time

Data from slave valid delay time

Data from slave setup time

Data from slave hold time

2

t_DMs

20

40

2

t_DMh

t_DSd

t_DSs

20

40

t_DSh

Note:

tspix_clk is programmable by the user.

26

DS645A1

EP9303

ARM9 SOC with Display, USB and Touchscreen

’

Texas Instruments Synchronous Serial Format

t_{clk_per}

t_{clk_high}

t_clkrf

SCLK

t_{clk_low}

SFRM

SSPTXD/

MSB

LSB

SSPRXD

4 to 16 bits

Figure 17. SPI Single Transfer Timing Measurement

Microwire

t_{clk_high}

t_{clk_per}

t_clkrf

SCLK

SFRM

t_{clk_low}

LSB

MSB

SSPTXD

SSPRXD

8-bit control

0

MSB

LSB

4 to 16 bits output data

Figure 18. Microwire Frame Format, Single Transfer

DS645A1

27

EP9303

ARM9 SOC with Display, USB and Touchscreen

Motorola SPI

t_{clk_per}

t_{clk_high}

t_clkrf

SCLK

(SPO=0)

t_{clk_low}

SCLK

(SPO=1)

t_DMs

t_DMh

SSPTXD

from master

MSB

LSB

t_DMd

t_DSdt_DSs

t_DSd

SSPRXD

from slave

MSB

LSB

SFRM

Figure 19. SPI Format with SPH=1 Timing Measurement

28

DS645A1

EP9303

ARM9 SOC with Display, USB and Touchscreen

2

Inter-IC Sound - I S

Parameter

Symbol

t_{clk_per}

t_{clk_high}

t_{clk_low}

t_clkrf

Min

Typ

Max

Unit

SCLK cycle time

SCLK high time

SCLK low time

-

326

163

4

-

ns

SCLK rise/fall time

t_LRs

SCLK to LRCLK assert delay time

LRCLK from SCLK assert hold time

SDI to SCLK deassert setup time

SDI from SCLK deassert hold time

SCLK to SDO assert delay time

SDO from SCLK assert hold time

1.5

20

40

2

t_LRh

t_SDIs

t_SDIh

t_SDOd

t_SDOh

2

t_{clk_per}

t_clkrf

t_{clk_high}

t_{clk_low}

SCLK

t_LRh

t_LRs

LRCLK

t_SDOs

t_SDOh

SDO/SDI

t_SDIs

t_SDIh

Figure 20. Inter-IC Sound (I²S) Timing Measurement

DS645A1

29

EP9303

ARM9 SOC with Display, USB and Touchscreen

AC’97

Parameter

Symbol

t_{clk_per}

t_{clk_high}

t_{clk_low}

t_clkr

Min

Typ

Max

Unit

ABITCLK input cycle time

-

36

2

81.4

-

45

6

ns

ABITCLK input high time

-

ABITCLK input low time

ABITCLK input rise time

-

t_clkf

ABITCLK input fall time

2

-

6

t_s

ASDI setup to ABITCLK falling

ASDI hold after ABITCLK falling

ASDI input rise/fall time

10

2

23

53

-

t_h

-

t_rfin

6

ABITCLK rising to ASDO/ASYNC valid, C_L= 55 pF

ASYNC/ASDO rise time, C_L= 55 pF

ASYNC/ASDO fall time, C_L= 55 pF

t_co

2

-

15

6

t_rout

2

-

t_fout

2

-

6

t_{clk_per}

t_{clk_high}

t_{clk_low}

ABITCLK

t_clkrf

r

f

t_h

t_s

t_rfin

ASDI

ASDO

t

/t

foutt_rff_oo_uu_tt

t_co

ASYNC

t

t_rout

t_rf_f_o_o_u_u_t_t

rfout

Figure 21. AC ‘97 Configuration Timing Measurement

30

DS645A1

EP9303

ARM9 SOC with Display, USB and Touchscreen

LCD Interface

Parameter

Symbol

t_clkr

Min

Typ

Max

Unit

SPCLK rising time

SPCLK falling time

-

5

-

ns

t_clkf

5

1

t_CD

SPCLK rising edge to control signal transition time

SPCLK rising edge to data transition time

SPCLK falling edge to control signal transition time

SPCLK falling edge to data transition time

Data valid time

t_DD

0

t_CDi

(t_SPCLK)/2

t_SPCLK

t_DDi

t_Dv

t_clkr

t_clkf

SPCLK

HSYNC/

V_CSYNC/

BLANK/

t_CD

BRIGHT

t_DD

P [17:0]

t_Dv

t_clkr

t_clkf

SPLCK

t_CDi

HSYNC/

V_CSYNC/

BLANK/

BRIGHT

t_DDi

P [17:0]

t_Dv

Figure 22. LCD Timing Measurement

DS645A1

31

EP9303

ARM9 SOC with Display, USB and Touchscreen

JTAG

Parameter

Symbol

t_{clk_per}

t_{clk_high}

t_{clk_low}

t_JPs

Min

Max

Units

TCK clock period

100

50

20

45

-

ns

TCK clock high time

TCK clock low time

-

TMS/TDI to clock rising setup time

Clock rising to TMS/TDI hold time

JTAG port clock to output

-

t_JPh

-

t_JPco

25

t_JPzx

JTAG port high impedance to valid output

JTAG port valid output to high impedance

-

t_JPxz

-

TMS

TDI

t_{clk_per}

t_JPs

t_JPh

t_{clk_high}

t_{clk_low}

TCK

TDO

t_JPzx

t_JPco

t_JPxz

Figure 23. JTAG Timing Measurement

32

DS645A1

EP9303

ARM9 SOC with Display, USB and Touchscreen

Figure 24. 272 Pin TFBGA Pinout

1

2

3

4

5

6

7

8

9

10

11

12

TDI

13

14

15

16

17

Port E

GPIO[6]

U ^{GGPIO[6] GGPIO[5] GGPIO[4]}

P[0]

P[1]

P[2]

P[8]

DA[6]

AD[14]

DA[7]

P[3]

AD[12] AD[10] AD[8]

DA[5] DA[3] DA[1]

AD[13] AD[11] AD[9]

AD[15] DA[4] DA[2]

DA[0]

TCK

TDO

TMS

TREQA

SCLK1

SFRM1

SSPRX1

ASDO

GRLED

INT[2]

SSPTX1

INT[3]

RDLED

INT[0]

SLA[0]

RXD[2]

INT[1]

CTSn

RXD[0]

RXD[1]

U

T

Port E

GPIO[4]

Port E

GPIO[7]

T ^{GGPIO[7] GGPIO[2]}

P[5]

P[6]

P[7]

TACK

EECLK

Port E

GPIO[3]

R

P[10]

P[11]

GGPIO[3]

SPCLK

DSRn

DTRn

RTSn

R

P

Port E

GPIO[5]

P

N

M

L

BOOT[1] EEDAT

BOOT[0] ASYNC

USBp[1]

ABITCLK

DA[8]

AD[1]

P[12]

BLANK

AD[0]

HSYNC

P[13]

P[9]

P[14]

V_CSYNC P[4]

vddr vddr

gndr vddc

vddr

vddc

vddr

gndr

USBm[1]

USBm[0]

vddr

USBp[0]

TXD[0]

ROW[4]

ROW[7]

COL[0]

CSn[0]

TXD[1]

TXD[2]

ROW[0] N

M

P[15]

P[16]

vddr

gndr

vddc

gndr

vddc

gndr

ROW[3]

ROW[2]

ROW[1]

L

DA[9]

BRIGHT

AD[3]

P[17]

ROW[5] PLL_GND XTALI

K

J

AD[2]

DA[10]

AD[5]

DA[11]

AD[4]

gndc

vddr

ROW[6]

COL[1]

PRSTn

COL[7]

Ym

PLL_VDD XTALO

K

J

DA[13]

AD[6]

DA[12]

AD[7]

vddr

COL[2]

COL[5]

RSTOn

sYm

COL[3]

COL[4]

COL[6]

sYp

H

G

F

H

G

F

DA[14]

DA[17]

DA[19]

DA[15]

DQMn[0]

DA[23]

vddr

DA[16]

AD[21]

DA[20]

DA[18]

DA[21]

vddr

EGPIO[11] EGPIO[10]

DA[24]

CSn[7]

CSn[1]

AD[25]

gndr

vddc

vddr

RDn

WRn

vddc

vddr

gndr

ARSTn

EGPIO[9]

TRSTn

ASDI

E

D

C

E

D

C

B

A

AD[22] SDCSn[3] AD[24]

CSn[3] CSn[2] vddr

CSn[6] DA[27] DD[2]

DA[30] AD[18] DD[3]

MCDIR EGPIO[12] USBm[2]

EGPIO[8]

sXp

sXm

DQMn[1] DQMn[2] SDWEn

DQMn[3] CASn DA[22]

DA[25]

DA[26]

FGPIO[7] FGPIO[4] EGPIO[13] USBp[2]

FGPIO[5] FGPIO[3] EGPIO[14] IOWRn

RTCXTALO ADC_VDD

ADC_GND RTCXTALI

Yp

WAITn

Xm

Port E

B

A

RASn SDCSn[0] AD[23] SDCLKEN

DA[31]

AD[19]

5

DA[29] DA[28] DD[4] AD[16] MCWAITn FGPIO[2] EGPIO[15] MCRDn MCRESETn

EGPIO[2]

GPIO[2]

Xp

SDCSn[1] SDCSn[2] SDCLK

AD[20]

DD[7] DD[6] DD[5] AD[17]

FGPIO[6] FGPIO[1] IORDn

MCWRn

WP

EGPIO[0] EGPIO[1] EGPIO[7]

1

2

3

4

6

7

8

9

10

11

12

13

14

15

16

17

DS645A1

33

EP9303

ARM9 SOC with Display, USB and Touchscreen

272 Pin TFBGA Package Outline

272 TFBGA Diagram

Figure 25. 272 Pin TFBGA Diagram

D

E1

e

ddd

Øb

ddd

34

DS645A1

EP9303

ARM9 SOC with Display, USB and Touchscreen

Table R. 272 Pin Diagram Dimensions

dimension in mm

NOM

dimension in inches

MIN NOM MAX

Symbol

MIN

MAX

A

A1

A2

b

1.40

0.28

0.70

0.40

c

0.26

D

14.00

12.80

14.00

12.80

0.80

D3

E

E3

e

ddd

0.10

Note: 1. Controlling Dimension: Millimeter.

2. Primary Datum C and seating plane are defined by the spherical crowns of the solder balls.

3. Dimension b is measured at the maximum solder ball diameter, parallel to Primary Datum C.

4. There shall be a minimum clearance of 0.25 mm between the edge of the solder ball and the body edge.

5. Reference Document: JEDEC MO-151, BAL-2

272 Pin TFBGA Pinout (Bottom View)

The following table shows the 272 pin TFBGA pinout. (For better understanding, compare the coordinates on the x and

y axis on Figure 24, "272 Pin TFBGA Pinout", on page 33 with Figure 25, "272 Pin TFBGA Diagram", on page 34.

• VDD_core is vddc.

• VDD_ring is vddr.

• GND_core is gndc.

• GND_ring is gndr.

DS645A1

35

EP9303

ARM9 SOC with Display, USB and Touchscreen

Pin List

The following Thin-profile Fine-pitch Ball Grid Array (TFBGA) ball assignment table is sorted in order of ball.

Ball

Signal

Ball

Signal

Ball

Signal

Ball

Signal

A1

A2

SDCSn[1]

SDCSn[2]

SDCLK

AD[20]

E1

E2

DA[20]

AD[22]

SDCSn[3]

AD[24]

CSn[7]

CSn[3]

CSn[2]

vddr

J10

J12

J13

J14

J15

J16

J17

K1

gndc

vddc

P1

P2

P[11]

SPCLK

P[7]

A3

E3

vddr

P3

A4

E4

COL[0]

COL[1]

COL[2]

COL[3]

AD[2]

DA[10]

AD[3]

DA[11]

vddr

P4

P[8]

A5

AD[19]

E5

P5

P[3]

A6

DD[7]

E6

P6

AD[15]

DA[4]

A7

DD[6]

E7

P7

A8

DD[5]

E8

P8

DA[2]

A9

AD[17]

E9

vddr

K2

P9

Port E GPIO[5]

DTRn

A10

A11

A12

A13

A14

A15

A16

A17

B1

FGPIO[6]

FGPIO[1]

IORDn

E10

E11

E12

E13

E14

E15

E16

E17

F1

vddr

K3

P10

P11

P12

P13

P14

P15

P16

P17

R1

MCDIR

EGPIO[12]

USBm[2]

TRSTn

EGPIO[8]

sXp

K4

BOOT[1]

EEDAT

SSPRX1

USBp[1]

ABITCLK

RXD[2]

RXD[1]

P[10]

K5

MCWRn

WP

K6

gndr

K8

gndc

EGPIO[0]

EGPIO[1]

EGPIO[7]

RASn

K9

gndc

K10

K12

K13

K14

K15

K16

K17

L1

gndc

sXm

vddc

AD[21]

DA[19]

DA[21]

DA[23]

DA[24]

gndr

vddr

B2

SDCSn[0]

AD[23]

F2

ROW[7]

ROW[6]

PLL_VDD

XTALO

DA[9]

AD[0]

BRIGHT

P[17]

R2

GGPIO[3]

P[6]

B3

F3

R3

B4

SDCLKEN

DA[31]

F4

R4

P[2]

B5

F5

R5

DA[7]

B6

DA[29]

F6

R6

AD[13]

AD[11]

AD[9]

B7

DA[28]

F7

gndr

L2

R7

B8

DD[4]

F8

gndr

L3

R8

B9

AD[16]

F9

vddc

L4

R9

Port E GPIO[3]

DSRn

B10

B11

B12

B13

B14

B15

B16

B17

C1

MCWAITn

FGPIO[2]

EGPIO[15]

MCRDn

MCRESETn

Port E GPIO[2]

EGPIO[2]

Xp

F10

F11

F12

F13

F14

F15

F16

F17

G1

G2

G3

G4

G5

G6

G12

G13

vddc

L5

P[16]

R10

R11

R12

R13

R14

R15

R16

R17

T1

gndr

L6

gndr

TMS

gndr

L12

L13

L14

L15

L16

L17

M1

M2

M3

M4

M5

M6

M7

M8

gndr

EECLK

SFRM1

INT[2]

ARSTn

EGPIO[9]

Ym

vddr

ROW[4]

ROW[5]

PLL_GND

XTALI

AD[1]

BLANK

P[13]

RTSn

sYm

SLA[0]

RXD[0]

GGPIO[7]

GGPIO[2]

P[5]

sYp

DQMn[3]

CASn

DA[16]

DA[17]

DA[18]

DQMn[0]

vddr

C2

T2

C3

DA[22]

T3

C4

DA[26]

P[14]

T4

P[1]

C5

AD[25]

P[15]

T5

AD[14]

DA[5]

C6

DA[30]

gndr

T6

C7

AD[18]

gndr

T7

DA[3]

C8

DD[3]

EGPIO[11]

vddc

T8

DA[1]

36

DS645A1

EP9303

ARM9 SOC with Display, USB and Touchscreen

Ball

Signal

Ball

Signal

Ball

Signal

Ball

Signal

C9

C10

C11

C12

C13

C14

C15

C16

C17

D1

WRn

FGPIO[5]

FGPIO[3]

EGPIO[14]

IOWRn

WAITn

G14

G15

G16

G17

H1

EGPIO[10]

COL[7]

RSTOn

COL[6]

AD[6]

DA[14]

AD[7]

DA[15]

vddr

M9

M10

M11

M12

M13

M14

M15

M16

M17

N1

vddc

gndr

T9

T10

T11

T12

T13

T14

T15

T16

T17

U1

Port E GPIO[4]

Port E GPIO[7]

TDO

gndr

TACK

USBm[0]

TXD[0]

ROW[3]

ROW[2]

ROW[1]

DA[8]

SCLK1

GRLED

INT[3]

H2

ADC_GND

RTCXTALI

Xm

H3

H4

INT[0]

H5

CTSn

DQMn[1]

DQMn[2]

SDWEn

DA[25]

H6

vddc

GGPIO[6]

GGPIO[5]

GGPIO[4]

P[0]

D2

H8

gndc

N2

P[12]

U2

D3

H9

gndc

N3

HSYNC

P[9]

U3

D4

H10

H12

H13

H14

H15

H16

H17

J1

gndc

N4

U4

D5

CSn[1]

gndr

N5

V_CSYNC

P[4]

U5

DA[6]

D6

CSn[6]

vddr

N6

U6

AD[12]

AD[10]

AD[8]

D7

DA[27]

CSn[0]

PRSTn

COL[5]

COL[4]

DA[13]

AD[5]

DA[12]

AD[4]

vddr

N7

vddr

U7

D8

DD[2]

N8

vddr

U8

D9

RDn

N9

vddr

U9

DA[0]

D10

D11

D12

D13

D14

D15

D16

D17

FGPIO[7]

FGPIO[4]

EGPIO[13]

USBp[2]

ASDI

N10

N11

N12

N13

N14

N15

N16

N17

vddr

U10

U11

U12

U13

U14

U15

U16

U17

Port E GPIO[6]

TCK

BOOT[0]

ASYNC

USBm[1]

USBp[0]

TXD[1]

TXD[2]

ROW[0]

J2

TDI

J3

TREQA

ASDO

J4

RTCXTALO

ADC_VDD

Yp

J5

SSPTX1

RDLED

INT1

J6

vddc

J8

gndc

DS645A1

37

EP9303

ARM9 SOC with Display, USB and Touchscreen

The following section focuses on the EP9303 pin signals

•

P - Power pad

G - Ground pad

I - Pin is an input only

from two viewpoints

- the pin usage and pad

characteristics, and the pin multiplexing usage. The first

table (Table S) is a summary of all the EP9303 pin

signals. The second table (Table T) illustrates the pin

signal multiplexing and configuration options.

4mA - Pin is a 4mA output driver

8mA - Pin is an 8mA output driver

12mA - Pin is an 12mA output driver

Table S is a summary of the EP9303 pin signals, which

illustrates the pad type and pad pull type (if any). The

symbols used in the table are defined as follows. (Note: A

blank box means Not Applicable (NA) or, for Pull Type,

No Pull (NP).)

See the text description for additional information about

bi-directional pins.

Under the Pull Type Column:

•

PU - Resistor is a pull up to the RVDD supply

PD - Resistor is a pull down to the RGND supply

Under the Pad Type column:

•

A - Analog pad

.

Table S. Pin Descriptions (Continued)

Table S. Pin Descriptions

Pad

Type

Pull

Type

Pin Name

BLANK

Block

Description

Pad

Type

Pull

Type

Pin Name

TCK

Block

Description

Raster

ADC

8ma

4ma

A

PU Composite blanking signal out

JTAG

I

PD JTAG clock in

PD JTAG data in

BRIGHT

Xp, Xm

Yp, Ym

sXp, sXm

sYp, sYm

VDD_ADC

GND_ADC

COL[7:0]

ROW[7:0]

USBp[2:0]

USBm[2:0]

TXD0

-

PWM brightness control out

Touchscreen ADC X axis

TDI

TDO

JTAG

4ma

I

-

JTAG data out

ADC

A

Touchscreen ADC Y axis

TMS

JTAG

PD JTAG test mode select

PD JTAG reset

ADC

A

Touchscreen ADC X axis feedback

Touchscreen ADC Y axis feedback

Touchscreen ADC power, 3.3V

Touchscreen ADC ground

TRSTn

JTAG

I

ADC

A

BOOT[1:0]

XTALI

System

PLL

I

PD Boot mode select in

ADC

P

A

-

Main oscillator input

ADC

G

XTALO

VDD_PLL

GND_PLL

RTCXTALI

RTCXTALO

WRn

PLL

A

Main oscillator output

Main oscillator power, 1.8V

Main oscillator ground

RTC oscillator input

Key

8ma

A

PU Key matrix column inputs

PU Key matrix row outputs

PLL

P

Key

PLL

G

USB

-

USB positive signals

USB negative signals

Transmit out

RTC

A

USB

A

RTC

A

RTC oscillator output

SRAM Write strobe out

SRAM Read/OE strobe out

UART1

UART2

UART3

LED

4ma

I

EBUS

SDRAM

Raster

4ma

I

RXD0

PU Receive in

RDn

CTSn

I

PU Clear to send/transmit enable

PU Data set ready/Data Carrier Detect

WAITn

PU SRAM Wait in

DSRn

I

AD[25:0]

DA[31:0]

CSn[3:0]

CSn[7:6]

DQMn[3:0]

SDCLK

SDCLKEN

SDCSn[3:0]

RASn

8ma

4ma

8ma

4ma

8ma

4ma

12ma

8ma

-

Shared Address bus out

DTRn

4ma

I

-

Data Terminal Ready output

Ready to send

PU Shared Data bus in/out

PU Chip select out

RTSn

TXD1

Transmit/IrDA output

RXD1

PU Receive/IrDA input

Transmit

PU Receive

-

Shared data mask out

SDRAM clock out

TXD2

4ma

I

-

RXD2

SDRAM clock enable out

SDRAM chip selects out

SDRAM RAS out

GRLED

RDLED

EECLK

EEDAT

ABITCLK

ASYNC

ASDI

12ma

4ma

8ma

I

-

Green LED

Red LED

LED

EEPROM

AC97

PU EEPROM/Two-wire Interface clock

PU EEPROM/Two-wire Interface data

PD AC97 bit clock

CASn

SDRAM CAS out

SDWEn

P[17:0]

SDRAM write enable out

PU Pixel data bus out

PD AC97 frame sync

SPCLK

HSYNC

PU Pixel clock in/out

PD AC97 Primary input

PU AC97 output

PU Horizontal synchronization/ line pulse out

ASDO

8ma

Vertical or composite synchronization/frame

V_CSYNC

Raster

8ma

PU

ARSTn

-

AC97 reset

pulse out

38

DS645A1

EP9303

ARM9 SOC with Display, USB and Touchscreen

Table S. Pin Descriptions (Continued)

Pad

Type

Pull

Type

Pin Name

SCLK1

Block

Description

SPI1

8ma

I

PD SPI bit clock

PD SPI Frame Clock

PD SPI input

SFRM1

SSPRX1

SSPTX1

INT[3:0]

PRSTn

RSTOn

SLA[0]

SPI1

8ma

I

-

SPI output

INT

PD External interrupts

PU Power on reset

Syscon

EEPROM

GPIO

I

4ma

I/O

P

-

User Reset in out - open drain

Flash programming voltage control

EGPIO[15:7]

EGPIO[2:0]

vddc

PU Enhanced GPIO

GPIO

Power

Ground

-

Digital power, 1.8V

Digital power, 3.3V

Digital ground

vddr

P

gndc

G

gndr

G

Digital ground

DS645A1

39

EP9303

ARM9 SOC with Display, USB and Touchscreen

Table T illustrates the pin signal multiplexing and configuration options.

Table T. Pin Multiplex Usage Information

Physical

Pin Name

Description

Multiplex signal name

COL[7:0]

ROW[7:0]

EGPIO[0]

EGPIO[1]

EGPIO[2]

EGPIO[7]

EGPIO[8]

EGPIO[9]

EGPIO[10]

EGPIO[11]

EGPIO[12]

EGPIO[13]

ABITCLK

ASYNC

GPIO

GPIO Port D[7:0]

GPIO Port C[7:0]

RI

GPIO

Ring Indicator Input

1Hz clock monitor

DMA request

CLK1HZ

DMARQ

DREQ0

DACK0

DEOT0

DREQ1

DACK1

DEOT1

SDI2

DMA Request 0

DMA Acknowledge 0

DMA EOT 0

DMA Request 1

DMA Acknowledge 1

DMA EOT 1

I2S Receive Data 2

I2S Serial clock

I2S Frame Clock

I2S Transmit Data 0

I2S Receive Data 0

I2S Master clock

I2S Serial clock

I2S Frame Clock

I2S Transmit Data 0

I2S Receive Data 0

SCLK

LRCK

ASDO

SDO0

ASDI

SDI0

ARSTn

MCLK

SCLK1

SCLK

SFRM1

LRCK

SSPTX1

SSPRX1

SDO0

SDI0

40

DS645A1

EP9303

ARM9 SOC with Display, USB and Touchscreen

Acronyms and Abbreviations

Term

Definition

The following tables list abbreviations and acronyms

used in this data sheet.

OHCI

Open Host Controller Interface

Ethernet PHYsical layer interface

Programmed I/O

PHY

PIO

Term

Definition

ADC

Analog-to-Digital Converter

RISC

SDMI

Reduced Instruction Set Computer

Secure Digital Music Initiative

ALT

Alternative

AMBA

ATAPI

Advanced Micro-controller Bus Architecture

ATA Packet Interface

SDRAM Synchronous Dynamic RAM

SPI

Serial Peripheral Interface

CODEC COder/DECoder

SRAM

Static Random Access Memory

CRC

DAC

DMA

Cyclic Redundancy Check

Station - Any device that contains an IEEE 802.11

conforming Medium Access Control (MAC) and physical

layer (PHY) interface to the wireless medium

STA

Digital-to-Analog Converter

Direct-Memory Access

TFT

TLB

USB

Thin Film Transistor

EEPROM Electronically Erasable Programmable Read Only Memory

Translation Lookaside Buffer

Universal Serial Bus

EMAC

EBUS

FIFO

FIQ

Ethernet Media Access Controller

External Bus

Units of Measurement

First In/First Out

Fast Interrupt Request

Flash memory

Symbol

Unit of Measure

FLASH

GPIO

HDLC

I/F

degree Celsius

°C

General Purpose I/O

High-level Data Link Control

Interface

Hz

Hertz = cycle per second

Kilobits per second

Kilobyte

Kbps

Kbyte

KHz

Mbps

MHz

µA

I²S

KiloHertz = 1000 Hz

Megabits per second

MegaHertz = 1,000 KiloHertz

Inter-IC Sound

IC

Integrated Circuit

ICE

In-Circuit Emulator

microAmpere = 10^-6Ampere

IDE

Integrated Drive Electronics

Institute of Electronics and Electrical Engineers

Infrared Data Association

microsecond = 1,000 nanoseconds = 10^-6seconds

milliAmpere = 10^-3Ampere

µs

IEEE

IrDA

IRQ

ISO

JTAG

LFSR

MII

mA

ms

mW

ns

millisecond = 1,000 microseconds = 10^-3seconds

milliWatt = 10^-3Watts

Standard Interrupt Request

International Standards Organization

Joint Test Action Group

nanosecond = 10^-9seconds

picoFarad = 10^-12Farads

pF

V

Linear Feedback Shift Register

Media Independent Interface

Memory Management Unit

Volt

W

Watt

MMU

DS645A1

41

EP9303

ARM9 SOC with Display, USB and Touchscreen

ORDERING INFORMATION

The order numbers for the device are:

EP9303-CB

EP9303-CBZ

EP9303-IB

0°C to +70°C

-40°C to +85°C

272 pin TFBGA

Lead Free

EP9303-IBZ

EP9303 — CBZ

Lead Material:

Z = Lead Free

Part Number

Package Type:

B = 272 pin TFBGA

Product Line:

Embedded Processor

Temperature Range:

C = Commercial

E = Extended Operating Version

I = Industrial Operating Version

Note: Go to the Cirrus Logic Internet site at http://www.cirrus.com to find contact information for your local sales representative.

42

DS645A1


型号：	EP9303-CBZ
厂家：	CIRRUS LOGIC
描述：	Microprocessor
文件：	总42页 (文件大小：654K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

EP9303-CBZ [CIRRUS]

相关型号：

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EP9307

EP9307-CBZ

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EP9307-CRZ

EP9307-ERZ

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EP9307-IBZ