WM8773SEFT/V [CIRRUS]
ADC, Delta-Sigma, 24-Bit, 1 Func, 8 Channel, Serial Access, CMOS, PQFP64, TQFP-64;
| 型号： | WM8773SEFT/V |
| 厂家： | 
CIRRUS LOGIC |
| 描述： | ADC, Delta-Sigma, 24-Bit, 1 Func, 8 Channel, Serial Access, CMOS, PQFP64, TQFP-64 转换器 |
| 文件： | 总30页 (文件大小：322K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WM8773
w
24-bit, 96kHz ADC with 8 Channel I/P Multiplexer
DESCRIPTION
FEATURES
•
Audio Performance
102dB SNR (‘A’ weighted @ 48kHz) ADC
The WM8773 is a high performance, stereo audio ADC with
an 8 channel input selector. The WM8773 is ideal for
digitising multiple analogue sources for surround sound
processing applications for home hi-fi, automotive and other
audio visual equipment.
−
•
•
•
•
ADC Sampling Frequency: 8kHz – 96kHz
3-Wire SPI MPU Serial Control Interface
Master or Slave Clocking Mode
A stereo 24-bit multi-bit sigma delta ADC is used with an
eight stereo channel input selector. Each channel has
analogue domain mute and programmable gain control.
Digital audio output word lengths from 16-32 bits and
sampling rates from 8kHz to 96kHz are supported.
Programmable Audio Data Interface Modes
−
−
I2S, Left, Right Justified or DSP
16/20/24/32 bit Word Lengths
•
•
Analogue Record Monitor Outputs
Eight stereo ADC inputs with analogue gain adjust from
+19dB to –12dB in 1dB steps
The audio data interface supports I2S, left justified, right
justified and DSP digital audio formats.
•
•
2.7V to 5.5V Analogue, 2.7V to 3.6V Digital supply
Operation
The device is controlled via a 3 wire serial interface. The
interface provides access to all features including channel
selection, volume controls, mutes, de-emphasis and power
management facilities. The device is available in a 64-pin
TQFP package.
5V tolerant digital inputs
APPLICATIONS
•
•
Surround Sound AV Processors and Hi-Fi systems
Automotive Audio
BLOCK DIAGRAM
W
WM8773
AIN1L
AIN1R
AIN2L
AIN2R
AIN3L
AIN3R
AIN4L
AIN4R
AIN5L
AIN5R
AUDIO INTERFACE
AND
MCLK
DOUT
STEREO
ADC
ADCLRC
BCLK
AIN6L
AIN6R
DIGITAL FILTERS
AIN7L
AIN7R
AIN8L
AIN8R
AINOPL
AINOPR
RECL
MUTE
CONTROL INTERFACE
RECR
WOLFSON MICROELECTRONICS plc
Production Data, August 2004, Rev 4.0
w :: www.wolfsonmicro.com
Copyright 2004 Wolfson Microelectronics plc
WM8773
Production Data
TABLE OF CONTENTS
DESCRIPTION .......................................................................................................1
FEATURES.............................................................................................................1
APPLICATIONS .....................................................................................................1
BLOCK DIAGRAM .................................................................................................1
TABLE OF CONTENTS .........................................................................................2
PIN CONFIGURATION...........................................................................................3
ORDERING INFORMATION ..................................................................................3
PIN DESCRIPTION ................................................................................................4
PIN DESCRIPTION ................................................................................................4
ABSOLUTE MAXIMUM RATINGS.........................................................................6
ELECTRICAL CHARACTERISTICS ......................................................................7
TERMINOLOGY.....................................................................................................8
MASTER CLOCK TIMING......................................................................................9
DIGITAL AUDIO INTERFACE – MASTER MODE......................................................... 9
DIGITAL AUDIO INTERFACE – SLAVE MODE .......................................................... 10
MPU INTERFACE TIMING.......................................................................................... 12
DEVICE DESCRIPTION.......................................................................................13
INTRODUCTION......................................................................................................... 13
AUDIO DATA SAMPLING RATES............................................................................... 13
POWERDOWN MODES ............................................................................................. 14
DIGITAL AUDIO INTERFACE..................................................................................... 14
CONTROL INTERFACE OPERATION........................................................................ 18
CONTROL INTERFACE REGISTERS ........................................................................ 19
REGISTER MAP...................................................................................................23
DIGITAL FILTER CHARACTERISTICS...............................................................26
ADC FILTER RESPONSES .................................................................................26
ADC HIGH PASS FILTER ........................................................................................... 26
APPLICATION INFORMATION............................................................................27
RECOMMENDED EXTERNAL COMPONENTS.......................................................... 27
EXTERNAL CIRCUIT CONFIGURATION ................................................................... 28
IMPORTANT NOTICE..........................................................................................30
ADDRESS: .................................................................................................................. 30
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WM8773
PIN CONFIGURATION
ORDERING INFORMATION
MOISTURE SENSITIVITY
LEVEL
PEAK SOLDERING
TEMPERATURE
TEMPERATURE
DEVICE
RANGE
PACKAGE
WM8773EFT/V
WM8773SEFT/V
-25 to +85oC
-25 to +85oC
64-pin TQFP
MSL3
MSL3
240°C
260°C
64-pin TQFP
(lead free)
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PIN DESCRIPTION
PIN
1
NAME
AIN1L
TYPE
DESCRIPTION
Channel 1 left input multiplexor virtual ground
Channel 1 right input multiplexor virtual ground
Channel 2 left input multiplexor virtual ground
Channel 2 right input multiplexor virtual ground
Channel 3 left input multiplexor virtual ground
Channel 3 right input multiplexor virtual ground
Channel 4 left input multiplexor virtual ground
Channel 4 right input multiplexor virtual ground
Channel 5 left input multiplexor virtual ground
Channel 5 right input multiplexor virtual ground
Channel 6 left input multiplexor virtual ground
Channel 6 right input multiplexor virtual ground
Channel 7 left input multiplexor virtual ground
Channel 7 right input multiplexor virtual ground
Channel 8 left input multiplexor virtual ground
Channel 8 right input multiplexor virtual ground
Analogue Input
Analogue Input
Analogue Input
Analogue Input
Analogue Input
Analogue Input
Analogue Input
Analogue Input
Analogue Input
Analogue Input
Analogue Input
Analogue Input
Analogue Input
Analogue Input
Analogue Input
Analogue Input
2
AIN1R
AIN2L
3
4
AIN2R
AIN3L
5
6
AIN3R
AIN4L
7
8
AIN4R
AIN5L
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
AIN5R
AIN6L
AIN6R
AIN7L
AIN7R
AIN8L
AIN8R
AINOPL
AINVGL
AINVGR
AINOPR
RECL
Analogue Output Left channel multiplexor output
Analogue Input
Analogue Input
Left channel multiplexor virtual ground
Right channel multiplexor virtual ground
Analogue Output Right channel multiplexor output
Analogue Output Left channel input mux select output
Analogue Output Right channel input mux select output
RECR
REFADC
VMIDADC
AGND1
AVDD1
Analogue Output ADC reference buffer decoupling pin; 10uF external decoupling
Analogue Output ADC midrail divider decoupling pin; 10uF external decoupling
Supply
Supply
NC
Analogue negative supply and substrate connection
Analogue positive supply
No connection
NC
No connection
NC
No connection
NC
No connection
NC
No connection
NC
No connection
AVDD2
Supply
NC
Analogue positive supply
No connection
NC
No connection
NC
No connection
NC
No connection
NC
No connection
NC
No connection
NC
No connection
NC
No connection
NC
No connection
NC
No connection
NC
No connection
NC
No connection
NC
No connection
AGND2
DGND
DVDD
Supply
Supply
Supply
Analogue negative supply and substrate connection
Digital negative supply
Digital positive supply
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WM8773
PIN
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
NAME
TYPE
NC
DESCRIPTION
No connection
No connection
ADC data output
Test reference
Test reference
Test reference
Test reference
Test reference
NC
DOUT
TESTREF1
TESTREF2
TESTREF3
TESTREF4
TESTREF5
ADCLRC
BCLK
Digital output
Digital input
Digital input
Digital input
Digital input
Digital input
Digital input/output ADC left/right word clock
Digital input/output ADC audio interface bit clock
MCLK
Digital input
Digital input
Digital input
Digital input
Digital input
Master ADC clock; 256, 384, 512 or 768fs (fs = word clock frequency)
Serial interface clock (5V tolerant)
CL
DI
Serial interface data (5V tolerant)
CE
Serial interface Latch signal (5V tolerant)
Device reset input (resets gain stages to 0dB)
(5V tolerant)
RESETB
Note : Digital input pins have Schmitt trigger input buffers and are 5V tolerant.
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ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
The Moisture Sensitivity Level for each package type is specified in Ordering Information.
CONDITION
MIN
-0.3V
MAX
+3.63V
Digital supply voltage
Analogue supply voltage
-0.3V
+7V
Voltage range digital inputs (DI, CL, CE & RESETB)
Voltage range digital inputs (MCLK, ADCLRC & BCLK)
Voltage range analogue inputs
Master Clock Frequency
DGND -0.3V
DGND -0.3V
AGND -0.3V
+7V
DVDD + 0.3V
AVDD +0.3V
37MHz
Operating temperature range, TA
Storage temperature
-25°C
-65°C
+85°C
+150°C
Notes:
1. Analogue and digital grounds must always be within 0.3V of each other.
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WM8773
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
2.7
TYP
MAX
3.6
UNIT
Digital supply range
Analogue supply range
Ground
DVDD
V
V
V
V
AVDD
2.7
5.5
AGND, DGND
0
0
Difference DGND to AGND
-0.3
+0.3
Note: Digital supply DVDD must never be more than AVDD + 0.3V.
ELECTRICAL CHARACTERISTICS
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital Logic Levels (TTL Levels)
Input LOW level
VIL
VIH
0.8
V
V
V
V
Input HIGH level
2.0
Output LOW
VOL
VOH
I
OL=1mA
0.1 x DVDD
Output HIGH
IOH=1mA
0.9 x DVDD
Analogue Reference Levels
Reference voltage
VVMID
RVMID
AVDD/2 –
50mV
AVDD/2
50k
AVDD/2 +
50mV
V
Potential divider resistance
AVDD to VMIDADC
and VMIDADC to
AGND
40k
60k
Ω
ADC Performance
Input Signal Level (0dB)
1.0 x
AVDD/5
102
Vrms
dB
SNR (Note 1,2)
SNR (Note 1,2)
A-weighted, 0dB gain
@ fs = 48kHz
90
A-weighted, 0dB gain
@ fs = 96kHz
98
dB
Dynamic Range (note 2)
A-weighted, -60dB
full scale input
102
dB
Total Harmonic Distortion (THD)
1kHz, 0dBFs
1kHz, -1dBFs
1kHz Input
-90
-95
dB
dB
dB
dB
dB
dB
dB
dB
-90
1.9
ADC Channel Separation
Programmable Gain Step Size
Programmable Gain Range
Mute Attenuation
90
0.5
1.0
1kHz Input
1kHz Input, 0dB gain
1kHz 100mVpp
-12 to +19
97
Power Supply Rejection Ratio
PSRR
50
20Hz to 20kHz
100mVpp
45
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Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analogue input (AIN) to Analogue output (VOUT) (Load=10k ohms, 50pF, gain = 0dB) Record Monitor Output
0dB Full scale output voltage
1.0 x
AVDD/5
100
Vrms
SNR (Note 1)
THD
dB
dB
dB
dB
dB
1kHz, 0dB
1kHz, -3dB
-90
-95
Power Supply Rejection Ratio
PSRR
1kHz 100mVpp
50
20Hz to 20kHz
100mVpp
45
Mute Attenuation (REC Output
Only)
1kHz, 0dB
100
dB
Supply Current
Analogue supply current
Digital supply current
AVDD = 5V
100
20
mA
mA
DVDD = 3.3V
Notes:
1. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured ‘A’
weighted.
2. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use
such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical
Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic
specification values.
3. VMID decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance).
TERMINOLOGY
1. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output
with no signal applied. (No Auto-zero or Automute function is employed in achieving these results).
2. Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal.
Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB
to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB).
3. THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal.
4. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band).
5. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from
the other. Normally measured by sending a full scale signal down one channel and measuring the other.
6. Pass-Band Ripple - Any variation of the frequency response in the pass-band region.
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WM8773
MASTER CLOCK TIMING
tMCLKL
MCLK
tMCLKH
tMCLKY
Figure 1 Master Clock Timing Requirements
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND = 0V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK System clock pulse width high
MCLK System clock pulse width low
MCLK System clock cycle time
MCLK Duty cycle
tMCLKH
tMCLKL
tMCLKY
11
11
ns
ns
ns
28
40:60
60:40
Table 1 Master Clock Timing Requirements
DIGITAL AUDIO INTERFACE – MASTER MODE
BCLK
DSP/
WM8773
ADC
ENCODER/
ADCLRC
DOUT
DECODER
Figure 2 Audio Interface - Master Mode
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BCLK
(Output)
tDL
ADCLRC
DOUT
tDDA
Figure 3 Digital Audio Data Timing – Master Mode
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25oC, Master Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
ADCLRC propagation delay
from BCLK falling edge
tDL
0
0
10
10
ns
ns
DOUT propagation delay
from BCLK falling edge
tDDA
Table 2 Digital Audio Data Timing – Master Mode
DIGITAL AUDIO INTERFACE – SLAVE MODE
Figure 4 Audio Interface – Slave Mode
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WM8773
Figure 5 Digital Audio Data Timing – Slave Mode
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise
stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
tBCY
tBCH
tBCL
50
20
20
10
ns
ns
ns
ns
BCLK pulse width high
BCLK pulse width low
ADCLRC set-up time to
BCLK rising edge
tLRSU
ADCLRC hold time from
BCLK rising edge
tLRH
tDD
10
0
ns
ns
DOUT propagation delay
from BCLK falling edge
10
Table 3 Digital Audio Data Timing – Slave Mode
Note:
1. ADCLRC should be synchronous with MCLK, although the WM8773 interface is tolerant of phase variations or jitter on
these signals.
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MPU INTERFACE TIMING
tRCSU
tRCHO
RESETB
CE
tCSL
tCSH
tSCY
tCSS
tSCS
tSCH
tSCL
CL
DI
LSB
tDSU
tDHO
Figure 6 SPI Compatible Control Interface Input Timing
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated
PARAMETER
CE to RESETB hold time
SYMBOL
tRCSU
tRCHO
tSCS
MIN
20
20
60
80
30
30
20
20
20
20
20
TYP
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RESETB to CL setup time
CL rising edge to CE rising edge
CL pulse cycle time
CL pulse width low
tSCY
tSCL
CL pulse width high
DI to CL set-up time
CL to DI hold time
tSCH
tDSU
tDHO
CE pulse width low
tCSL
CE pulse width high
CE rising to CL rising
tCSH
tCSS
Table 4 3-wire SPI Compatible Control Interface Input Timing Information
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WM8773
DEVICE DESCRIPTION
INTRODUCTION
WM8773 is a complete stereo audio ADC with 8-channel multiplexed input.
The input multiplexor to the ADC is configured to allow large signal levels to be input to the ADC,
using external resistors to reduce the amplitude of larger signals to within the normal operating range
of the ADC. The ADC input PGA also allows input signals to be gained up to +19dB and attenuated
down to -12dB. This allows the user maximum flexibility in the use of the ADC.
Analogue record monitor outputs are also available, to allow stereo analogue signals from any of the
8 stereo inputs to be sent to sent to one of the two stereo outputs. This allows the user to monitor
the signal that is being digitised either prior to the input programmable gain amplifier (PGA) or after
gain has been applied. It is intended that the RECL/R outputs are only used to drive a high
impedance buffer.
The Audio Interface may be configured to operate in either master or slave mode. In Slave mode
ADCLRC and BCLK are both inputs. In Master mode ADCLRC and BCLK are all outputs.
Control of internal functionality of the device is by 3-wire serial control interface. The control interface
may be asynchronous to the audio data interface as control data will be re-synchronised to the audio
processing internally. CE, CL, DI and RESETB are 5V tolerant with TTL input thresholds, allowing
the WM8773 to used with DVDD = 3.3V and be controlled by a controller with 5V output.
Operation using system clock of 256fs, 384fs, 512fs or 768fs is provided. In Slave mode selection
between clock rates is automatically controlled. In master mode the master clock to sample rate ratio
is set by control bit ADCRATE. Sample rates (fs) from less than 8ks/s up to 96ks/s are allowed,
provided the appropriate system clock is input.
The audio data interface supports right, left and I2S interface formats along with a highly flexible DSP
serial port interface.
AUDIO DATA SAMPLING RATES
In a typical digital audio system there is only one central clock source producing a reference clock to
which all audio data processing is synchronised. This clock is often referred to as the audio system’s
Master Clock. The external master system clock can be applied directly through the MCLK input pin
with no software configuration necessary. In a system where there are a number of possible sources
for the reference clock it is recommended that the clock source with the lowest jitter be used to
optimise the performance of the ADC.
The master clock for WM8773 supports ADC audio sampling rates from 256fs to 768fs, where fs is
the audio sampling frequency (ADCLRC) typically 32kHz, 44.1kHz, 48kHz or 96kHz. The master
clock is used to operate the digital filters and the noise shaping circuits.
In Slave mode the WM8773 has a master detection circuit that automatically determines the
relationship between the master clock frequency and the sampling rate (to within +/- 32 system
clocks). If there is a greater than 32 clocks error the interface is disabled and maintains the output
level at the last sample. The master clock must be synchronised with ADCLRC, although the
WM8773 is tolerant of phase variations or jitter on this clock. Table 5 shows the typical master clock
frequency inputs for the WM8773.
The signal processing for the WM8773 typically operates at an oversampling rate of 128fs for the
ADC. For ADC operation at 96kHz, it is recommended that the user set the ADCOSR bit. This
changes the ADC signal processing oversample rate to 64fs.
SAMPLING
RATE
System Clock Frequency (MHz)
256fs
384fs
512fs
768fs
(ADCLRC)
32kHz
44.1kHz
48kHz
8.192
11.2896
12.288
12.288
16.9340
18.432
16.384
22.5792
24.576
24.576
33.8688
36.864
Table 5 System Clock Frequencies Versus Sampling Rate
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In Master mode BCLK and ADCLRC are generated by the WM8773. The frequency of ADCLRC is
determined by setting the required ratio of MCLK to ADCLRC using the ADCRATE control bits (Table
6).
ADCRATE[2:0]
MCLK:ADCLRC RATIO
010
011
100
101
256fs
384fs
512fs
768fs
Table 6 Master Mode MCLK:ADCLRC Ratio Select
Table 7 shows the settings for ADCRATE for common sample rates and MCLK frequencies.
SAMPLING
RATE
System Clock Frequency (MHz)
256fs
384fs
512fs
768fs
ADCLRC
ADCRATE
=010
ADCRATE
=011
ADCRATE
=100
ADCRATE
=101
32kHz
44.1kHz
48kHz
8.192
11.2896
12.288
24.576
12.288
16.9340
18.432
36.864
16.384
22.5792
24.576
24.576
33.8688
36.864
96kHz
Unavailable Unavailable
Table 7 Master Mode ADC Frequency Selection
BCLK is also generated by the WM8773. The frequency of BCLK depends on the mode of operation.
In 256/384/512fs modes (ADCRATE=010 or 011, 100 or 101) BCLK = MCLK/4. However if DSP
mode is selected as the audio interface mode then BCLK=MCLK.
POWERDOWN MODES
The WM8773 has powerdown control bits allowing specific parts of the WM8773 to be powered off
when not being used. The 8-channel input source selector and input buffer may be powered down
using control bit AINPD. When AINPD is set all inputs to the source selector (AIN1l/R to AIN8L/R)
are switched to a buffered VMIDADC. Control bit ADCPD powers off the ADC and also the ADC input
PGAs. Setting AINPD and ADCPD will powerdown everything except the references VMIDADC and
ADCREF. These may be powered down by setting PDWN. Setting PDWN will override all other
powerdown control bits. It is recommended that the 8-channel input mux and buffer and ADC are
powered down before setting PDWN. The default is for all powerdown bits to be set except PDWN.
The Powerdown control bits allow parts of the device to be powered down when not in use.
DIGITAL AUDIO INTERFACE
MASTER AND SLAVE MODES
The audio interface operates in either Slave or Master mode, selectable using the MS control bit. In
both Master and Slave modes, ADCDAT is always an output. The default is Slave mode.
In Slave mode (MS=0) ADCLRC and BCLK are inputs to the WM8773 (Figure 7). ADCLRC is
sampled by the WM8773 on the rising edge of BCLK. ADC data is output on DOUT and changes on
the falling edge of BCLK. By setting control bit BCLKINV the polarity of BCLK may be reversed so
that ADCLRC is sampled on the falling edge of BCLK and DOUT changes on the rising edge of
BCLK.
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WM8773
Figure 7 Slave Mode
In Master mode (MS=1) ADCLRC and BCLK are outputs from the WM8773 (Figure 8). ADCLRC and
BITCLK are generated by the WM8773. ADCDAT is output on DOUT and changes on the falling
edge of BCLK. By setting control bit BCLKINV the polarity of BCLK may be reversed so that DOUT
changes on the rising edge of BCLK.
BCLK
DSP/
WM8773
ADC
ENCODER/
ADCLRC
DOUT
DECODER
Figure 8 Master Mode
AUDIO INTERFACE FORMATS
Audio data is output from the ADC filters, via the Digital Audio Interface. Five popular interface
formats are supported:
•
•
•
•
•
Left Justified mode
Right Justified mode
I2S mode
DSP Early mode
DSP Late mode
All five formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits, with the
exception of 32 bit right justified mode, which is not supported.
In left justified, right justified and I2S modes, the digital audio interface outputs ADC data on DOUT.
Audio Data for each stereo channel is time multiplexed with ADCLRC indicating whether the left or
right channel is present. ADCLRC is also used as a timing reference to indicate the beginning or end
of the data words.
In left justified, right justified and I2S modes, the minimum number of BCLKs per ADCLRC period is 2
times the selected word length. ADCLRC must be high for a minimum of word length BCLKs and
low for a minimum of word length BCLKs. Any mark to space ratio on ADCLRC is acceptable
provided the above requirements are met.
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The ADC data may also be output in DSP early or late modes, with ADCLRC used as a frame sync
to identify the MSB of the first word. The minimum number of BCLKs per ADCLRC period is 2 times
the selected word length
LEFT JUSTIFIED MODE
In left justified mode, the MSB of the ADC data is output on DOUT and changes on the same falling
edge of BCLK as ADCLRC and may be sampled on the rising edge of BCLK. ADCLRC is high
during the left samples and low during the right samples (Figure 9).
1/fs
LEFT CHANNEL
RIGHT CHANNEL
ADCLRC
BCLK
DOUT
1
2
3
n
n-2 n-1
1
2
3
n
n-2 n-1
MSB
LSB
MSB
LSB
Figure 9 Left Justified Mode Timing Diagram
RIGHT JUSTIFIED MODE
In right justified mode, the LSB of the ADC data is output on DOUT and changes on the falling edge
of BCLK preceding an ADCLRC transition and may be sampled on the rising edge of BCLK.
ADCLRC is high during the left samples and low during the right samples).
1/fs
LEFT CHANNEL
RIGHT CHANNEL
ADCLRC
BCLK
1
2
3
n
1
2
3
n
DOUT
n-2 n-1
n-2 n-1
MSB
LSB
MSB
LSB
Figure 10 Right Justified Mode Timing Diagram
I2S MODE
In I2S mode, the MSB of the ADC data is output on DOUT and changes on the first falling edge of
BCLK following an ADCLRC transition and may be sampled on the rising edge of BCLK. ADCLRC is
low during the left samples and high during the right samples.
1/fs
LEFT CHANNEL
RIGHT CHANNEL
ADCLRC
BCLK
1 BCLK
1 BCLK
DOUT
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
LSB
LSB
MSB
MSB
Figure 11 I2S Mode Timing Diagram
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DSP EARLY MODE
The MSB of the left channel ADC data is output on DOUT and changes on the first falling edge of
BCLK following a low to high ADCLRC transition and may be sampled on the rising edge of BCLK.
The right channel ADC data is contiguous with the left channel data (Figure 12)
1 BCLK
1 BCLK
1/fs
ADCLRC
BCK
LEFT CHANNEL
RIGHT CHANNEL
NO VALID DATA
DOUT
1
2
n
1
2
n
n-1
n-1
MSB
LSB
Word Length (WL)
Figure 12 DSP Early Mode Timing Diagram – ADC Data Output
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DSP LATE MODE
The MSB of the left channel ADC data is output on DOUT and changes on the same falling edge of
BCLK as the low to high ADCLRC transition and may be sampled on the rising edge of BCLK. The
right channel ADC data is contiguous with the left channel data (Figure 13).
1/fs
ADCLRC
BCK
LEFT CHANNEL
RIGHT CHANNEL
NO VALID DATA
1
2
n
1
2
n
1
DOUT
n-1
n-1
MSB
LSB
Word Length (WL)
Figure 13 DSP Late Mode Timing Diagram – ADC Data Output
CONTROL INTERFACE OPERATION
The WM8773 is controlled using a 3-wire SPI compatible serial configuration.
The control interface is 5V tolerant, meaning that the control interface input signals CE, CL and DI
may have an input high level of 5V while DVDD is 3V. Input thresholds are determined by DVDD.
RESETB is also 5V tolerant.
3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE
DI is used for the program data, CL is used to clock in the program data and CE is used to latch the
program data. DI is sampled on the rising edge of CL. The 3-wire interface protocol is shown in
Figure 14.
CE
CL
DI
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Figure 14 3-wire SPI Compatible Interface
Note:
1. B[15:9] are Control Address Bits
2. B[8:0] are Control Data Bits
3. CE is edge sensitive – the data is latched on the rising edge of CE.
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CONTROL INTERFACE REGISTERS
DIGITAL AUDIO INTERFACE CONTROL REGISTER
Interface format is selected via the FMT[1:0] register bits:
REGISTER ADDRESS
10110
BIT
LABEL
DEFAULT
DESCRIPTION
1:0 FMT[1:0]
10
Interface Format Select
Interface Control
00 : right justified mode
01: left justified mode
10: I2S mode
11: DSP (early or late) mode
In left justified, right justified or I2S modes, the LRP register bit controls the polarity of ADCLRC. If
this bit is set high, the expected polarity of ADCLRC will be the opposite of that shown Figure 9, and.
Note that if this feature is used as a means of swapping the left and right channels, a 1 sample
phase difference will be introduced. In DSP modes, the LRP register bit is used to select between
early and late modes.
REGISTER ADDRESS
10110
BIT
LABEL
DEFAULT
DESCRIPTION
In Left/Right/I2S Modes:
ADCLRC Polarity (normal)
0 : normal ADCLRC polarity
1: inverted ADCLRC polarity
In DSP Mode:
2
LRP
0
Interface Control
0 : Early DSP mode
1: Late DSP mode
By default, ADCLRC is sampled on the rising edge of BCLK and should ideally change on the falling
edge. Data sources that change ADCLRC on the rising edge of BCLK can be supported by setting
the BCP register bit. Setting BCP to 1 inverts the polarity of BCLK to the inverse of that shown in
Figure 9, Figure 10, Figure 11, Figure 12, and Figure 13.
REGISTER ADDRESS
10110
BIT
LABEL
DEFAULT
DESCRIPTION
BCLK Polarity (DSP modes)
0 : normal BCLK polarity
1: inverted BCLK polarity
3
BCP
0
Interface Control
The WL[1:0] bits are used to control the word length.
REGISTER ADDRESS
10110
BIT
LABEL
DEFAULT
DESCRIPTION
Word Length
5:4
WL[1:0]
10
Interface Control
00 : 16 bit data
01: 20 bit data
10: 24 bit data
11: 32 bit data
Note:
1. If 32-bit mode is selected in right justified mode, the WM8773 defaults to 24 bits.
2. In 24 bit I2S mode, any width of 24 bits or less is supported provided that ADCLRC is high for a
minimum of 24 BCLKs and low for a minimum of 24 BCLKs.
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Control bit MS selects between audio interface Master and Slave Modes. In Master mode ADCLRC
and BCLK are outputs and are generated by the WM8773. In Slave mode ADCLRC and BCLK are
inputs to WM8773.
REGISTER ADDRESS
10111
BIT
LABEL
DEFAULT
DESCRIPTION
8
MS
0
Audio Interface Master/Slave Mode
Select:
Interface Control
0 : Slave Mode
1: Master Mode
MASTER MODE ADCLRC FREQUENCY SELECT
In Master mode the WM8773 generates ADCLRC and BCLK. These clocks are derived from master
clock and the ratio of MCLK to ADCLRC and are set by ADCRATE.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
10111 ADCLRC
Frequency Select
2:0 ADCRATE[2:0]
010
Master Mode MCLK:ADCLRC
Ratio Select:
010: 256fs
011: 384fs
100: 512fs
101: 768fs
ADC OVERSAMPLING RATE SELECT
For ADC operation at 96kHz it is recommended that the user set the ADCOSR bit. This changes the
ADC signal processing oversample rate to 64fs.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
ADC Oversampling Rate Select
0: 128x oversampling
10111
3
ADCOSR
0
ADC Oversampling
Rate
1: 64x oversampling
MUTE MODES
Each ADC channel has an individual mute control bit, which mutes the input to the ADC. In addition
both channels may be muted by setting ADCMUTE.
REGISTER ADDRESS
11001
BIT
LABEL
DEFAULT
DESCRIPTION
ADC MUTE Left and Right
0 : Normal operation
7
ADCMUTE
0
ADC Mute
1: mute ADC left and ADC
right
11001
5
5
MUTE
MUTE
0
0
ADC Mute Select
0 : Normal operation
1: mute ADC left
ADC Mute Select
0 : Normal operation
1: mute ADC right
ADC Mute Left
11010
ADC Mute Right
The Record outputs may be enabled by setting RECEN, where RECEN enables the RECL and
RECR outputs.
REGISTER ADDRESS
10100
BIT
LABEL
DEFAULT
DESCRIPTION
REC Output Enable
5
RECEN
0
REC Enable
0 : REC output muted
1: REC output enabled
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POWERDOWN MODE AND ADC DISABLE
Setting the PDWN register bit immediately powers down the WM8773, including the references,
overriding all other powerdown control bits. All trace of the previous input samples are removed, but
all control register settings are preserved. When PDWN is cleared the digital filters will be
reinitialised. It is recommended that the 8-channel input mux and buffer, and ADC are powered down
before setting PDWN.
REGISTER ADDRESS
11000
BIT
LABEL
DEFAULT
DESCRIPTION
Power Down Mode Select:
0 : Normal Mode
0
PDWN
0
Powerdown Control
1: Power Down Mode
The ADC may also be powered down by setting the ADCD disable bit. Setting ADCD will disable the
ADC and select a low power mode. The ADC digital filters will be reset and will reinitialise when
ADCD is reset.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
ADC Disable:
11000
1
ADCD
1
ADC Powerdown
Control
0 : Normal Mode
1: Power Down Mode
ADC GAIN CONTROL
Control bits LAG[4:0] and RAG[4:0] control the ADC input gain, allowing the user to attenuate the
ADC input signal to match the full-scale range of the ADC. The gain is independently adjustable on
left and right inputs. Left and right inputs may also be independently muted. The LRBOTH control bit
allows the user to write the same attenuation value to both left and right volume control registers. The
ADC volume and mute also applies to the bypass signal path.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
11001
4:0
LAG[4:0]
01100
(0dB)
0
Attenuation data for Left channel ADC gain in 1dB steps. See Table
8
Attenuation
ADCL
5
MUTE
Mute for Left channel ADC:
0: Mute off
1: Mute on
6
LRBOTH
RAG[4:0]
0
Setting LRBOTH will write the same gain value to LAG[4:0] and
RAG[4:0]
11010
4:0
01100
(0dB)
0
Attenuation data for right channel ADC gain in 1dB steps. See Table
8
Attenuation
ADCR
5
6
MUTE
Mute for Right channel ADC:
0: Mute off
1: Mute on
LRBOTH
0
Setting LRBOTH will write the same gain value to RAG[4:0] and
LAG[4:0]
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ADC INPUT GAIN
Registers LAG and RAG control the left and right channel gain into the stereo ADC in 1dB steps from
+19dB to –12dB Table 8 shows how the attenuation levels are selected from the 5-bit words.
L/RAG[6:0]
ATTENUATION LEVEL
0
-12dB
:
:
0dB
:
01100
:
11111
+19dB
Table 8 ADC Gain Control
ADC HIGHPASS FILTER DISABLE
The ADC digital filters contain a digital highpass filter. This defaults to enabled and can be disabled
using software control bit ADCHPD.
REGISTER ADDRESS
10110
BIT
LABEL
DEFAULT
DESCRIPTION
ADC Highpass Filter Disable:
0: Highpass filter enabled
1: Highpass filter disabled
8
ADCHPD
0
ADC Control
ADC INPUT MUX AND POWERDOWN CONTROL
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
11011
2:0
LMX[2:0]
000
ADC Left Channel Input Mux
Control Bits (see Table 9)
ADC Mux and
Powerdown
Control
6:4
8
RMX[2:0]
AINPD
000
1
ADC Right Channel Input Mux
Control Bits (see Table 9)
Input Mux and Buffer Powerdown
0: Input mux and buffer enabled
1: Input mux and buffer powered
down
Register bits LMX and RMX control the left and right channel inputs into the stereo ADC. The default
is AIN1. However if the analogue input buffer is powered down, by setting AINPD, then all 8-channel
mux inputs are switched to buffered VMIDADC.
LMX[2:0]
LEFT ADC INPUT
RMX[2:0]
RIGHT ADC INPUT
000
001
010
011
100
101
110
111
AIN1L
AIN2L
AIN3L
AIN4L
AIN5L
AIN6L
AIN7L
AIN8L
000
001
010
011
100
101
110
111
AIN1R
AIN2R
AIN3R
AIN4R
AIN5R
AIN6R
AIN7R
AIN8R
Table 9 ADC Input Mux Control
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SOFTWARE REGISTER RESET
Writing to register 11111 will cause a register reset, resetting all register bits to their default values.
REGISTER MAP
The complete register map is shown below. The detailed description can be found in the relevant text of the device description. The
WM8773 can be configured using the Control Interface. All unused bits should be set to ‘0’.
REGISTER
R20(14h)
R22(16h)
R23(17h)
R24(18h)
R25(19h)
R26(1Ah)
R27(1Bh)
R31(1Fh)
B15
0
B14
0
B13
1
B12
0
B11
1
B10
0
B9
0
B8
B7
B6
B5
B4
0
B3
B2
B1
0
B0
0
DEFAULT
0
0
0
0
0
0
RECEN
0
0
000000000
ADCHPD
0
0
0
WL[1:0]
BCP
ADCOSR
1
LRP
ADCRATE[2:0]
ADCD
FMT[1:0]
000100010
000000010
0
0
1
0
1
1
0
MS
0
1
0
1
0
0
1
0
1
1
1
0
1
PWDN 000111110
000001100
000001100
100000000
not reset
0
0
1
1
0
0
0
0
0
ADCMUTE LRBOTH
MUTE
MUTE
RMX[2:0]
LAG[4:0]
RAG[4:0]
0
0
1
1
0
0
1
0
0
LRBOTH
0
0
1
1
0
1
0
AINPD
0
LMX[2:0]
0
0
1
1
0
1
1
RESET
DATA
0
0
1
1
1
1
1
DEFAULT
ADDRESS
Table 10 Register Map
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REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
10100
Mute
5
RECEN
0
REC Output Enable
0 : REC output muted
1: REC output enabled
Interface Format Select
1:0
FMT[1:0]
LRP
10
0
10110
00: Rright justified mode
01: Left justified mode
10: I2S mode
Interface
Control
11: DSP mode
2
ADCLRC Polarity or DSP Early/Late mode select
Left Justified / Right Justified /
I2S
DSP Mode
0: Early DSP mode
1: Late DSP mode
0: Standard ADCLRC Polarity
1: Inverted ADCLRC Polarity
BITCLK Polarity
3
BCP
0
0: Normal - ADCLRC sampled on rising edge of BCLK; DOUT
changes on falling edge of BCLK.
1: Inverted - ADCLRC sampled on falling edge of BCLK; DOUT
changes on rising edge of BCLK.
5:4
WL[1:0]
10
Input Word Length
00: 16-bit Mode
01: 20-bit Mode
10: 24-bit Mode
11: 32-bit Mode (not supported in right justified mode)
ADC Highpass Filter Disable:
0: Highpass filter enabled
8
ADCHPD
0
1: Highpass filter disabled
10111
2:0
ADCRATE[2:0]
010
Master Mode MCLK:ADCLRC Ratio Select:
010: 256fs
Master Mode
control
011: 384fs
100: 512fs
3
8
0
1
ADCOSR
MS
0
0
0
1
ADC Oversample Rate Select
0: 128x oversampling
1: 64x oversampling
Maser/Slave Interface Mode Select
0: Slave Mode – ADCLRC and BCLK are inputs
1: Master Mode – ADCLRC and BCLK are outputs
Chip Powerdown Control (works in together with ADCD)
0: All circuits running, outputs are active
1: All circuits in power save mode, outputs muted
ADC Powerdown:
11000
PWDN
ADCD
Powerdown
Control
0: ADC enabled
1: ADC disabled
11001
4:0
5
LAG[4:0]
MUTE
01100
(0dB)
0
Attenuation Data for Left Channel ADC gain in 1dB steps
Attenuation
ADCL
Mute for Left channel ADC:
0: Mute off
1: Mute on
6
LRBOTH
0
Setting LRBOTH will write the same gain value to LAG[4:0] and
RAG[4:0]
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REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
7
ADCMUTE
0
Mute for Left and Right Channel ADC:
0: Mute off
1: Mute on
11010
4:0
5
RAG[4:0]
MUTE
01100
(0dB)
0
Attenuation Data for Right Channel ADC gain in 1dB steps
Attenuation
ADCR
Mute for Right Channel ADC:
0: Mute off
1: Mute on
6
LRBOTH
0
Setting LRBOTH will write the same gain value to RAG[4:0] and
LAG[4:0]
11011
2:0
6:4
8
LMX[2:0]
RMX[2:0]
AINPD
000
000
1
ADC Left Channel Input Mux Control Bits
ADC Right Channel Input Mux Control Bits
Input Mux and Buffer Powerdown
ADC Mux
Control
0: Input mux and buffer enabled
1: Input mux and buffer powered down
Writing to this register will apply a reset to the device registers.
11111
[8:0]
RESET
Not reset
Software
Reset
Table 11 Register Map Description
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DIGITAL FILTER CHARACTERISTICS
PARAMETER
ADC Filter
Passband
TEST CONDITIONS
MIN
TYP
MAX
0.4535fs
0.01
UNIT
0.01 dB
-6dB
0
0.5fs
Passband ripple
Stopband
dB
0.5465fs
-65
Stopband Attenuation
Group Delay
f > 0.5465fs
dB
fs
22
Table 12 Digital Filter Characteristics
ADC FILTER RESPONSES
0.02
0.015
0.01
0
-20
-40
-60
-80
0.005
0
-0.005
-0.01
-0.015
-0.02
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0
0.5
1
1.5
2
2.5
3
Frequency (Fs)
Frequency (Fs)
Figure 16 ADC Digital Filter Ripple
Figure 15 ADC Digital Filter Frequency Response
ADC HIGH PASS FILTER
The WM8773 has a selectable digital highpass filter to remove DC offsets. The filter response is characterised by the
following polynomial.
1 - z-1
H(z) =
1 - 0.9995z-1
0
-5
-10
-15
0
0.0005
0.001
Frequency (Fs)
0.0015
0.002
Figure 17 ADC Highpass Filter Response
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WM8773
APPLICATION INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
Figure 18 External Component Diagram
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EXTERNAL CIRCUIT CONFIGURATION
In order to allow the use of 2V rms and larger inputs to the ADC inputs, a structure is used that uses
external resistors to drop these larger voltages. This also increases the robustness of the circuit to
external abuse such as ESD pulse.
Figure 19 shows the ADC input multiplexor circuit with external components allowing 2Vrms inputs to
be applied.
5K
AINOPL
AINVGL
10uF 10K
AIN1L
10uF 10K
AIN2L
10uF 10K
AIN3L
10uF 10K
AIN7L
10uF 10K
AIN8L
5K
SOURCE
AINOPR
SELECTOR
INPUTS
AINVGR
10uF 10K
10uF 10K
10uF 10K
AIN1R
AIN2R
AIN3R
10uF 10K
10uF 10K
AIN7R
AIN8R
Figure 19 ADC Input Multiplexor Configuration
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WM8773
PACKAGE DIMENSIONS
FT: 64 PIN TQFP (10 x 10 x 1.0 mm)
DM027.B
b
e
48
33
32
49
E
E1
17
64
GAUGE
PLANE
Θ
16
1
D1
D
0.25
L
c
L
1
A A2
A1
ccc
C
-C-
SEATING
PLANE
Dimensions
(mm)
Symbols
MIN
-----
0.05
0.95
0.17
0.09
NOM
-----
-----
1.00
0.22
-----
MAX
1.20
0.15
1.05
0.27
0.20
A
A1
A2
b
c
D
D1
E
12.00 BSC
10.00 BSC
12.00
BSC
E1
e
L
10.00 BSC
0.50 BSC
0.60
0.45
0.75
7o
L1
Θ
1.00 REF
3.5o
o
0
Tolerances of Form and Position
0.08
ccc
REF:
JEDEC.95, MS-026, VARIATION ACD
NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM.
D. MEETS JEDEC.95 MS-026, VARIATION = ACD. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
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IMPORTANT NOTICE
Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or
service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing
orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale
supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation
of liability.
WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM’s
standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support
this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by
government requirements.
In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used
by the customer to minimise inherent or procedural hazards. Wolfson products are not authorised for use as critical
components in life support devices or systems without the express written approval of an officer of the company. Life
support devices or systems are devices or systems that are intended for surgical implant into the body, or support or
sustain life, and whose failure to perform when properly used in accordance with instructions for use provided, can be
reasonably expected to result in a significant injury to the user. A critical component is any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that
any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual
property right of WM covering or relating to any combination, machine, or process in which such products or services might
be or are used. WM’s publication of information regarding any third party’s products or services does not constitute WM’s
approval, license, warranty or endorsement thereof.
Reproduction of information from the WM web site or datasheets is permissible only if reproduction is without alteration and
is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this
information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive
business practice, and WM is not responsible nor liable for any such use.
Resale of WM’s products or services with statements different from or beyond the parameters stated by WM for that
product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and
deceptive business practice, and WM is not responsible nor liable for any such use.
ADDRESS:
Wolfson Microelectronics plc
Westfield House
26 Westfield Road
Edinburgh
EH11 2QB
United Kingdom
Tel :: +44 (0)131 272 7000
Fax :: +44 (0)131 272 7001
Email :: sales@wolfsonmicro.com
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