SCG4010-125.0M [CONNOR-WINFIELD]
Support Circuit, 1-Func,;
| 型号： | SCG4010-125.0M |
| 厂家： | 
CONNOR-WINFIELD CORPORATION |
| 描述： | Support Circuit, 1-Func, ATM 异步传输模式 电信 电信集成电路 |
| 文件： | 总16页 (文件大小：377K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SCG4000 V3.0 Series
Synchronous Clock
Generators
PLL
2111 Comprehensive Drive
Aurora, Illinois 60505
Phone: 630-851-4722
Fax: 630- 851- 5040
www.conwin.com
Application
Features
The Connor-Winfield SCG4000 Series
provides high precision phase lock loop
frequency translation for the
• 3.3V High
Precision PLL
• Tri-State
Capability
telecommunication applications.
SCG4000 Series is well suited for use in
line cards, service termination cards and
similar functions to provide reliable
reference, phase locked, synchronization
for TDM, PDH, SONET and SDH network
equipment. The SCG4000 Series provides
a jitter filtered, wander following output
signal sychronized to a superior Stratum or
peer input reference signal.
• Active Alarms
• Guaranteed Free
Run ±20ppm
• 1 sec. Acquisition
Time
Bulletin
SG031
Page
1 of 12
Revision
01
Date
30 JULY 02
Issued By
MBatts
General Description
The SCG4000 Series is a digital phase locked loop
generating a LVPECL outputs from an intrinsically low
jitter voltage controlled crystal oscillator. The LVPECL
outputs may be disabled. The jitter attenuated internal
reference, divided down from the output frequency, is also
output to a pin.
The SCG4000 Series can lock to one of four possible
reference frequencies from 8 to 64 kHz, which is
selectable using two input select pins. A filtered reference
output signal is available at the same frequency. The unit
has an acquisition time of about 1 second and it is tolerant
of different reference duty cycles.
Further features include alarm outputs for Loss-of-
Reference (LOR) and Loss-of-Lock (LOL). During the
LOR alarm, the SCG4000 will also enter a Free Run
state, which will guarantee a 20 ppm accurate output.
Additionally the Free Run mode may be entered
manually.
The alarms and reference output may be put into
the tri-state high impedance condition for external
testing purposes.
The maximum package dimensions are 1” x 1.025”
x .450” on a 6 layer FR4 board with castellated pins.
Parts are assembled using high temperature solder to
withstand 63/37 alloy, 180° C surface mount reflow
processes.
Functional Block Diagram
Figure 1
SCG4000 Series
Block Diagram
LOL Alarm Output
(Pin 11)
ALARM
DETECTION
LOR Alarm Output
(Pin 12)
Force Free Run
(Pin 13)
Q
(Pin 18)
Differential
FREE RUN
ANALOG
FILTER
VCXO
DIVIDER
DPFD
LVPECL
Outputs
Reference Input
(Pin 4)
CONTROL
QN
(Pin 16)
DIVIDER
CMOS
Reference Output
(Pin 7)
Select A
(Pin 5)
Select B
(Pin 6)
VCXO Enable
(Pin 1)
Model Comparison Table
Table 1
Max
CMOS
LVPECL
Model
Input
Ref Freq
Duty
Cycle
Reference Output
(Pin #7)
Oscillator Output
(Pin #16 & 18)
Notes
SCG4000 8-64 kHz
SCG4010 19.44 MHz
SCG4030 8-64 kHz
40/60
40/60
45/55
= Input Ref Freq.
19.44 MHz
125.0 MHz, 155.52 MHz
125.0 MHz, 155.52 MHz
125.0 MHz, 155.52 MHz
Basic Model
= Input Ref Freq.
Tighter Duty Cycle
*Features which differentiate a model from the base model (SCG4000) are highlighted in boldface, color and in the notes column.
Data Sheet #: SG031
Page 2 of 16
Rev: 01
Date: 07/30/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Absolute Maximum Rating
Table 2
All SCG4000 Models
Symbol
Vcc
Parameter
Minimum
3.0
Nominal
Maximum
3.6
Units
Volts
Notes
Power Supply Voltage
Input Voltage
V1
-0.5
5.5
Volts
Ts
Storage Temperature
-65
150
deg. C
Operating Specifications
Table 3
All SCG4000 Models
Symbol
Vcc
Parameter
Minimum
Nominal
Maximum
3.465
280
Units
Volts
mA
Notes
1.0
Power Supply Voltage
Power Supply Current
Temperature Range
Free Run Accuracy
Capture/pull-in range
Jitter Filter Bandwidth
Input Jitter Tolerance
3.135
3.3
Icc
-
230
To
0
-
-
-
-
70
°C
Ffr
-20
-25
-
20
ppm
ppm
Hz
Fcap
Fbw
Tjtol
25
10
-
-
-
-
31.25
1.0
µs SCG4000, SCG4030
µs
SCG4010
Taq
Trf
Acquisition Time
-
1
-
s
2.0
Output Rise and Fall Time (20% 80%)
100
225
350
ps
3.0
Features
All SCG4000 Models
Table 4
Parameter
Specifications
Notes
Alarms
LOR, LOL Status on seperate CMOS Outputs
70 ps (typical)
TDEV
MTIE
800 ps (typical)
Static Offset
Dynamic Offset
VCXO Output Logic Type
Reference Output Logic Type
Package
± 26 ns Maximum
± 20 ns Maximum
LVPECL
4.0
5.0
CMOS
FR4 SM 1.0" x 1.025" x 0.45"
CMOS Input And Output Characteristics
Table 5
All SCG4000 Models
Symbol
VIH
Parameter
Minimum
Nominal
Maximum
Units
V
Notes
High Level Input Voltage
Low Level Input Voltage
I/O to Output Valid
2
0
5.5
0.8
10
VIL
V
TIO
nS
pF
CO
Output Capacitance
10
VHO
VIO
High Level Output Voltage loh = 04mA
Low Level Output Voltage lo1 = 8mA
Input Reference Signal Pulse Width
2.4
Vcc Min.
Vcc Max.
0.4
nS
TIR
12.5
NOTES: 1.0: Requires external regulation and filter (22uF, 330 pF)
2.0: From a 20 ppm offset in reference frequency
3.0: 50Ω load biased to 1.3V
4.0: Offset between Reference Input and Reference Output @ room temp.
5.0: Offset change between Reference Input and Reference Output over temperature range from room temperature.
Data Sheet #: SG031
Page 3 of 16
Rev: 01
Date: 07/30/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
LVPECL Output Characteristics
Table 6
All SCG4000 Models
Symbol
VOH
Parameter
Minimum
2.27
Nominal
2.34
Maximum
2.42
Units
V
Notes
High Level PECL Voltage
Low Level PECL Voltage
Output Capacitance
Differential Output Skew
VOL
1.49
1.51
1.68
V
CL
10
pF
ps
TSKEW
50
Output Jitter Specifications
Table 7
All SCG4000 Models
Jitter BW 10 Hz - 20 MHz
SONET Jitter BW 12 kHz - 20 MHz
Frequency (MHz)
125.00
pS (RMS)
m UI
pS (RMS)
m UI
6(typical)
6(typical)
0.750 (typical)
0.933 (typical)
1 (max), 0.3 (typical)
1 (max), 0.4 (typical)
0.125(max)
0.156 (max)
155.52
Output Programming
Alarm Status
All SCG4000 Models
Table 8
All SCG4000 Models
Table 9
Tristate Free Run Output
LOL Output LOR Output Alarm Output
0
1
0
0
X
1
Locked to reference selected (default)
0
1
X
0
0
1
No alarm
Hi-Z Tristate condition
Loss-of-Lock
Loss-of-Reference
Free run at nominal frequency
Pin Description
All SCG4000 Models
Table 10
Pin #
1
Connection
Enable/Disable
TCK
Description
Enable = 0, Disable = 1 for VCXO Ouputs, Default = 0 (for No Connect)
2
JTAG pin that is used only by Connor-Winfield for programming. Do not connect
JTAG pin that is used only by Connor-Winfield for programming. Do not connect
CMOS Reference Frequency Input
3
TDO
4
Reference In
Select A
5
Reference Frequency Select Pin, Default = 0 (for No Connect)
Reference Frequency Select Pin, Default = 0 (for No Connect)
Filtered Reference Output
6
Select B
7
Reference Out
Ground
8
Power Ground
9
Tri-State Enable
VCC
CMOS Output Tri-State enable (Hi-Z =1, Default = 0)
3.3V Supply Voltage.
10
11
12
13
14
15
16
17
18
Loss of Lock
Loss of Reference
Free Run
TDI
LOL Alarm Output
LOR Alarm Output
Force output frequency to Free Run (FR = 1, Default = 0)
JTAG pin that is used only by Connor-Winfield for programming. Do not connect
JTAG pin that is used only by Connor-Winfield for programming. Do not connect
VCXO differential LVPECL Output
TMS
VCXO Out
Signal Ground
VCXO Out
VCXO output ground (Shield)
VCXO differential LVPECL Output
Data Sheet #: SG031
Page 4 of 16
Rev: 01
Date: 07/30/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Maximum Package Dimensions
Figure 2
Recommended Footprint and Keepout Area Dimensions
Figure 3
Keep Out
Area
Data Sheet #: SG031
Page 5 of 16
Rev: 01
Date: 07/30/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Tape and Reel Dimensions
Figure 4
Solder Profile
Figure 5
250
200
150
100
50
Temp
(C˚)
0
1
2
3
4
5
6
Time(minutes)
Recommended Reflow Profile
Peak Temp:217C˚
MaxRiseSlope:1.5C˚/Sec
Time Above150C˚:100Sec
Data Sheet #: SG031
Page 6 of 16
Rev: 01
Date: 07/30/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Typical Application
Figure 6
Typical Application of
Connor-Winfield’s
SCG4000 Series Timing Products
BITS
System
Signal
Line Cards
Input Select
Timing Card #1
S
A
B
A
CW’s SCG
4000
MUX
Clock out
RCV
Y
CW’s STM/MSTM module
Y
B
MUX
C
S
Timing Card #2
S
A
A
CW’s SCG
4000
Clock out
RCV
MUX
CW’s STM/MSTM module
Y
B
B
Y
MUX
C
S
System Select
Typical System Test Set-up
Figure 7
GPS or LORAN
Timing Source
This device supplies system time
information. It can be thought of as
supplying "absolute time" reference
information
Sample
M TIE Data for STM -S 3/M STM-S3
1.0E-6
T
re
y
f
picalresponse- 3000second
dat AP R 22 1998
kdh
tes
t
-
Jitterapplied
(
2
UI
@
10H
z)
e
Possible Choices Include
Stanford Research Model: FS700
Truetime Model XXX
100.0E-9
10
MTI
E
10.0E-9
1244-5.2 Mas
1244-5.2 Mas
1244-5.6 Mas
k
k
k
(A
(B
)
MHz
)
G
R253-5.4.4.3.2
1.0E-9
100
.0E-
3
1
.0E+
0
10.0E+0
10
0.0E+
0
1.0E+
3
10.0E+3
Observation Tim
e
(s
)
C
o
py
r
ight
1
9
9
8
Connor-Winf
ield
a
l
l
righ
ts
reserv
ed
Target System Under Test
External
Standards
Compliance
Documents
Reference
DS1 rate RZ (1.544 MHz), E1 rate RZ or 8 kHz
clock RZ with noise modulation
Arbitrary
Waveform
Generator
Input
Clock or BITS logic level
clock input (TTL, CMOS,
etc.)
MTIE, TDEV, Wander Transfer,
and Wander Generation Plots
Sample Wande
r
G
eneration
UI 10 Hz)
(
T
D
EV) for
S
TM/M STM-S 3
1.0E-6
Ty
ef dat
dh
p
i
calresponse
e A
-
300 second est itterapplied
0
t
-
J
(
2
@
r
k
PR 221998
10
100.0E-9
MHz
. . . . ...
1
0.0E-9
TDE
V
G
G
R1244-Fig5.1
R1244-Fig5-3
1.0E-9
Arbitrary
Waveform
Generator
[Noise
100
.0E
-
12
0.0E
1
-
3
100.0E-
3
1.0E+0
Inte ratio
10.0E+0
100.0E+0
ight 1998 Connor-Winfielda lll rights re
1.0E+3
served
C
o
pyr
g
n Time (sec)
External
Reference
Input
Source]
Time-stamped ensemble
based on absolute time
reference (10MHz input)
10
MHz
DS1 rate [1.544 MHz] BITS Bipolar
Phase Error data output
DS-1, OC-3, OC-12 electrical or optical signals
External
Tektronix
SJ300E
10
Reference
HP53310A
Input
MHz
Modulation Analyzer / Time Interval Analyzer
Wander Analyzer data (IEEE-488)
External
Reference
Input
IEEE-488 Controller
Platform for software
HP 53305A Phase Analyzer
HP E1748A Sync
Measurement
TEKTRONIX SJ300E
Tektronix Wander Analyzer
Data Sheet #: SG031
Page 7 of 16
Rev: 01
Date: 07/30/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Alarm Timing Diagram
Figure 8
Start-up
Region
LOR
Output
4
LOL
Output
2
1
1
Phase
Detector
3
External
Reference
Internal
Reference
2
2
2
2
2
2
2
2
2
2
2
2
2
2
LOR
Output
LOL
Output
5
1
1
1
1
1
Phase
Detector
3
3
External
Reference
Internal
Reference
2
2
2
2
2
2
2
2
2
2
2
2
2
2
19.44 MHz &77.76 MHz
8 kHz Reference Input Units
Reference Input Units
< 1 µsec
< 31.25 µsec
31.25 µsec
1
1 µsec
2
3
4
5
> 1 µsec
> 31.25 µsec
LOR is active when LOL is active
125 µsec wide range
Minimum pulse width = 2 µsec
Minimum pulse width = 62.5 µsec
During Start-up, The LOL Alarm will pulse
during the first second of operation
Start-up Region
Data Sheet #: SG031
Page 8 of 16
Rev: 01
Date: 07/30/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
SCG4000 Series Typical MTIE
Figure 9
1.0E -9
100.0E -12
1.0E -3
10.0E -3
100.0E -3
1.0E +0
10.0E +0
100.0E +0
Ob servation W indow (T au)
SCG4000 Series Typical TDEV
Figure 10
100.0E -12
10.0E -12
1.0E-3
10.0E -3
100.0E-3
1.0E +0
10.0E +0
Tau
Data Sheet #: SG031
Page 9 of 16
Rev: 01
Date: 07/30/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
SCG4000
The SCG4000 is Connor-Winfield’s base model
SCG4000 Individual Features:
• Four selectable References: 8, 16, 32, and 64
kHz.
for the SCG4000 Series product line. The
SCG4000 can lock to one of four input
reference frequencies from 8 to 64 kHz which is
selectable using two input control pins.
• LVPECL Oscillator Output: 125.0 MHz or 155.52
MHz
• CMOS reference output frequency equals input
reference frequency.
Input Reference Selection
Table 11
SCG4000
Input Sel A
(Pin #5)
Input Sel B
(Pin #6)
Reference Frequency
(Pin #8)
8 kHz (default)
16 kHz
0
1
0
1
0
0
1
1
32 kHz
64 kHz
Reference and Output Availability
Table 12
SCG4000
LVPECL
CMOS
Input Reference
(Pin #4)
Oscillator Output
(Pin #16 & #18)
Reference Output
(Pin #7)
8 kHz
125.0 MHz
8 kHz
8 kHz
16 kHz
32 kHz
64 kHz
8 kHz
16 kHz
32 kHz
64 kHz
155.52 MHz
Ordering Information
SCG4000-125.0M
SCG4000-155.52M
Data Sheet #: SG031
Page 10 of 16
Rev: 01
Date: 07/30/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
SCG4010
The SCG4010 only accepts a 19.44 MHz
SCG4010 Individual Features:
• Input Reference: 19.44 MHz
input while providing a phase locked LVPECL
output. Also provided is a phase locked 19.44
MHz CMOS reference output.
• LVPECL Oscillator Output: 125.0 MHZ or
155.52 MHz
• CMOS Reference Output: 19.44 MHz
Input Reference Selection
Table 13
SCG4010
Input Sel A
(Pin #5)
Input Sel B
(Pin #6)
Reference Frequency
(Pin #8)
X
X
19.44 MHz (default)
Note: X= Don’t Care
Reference and Output Availability
Table 14
SCG4010
LVPECL
CMOS
Input Reference
(Pin #4)
Oscillator Output
(Pin #16 & #18)
Reference Output
(Pin #7)
19.44 MHz
125.0 MHz, 155.52 MHz
19.44 MHz
Ordering Information
SCG4010-125.0M
SCG4010-155.52M
Data Sheet #: SG031
Page 11 of 16
Rev: 01
Date: 07/30/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
SCG4030
The SCG 4030 is similar to the SCG4000
SCG4030 Individual Features:
• Four selectable References: 8, 16, 32, and 64
kHz.
except the SCG4030 offers a duty cycle of 45/
55 for applications that require a tighter duty
cycle.
The SCG4030 can lock to one of four input
reference frequencies from 8 to 64 kHz which is
selectable using two input control pins.
• 45/55 Duty cycle
• LVPECL Oscillator Output: 125.0MHz or 155.52
MHz
• CMOS reference output frequency equals input
reference frequency.
Input Reference Selection
Table 15
SCG4030
Input Sel A
(Pin #5)
Input Sel B
(Pin #6)
Reference Frequency
(Pin #8)
8 kHz (default)
16 kHz
0
1
0
1
0
0
1
1
32 kHz
64 kHz
Reference and Output Availability
Table 16
SCG4030
LVPECL
CMOS
Input Reference
(Pin #4)
Oscillator Output
(Pin #16 & #18)
Reference Output
(Pin #7)
8 kHz
125.0 MHz
8 kHz
8 kHz
16 kHz
32 kHz
64 kHz
8 kHz
16 kHz
32 kHz
64 kHz
155.52 MHz
Ordering Information
SCG4030-125.0M
SCG4030-155.52M
Data Sheet #: SG031
Page 12 of 16
Rev: 01
Date: 07/30/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Data Sheet #: SG031
Page 13 of 16
Rev: 01
Date: 07/30/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Data Sheet #: SG031
Page 14 of 16
Rev: 01
Date: 07/30/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Data Sheet #: SG031
Page 15 of 16
Rev: 01
Date: 07/30/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
2111 Comprehensive Drive
Aurora, Illinois 60505
Phone: 630-851-4722
Fax: 630- 851- 5040
www.conwin.com
Revision
Revision Date
6/14/02
Note
00
01
Final Product Release
Advanced to V3.0
7/30/02
相关型号：
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