CY23S09ZXC-1HT [CYPRESS]
PLL Based Clock Driver, 23S Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, TSSOP-16;
| 型号： | CY23S09ZXC-1HT |
| 厂家： | 
CYPRESS |
| 描述： | PLL Based Clock Driver, 23S Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, TSSOP-16 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总13页 (文件大小：288K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY23S09, CY23S05
Low Cost 3.3 V Spread Aware
Zero Delay Buffer
All parts have on-chip PLLs that lock to an input clock on the REF
pin. The PLL feedback is on-chip and is obtained from the
CLKOUT pad.
Features
■ 10 MHz to 100 MHz and 133 MHz operating range, compatible
with CPU and PCI bus frequencies
The CY23S09 has two bans of four outputs each, which can be
controlled by the select inputs as shown in the Select Input
Decoding table on Select Input Decoding for CY23S09 on page
4. If all output clocks are not required, Bank B can be
three-stated. The select inputs also allow the input clock to be
directly applied to the outputs for chip and system testing
purposes.
■ Zero input-output propagation delay
■ Multiple low skew outputs
❐ Output-output skew less than 250 ps
❐ Device-device skew less than 700 ps
❐ One input drives five outputs (CY23S05)
❐ One input drives nine outputs, grouped as 4 + 4 + 1
The CY23S09 and CY23S05 PLLs enter a power down mode
when there are no rising edges on the REF input. In this state,
the outputs are three-stated and the PLL is turned off, resulting
in less than 12.0 A of current draw (for commercial temperature
devices) and 25.0 A (for industrial temperature devices). The
CY23S09 PLL shuts down in one additional case, as shown in
the Select Input Decoding for CY23S09 on page 4.
(CY23S09)
■ Less than 200 ps Cycle-to-cycle jitter
■ Test mode to bypass PLL (CY23S09 only, see Select Input
Decoding for CY23S09 on page 4)
■ Available in space saving 16-pin, 150-mil SOIC, 4.4 mm
TSSOP (CY23S09) or 8-pin, 150-mil
SOIC package (CY23S05)
Multiple CY23S09 and CY23S05 devices can accept the same
input clock and distribute it. In this case, the skew between the
outputs of two devices is guaranteed to be less than 700 ps.
■ 3.3 V operation, advanced 0.65 CMOS technology
■ Spread Aware
All outputs have less than 200 ps of cycle-to-cycle jitter. The input
to output propagation delay on both devices is guaranteed to be
less than 350 ps; the output to output skew is guaranteed to be
less than 250 ps.
Functional Description
The CY23S05 and CY23S09 is available in two different config-
urations, as shown in the Ordering Information on page 8. The
CY23S05-1 and CY23S09-1 is the base part. The CY23S05-1H
and CY23S09-1H is the high drive version of the -1, and its rise
and fall times are much faster than -1.
The CY23S09 is a low cost 3.3 V zero delay buffer designed to
distribute high speed clocks and is available in a 16-pin SOIC
package. The CY23S05 is an 8-pin version of the CY23S09. It
accepts one reference input, and drives out five low skew clocks.
The -1H versions of each device operate at up to 100 and
133 MHz frequencies and have higher drive than the -1 devices.
For a complete list of related resources, click here.
Logic Block Diagram
Cypress Semiconductor Corporation
Document Number: 38-07296 Rev. *I
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 07, 2014
CY23S09, CY23S05
Contents
Pinouts ..............................................................................3
Select Input Decoding for CY23S09 ................................4
Functional Overview ........................................................4
Zero Delay and Skew Control ..................................... 4
Spread Aware.............................................................. 4
Maximum Ratings .............................................................5
Operating Conditions for CY23S05SXX-XX and
Thermal Resistance ..........................................................7
Ordering Information ........................................................8
Ordering Code Definitions........................................... 8
Package Diagrams ............................................................9
Acronym ..........................................................................11
Document Conventions .................................................11
Units of Measure ....................................................... 11
Document History Page .................................................12
Sales, Solutions, and Legal Information ......................13
Worldwide Sales and Design Support....................... 13
Products.................................................................... 13
PSoC® Solutions ...................................................... 13
Cypress Developer Community................................. 13
Technical Support ..................................................... 13
............. 5
CY23S09SXX-XX (Industrial, Commercial Devices)
Electrical Characteristics for CY23S05SXX-XX and
CY23S09SXX-XX (Industrial, Commercial Devices) ..........5
Switching Characteristics for CY23S05SXC-1 and
CY23S09SXC-1 Commercial Temperature Devices............... 5
Switching Characteristics for CY23S05SXI-1H Industrial
Temperature Devices.......................................................................... 6
Switching Waveforms ......................................................6
Test Circuits ......................................................................7
Document Number: 38-07296 Rev. *I
Page 2 of 13
CY23S09, CY23S05
Pinouts
Figure 1. Pin Configuration – CY23S09
Figure 2. Pin Configuration – CY23S05
Table 1. Pin Description for CY23S09
Pin
1
Signal
Description
Input reference frequency, 5 V tolerant input
REF[1]
CLKA1[2]
CLKA2[2]
VDD
2
Buffered clock output, bank A
Buffered clock output, bank A
3.3 V supply
3
4
5
GND
Ground
6
CLKB1[2]
CLKB2[2]
S2[3]
Buffered clock output, bank B
Buffered clock output, bank B
Select input, bit 2
7
8
9
S1[3]
Select input, bit 1
10
11
12
13
14
15
16
CLKB3[2]
CLKB4[2]
GND
Buffered clock output, bank B
Buffered clock output, bank B
Ground
VDD
CLKA3[2]
CLKA4[2]
CLKOUT[2]
3.3 V supply
Buffered clock output, bank A
Buffered clock output, bank A
Buffered output, internal feedback on this pin
Table 2. Pin Description for CY23S05
Pin
1
Signal
Description
REF[1]
CLK2[2]
CLK1[2]
GND
Input reference frequency, 5 V tolerant input
Buffered clock output
2
3
Buffered clock output
4
Ground
5
CLK3[2]
Buffered clock output
6
VDD
3.3 V supply
7
CLK4[2]
Buffered clock output
8
CLKOUT[2]
Buffered clock output, internal feedback on this pin
Notes
1. Weak pull down.
2. Weak pull down on all outputs.
3. Weak pull up on these inputs.
Document Number: 38-07296 Rev. *I
Page 3 of 13
CY23S09, CY23S05
Select Input Decoding for CY23S09
S2
0
S1
0
CLOCK A1–A4
Three-state
Driven
CLOCK B1–B4
Three-state
Three-state
Driven
CLKOUT[4]
Driven
Output Source
PLL Shutdown
PLL
PLL
N
N
Y
N
0
1
Driven
1
0
Driven
Driven
Reference
PLL
1
1
Driven
Driven
Driven
Spread Aware
Functional Overview
Many systems being designed now use a technology called
Spread Spectrum Frequency Timing Generation. Cypress is one
of the pioneers of SSFTG development and designed this
product so as not to filter off the Spread Spectrum feature of the
Reference input, assuming it exists. When a zero delay buffer is
not designed to pass the SS feature through, the result is a signif-
icant amount of tracking skew, which may cause problems in
systems requiring synchronization.
Zero Delay and Skew Control
All outputs must be uniformly loaded to achieve Zero Delay
between the input and output. Because the CLKOUT pin is the
internal feedback to the PLL, its relative loading can adjust the
input-output delay. This is shown in the above graph.
For applications requiring zero input-output delay, all outputs,
including CLKOUT, must be equally loaded. Even if CLKOUT is
not used, it must have a capacitive load equal to that on other
outputs, to obtain zero input-output delay. If input to output delay
adjustments are required, use the above graph to calculate
loading differences between the CLKOUT pin and other outputs.
For more details on Spread Spectrum timing technology, please
see the Cypress Whitepaper EMI and Spread Spectrum
Technology.
For zero output-output skew, be sure to load all outputs equally.
For further information refer to the application note titled AN1234
- Understanding Cypress’s Zero Delay Buffers.
Figure 3. REF. Input to CLKA/CLKB Delay vs. Loading Difference between CLKOUT and CLKA/CLKB Pins
Note
4. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output.
Document Number: 38-07296 Rev. *I
Page 4 of 13
CY23S09, CY23S05
Maximum Ratings
Supply voltage to ground potential ...............–0.5 V to +7.0 V
DC input voltage (Except REF) ..........–0.5 V to VDD + 0.5 V
DC input voltage REF 0.5 V to 7 V
Storage temperature ................................–65 C to +150 C
Maximum soldering temperature (10 seconds) ......... 260 C
Junction temperature................................................. 150 C
Static discharge voltage
(per MIL-STD-883, Method 3015) ..........................> 2,000 V
Operating Conditions for CY23S05SXX-XX and CY23S09SXX-XX (Industrial, Commercial Devices)[5]
Parameter
VDD
Description
Min
3.0
0
Max
3.6
70
85
30
10
7
Unit
V
Supply voltage
TA
Operating temperature - Ambient (Commercial)
Operating temperature - Ambient (Industrial)
Load capacitance, below 100 MHz
Load capacitance, from 100 MHz to 133 MHz
Input capacitance
C
C
pF
pF
pF
-40
CL
CL
CIN
Electrical Characteristics for CY23S05SXX-XX and CY23S09SXX-XX (Industrial, Commercial Devices)
Parameter
VIL
Description
Input LOW voltage[6]
Input HIGH voltage[6]
Input LOW current
Input HIGH current
Output LOW voltage[7]
Test Conditions
Min
Max
Unit
V
0.8
VIH
IIL
2.0
V
VIN = 0 V
VIN = VDD
50.0
A
A
IIH
100.0
VOL
IOL = 8 mA (–1)
OH = 12 mA (–1H)
0.4
V
I
VOH
Output HIGH voltage[7]
IOH = –8 mA (–1)
OL = –12 mA (–1H)
2.4
V
I
IDD (PD mode) Power-down supply current REF = 0 MHz
12.0
32.0
A
mA
IDD
Supply current
Unloaded outputs at 66.67 MHz, SEL
inputs at VDD
Switching Characteristics for CY23S05SXC-1 and CY23S09SXC-1 Commercial Temperature Devices [8]
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
t1
Output frequency
30 pF load
10 pF load
10
10
100
133.33
MHz
MHz
Duty cycle[7] = t2 t1
Rise time[7]
Fall time[7]
Measured at 1.4 V, Fout = 66.67 MHz
Measured between 0.8 V and 2.0 V
Measured between 0.8 V and 2.0 V
40.0
50.0
60.0
2.50
2.50
250
%
ns
ns
ps
ps
t3
t4
t5
t6
Output-to-output skew[7] All outputs equally loaded
Delay, REF Rising Edge to Measured at VDD/2
0
0
±350
CLKOUT Rising Edge[7]
t7
tJ
Device-to-device skew[7] Measured at VDD/2 on the CLKOUT pins
Cycle-to-cycle jitter[7]
PLL lock time[7]
700
200
1.0
ps
ps
Measured at 66.67 MHz, loaded outputs
tLOCK
Stable power supply, valid clock presented
on REF pin
ms
Notes
5. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power up. Power supply sequencing is NOT required.
6. REF input has a threshold voltage of V /2.
DD
7. Parameter is guaranteed by design and characterization. Not 100% tested in production.
8. All parameters specified with loaded outputs.
Document Number: 38-07296 Rev. *I
Page 5 of 13
CY23S09, CY23S05
Switching Characteristics for CY23S05SXI-1H Industrial Temperature Devices[8]
Parameter
t1
Description
Test Conditions
Min
Typ
Max
Unit
Output frequency
30 pF load
10 pF load
10
10
100
133.33
MHz
MHz
Duty cycle[7] = t2 t1
Duty cycle[7] = t2 t1
Rise time[7]
Fall time[7]
Output-to-output skew[7]
Measured at 1.4 V, Fout = 66.67 MHz
Measured at 1.4 V, Fout <50.0 MHz
Measured between 0.8 V and 2.0 V
Measured between 0.8 V and 2.0 V
All outputs equally loaded
40.0
45.0
50.0
50.0
60.0
55.0
1.50
1.50
250
%
%
t3
t4
t5
t6
ns
ns
ps
Delay, REF Rising Edge to Measured at VDD/2
CLKOUT Rising Edge[7]
Device-to-Device Skew[7]
0
0
±350
700
ps
ps
t7
t8
Measured at VDD/2 on the CLKOUT pins
of devices
Output slew rate[7]
Measured between 0.8 V and 2.0 V using
Test Circuit #2
1
V/ns
ps
tJ
Cycle-to-cycle jitter[7]
PLL lock time[7]
Measured at 66.67 MHz, loaded outputs
200
1.0
tLOCK
Stable power supply, valid clock
presented on REF pin
ms
Switching Waveforms
Figure 4. Duty Cycle Timing
t
1
t
2
1.4 V
1.4 V
1.4 V
Figure 5. All Outputs Rise/Fall Time
3.3 V
0 V
2.0 V
0.8 V
2.0 V
0.8 V
OUTPUT
t
3
t
4
Figure 6. Output-Output Skew
1.4 V
OUTPUT
1.4 V
OUTPUT
t
5
Figure 7. Input-Output Propagation Delay
V
DD/2
INPUT
VDD/2
OUTPUT
t
6
Document Number: 38-07296 Rev. *I
Page 6 of 13
CY23S09, CY23S05
Switching Waveforms continued
Figure 8. Device-Device Skew
VDD/2
CLKOUT, Device 1
VDD/2
CLKOUT, Device 2
t7
2309–8
Test Circuits
Test Circuit # 2
Test Circuit # 1
V
DD
OUTPUTS
V
1 kW
DD
0.1 F
0.1 F
CLK out
0.1 F
0.1 F
OUTPUTS
10 pF
1 kW
C
LOAD
V
DD
V
DD
GND
GND
GND
GND
For parameter t8 (output slew rate) on –1H devices
Thermal Resistance
Parameter[9]
Description
Test Conditions
8-pin SOIC 16-pin SOIC 16-pin TSSOP
Unit
Thermal resistance
(junction to ambient)
Test conditions follow standard test
methods and procedures for
measuring thermal impedance, in
accordance with EIA/JESD51.
Theta JA
132
43
108
37
108
17
°C/W
Thermal resistance
(junction to case)
Theta JC
°C/W
Note
9. These parameters are guaranteed by design and are not tested.
Document Number: 38-07296 Rev. *I
Page 7 of 13
CY23S09, CY23S05
Ordering Information
Ordering Code
Pb-Free
Package Name
Package Type
8-pin 150-mil SOIC
Operating Range
CY23S05SXC-1
CY23S05SXC-1T
CY23S05SXC-1H
CY23S05SXC-1HT
CY23S05SXI-1
SZ08
SZ08
SZ08
SZ08
SZ08
SZ08
SZ16
SZ16
SZ16
SZ16
ZZ16
ZZ16
Commercial (0 to 70 C)
Commercial (0 to 70 C)
Commercial (0 to 70 C)
Commercial (0 to 70 C)
Industrial (–40 to 85 C)
Industrial (–40 to 85 C)
Commercial (0 to 70C)
Commercial (0 to 70 C)
Commercial (0 to 70 C)
Commercial (0 to 70 C)
Commercial (0 to 70 C)
Commercial (0 to 70 C)
8-pin 150-mil SOIC – Tape and Reel
8-pin 150-mil SOIC
8-pin 150-mil SOIC – Tape and Reel
8-pin 150-mil SOIC
CY23S05SXI-1T
CY23S09SXC-1
CY23S09SXC-1T
CY23S09SXC-1H
CY23S09SXC-HT
CY23S09ZXC-1H
CY23S09ZXC-1HT
8-pin 150-mil SOIC – Tape and Reel
16-pin 150-mil SOIC
16-pin 150-mil SOIC – Tape and Reel
16-pin 150-mil SOIC
16-pin 150-mil SOIC – Tape and Reel
16-pin 4.4 mm TSSOP
16-pin 4.4 mm TSSOP – Tape and Reel
Ordering Code Definitions
CY
1(H)
(T)
23S05 S(X) C
-
Tape and Reel
Output Drive:
1 = standard drive
1H = high drive
Temperature Range:
C = Commercial
I = Industrial
Package:
S = SOIC, leaded
Z = TSSOP, leaded
SX = SOIC, Pb-free
ZX = TSSOP, Pb-free
Base device part number (S = Spread aware)
05 = 5-output zero delay buffer
09 = 9-output zero delay buffer
Company ID: CY = Cypress
Document Number: 38-07296 Rev. *I
Page 8 of 13
CY23S09, CY23S05
Package Diagrams
Figure 9. 8-Pin (150-Mil) SOIC S08 and SZ08
51-85066 *H
Document Number: 38-07296 Rev. *I
Page 9 of 13
CY23S09, CY23S05
Package Diagrams continued
Figure 10. 16-Pin (150-Mil) SOIC S16 and SZ16
51-85068 *E
Figure 11. 16-Pin TSSOP 4.40 mm Body Z16 and ZZ16
51-85091 *E
Document Number: 38-07296 Rev. *I
Page 10 of 13
CY23S09, CY23S05
Acronym
Acronym
CMOS
EMI
Description
complementary metal oxide semiconductor
electromagnetic interference
phase-locked loop
PLL
SOIC
small outline integrated circuit
spread spectrum
SS
SSFTG
SSOP
TSSOP
spread spectrum frequency timing generator
shrunk small outline package
thin shrunk small outline package
Document Conventions
Units of Measure
Symbol
C
Unit of Measure
degree Celsius
megahertz
microamperes
milliamperes
milliseconds
nanoseconds
percent
MHZ
uA
mA
ms
ns
%
pF
ps
picofarads
picoseconds
volt
V
Document Number: 38-07296 Rev. *I
Page 11 of 13
CY23S09, CY23S05
Document History Page
Document Title: CY23S09/CY23S05 Low Cost 3.3 V Spread Aware Zero Delay Buffer
Document Number: 38-07296
Submission
Date
Orig. of
Change
Rev.
ECN No.
Description of Change
**
111147
111773
11/14/01
02/20/02
12/22/02
See ECN
10/23/08
09/10/09
DSG
CTK
RBI
Changed from spec number 38-01094 to 38-07296
Added 150-mil SSOP option
*A
*B
*C
*D
*E
122885
267849
2595524
2761988
Added power-up requirements to Operating Conditions
Added Lead-Free devices
RGL
CXQ/PYRS Added device “Status” to Ordering Information
KVM
Removed obsolete parts from Ordering Information table: CY23S09ZC-1,
CY23S09OC-1, CY23S09OC-1H, CY23S09ZXC-1, CY23S09OXC-1,
CY23S09OXC-1H.
Added CY23S05SXC-1T, CY23S05SXC-1HT, CY23S09SXC-1T,
CY23S09SXC-1HT, CY23S09ZXC-1HT.
Removed Status column from Ordering Information table; added footnote.
Updated package names and added numerical temperature range to
Ordering Information table.
Removed QSOP package drawing.
*F
2897373
03/22/10
CXQ
Removed part numbers CY23S05SC-1, CY23S05SC-1H, CY23S09SC-1,
CY23S09SC-1H, and CY23S09ZC-1H from Ordering Information table.
Added CY23S05SXI-1 and CY23S05SXI-1T to Ordering Information table.
Updated package diagrams.
Updated copyright section.
*G
*H
3394655
4564025
10/04/11
PURU
TAVA
Added Figure 3
Updated Hyper links
Updated Package Diagrams
Added Ordering Code Definitions, Acronym, and Units of Measure.
11/07/2014
Removed the SSOP package in Features.
Updated Figure 1 (removed SSOP).
Updated Figure 7.
Replaced all occurrences of SC and SI with SXC and SXI in the following
tables:
Operating Conditions for CY23S05SXX-XX and CY23S09SXX-XX
(Industrial, Commercial Devices)[5]
Electrical Characteristics for CY23S05SXX-XX and CY23S09SXX-XX
(Industrial, Commercial Devices)
Switching Characteristics for CY23S05SXC-1 and CY23S09SXC-1
Commercial Temperature Devices [8]
Switching Characteristics for CY23S05SXI-1H Industrial Temperature
Devices[8]
Updated the table, Operating Conditions for CY23S05SXX-XX and
CY23S09SXX-XX (Industrial, Commercial Devices)[5]
.
Removed CY23S09SI-1H in the table title, in Switching Characteristics for
CY23S05SXI-1H Industrial Temperature Devices[8]
.
Updated Figure 9, Figure 10, and Figure 11 in Package Diagrams.
*I
5738816
05/24/2017
PSR
Updated the link for AN1234.
Added Thermal Resistance.
UpdatedtheCypresslogo, copyrightinformation, Sales, Solutions, andLegal
Information based on the new template.
Document Number: 38-07296 Rev. *I
Page 12 of 13
CY23S09, CY23S05
Sales, Solutions, and Legal Information
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Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2001-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
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modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
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TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
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damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners
Document Number: 38-07296 Rev. *I
Revised May 24, 2017
Page 13 of 13
相关型号：
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CYPRESS
CY2410SXC-1T
Video Clock Generator, 27MHz, CMOS, PDSO8, 0.150 INCH, LEAD FREE, MS-012, SOIC-8
CYPRESS
CY2410SXC-5
Video Clock Generator, 27MHz, CMOS, PDSO8, 0.150 INCH, LEAD FREE, MS-012, SOIC-8
CYPRESS
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