CY24212SC-5T [CYPRESS]
MediaClock MPEG Clock Generator with VCXO; MediaClock MPEG时钟发生器与VCXO
| 型号： | CY24212SC-5T |
| 厂家： | 
CYPRESS |
| 描述： | MediaClock MPEG Clock Generator with VCXO |
| 文件： | 总6页 (文件大小：114K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY24212
PRELIMINARY
MediaClock™
MPEG Clock Generator with VCXO
Features
• Integrated phase-locked loop (PLL)
• Low jitter, high-accuracy outputs
• VCXO with analog adjust
• 3.3V operation
Benefits
Highest-performance PLL tailored for multimedia applications
Meets critical timing requirements in complex system designs
Large ±150-ppm range, better linearity
Enables application compatibility
Part Number Outputs
Input Frequency Range
13.5 MHz/27 MHz (selectable)
Output Frequencies
CY24212-1
CY24212-2
CY24212-3
CY24212-5
1
2
2
2
27 MHz
13.5 MHz/27 MHz (selectable)
Two copies of 27 MHz
27 MHz/27.027 MHz (-1 ppm)
27 MHz/27.027 MHz (0 ppm)
27 MHz
27 MHz
Logic Block Diagram
OUTPUT
DIVIDERS
XIN
OSC
Q
Φ
CLKA (27 MHz)
XOUT
VCO
27 MHz (-2)
27/27.027 MHz (-3)
P
VCXO
FSEL
PLL
VSS
VDD
Pin Configurations
CY24212-3,-5
8-pin SOIC
CY24212-1
8-pin SOIC
CY24212-2
8-pin SOIC
XOUT
1
XOUT
VSS
1
2
3
4
XOUT
8
1
XIN
8
7
6
5
8
XIN
XIN
7
6
5
2
3
4
CLKB (27/27.027 MHz)
7
6
5
VDD
VCXO
VSS
2
3
4
CLKB 27 MHz
VDD
VCXO
VSS
VDD
VCXO
VSS
FSEL
FSEL
FSEL
CLKA 27 MHz
CLKA 27 MHz
CLKA 27 MHz
Table 1. CY24212 (-1, -2) Frequency Select Option
FSEL
Reference
13.5 MHz
27 MHz
CLKA/CLKB
27 MHz
0
1
27 MHz
Table 2. CY24212 (-3, -5) Frequency Select Option
FSEL
Reference
27 MHz
CLKA
27 MHz
27 MHz
CLKB
0
1
27 MHz
27 MHz
27.027 MHz
Cypress Semiconductor Corporation
Document #: 38-07402 Rev. *B
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised February 18, 2003
PRELIMINARY
CY24212
Pin Description
Name
Pin Number Description
XIN
1
2
3
4
5
6
Reference Input.
Voltage Supply.
VDD
VCXO
VSS
Input Analog Control for VCXO.
Ground.
CLKA
FSEL (-1,-2)
27-MHz Clock Output.
Input Frequency Select, Weak Internal Pull-up.
FSEL = 0, XIN = 13.5 MHz
FSEL = 1, XIN = 27 MHz
FSEL (-3,-5)
6
Output Frequency Select, Weak Internal Pull-up.
FSEL = 0, CLKA = 27 MHz, CLKB = 27 MHz
FSEL = 1, CLKA = 27 MHz, CLKB = 27.027 MHz
VSS (-1)
7
7
7
8
Ground.
CLKB (-2)
CLKB (-3,-5)
XOUT[1]
27 MHz.
27 MHz/27.027 MHz.
Reference Output.
Pullable Crystal Specifications
Parameter
CRload
Name
Min
Typ
Max
Unit
Crystal Load Capacitance
14
pF
C0/C1
240
50
ESR
Equivalent Series Resistance
Operating Temperature
35
Ω
To
0
70
°C
Crystal Accuracy
TTs
Crystal Accuracy
+ 20
+ 50
ppm
ppm
Stability over Temperature and Aging
Absolute Maximum Conditions
Parameter
VDD
Description
Min
–0.5
–65
Max
7.0
Unit
V
Supply Voltage
TS
TJ
Storage Temperature[2]
Junction Temperature
Digital Inputs
125
125
°C
°C
V
VSS – 0.3
VDD + 0.3
Electrostatic Discharge
2
kV
Recommended Operating Conditions
Parameter
VDD
Description
Operating Voltage
Min
3.135
0
Typ
3.3
Max
Unit
V
3.465
70
TA
Ambient Temperature
Max. Load Capacitance
Reference Frequency
°C
CLOAD
15
pF
fREF
13.5
27
MHz
Notes:
1. Float XOUT if XIN is externally driven.
2. Rated for ten years.
Document #: 38-07402 Rev. *B
Page 2 of 6
PRELIMINARY
CY24212
DC Electrical Specifications
Parameter
IOH
Name
Description
Min
12
Typ
24
Max
Unit
mA
mA
pF
Output High Current
Output Low Current
Input Capacitance
Input High Current
Input Low Current
VCXO Pullability Range
VCXO Input Range
Supply Current
VOH = VDD – 0.5, VDD = 3.3V (source)
VOL = 0.5, VDD = 3.3V (sink)
IOL
12
24
CIN
7
IIH
VIH = VDD
VIL = 0V
–
–
5
10
50
µA
IIL
–
µA
f∆XO
VVCXO
IDD
+150
0
ppm
V
VDD
35
Sum of Core and Output Current
CMOS levels, 70% of VDD
CMOS levels, 30% of VDD
mA
VDD
VDD
kΩ
VIH
Input High Voltage
Input Low Voltage
0.7
VIL
0.3
RUP
Pull-up resistor on inputs VDD = 3.14 to 3.47V, measured VIN = 0V
100
150
AC Electrical Specifications (V = 3.3V)
DD
Parameter[3]
Name
Description
Min
45
Typ
Max
55
Unit
%
DC
ER
Output Duty Cycle
Rising Edge Rate
Duty Cycle is defined in Figure 1, 50% of VDD
50
Output Clock Edge Rate, Measured from 20%
0.8
1.4
V/ns
to 80% of VDD, CLOAD = 15 pF. See Figure 2.
EF
Falling Edge Rate
Output Clock Edge Rate, Measured from 80%
to 20% of VDD, CLOAD = 15 pF. See Figure 2.
0.8
1.4
V/ns
t9
Clock Jitter
Peak-to-peak period jitter
300
ps
t10
PLL Lock Time
3
ms
Test and Measurement Set-up
VDDs
Outputs
CLOAD
0.1 µF
DUT
GND
Note:
3. Not 100% tested.
Document #: 38-07402 Rev. *B
Page 3 of 6
PRELIMINARY
CY24212
Voltage and Timing Definitions
t1
t2
VDD
50% of VDD
0V
Clock
Output
Figure 1. Duty Cycle Definition
t4
t3
V DD
80% of VDD
20% of VDD
0V
Clock
Output
Figure 2. ER = (0.6 x VDD) /t3, EF = (0.6 x VDD) /t4
Ordering Information
Ordering Code
Package Name
S8
Package Type
Operating Range
Operating Voltage
CY24212SC-1
CY24212SC-1T
CY24212SC-2
CY24212SC-2T
CY24212SC-3
CY24212SC-3T
CY24212SC-5
CY24212SC-5T
8-Pin SOIC
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
S8
S8
S8
S8
S8
S8
S8
8-Pin SOIC -Tape and Reel
8-Pin SOIC
8-Pin SOIC -Tape and Reel
8-Pin SOIC
8-Pin SOIC -Tape and Reel
8-Pin SOIC
8-Pin SOIC -Tape and Reel
Document #: 38-07402 Rev. *B
Page 4 of 6
PRELIMINARY
CY24212
Package Drawing and Dimensions
8-Lead (150-Mil) SOIC S8
51-85066-*A
MediaClock is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document
may be the trademarks of their respective holders.
Document #: 38-07402 Rev. *B
Page 5 of 6
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
PRELIMINARY
CY24212
Document History Page
Document Title: CY24212 MediaClock™ MPEG Clock Generator with VCXO
Document Number: 38-07402
Issue
Date
Orig. of
REV.
**
ECN NO.
117089
120888
123064
Change Description of Change
09/09/02
12/06/02
02/19/03
CKN
CKN
CKN
New Data Sheet
Added -3
*A
*B
Added -5
Document #: 38-07402 Rev. *B
Page 6 of 6
相关型号：
CY24212SXC-5
27.027 MHz, VIDEO CLOCK GENERATOR, PDSO8, 0.150 INCH, LEAD FREE, MS-012, SOIC-8
ROCHESTER
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